P-type tin oxide thin film, thin film transistor, inverter circuit and preparation method thereof

Abstract

The invention provides a P-type stannous oxide thin film. The P-type stannous oxide thin film is obtained by carrying out magnetron sputtering on a Sn target material with the Te content of 1-10at%, packaging and annealing. The invention also provides a thin film transistor comprising the P-type stannous oxide and an inverter comprising the thin film transistor. Meanwhile, the invention also provides a preparation method of the thin film transistor and the phase inverter.

Description

Technical Field

[0001] This invention belongs to the field of semiconductors, specifically relating to a method for preparing Te-doped P-type tin oxide and its application. Background Technology

[0002] Thin-film transistors (TFTs) are important semiconductor devices used in the fabrication of TFT-type liquid crystal displays (LCDs). Since each liquid crystal pixel in a TFT LCD is driven by a thin-film transistor integrated behind it, the performance of the TFT directly affects the overall performance of the TFT LCD. A TFT LCD screen can be viewed as two glass substrates with a layer of liquid crystal sandwiched between them. The upper glass substrate contains a color filter, while the lower glass substrate contains the TFTs. When an electric current passes through the TFT, creating a change in the electric field, the liquid crystal molecules deflect, altering the polarity of the light. This polarity, combined with the light passing through the polarizer and color filter, ultimately forms the image on the display screen.

[0003] A thin-film transistor (TFT) consists of a gate, a gate dielectric layer on the gate surface, and a channel layer, arranged from bottom to top. The channel layer has a source electrode at one end and a drain electrode at the other. Based on the principle of field-effect transistors (FETs), the conductivity of the channel layer changes when different voltages are applied to the gate. When the conductivity of the channel layer increases, the source and drain electrodes at both ends of the channel layer conduct. When the conductivity of the channel layer decreases, the source and drain electrodes at both ends of the channel layer become insulated. Due to these phenomena, the TFT can achieve both on and off states. Therefore, the channel layer is the core component of the TFT and is crucial for realizing the "switching" function of the TFT.

[0004] The applications of thin-film transistors (TFTs) extend far beyond TFT-based liquid crystal displays. In digital integrated circuits, the embedding of TFTs enhances circuit speed and analog signal control capabilities. In the field of solar cells, the application of TFTs has brought about increased efficiency and reduced costs. In short, as a key component of modern technology, thin-film transistors are driving innovation across various industries with their unique advantages.

[0005] Thin-film transistor (TFT) channel layer materials are classified into N-type and P-type materials. N-type materials have demonstrated significant commercial application potential in the display industry. For example, amorphous IGZO from metal oxides has already been commercialized in flexible displays. However, P-type materials still face considerable challenges. Common types of P-type materials include organic semiconductors (π-conjugated polymers / small molecules), two-dimensional layered materials (black phosphorus (BP)), oxide P-type materials (such as Cu₂O and NiO), and low-temperature polycrystalline silicon (LTPS). The advantages and disadvantages of these materials are as follows: Organic semiconductors (π-conjugated polymers / small molecules): Advantages: simple film formation process, designable molecular structure, and controllable bandgap and mobility; Disadvantages: poor environmental stability and poor device uniformity.

[0006] Two-dimensional layered materials (black phosphorus (BP)): Advantages: atomic-level thickness, few interface defects; high carrier mobility; Disadvantages: black phosphorus is easily oxidized and degraded in air, and has high preparation costs.

[0007] P-type oxide materials (such as Cu₂O, NiO, SnO): Advantages: low cost, simple thin film fabrication process; Disadvantages: low carrier mobility (typically <10 cm⁻¹). 2 / Vs), poor conductivity, requires high concentration of doping.

[0008] Low-temperature polycrystalline silicon (LTPS): Advantages: high carrier mobility and strong compatibility with the silicon-based industry chain; Disadvantages: high film formation temperature (>500℃), complex preparation process, and higher cost than oxides.

[0009] To meet the commercial standards for low-power displays, currently, expensive low-temperature polycrystalline silicon (LTPS) is commonly used as the P-type material. If P-type oxide materials can overcome the challenge of low mobility, they will have significant application prospects due to their low cost and simple processing. Tin-based oxides are the most representative P-type oxide materials. The channel layer in thin-film transistors can be fabricated using tin-based oxides. As mentioned above, P-type oxide materials consistently face the problems of low mobility and poor conductivity; the mobility of tin-based oxide P-type thin-film transistors is around 10 cm⁻¹. 2 / Vs and below.

[0010] Therefore, existing technologies disclose many improved methods for tin-based oxide P-type thin film crystals, as follows: In their paper "Mobility enhancement in P-type SnOthin-film transistors via Ni incorporation by co-sputtering", Hsu SM, Yang CE, Lu MH, et al. disclosed a technique for improving the mobility of tin-based oxide P-type thin film crystals by using Ni doping.

[0011] In their paper "Compositional Engineering of Cu-Doped SnO Film for Complementary Metal Oxide Semiconductor Technology," Hong Ruohao, He Penghui, Zhang Sen, et al. disclosed a technique for improving the mobility of tin-based oxide P-type thin film crystals by using Cu doping.

[0012] Liang Lingyan, Liu Zhimin, Cao Hongtao, et al., in their paper "The structural, optical and electrical properties of Y-doped SnO thin films and their p-type TFT application," disclose a technique for improving the mobility of tin-based oxide p-type thin film crystals using Y-doping. Chen Po-Chun, Chiu Yu-Chien, Liou Guan-Lin, et al., in their paper "Performance Enhancements in p-Type Al-Doped Tin-Oxide Thin Film Transistors by Using Fluorine Plasma Treatmen," disclose the use of Fluorine Plasma Treatmen. - An implantation doping technique to improve the mobility of tin-based oxide P-type thin film crystals.

[0013] Lee Alex W., Le Dong, Matsuzaki Kosuke, et al., in their paper "Hydrogen-Defect Termination in SnO for p-Channel TFTs," disclose the use of H... + A doping technique to improve the mobility of tin-based oxide P-type thin film crystals.

[0014] Bae Sang-Dae, Kwon Soo-Hun, Jeong Hwan-Seok, and Kwon Hyuck-In, in their paper "Demonstration of high-performance p-type tin oxide thin-film transistors using argon-plasma surface treatments," disclose the use of Ar... + A doping technique to improve the mobility of tin-based oxide P-type thin film crystals.

[0015] In their paper "Atomically Thin TinMonoxide-Based p-Channel Thin-Film Transistor and a Low-Power Complementary Inverter", Chi-Hsin Huang, Yalun Tang, Tzu-Yi Yang, et al. disclosed a technical solution using a liquid metal method to improve the mobility of tin-based oxide p-type thin film crystals.

[0016] In their paper "Fabrication of high-performance p-type thin film transistors using atomic-layer-deposited SnO films," Kim Soo Hyun, Baek In-Hwan, Kim Da Hye, et al. disclosed a technique for improving the mobility of tin-based oxide p-type thin film crystals using atomic-layer deposition.

[0017] However, none of the aforementioned existing technologies have solved the problem of difficulty in improving the mobility of tin-based oxide P-type thin film crystals. Summary of the Invention

[0018] The first objective of this invention is to provide a p-type tin oxide thin film with high mobility.

[0019] A second objective of the present invention is to provide a thin-film transistor comprising the aforementioned P-type tin oxide thin film.

[0020] A third objective of this invention is to provide a method for fabricating the thin-film transistor.

[0021] A fourth object of the present invention is to provide an inverter comprising the aforementioned P-type tin oxide thin-film transistor.

[0022] The fifth objective of this invention is to provide a method for fabricating the inverter circuit.

[0023] This invention is achieved through the following technical solution: A P-type tin oxide thin film is obtained by magnetron sputtering of a Sn target with a Te content of 1-10 at%, followed by encapsulation and annealing.

[0024] The substrate used in the magnetron sputtering includes a P-type silicon wafer; P-type silicon wafers have good conductivity, mature manufacturing process, and are suitable for use as substrates and back gates.

[0025] The magnetron sputtering process uses an radio frequency (RF) power supply. RF power supplies provide a stable sputtering rate, which is beneficial for depositing more uniform thin film materials; it also balances the mechanical stability, electrical compatibility, cost, and functional suitability of the silicon wafer. The thickness of the substrate is 500-800 μm; The power of the radio frequency power supply is 25-35W; the power of 25-35W is beneficial to protect the target material from excessive bombardment, and at the same time can deposit uniform thin film material.

[0026] The thickness of the P-type tin oxide thin film is 15-30 nm; The purity of the Sn target material with a Te content of 1-10 at% is 99.99%.

[0027] A thin-film transistor comprising the aforementioned P-type tin oxide thin film.

[0028] The method for fabricating the thin-film transistor includes the following steps: A gate dielectric layer is grown on the substrate using ALD (Atomic Layer Deposition) growth method; P-type tin oxide thin films are deposited on the surface of the gate dielectric layer using magnetron sputtering; Source and drain electrodes are deposited onto the surface of a P-type tin oxide thin film by vapor deposition; Finally, the gate dielectric layer, P-type tin oxide film, and source / drain electrodes were passivated, encapsulated, and annealed using ALD growth.

[0029] The gate dielectric layer is HfO2, Al2O3, SiO2, ZrO2 or Ta2O5; other oxides with good insulating properties can also be used to realize this invention.

[0030] The annealing temperature is 150-250℃; this temperature range is compatible with most low-temperature processes, which helps to reduce costs.

[0031] The source and drain electrodes are one of Pd, Au, Ag, Ni, or Al. Other metals with good conductivity can also be used to implement this invention.

[0032] An inverter includes the aforementioned P-type tin oxide thin-film transistor.

[0033] The method for fabricating the inverter includes the following steps: A gate dielectric layer is grown on the substrate using the ALD growth method. InSnZnO thin films and P-type tin oxide thin films were deposited on the surface of the gate dielectric layer by magnetron sputtering; Source and drain electrodes are deposited onto the surfaces of n-type InSnZnO thin films and p-type tin oxide thin films by vapor deposition; Finally, the gate dielectric layer, n-type InSnZnO thin film, p-type tin oxide thin film and source / drain electrodes were passivated, encapsulated and annealed using ALD growth method.

[0034] The method for fabricating the inverter, wherein the magnetron sputtering uses an radio frequency power supply; The power of the radio frequency power supply is 45-55W. A power of 45-55W is beneficial for protecting the target material from excessive bombardment and for depositing uniform thin film materials. The InSnZnO thin film has a thickness of 15-30 nm; The InSnZnO thin film has an In:Sn:Zn ratio of 1-1.2:0.1:1-1.2at%.

[0035] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention provides a p-type tin suboxide thin film, which is obtained by magnetron sputtering using a Sn target doped with 1-10 at% Te. After passivation and encapsulation with hafnium oxide (HfO2) deposited in an ALD, followed by annealing, a high-mobility p-type tin suboxide thin film is obtained. This p-type tin suboxide thin film is mainly composed of three components: Sn, SnO, and SnO2. SnO is a p-type semiconductor and is the main reason for the material's p-type characteristics. SnO2 provides electron carriers to recombine intrinsic hole carriers in the thin film, mainly playing a role in reducing off-state current.

[0036] The high mobility of the p-type tin suboxide thin film provided by this invention is due to the low concentration of Te doping. Because of the low doping concentration, Te is distributed in different valence states within the tin suboxide thin film material, with Te primarily existing as tetravalent Te (Te2). 4+ ) and elemental tellurium (Te 0 )exist. Te 4+ Sn can replace tin oxide in the lattice 2+ / Sn 4+ Site. Because Te 4+ The 5s / 5p orbitals exhibit greater spatial extension and can undergo strong hybridization with the 2p orbitals of O, enhancing valence band dispersion and optimizing P-type transport capabilities.0 When tin oxide exists at grain boundaries in the form of atomic-level dispersion or nano-scale clusters, its metallic properties can form local low-resistivity conductive pathways in insulating grain boundary regions, indirectly contributing to the improvement of mobility.

[0037] The effect of Te doping on p-type tin oxide thin films is mainly manifested in three aspects: 1. Induces slight lattice shrinkage: After Te doping, the interplanar spacing of the p-type tin suboxide film decreases, which enhances the overlap between Sn 5s / 5p and O 2p orbitals, intensifies sp-p hybridization, increases valence band dispersion, and reduces the effective hole mass. This decreases, thereby increasing the migration rate.

[0038] Please refer to the following formula for details:

[0039] Carrier mobility (μ) and effective mass Band curvature ( The effective mass is inversely proportional to the energy level. Its physical essence is that the curvature of the band structure determines the effective mass, which in turn directly affects the carrier mobility. E is energy, and k is the wave vector.

[0040] 2. Secondly, Te doping promotes lattice ordering in tin suboxide, thereby reducing intrinsic defects and improving crystallinity. This aligns with Matthiessen's law. It can be known that (μ) ph It is phonon scattering, μ imp It is ionized impurity scattering, μ gb It is grain boundary scattering), defect density decreases grain boundary scattering (μ gb The carrier relaxation time (τ) decreases, the mobility increases, and the carrier relaxation time (τ) increases.

[0041] 3. Most importantly, after Te doping, a significant increase in the intensity of diffraction peaks in the β-Sn(101)(200) crystal plane orientations can be observed, and even a new β-Sn(211) crystal plane orientation appears. This indicates that Te doping induces the enhancement and generation of the β-Sn crystal phase, which contributes to the increase in mobility. As is well known, in p-type tin-based semiconductor materials, the β-Sn 5p orbitals participate in the formation of their valence band, which can reduce the regionality of the O 2p orbitals. The valence band apex changes from O 2p dominance to a Sn 5p-O 2p mixed state, thereby significantly improving hole transport capacity and increasing mobility.

[0042] In summary, the hole mobility of the P-type tin oxide thin film provided by this invention can reach 50 cm⁻¹. 2 / Vs and above.

[0043] The present invention provides a thin-film transistor that, because it includes the aforementioned P-type tin oxide thin film, has high mobility and can be used to fabricate semiconductor devices.

[0044] This invention provides a method for fabricating the aforementioned thin-film transistor. Compared to existing technologies, this method selects a different target material during magnetron sputtering and, after hafnium oxide (HfO2) encapsulation and passivation, anneals the thin film to obtain a thin-film transistor with high mobility. This high mobility characteristic lays a solid foundation for the future application of tin-based oxide P-type thin-film transistors in high-speed logic circuits, high-frequency radio frequency devices, optoelectronic devices, and other fields.

[0045] The magnetron sputtering target used in this invention is a Te-doped Sn alloy target. Compared with Te and Sn bimetallic target sputtering, single-target sputtering produces a more uniform film, effectively reducing the concentration of bulk defects in the film and improving the transport of hole carriers in the film material, thereby facilitating the acquisition of high-mobility film materials.

[0046] Based on the P-type tin oxide thin-film transistor provided in this invention, an all-oxide complementary inverter circuit was successfully fabricated by combining it with an n-type InSnZnO thin-film transistor. The inverter fabricated in this invention has a voltage gain of 60 Ω (voltage gain is dV). OUT / dV IN V OUT Represents the output voltage, V IN (Represents input voltage). Attached Figure Description

[0047] Figure 1 A schematic diagram of the thin-film transistor structure provided by the present invention is shown; Figure 2 A schematic diagram of the fabrication process of the thin-film transistor provided by the present invention is shown; Figure 3 The graph shows the compositional variations of thin films with different Te doping concentrations as measured by XPS; where Figure 3 (a) shows the percentage of Sn valence states in films with different Te doping concentrations. Figure 3 (b) shows the percentage of Te valence states in films with different Te doping concentrations; Figure 4 The XRD diffraction patterns of films with different Te doping concentrations are shown; among them, Figure 4 (a) shows the XRD diffraction pattern at 20–50°; Figure 4 (b) shows the XRD diffraction pattern at 30–35°; from Figure 4 As can be seen from the XRD diffraction peaks shifting to the right, the interplanar spacing decreases, which enhances the overlap between Sn 5s / 5p and O 2p orbitals, intensifies sp-p hybridization, and increases valence band dispersion. Figure 4The diffraction peaks with β-Sn(101)(200) crystal plane orientations were enhanced, and even a new β-Sn(211) crystal plane orientation appeared; this indicates that Te doping induced the enhancement and generation of the β-Sn crystal phase. Figure 5 The TEM cross-sectional view and Fourier transform diffraction pattern of the thin film prepared in Example 2 are shown. Figure 5 (a) shows the microstructure characterization of a 3 at% Te-doped tin oxide film determined by TEM. Figure 5 (b) to Figure 5 (e) High-resolution transmission electron microscopy images of α-Sn(111) and α-Sn(200), β-Sn(200), β-Sn(101) and α-Sn(220), and α-SnO(110) crystal planes, respectively; Figure 5 The regular HRTEM crystal plane fringes indicate that Te doping can promote lattice ordering, reduce intrinsic defects, and improve lattice crystallinity. Figure 6 The transport characteristics and mobilities of different Te doping concentrations are shown; where Figure 6 (a) is the transition curve; Figure 6 (b) represents the migration rate; Figure 7 A schematic diagram of the fabrication process of InSnZnO and SnO:Te inverter circuits is shown; Figure 8 The voltage transfer characteristics and gain of the InSnZnO and SnO:Te thin-film complementary inverter circuit prepared in Example 6 are shown. Figure 8 (a) shows a schematic diagram of the CMOS structure; Figure 8 (b) shows the gain diagram of the inverter. Figure 8 (c) shows the noise margin diagram of the inverter. Figure 8 (d) shows the static power consumption diagram of the inverter. Figure 8 (e) shows the frequency response diagram of the inverter. Detailed Implementation

[0048] The present invention will be further described below with reference to specific embodiments.

[0049] Example 1 Thin film material preparation Prepare a P-type silicon wafer with a thickness of about 500μm.

[0050] The first step involves covering and securing a metal mask onto a silicon wafer, or using a photolithography lift-off process, and placing it into the sample stage of a magnetron deposition apparatus. A SnO:Te thin film of approximately 15 nm is then deposited using a 25W RF power supply for sputtering. The target used is a Te-doped (2 at%) Sn target with a purity of 99.99%.

[0051] The second step involves placing the silicon wafer after the thin film material is deposited into an ALD to grow a 5nm Ta2O5 layer as a passivation encapsulation layer.

[0052] The third step is to perform low-temperature annealing (150°C) on the packaged and passivated device.

[0053] Example 2 Thin film material preparation Prepare a P-type silicon wafer with a thickness of about 500μm.

[0054] The first step involves covering and securing a metal mask onto a silicon wafer, or using a photolithography lift-off process, and placing it into the sample stage of a magnetron deposition apparatus. A SnO:Te thin film of approximately 30 nm is then deposited using a 35W RF power supply. The target used is a Te-doped (6 at%) Sn target with a purity of 99.99%.

[0055] The second step involves placing the silicon wafer after the thin film material is deposited into an ALD to grow a 15nm HfO2 layer as a passivation encapsulation layer.

[0056] The third step is to perform low-temperature annealing (250°C) on the packaged and passivated device.

[0057] Example 3 Thin film material preparation Prepare a P-type silicon wafer with a thickness of about 500μm.

[0058] The first step involves covering and securing a metal mask onto a silicon wafer, or using a photolithography lift-off process, and placing it into the sample stage of a magnetron deposition apparatus. A SnO:Te thin film of approximately 25 nm is then deposited using a 30W RF power supply for sputtering. The target used is a Te-doped (10 at%) Sn target with a purity of 99.99%.

[0059] The second step involves placing the silicon wafer after the thin film material is deposited into an ALD to grow a 5-15nm ZrO2 layer as a passivation encapsulation layer.

[0060] The third step is to perform low-temperature annealing (200℃) on the packaged and passivated device.

[0061] Comparative Example 1 Thin film material preparation Prepare a P-type silicon wafer with a thickness of about 500μm.

[0062] The first step involves covering and fixing a metal mask onto the silicon wafer, or using a photolithography lift-off process, and placing it into the sample stage of a magnetron deposition apparatus. An approximately 15nm SnO thin film is then deposited using a 25W RF power supply via sputtering, with a 99.99% pure metallic Sn target used.

[0063] The second step involves placing the silicon wafer after the thin film material is deposited into an ALD to grow a 5-15 nm Ta2O5 layer as a passivation encapsulation layer.

[0064] The third step is to perform low-temperature annealing (150-250℃) on the packaged and passivated device.

[0065] Tin suboxide thin films are polycrystalline p-type semiconductors, and crystal quality is a crucial factor determining their mobility. For example... Figure 4 According to XRD analysis, as the Te content increases, polycrystalline structures of Sn and SnO gradually form. When the Te doping in the film is 0-2 at%, the film exhibits obvious β-Sn(101)(200) and α-SnO(110) crystal orientations, but the corresponding weak diffraction peak intensities indicate poor crystal quality, thus reflecting a mobility value maintained at 10 cm⁻¹. 2 The doping intensity was only slightly increased at around / Vs; however, when the Te doping of the film was 6at%, the diffraction peak intensities corresponding to β-Sn(101)(200) and α-SnO(110) increased significantly, indicating a significant improvement in the crystallinity of the film and the formation of new crystal planes β-Sn(211) and α-SnO(110), enriching the polycrystalline structure of the film (e.g., ...). Figure 5 (as confirmed by TEM diffraction patterns), thus the mobility is greatly increased to 50 cm⁻¹. 2 / Vs or more. Then, after the Te doping increased to 10at%, although the peak intensity of each crystal plane orientation decreased, it remained within the range of / Vs. Figure 4 In b, the positions of the diffraction peaks of each crystal plane show a trend of increasing angle, indicating that 10at%Te induces lattice shrinkage and reduces the interplanar spacing, thereby increasing the overlap between Sn 5s / 5p and O 2p orbitals, intensifying sp-p hybridization, improving valence band dispersion, and increasing the effective hole mass. The migration rate is reduced, so even with poor crystal quality, the migration rate remains as high as 40 cm⁻¹. 2 / Vs and above.

[0066] Example 4 Thin-film transistor fabrication Prepare a P-type silicon wafer approximately 500μm thick. The process is as follows: Figure 2 As shown.

[0067] The first step is to grow an 18nm Ta2O5 gate dielectric layer on a P-type silicon substrate using ALD growth.

[0068] The second step involves covering and fixing a metal mask onto a silicon oxide wafer, or using a photolithography lift-off process, and placing it into the sample stage of a magnetron deposition apparatus. An approximately 15nm SnO:Te thin film is deposited using a 25W RF power supply for sputtering. The target used is a Te-doped (1 at%) Sn target with a purity of 99.99%.

[0069] The third step involves covering and fixing an electrode mask onto the SnO:Te thin film, or using a photolithography lift-off process, placing it in a deposition apparatus, and using a thermal evaporation process to deposit a layer of Ag metal as the source and drain electrodes.

[0070] The fourth step involves placing the device with deposited metal electrodes into an ALD to grow a 5nm Ta2O5 layer as a passivation encapsulation layer.

[0071] The fifth step is to perform low-temperature annealing (150°C) on the packaged and passivated device.

[0072] Example 5 Thin-film transistor fabrication Prepare a P-type silicon wafer approximately 500μm thick. The process is as follows: Figure 2 As shown.

[0073] The first step is to grow an 18nm Ta2O5 gate dielectric layer on a P-type silicon substrate using ALD growth.

[0074] The second step involves covering and fixing a metal mask onto a silicon oxide wafer, or using a photolithography lift-off process, and placing it into the sample stage of a magnetron deposition apparatus. An approximately 15nm SnO:Te thin film is deposited using a 25W RF power supply for sputtering. The target used is a Te-doped (5at%) Sn target with a purity of 99.99%.

[0075] The third step involves covering and fixing an electrode mask onto the SnO:Te thin film, or using a photolithography lift-off process, placing it in a deposition apparatus, and using a thermal evaporation process to deposit a layer of Ag metal as the source and drain electrodes.

[0076] The fourth step involves placing the device with deposited metal electrodes into an ALD to grow a 5nm Ta2O5 layer as a passivation encapsulation layer.

[0077] The fifth step is to perform low-temperature annealing (150°C) on the packaged and passivated device.

[0078] Example 6 Inverter fabrication Prepare a P-type silicon wafer approximately 500μm thick. The process is as follows: Figure 7 As shown.

[0079] The first step is to grow an 18nm HfO2 gate dielectric layer on a P-type silicon substrate using ALD growth.

[0080] The second step involves covering and fixing a metal mask onto a silicon oxide wafer, or using a photolithography lift-off process, and placing it into the sample stage of a magnetron deposition apparatus. An approximately 15nm InSnZnO thin film is deposited using a 45W RF power sputtering system with an InSnZnO (In:Sn:Zn = 1.1:0.1:1at%) target with a purity of 99.99%.

[0081] The third step involves covering and fixing a metal mask onto a silicon oxide wafer, or using a photolithography lift-off process, and placing it into the sample stage of a magnetron deposition apparatus. An approximately 15nm SnO:Te thin film is then deposited using a 25-35W RF power supply for sputtering. The target used is a Te-doped (1-10 at%) metal Sn target with a purity of 99.99%.

[0082] The fourth step involves depositing InSnZnO and SnO:Te thin films onto a silicon wafer, covering and fixing an electrode mask, or using a photolithography lift-off process, placing it in a deposition equipment, and using a thermal evaporation process to deposit a layer of Ag metal as the source and drain electrodes.

[0083] The fifth step involves placing the device with deposited metal electrodes into an ALD to grow a 5-15 nm HfO2 layer as a passivation encapsulation layer.

[0084] The sixth step is to perform low-temperature annealing (150-250℃) on the packaged and passivated device.

[0085] The inverter prepared in Example 6 has good noise margin characteristics, with a high-level noise margin (NM) of 100%. H The power supply voltage is 0.48V. DD Its low-level noise margin is 0.33V. DD The inverter has an average peak static power consumption of 10.28 pW. Figure 8 This is significantly lower than the 43.5 nW value of Si-based 3D inverters by more than 1000 times. Furthermore, the dynamic response characteristics of the inverter at different frequencies are as follows: Figure 8 As shown. The complementary inverter operates normally in the range of 1 to 200 Hz, V OUT With V IN The switching is completely synchronized with no noticeable delay, demonstrating the stable dynamic performance of the inverter. At 500Hz, V OUT Still able to follow V IN The inversion of logic results in slight oscillations at the edges, which is due to the parasitic capacitance of the device at high frequencies. The fact that the inverter still functions normally at this frequency indicates that its bandwidth can cover low-to-medium frequency applications (such as display drivers and low-speed logic circuits). Therefore, this inverter circuit structure has broad application prospects in digital and analog electronic circuits, such as display driver circuits, flexible electronic circuits, and low-power nodes for the Internet of Things.

[0086] Example 7 Inverter fabrication Prepare a P-type silicon wafer approximately 500μm thick. The process is as follows: Figure 7 As shown.

[0087] The first step is to grow a 22 nm HfO2 gate dielectric layer on a P-type silicon substrate using ALD growth.

[0088] The second step involves covering and fixing a metal mask onto a silicon oxide wafer, or using a photolithography lift-off process, and placing it into the sample stage of a magnetron deposition apparatus. An approximately 30nm InSnZnO thin film is deposited using a 55W RF power sputtering system with an InSnZnO (In:Sn:Zn = 1.1:0.1:1at%) target with a purity of 99.99%.

[0089] The third step involves covering and fixing a metal mask onto a silicon oxide wafer, or using a photolithography lift-off process, and placing it into the sample stage of a magnetron deposition apparatus. An approximately 30nm SnO:Te thin film is deposited using a 35W RF power supply for sputtering. The target used is a Te-doped (1-10 at%) metal Sn target with a purity of 99.99%.

[0090] The fourth step involves depositing InSnZnO and SnO:Te thin films onto a silicon wafer, covering and fixing an electrode mask, or using a photolithography lift-off process, placing it in a deposition equipment, and using a thermal evaporation process to deposit a layer of Ag metal as the source and drain electrodes.

[0091] The fifth step involves placing the device with deposited metal electrodes into an ALD to grow a 5-15 nm HfO2 layer as a passivation encapsulation layer.

[0092] The sixth step is to perform low-temperature annealing (150-250℃) on the packaged and passivated device.

Claims

1. A p-type tin oxide thin film, characterized in that: It is obtained by magnetron sputtering, encapsulation and annealing of Sn target material with Te content of 1-10 at% 2. The p-type tin oxide thin film as described in claim 1, characterized in that: The substrate used for magnetron sputtering includes a P-type silicon wafer; The magnetron sputtering process uses an radio frequency power supply.

3. The p-type tin oxide thin film as described in claim 1, characterized in that: The thickness of the substrate is 500-800 μm; The power of the radio frequency power supply is 25-35W; The thickness of the P-type tin oxide thin film is 15-30 nm; The purity of the Sn target material with a Te content of 1-10 at% is 99.99%.

4. A thin-film transistor, characterized in that: Including the P-type tin oxide thin film as described in claim 1.

5. The method for fabricating a thin-film transistor as described in claim 4, characterized in that: Includes the following steps: A gate dielectric layer is grown on the substrate using the ALD growth method. P-type tin oxide thin films are deposited on the surface of the gate dielectric layer using magnetron sputtering; Source and drain electrodes are deposited onto the surface of a P-type tin oxide thin film by vapor deposition; Finally, the gate dielectric layer, P-type tin oxide film, and source / drain electrodes were passivated, encapsulated, and annealed using ALD growth.

6. The method for fabricating a thin-film transistor as described in claim 4, characterized in that: The gate dielectric layer is HfO2, Al2O3, SiO2, ZrO2, or Ta2O5; The annealing temperature is 150-250℃; The source and drain electrodes are one of Pd, Au, Ag, Ni or Al.

7. An inverter, characterized in that: Including the P-type tin oxide thin-film transistor as described in claim 1.

8. The method for preparing an inverter as described in claim 7, characterized in that: Includes the following steps: A gate dielectric layer is grown on the substrate using the ALD growth method. InSnZnO thin films and P-type tin oxide thin films were deposited on the surface of the gate dielectric layer by magnetron sputtering; Source and drain electrodes are deposited onto the surfaces of n-type InSnZnO thin films and p-type tin oxide thin films by vapor deposition; Finally, the gate dielectric layer, n-type InSnZnO thin film, p-type tin oxide thin film and source / drain electrodes were passivated, encapsulated and annealed using ALD growth method.

9. The method for fabricating the inverter circuit as described in claim 8, characterized in that: The magnetron sputtering process uses an radio frequency power supply. The power of the radio frequency power supply is 45-55W.

10. The method for fabricating the inverter circuit as described in claim 8, characterized in that: The InSnZnO thin film has a thickness of 15-30 nm; The InSnZnO thin film has an In:Sn:Zn ratio of 1-1.2:0.1:1-1.2at%.

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