Semiconductor device and forming method thereof

Abstract

Semiconductor structures and methods of manufacturing the structures are disclosed. The method comprises: forming a superlattice structure having a nanostructure layer and a sacrificial nanostructure layer on a base structure on a substrate; forming a polycrystalline silicon structure on the superlattice structure; and forming an S / D region in the superlattice structure. An S / D portion of the S / D region extends over the nanostructure layer. The method further includes modifying a thickness of the S / D portion; depositing a dielectric layer on the modified S / D portion; and replacing the polysilicon structure and the sacrificial nanostructure layer with a gate structure. The embodiment of the invention also relates to a semiconductor device and a forming method thereof.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor devices and methods of forming the same. Background Technology

[0002] As semiconductor technology advances, the demand for higher storage capacity, faster processing systems, higher performance, and lower costs continues to grow. To meet these demands, the semiconductor industry continues to shrink the size of semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), including planar MOSFETs, fin field-effect transistors (finFETs), and all-gate-around field-effect transistors (GAAFETs). This shrinkage increases the complexity of semiconductor manufacturing processes. Summary of the Invention

[0003] Some embodiments of this application provide a method for forming a semiconductor device, comprising: forming a superlattice structure having a nanostructure layer and a sacrificial nanostructure layer on a substrate structure on a substrate; forming a polycrystalline silicon structure on the superlattice structure; forming a source / drain region in the superlattice structure, wherein the source / drain portion of the source / drain region extends over the nanostructure layer; modifying the thickness of the source / drain portion; depositing a dielectric layer on the modified source / drain portion; and replacing the polycrystalline silicon structure and the sacrificial nanostructure layer with a gate structure.

[0004] Other embodiments of this application provide a method for forming a semiconductor device, comprising: forming a stack of a nanostructure layer and a sacrificial nanostructure layer on a substrate structure on a substrate; forming a polysilicon structure surrounding the stack of the nanostructure layer and the sacrificial nanostructure layer; epitaxially growing a source / drain region adjacent to the nanostructure layer; modifying the cross-sectional profile of the source / drain portion of the source / drain region extending above the nanostructure layer; and replacing the polysilicon structure and the sacrificial nanostructure layer with a gate structure.

[0005] Some embodiments of this application provide a semiconductor device, including: a substrate; a nanostructured channel region disposed on the substrate; a source / drain region disposed adjacent to the nanostructured channel region, wherein a source / drain portion of the source / drain region extends over the nanostructured channel region, and wherein the top surface of the source / drain portion includes a W-shaped or concave cross-sectional profile; a first dielectric layer disposed on the sidewall of the source / drain region; and a second dielectric layer disposed on the top surface of the source / drain portion and the first dielectric layer, wherein the materials of the first dielectric layer and the second dielectric layer are different from each other. Attached Figure Description

[0006] Various aspects of embodiments of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings.

[0007] Figure 1A An isometric view of a semiconductor device according to some embodiments is shown.

[0008] Figures 1B to 1H Different cross-sectional views of a semiconductor device according to some embodiments are shown.

[0009] Figure 2 This is a flowchart of a method for manufacturing a semiconductor device according to some embodiments.

[0010] Figures 3A to 14A , Figures 3B to 14B and Figures 3C to 14C Isometric views and cross-sectional views of a semiconductor device at various stages of its manufacturing process, according to some embodiments, are shown.

[0011] Figure 15 and Figure 16 Cross-sectional views of another semiconductor device at various stages of its manufacturing process, according to some embodiments, are shown.

[0012] Illustrative embodiments will now be described with reference to the accompanying drawings. In the drawings, the same reference numerals generally indicate identical, functionally similar, and / or structurally similar elements. Detailed Implementation

[0013] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, a process for forming a first component over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. As used herein, forming a first component over a second component means that the first and second components are in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of embodiments of this disclosure. This repetition itself does not indicate a relationship between the various embodiments and / or configurations discussed.

[0014] For ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0015] It should be noted that references to "an embodiment," "embodiment," "exemplary embodiment," "exemplary," etc., in the specification indicate that the described embodiment may include specific components, structures, or features, but each embodiment may not necessarily include specific components, structures, or features. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific component, structure, or feature is described in connection with an embodiment, implementing such a component, structure, or feature in conjunction with other embodiments, whether explicitly described or not, is within the knowledge of those skilled in the art.

[0016] It should be understood that the wording or terminology used herein is for descriptive purposes and not for limiting purposes, and that the terminology or terminology used herein shall be interpreted by those skilled in the art based on the teachings herein.

[0017] In some embodiments, the terms “about” and “substantially” may indicate a value of a given quantity that varies within 5-20% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%, ±10%, ±10-15%, ±15-20% of the value). These values ​​are merely examples and are not intended to be limiting. The terms “about” and “substantially” may refer to a percentage of the value as interpreted by one of skill in the art in accordance with the teachings herein.

[0018] GAA transistor structures can be patterned using any suitable method. For example, the structure can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Dual-patterning or multi-patterning processes can combine photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, smaller pitches than that achievable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed and patterned using a photolithography process over a substrate. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA transistor structure.

[0019] A GAA FET may include a first finned substrate structure and a second finned substrate structure disposed on a substrate, a first stack and a second stack disposed on the first finned substrate structure and the second finned substrate structure, respectively, a source / drain (S / D) region disposed between the first stack and the second stack in the nanostructured channel region, and a first gate structure and a second gate structure surrounding the nanostructured channel region in the first stack and the second stack, respectively. The S / D region is epitaxially formed along the sidewalls of the nanostructured channel region facing the S / D region. To ensure sufficient sidewall coverage of the nanostructured channel region, the S / D region extends above the top surface of the topmost nanostructured channel region. Therefore, the extended portion of the S / D region overlaps with the adjacent gate structure along the vertical cross-sectional plane, which increases the challenge of minimizing the parasitic capacitance between the S / D region and the gate structure.

[0020] To address the aforementioned challenges, embodiments of this disclosure provide exemplary GAA FETs with reduced parasitic capacitance between the gate structure and the S / D region, and exemplary methods for manufacturing these GAA FETs. In some embodiments, forming the S / D region may subsequently be an etching process on the S / D region to reduce the thickness of the extended S / D portion without affecting the sidewall coverage of the S / D region to the nanostructure channel region. In some embodiments, to ensure sufficient sidewall coverage of the nanostructure channel region by the S / D region, the etching process may be controlled to achieve a W-shaped or concave cross-sectional profile (also referred to as an “etch profile”) along a vertical cross-sectional plane (e.g., the XZ and YZ planes) for the S / D top surface. In some embodiments, for a W-shaped or concave cross-sectional profile of the S / D top surface extending between adjacent nanostructure channel regions, the edge of the S / D top surface may rise above the top surface of the topmost nanostructure channel region, and the middle portion of the S / D top surface may have a convex or concave profile. In some embodiments, during the etching process, the thickness of the extended S / D portion may be reduced from a first thickness of about 4 nm to about 12 nm to a second thickness of about 2 nm to about 8 nm. This reduction in the thickness of the extended S / D portion can reduce the parasitic capacitance between the S / D region and the gate structure by about 2% to about 3%. In some embodiments, reducing the thickness of the extended S / D portion can also facilitate the formation of a gate structure with a shorter height, which facilitates the miniaturization of GAA FETs to meet the growing demand for small and portable semiconductor devices.

[0021] In some embodiments, the etching process may subsequently form an etch control layer (e.g., a silicon nitride (SiN) layer; also known as a "hard mask layer") on the top surface of the S / D region and on the top surface of the etch stop layer and interlayer dielectric layer disposed on the S / D region. The etch control layer can maintain the integrity of the edge profile of the S / D top surface during subsequent processes on the S / D region. In some embodiments, the etch control layer can also facilitate the formation of deep contact openings in the S / D region while preventing the etch stop layer and interlayer dielectric layer from being over-etched during the formation of the contact openings. Thus, the contact structure on the S / D region can be formed with a larger contact area with the S / D region, and the portion of the contact structure on the etch stop layer and interlayer dielectric layer can have a shallower depth than if formed without a barrier layer on the S / D region. In some embodiments, due to this shallow depth of the contact structure, the parasitic capacitance between the S / D region and the portion of the contact structure on the etch stop layer and interlayer dielectric layer can be reduced by about 1% to about 4%. Therefore, the total parasitic capacitance of the GAA FET can be reduced by about 3% to about 7%.

[0022] Figure 1A An isometric view of a semiconductor device 100 according to some embodiments is shown. The semiconductor device 100 may represent a GAA FET 100. Figure 1B , Figure 1E and Figure 1H A GAA FET 100 according to some embodiments is shown. Figure 1A Different cross-sectional views of line AA, where for simplicity, Figure 1A Additional structures are not shown. Figure 1C and Figure 1F A GAA FET 100 according to some embodiments is shown. Figure 1A Different cross-sectional views of line BB, where for simplicity, Figure 1A and Figure 1B Additional structures are not shown. Figure 1D and Figure 1G A GAA FET 100 according to some embodiments is shown. Figure 1A Different cross-sectional views of line CC, where for simplicity, Figure 1A Additional structures are not shown. Figures 1A to 1H Discussions of elements with the same annotations apply to each other unless otherwise stated.

[0023] refer to Figures 1A to 1H In some embodiments, the GAA FET 100 may include: (i) a substrate 102 ( Figure 1A As shown; for simplicity, Figures 1B to 1H (i) STI region 104 disposed on substrate 102 (not shown); (ii) STI region 104 disposed on substrate 102 (in Figure 1B , Figure 1Eand Figure 1H (iii) A finned substrate structure 106 disposed on substrate 102 (also referred to as "sheet substrate 106" or "fin substrate 106"); (iv) A stack of nanostructured channel regions 108A-108C disposed on each of the finned substrate structures 106A-106D (not visible in the cross-sectional view); Figure 1C , Figure 1D , Figure 1F and Figure 1G (v) Gate structure 110 surrounding the nanostructure channel region 108A-108C (also known as "GAA structure 110"); Figure 1C , Figure 1D , Figure 1F and Figure 1G (not visible in the cross-sectional view); (vi) external gate spacer 112 (in Figure 1C , Figure 1D , Figure 1F and Figure 1G (not visible in the cross-sectional view); (vii) internal gate spacer 114 (in Figure 1C , Figure 1D , Figure 1F and Figure 1G (not visible in the cross-sectional view); (viii) S / D region 116; (ix) Intermediate layer 118; (x) Etch stop layers (ESL) 120A and 120B (ESL 120A in Figure 1B , Figure 1E and Figure 1H (Not visible in the cross-sectional view); (xi) Interlayer dielectric (ILD) layers 122A and 122B (ILD layer 122A is in...) Figure 1B , Figure 1E and Figure 1H (not visible in the cross-sectional view); (xii) etched control layer 124 (also known as "hard mask layer 124"); (xiii) device isolation structure 126 (also known as "cut metal gate (CMG) structure 126"); in Figure 1B , Figure 1E and Figure 1H (not visible in the cross-sectional view); (xiv) contact structure 128; and (xv) dielectric layer 130. Each of the S / D regions 116 may refer to a source or drain, individually or collectively, depending on the context.

[0024] In some embodiments, substrate 102 may be a semiconductor material, such as silicon (Si), germanium (Ge), silicon-germanium (SiGe), silicon-on-insulator (SOI) structures, and combinations thereof. Furthermore, substrate 102 may be doped with a p-type dopant (e.g., boron, indium, aluminum, or gallium) or an n-type dopant (e.g., phosphorus or arsenic). In some embodiments, STI region 104 may include an insulating material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiOCN), and silicon germanium oxide (SiGeO). x In some embodiments, the fin-shaped substrate structure 106 may comprise a material similar to the substrate 102. The fin-shaped substrate structure 106 may have elongated sides extending along the X-axis.

[0025] In some embodiments, the nanostructured channel regions 108A-108C may be in the form of nanosheets, nanowires, nanorods, nanotubes, or other suitable nanostructure shapes. As used herein, the term "nanostructure" defines a structure, layer, and / or region having a horizontal dimension (e.g., along the X-axis and / or Y-axis) and / or a vertical dimension (e.g., along the Z-axis) of less than about 100 nm, such as about 90 nm, about 50 nm, about 10 nm, or other values ​​less than about 100 nm. The nanostructured channel regions 108A-108C may comprise semiconductor materials similar to or different from substrate 102. In some embodiments, the nanostructured channel regions 108A-108C may comprise Si, silicon arsenide (SiAs), silicon phosphide (SiP), silicon carbide (SiC), silicon phosphide carbon (SiCP), silicon germanium (SiGe), silicon germanium boron (SiGeB), germanium boron (GeB), silicon germanium tin boron (SiGeSnB), group III-V semiconductor compounds, or other suitable semiconductor materials. In some embodiments, each of the nanostructured channel regions 108A-108C may have a thickness of about 3 nm to about 15 nm along the Z-axis. Although three nanostructured channel regions 108A-108C are shown in each stack, the GAA FET 100 may have any number of nanostructured channel regions. Although a rectangular cross-section of the nanostructured channel regions 108A-108C is shown, the nanostructured channel regions 108A-108C may have cross-sections of other geometries (e.g., circular, elliptical, triangular, or polygonal).

[0026] Each gate structure 110 may be a multilayer structure and may surround nanostructured channel regions 108A-108C. For the nanostructured channel regions 108A-108C, the gate structure 110 may be referred to as a "GAA structure". Each gate structure 110 may include: (i) an interface oxide (IL) layer 110A; (ii) a high-k (HK) gate dielectric layer 110B; and (iii) a conductive layer 110C. In some embodiments, the IL layer 110A may be directly disposed on the topmost nanostructured channel region 108A. In some embodiments, the IL layer 110A may include SiO2, SiGeO, etc. x or germanium oxide (GeO) x The HK gate oxide layer 110B can have a thickness of about 0.5 nm to about 2 nm. In some embodiments, the HK gate dielectric layer 110B can be directly disposed on the IL layer 110A and can have a thickness of about 1 nm to about 3 nm. In some embodiments, the HK gate oxide layer 110B can include a high-k dielectric material, such as hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), and zirconium silicate (ZrSiO2). In some embodiments, the sidewalls of the IL layer 110A and the HK gate oxide layer 110B can contact the sidewalls of the outer gate spacer 112 and the inner gate spacer 114.

[0027] In some embodiments, the conductive layer 110C may be disposed on the HK gate dielectric layer 110B and may be a multilayer structure. For simplicity, the different layers of the conductive layer 110C are not shown. In some embodiments, the conductive layer 110C may include a work function metal (WFM) layer disposed on the HK gate dielectric layer 110B and a gate metal fill layer disposed on the WFM layer. In some embodiments, the WFM layer may include a substantially Al-free (e.g., Al-free) Ti-based or Ta-based nitride or alloy, such as titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium gold (Ti-Au) alloy, titanium copper (Ti-Cu) alloy, tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum gold (Ta-Au) alloy, and tantalum copper (Ta-Cu). In some embodiments, the WFM layer may include titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), Al-doped Ti, Al-doped TiN, Al-doped Ta, Al-doped TaN, or other suitable Al-based materials. In some embodiments, the gate metal filling layer may include suitable conductive materials such as tungsten (W), titanium (Ti), silver (Ag), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), Al, iridium (Ir), nickel (Ni), metal alloys, and combinations thereof.

[0028] The external gate spacer 112 electrically isolates the gate structure 110 from the adjacent S / D region 116 and contact structure 128. The internal gate spacer 114 electrically isolates the gate portion between the nanostructured channel regions 108A-108C from the adjacent S / D region 116. In some embodiments, each of the internal gate spacers 114 may have a thickness T1 of about 4 nm to about 6 nm. Within this thickness range, the internal gate spacers 114 can sufficiently electrically isolate the gate portion from the adjacent S / D region 116 without affecting device size and manufacturing cost. In some embodiments, the external gate spacer 112 and the internal gate spacer 114 may include dielectric materials such as SiO2, SiN, SiON, SiCN, and SiOCN.

[0029] In some embodiments, the S / D region 116 may include epitaxially grown semiconductor material (such as Si) and n-type dopant (such as phosphorus and other suitable n-type dopant for n-type GAA FET 100). The S / D region 116 may also include epitaxially grown semiconductor material (such as Si and SiGe) and p-type dopant (such as boron and other suitable p-type dopant for p-type GAA FET 100).

[0030] In some embodiments, the S / D region 116 is epitaxially formed along the sidewalls of the nanostructure channel regions 108A-108C, such as... Figure 1A , Figure 1B , Figure 1E and Figure 1HAs shown in the diagram. To ensure sufficient sidewall coverage of the topmost nanostructure channel region 108A for adequate conductivity between them, the S / D region 116 extends above the top surface of the topmost nanostructure channel region 108A. Therefore, the extended S / D portion 116a overlaps with the adjacent conductive layer 110C of the gate structure 110 along a vertical cross-sectional plane (e.g., the XZ plane), which may result in parasitic capacitance between the gate structure 110 and the S / D region 116. To prevent or minimize this parasitic capacitance between the gate structure 110 and the S / D region 116, the thickness T2 of the extended S / D portion 116a can be from about 2 nm to about 8 nm. In some embodiments, if the thickness T2 is less than about 2 nm, the sidewalls of the topmost nanostructure channel region 108A may not be adequately covered by the S / D region 116, thus reducing the performance of the GAA FET 100. On the other hand, if the thickness T2 is greater than about 8 nm, the overlap between the gate structure 110 and the S / D region 116 increases, and thus the parasitic capacitance between the gate structure 110 and the S / D region 116 increases by about 2% to about 3% or more. Furthermore, if the thickness T2 is greater than about 8 nm, forming a gate structure 110 with a shorter height for shrinking the GAA FET 100 to meet the growing demand for small and portable semiconductor devices becomes challenging. By making the thickness T2 of the extended S / D portion 116a in the range of about 2 nm to about 8 nm, the height of the gate structure 110 can be reduced from about 12 nm to about 16 nm to about 8 nm to about 12 nm, while simultaneously reducing the parasitic capacitance between the gate structure 110 and the S / D region 116 by about 2% to about 3% or more.

[0031] In some embodiments, to further ensure sufficient sidewall coverage of the topmost nanostructure channel region 108A by the S / D region 116, the S / D top surface 116t of the S / D region 116 may be formed with a W-shaped cross-sectional profile (also referred to as an "etch profile") along a vertical cross-sectional plane (e.g., the XZ and YZ planes), such as... Figures 1A to 1D and Figure 1H As shown in the figure. In some embodiments, instead of a W-shaped cross-sectional profile, the S / D top surface 116t can be formed to have a concave cross-sectional profile along the vertical cross-sectional plane (e.g., the XZ and YZ planes), as shown in the figure. Figures 1E to 1G As shown in the figure. For the W-shaped or concave cross-sectional profile of the S / D top surface 116t along the XZ plane, the edge of the S / D top surface 116t can rise above the top surface of the topmost nanostructure channel region 108A, and the middle portion of the S / D top surface 116t can have a convex or concave profile.

[0032] In some embodiments, the interposer 118 may be disposed beneath the S / D region 116 and in a recessed region of the fin substrate structure 106. In some embodiments, the interposer 118 may prevent dopant from diffusing from the S / D region 116 to the fin substrate structure 106, thereby preventing current leakage between adjacent S / D regions 116 and short-channel effects in the GAA FET 100. In some embodiments, the interposer 118 may be a multilayer comprising an undoped semiconductor layer 118A and a dielectric layer 118B. In some embodiments, the interposer 118 may be an undoped semiconductor layer or a dielectric layer. The undoped semiconductor layer may be an undoped silicon or silicon-germanium layer.

[0033] In some embodiments, an undoped semiconductor layer 118A may be disposed in a recessed region of the fin substrate structure 106. In some embodiments, the undoped semiconductor layer 110A may comprise undoped silicon or other suitable undoped semiconductor material. In some embodiments, the undoped semiconductor layer 118A may extend to a distance of about 20 nm to about 40 nm in the fin substrate structure 106. In some embodiments, if the distance is less than about 20 nm, the undoped semiconductor layer 111A may not be able to adequately prevent dopant from diffusing from the S / D region 116 to the fin substrate structure 106. On the other hand, if the distance is greater than about 40 nm, the processing time (e.g., etching time, deposition time) for forming the undoped semiconductor layer 118A increases, and thus increases the manufacturing cost of the GAA FET 100.

[0034] In some embodiments, dielectric layer 118B may be directly disposed on undoped semiconductor layer 118A and disposed along the sidewall of the bottommost inner spacer 114. In some embodiments, each dielectric layer 118B may include a nitride material, such as SiN, SiO2, SiON, SiCON, SiOC, and SiCN. In some embodiments, each dielectric layer 118B may include a silicon-rich dielectric material. In some embodiments, the silicon-rich dielectric material may include: (i) a silicon-rich nitride (Si) having a silicon atom concentration higher than the nitrogen atom concentration. x N y (ii) Silicon-rich nitrides (SiO2) with a silicon atom concentration higher than that of oxygen and nitrogen atoms. x O y N z (iii) Silicon-rich carbon oxides (SiO2) with a silicon atom concentration higher than that of oxygen and carbon atoms. x O y C z (iv) Silicon-rich carbon nitrides (SiO2) with a silicon atom concentration higher than that of oxygen, carbon, and nitrogen atoms. w O x Cy N z (v) Silicon-rich boron oxynitride (SiO2) with a silicon atom concentration higher than that of oxygen, boron, and nitrogen atoms. w B x O y N z ); silicon-rich boron carbide (SiO2) with a silicon atom concentration higher than that of oxygen, boron, and carbon atoms. w B x O y C z (vii) other suitable silicon-rich nitride-based or carbide-based dielectric materials. During the formation of dielectric layer 118B, the silicon-rich dielectric material of dielectric layer 118B can provide high etch resistance to dielectric layer 118B. In some embodiments, each dielectric layer 118B may have a thickness T3 of about 2 nm to about 8 nm. Within this range of thickness, dielectric layer 118B can sufficiently prevent dopant from diffusing from S / D region 116 to semiconductor layer 111A without affecting the device size and manufacturing cost of GAA FET 100.

[0035] In some embodiments, (i) ESL 120A may be directly disposed on S / D region 116 and STI region 104, (ii) ILD layer 122A may be directly disposed on ESL 120A, (iii) ESL 120B may be directly disposed on etch control layer 124, gate structure 110, external gate spacer 112, and dielectric layer 130, and may surround contact structure 128, and (iv) ILD layer 122B may be directly disposed on ESL 120B and dielectric layer 130, and may surround contact structure 128. In some embodiments, ESL 120A and 120B may have a thickness of about 3 nm to about 6 nm. In some embodiments, ILD layer 122B may have a thickness T5 of about 10 nm to about 20 nm. In some embodiments, ESL 120A and 120B and ILD layers 122A and 122B may include dielectric materials such as SiO2, SiN, SiON, SiCN, SiOC, and SiOCN.

[0036] In some embodiments, the etch control layer 124 may be directly disposed on: (i) the S / D top surface 116t; (ii) the top surface of the ESL 120A; and (iii) the top surface of the ILD layer 122A. The etch control layer can be used to control the contact opening 1038 in the S / D region 116 (see below). Figures 10A to 10CThe etching profile is described below. Furthermore, the etching control layer 124 can be used to prevent the dielectric layer 130 from forming around portions of the contact structure 128 in the S / D region 116. The presence of the dielectric layer 130 around portions of the contact structure 128 in the S / D region can create an undesirable barrier to electronic conduction between the contact structure 128 and the topmost nanostructure channel region 108A. Therefore, by using the etching control layer 124, the conductivity between the contact structure 128 and the topmost nanostructure channel region 108A can be improved. Furthermore, the etching control layer 124 can be used to control the height of portions of the contact structure 128 formed on the ESL 120A and ILD layer 122A between adjacent S / D regions 116, as described in detail below. By controlling these heights, the parasitic capacitance between these portions of the contact structure 128 and the S / D region 116 can be controlled. In some embodiments, when using the etch control layer 124, the portions of the contact structure 128 located on the ESL 120A and ILD layer 122A can be formed with a height H2 of about 15 nm to about 65 nm to reduce the parasitic capacitance between these portions of the contact structure 128 and the S / D region 116 by about 1% to about 4%. In some embodiments, the etch control layer 124 can have a thickness T4 of about 4 nm to about 14 nm. Within this range of thickness T4, the etch control layer 124 can sufficiently (i) control the etch profile of the contact opening 1038, (ii) prevent the dielectric layer 130 from forming in the S / D region 116, and (iii) control the height of the contact structure 128 formed on the ESL 120A and ILD layer 122A without affecting the device size and manufacturing cost of the GAA FET 100. In some embodiments, the etch control layer 124 can include a dielectric material different from the dielectric materials of the ESL 120A and 120B. In some embodiments, the etch control layer 124 can include a SiN layer.

[0037] In some embodiments, in addition to the gate spacer 112, ESL 120A, and ILD layer 122A, the gate structure 110 can be electrically isolated from each other by a device isolation structure 126 to provide independently controlled gate structures. The device isolation structure 126 can be formed in a diced metal gate (CMG) process to cut long gate structures (e.g., along the Y-axis) into shorter gate structures, such as gate structure 110. In some embodiments, each device isolation structure 126 may include an oxide-filled layer 126A and a nitride pad 126B surrounding the oxide-filled layer 126A. In some embodiments, the oxide-filled layer 126A may include SiO2 or a SiO2-based material (e.g., silicon oxycarbide), and the nitride pad 126B may include a SiN material. In some embodiments, each device isolation structure 126 may include a width W1 of about 21 nm to about 33 nm and a height H3 of about 110 nm to about 160 nm. Within these ranges of width W1 and height H3, the device isolation structure 126 can adequately provide electrical isolation between the gate structures 110 without affecting the device size and manufacturing cost of the GAA FET 100.

[0038] In some embodiments, the contact structure 128 may be disposed on one or more S / D regions 116 of the GAA FET 100, such as... Figure 1A , Figure 1B , Figure 1C , Figure 1E , Figure 1F and Figure 1H As shown in the diagram. Some S / D regions 116 may not have contact structures 128 disposed on them, such as... Figure 1D and Figure 1G As shown in the figure. In some embodiments, a first contact portion 128t (also referred to as "top contact portion 128t") of the contact structure 128 may extend above the S / D top surface 116t, and a second contact portion 128b (also referred to as "bottom contact portion 128b") of the contact structure 128 may extend below the S / D top surface 116t. In some embodiments, the top contact portion 128t may be surrounded by a dielectric layer 130, and the bottom contact portion 128b may be surrounded by the S / D region 116. In some embodiments, along the XZ plane, each bottom contact portion 128b may have a height H4 of about 1 nm to about 45 nm and a width W2 of about 10 nm to about 16 nm. Within these ranges of height H4 and width W2, a large contact area can be formed between the contact structure 128 and the S / D region 116 without affecting the device size and manufacturing cost of the GAA FET 100. In some embodiments, the bottom contact portions 128b of different contact structures 128 may have the same height H4 and width W2, such as Figure 1B and Figure 1EAs shown in the figure. In some embodiments, the bottom contact portions 128b of the different contact structures 128 may have different heights and widths from each other, such as... Figure 1H As shown in the diagram. For example, the bottom contact portion 128b of one of the contact structures 128 may have a height H4 and a width W2, and the bottom contact portion 128b of the other of the contact structures 128 may have a height H5 and a width W3, as shown in the diagram. Figure 1H As shown in the figure. In some embodiments, the height H5 can be greater than the height H4, and the width W3 can be greater than the width W2.

[0039] In some embodiments, each contact structure 128 may include: (i) a silicide layer 128A disposed in the S / D region 116; and (ii) a conductive layer 128B disposed on the silicide layer 128A. In some embodiments, each silicide layer 128A may have: (i) a thickness T6 of about 2 nm to about 6 nm; and (ii) a U-shaped cross-sectional profile along the XZ plane. Figure 1B , Figure 1E and Figure 1H (as shown); and (iii) the W-shaped cross-sectional profile along the YZ plane (as shown in the diagram); Figure 1C (as shown) or a concave cross-sectional profile along the YZ plane (as shown) Figure 1F As shown in the diagram). In some embodiments, the silicide layer 128A in the n-type GAA FET 100 may include titanium silicide (Ti). x Si y ), tantalum silicide (Ta x Si y ), molybdenum silicide (Mo x Si y Zirconium silicide (Zr) x Si y ), Hafnium silicide (Hf) x Si y Scandium silicide (Sc) x Si y ), yttrium silicide (Y x Si y ), terbium silicide (Tb x Si y ), Lutetium silicide (Lu x Si y ), Erbium silicide (Er x Si y ), Ytterbium silicide (Yb x Si y Europium silicide (Eu) x Si y ), Thorium silicide (Th) x Si yOther suitable metal silicide materials or combinations thereof. In some embodiments, the silicide layer 128A in the p-type GAA FET 100 may include nickel silicide (Ni). x Si y ), cobalt silicide (Co) x Si y ), manganese silicide (Mn) x Si y ), Tungsten silicide (W) x Si y ), iron silicide (Fe) x Si y ), Rhodium silicide (Rh x Si y ), Palladium silicide (Pd) x Si y ), Ruthenium silicide (Ru) x Si y Platinum silicide (Pt) x Si y ), Iridium silicide (Ir) x Si y ), Osmium silicide (Os) x Si y Other suitable metal silicide materials or combinations thereof. In some embodiments, conductive layer 128B may include conductive materials such as Co, W, Ru, Al, Mo, Ir, Ni, osmium (Os), rhodium (Rh), other suitable conductive materials, and combinations thereof.

[0040] In some embodiments, dielectric layer 130 may be disposed on the S / D top surface 116t and surrounding the top contact portion 128t. Dielectric layer 130 may prevent or minimize: (i) the diffusion of oxygen atoms from ILD layer 122B to conductive layer 128B; and (ii) the diffusion of metal atoms from conductive layer 128B to gate structure 110. In some embodiments, dielectric layer 130 may include an oxygen-free dielectric nitride layer (e.g., a SiN layer), an oxygen-free dielectric carbide layer (e.g., a silicon carbide (SiC) layer), or an oxygen-free carbonitride layer (e.g., a silicon carbonitride (SiCN) layer). In some embodiments, dielectric layer 130 may have a thickness T7 of about 1 nm to about 3 nm to sufficiently prevent or minimize: (i) the diffusion of oxygen atoms from ILD layer 122B to conductive layer 128B; and (ii) the diffusion of metal atoms from conductive layer 128B to gate structure 110.

[0041] Figure 2 It is according to some embodiments for manufacturing as referenced above. Figures 1A to 1H A flowchart illustrating an exemplary method 200 for manufacturing a GAA FET 100 is provided. For illustrative purposes, reference will be made to methods for manufacturing such... Figures 3A to 14A , Figures 3B to 14B , Figures 3C to 14C , Figure 15 and Figure 16 The exemplary manufacturing process of the GAA FET 100 shown is described below. Figure 2 The operation shown is illustrated. Figures 3A to 14A These are isometric views of the GAA FET 100 at various manufacturing stages according to some embodiments. Figures 3B to 14B , Figure 15 and Figure 16 According to some embodiments, the GAA FET 100 is manufactured at various stages. Figure 1A A cross-sectional view of line AA. Figures 3C to 14C According to some embodiments, the GAA FET 100 is manufactured at various stages. Figure 1A A cross-sectional view of line BB. Operations may be performed in different orders or not at all, depending on the specific application. It should be noted that method 200 may not produce a complete GAA FET 100. Therefore, it should be understood that additional processes may be provided before, during, and after method 200, and some other processes may only be briefly described herein. Figures 1A to 1H , Figures 3A to 14A , Figures 3B to 14B , Figures 3C to 14C , Figure 15 and Figure 16 Discussions of elements with the same annotations apply to each other unless otherwise stated.

[0042] refer to Figure 2 In operation 205, a superlattice structure is formed on the finned substrate structure, and a polycrystalline silicon structure and an external gate spacer are formed on the superlattice structure. For example, as referenced... Figures 3A to 3C As described, a superlattice structure 309 (also referred to as "nanosheet stack 309") is formed on a fin-shaped substrate structure 106, and a polycrystalline silicon structure 310 is formed on the superlattice structure 309. The superlattice structure 309 and the polycrystalline silicon structure 310 are... Figure 3C Not visible in the cross-sectional view. In some embodiments, hard mask layers 332 and 334 may be formed during the formation of the polysilicon structure 310. The superlattice structure 309 may include nanostructure layers 108A-108C and sacrificial nanostructure layer 308 arranged in an alternating configuration. In some embodiments, nanostructure layers 108A-108C may include Si, and sacrificial nanostructure layer 308 may include SiGe. In some embodiments, each of nanostructure layers 108A-108C and sacrificial nanostructure layer 308 may have a thickness of about 3 nm to about 15 nm along the Z-axis. During subsequent processing, the polysilicon structure 310 and sacrificial nanostructure layer 308 may be replaced with gate structure 110 in a gate replacement process.

[0043] refer to Figure 2 In operation 210, internal gate spacers and S / D regions are formed in the superlattice structure. For example, as referenced... Figures 3A to 3C As described, an internal gate spacer 114 and an S / D region 116 are formed in the superlattice structure 309. The internal gate spacer 114 is... Figure 3C Not visible in the cross-sectional view. In some embodiments, S / D openings (not shown) may be formed in the superlattice structure 309, which may subsequently be used to form isolation trenches (not shown) in the finned substrate structure 106. Forming the isolation trenches may subsequently be used to form internal gate spacers 114 along the sidewalls of the sacrificial nanostructure layer 308, as... Figure 3A and Figure 3B As shown in the diagram. Forming the internal gate spacer 114 may subsequently involve forming an interposer 118 in an isolation trench, which may then involve epitaxially growing an S / D region 116 in the S / D opening. In some embodiments, the S / D region 116 may extend over the superlattice structure 309, and the extended S / D portion 116a may be formed with a thickness T8 of about 4 nm to about 12 nm, as shown in the diagram. Figure 3B As shown in the diagram. The S / D region 116 can then be followed by the formation of an ESL 120A and an ILD layer 122A on the S / D region 116, as... Figures 4A to 4C As shown in the image.

[0044] refer to Figure 2 In operation 215, the portion of the S / D region extending above the superlattice structure is modified. For example, as referenced... Figures 5A to 7A , Figures 5B to 7B and Figures 5C to 7C As described, the extended S / D portions 116a can be modified to reduce their thickness from thickness T8 to thickness T2. In some embodiments, the modification of the extended S / D portions 116a may include the following sequential operations: (i) to Figures 4A to 4C The structure undergoes a first etching process to remove a portion of the ILD layer 122A and expose the portion of ESL120A located on the extended S / D portion 116a, as shown. Figures 5A to 5C As shown; (ii) to Figures 5A to 5C The structure undergoes a second etching process to remove the exposed portion of ESL 120A and expose the extended S / D portion 116a, as shown. Figures 6A to 6C As shown; and (iii) to Figures 6A to 6C The structure undergoes a third etching process to etch the extended S / D portions 116a and reduce their thickness from thickness T8 to thickness T2, as follows. Figures 7A to 7CAs shown in the figure. In some embodiments, the third etching process may include a dry etching process using etching gases (such as carbon tetrafluoride (CF4) and nitrogen trifluoride (NF3)) and mixed gases (such as hydrogen (H2) and argon (Ar)). In some embodiments, the third etching process may include a wet etching process using a mixture of ammonium hydroxide (NH4OH) with H2O2 and deionized (DI) water. In some embodiments, depending on the etching parameters of the third etching process, the S / D top surface 116t of the extended S / D portion 116a may be formed with a W-shaped cross-sectional profile, as shown in the figure. Figures 7A to 7C As shown, it can also be formed with a concave cross-sectional profile, such as Figures 1E to 1G As shown in the image.

[0045] refer to Figure 2 In operation 220, an etch control layer is formed on the modified portion of the S / D region. For example, as referenced... Figures 8A to 8C As described, an etch control layer 124 is formed on the modified extended S / D portion 116a. Forming the etch control layer 124 may include the following sequential operations: (i) on Figures 7A to 7C (i) depositing a dielectric nitride layer (e.g., a SiN layer, not shown) on the structure; and (ii) performing a chemical mechanical polishing (CMP) process on the dielectric nitride layer to form Figures 8A to 8C The structure. In some embodiments, after the CMP process, the top surfaces of the etch control layer 124, the external gate spacer 112, and the polysilicon structure 310 may be substantially coplanar with each other.

[0046] refer to Figure 2 In operation 225, the polycrystalline silicon structure of the superlattice structure and the sacrificial nanostructure layer are replaced with a gate structure. For example, as referenced... Figures 9A to 9C As described, the polysilicon structure 310 and the sacrificial nanostructure layer 308 are used with the gate structure 110 (in... Figure 9C (Not visible in the cross-sectional view) Replacement. Forming the gate structure 110 may include: from Figure 8A and Figure 8B The polysilicon structure 310 and the sacrificial nanostructure layer 308 are removed to form a gate opening (not shown); and a gate structure 110 is formed in the gate opening, as shown in the figure. Figure 9A and Figure 9B As shown in the diagram. In some embodiments, the top surfaces of the etch control layer 124, the external gate spacer 112, and the gate structure 110 may be substantially coplanar with each other. In some embodiments, forming the gate structure 110 may subsequently form a device isolation structure 126, as shown in the diagram. Figure 9A and Figure 9C As shown (device isolation structure 126 in) Figure 9B (Not visible in the cross-sectional view). Forming the device isolation structure 126 can subsequently be in... Figures 9A to 9CAn ESL 120B, an ILD layer 122B, and a hard mask layer 1036 are deposited on the structure. In some embodiments, the hard mask layer 1036 may include a tungsten carbide (WC) layer.

[0047] refer to Figure 2 In operation 230, a contact structure is formed on the S / D region. For example, as shown in the reference... Figures 10A to 14A , Figures 10B to 14B and Figures 10C to 14C As described, a contact structure 128 is formed on the S / D region 116. Forming the contact structure 128 may include the following sequential operations: (i) performing a first etching process to remove portions of the hard mask layer 1036, ILD layer 122B, ESL 120B, and etch control layer 124 located on the S / D region 116 to form a contact opening 1038 on the S / D region 116, such as Figures 10A to 10C As shown; (ii) removing the hard mask layer 1036 (not shown); (iii) depositing a dielectric nitride layer 1040 on the top surface of the ILD layer 122B and on the exposed surfaces of the ILD layer 122B, ESL 120B, etch control layer 124, ILD layer 122A, ESL 120A and S / D region 116 in the contact opening 1038, as shown. Figures 11A to 11C As shown; (iv) to Figures 11A to 11C The structure undergoes a second etching process to form a dielectric layer 130, and the contact opening 1038 is extended to a depth D1 in the S / D region 116, as shown. Figures 12A to 12C As shown; (v) a third etching process is performed on the exposed S / D region 116 in the contact opening 1038 to increase the depth of the contact opening 1038 from depth D1 to depth D2, as shown. Figures 13A to 13C As shown; (vi) a silicide layer 128A is formed in the contact opening 1038, as... Figures 14A to 14C As shown; and (vii) a conductive layer 128B is formed on the silicide layer 128A, as shown. Figures 14A to 14C As shown in the figure. In some embodiments, after the conductive layer 128B is formed, the top surfaces of the conductive layer 128B, the ILD layer 122B, and the dielectric layer 130 may be substantially coplanar with each other.

[0048] In some embodiments, the second etching process may include a dry etching process using an etching gas (such as fluoromethane (CH3F), hexafluorocyclobutene (C4F6), and carbonyl sulfide (COS)) and a mixed gas (such as H2 and nitrogen (N2)), which may subsequently be a post-cleaning process using deionized (DI) water. In some embodiments, the third etching process may include a dry etching process using an etching gas (such as CF4) and a mixed gas (such as Ar), which may subsequently be a post-cleaning process using a hydrofluoric acid (HF) solution.

[0049] In some embodiments, having Figure 1H The cross-sectional view of the GAA FET 100 can be formed using method 200, except in operation 230: (i) the third etching process can subsequently be a fourth etching process on one or more S / D regions 116 to increase the depth of one or more contact openings 1038 from depth D2 to depth D3, as... Figure 15 As shown; and (ii) can be shown Figure 15 A silicide layer 128A and a conductive layer 128B are formed in the contact opening 1038 to form Figure 16 The structure. In some embodiments, the fourth etching process may include a dry etching process using an etching gas (such as CF4) and a mixed gas (such as Ar), which may subsequently be a post-cleaning process using an HF solution.

[0050] This disclosure provides exemplary GAA FETs (e.g., GAA FET 100) with reduced parasitic capacitance between the gate structure and the S / D region, as well as exemplary methods of manufacturing these GAA FETs. In some embodiments, forming the S / D region (e.g., S / D region 116) may subsequently be an etching process on the S / D region to reduce the thickness of the extended S / D portion (e.g., extended S / D portion 116a) without affecting the sidewall coverage of the S / D region over the nanostructured channel region (nanostructured channel regions 108A-108C). In some embodiments, to ensure sufficient sidewall coverage of the nanostructured channel region by the S / D region, the etching process may be controlled to achieve a W-shaped or concave cross-sectional profile along a vertical cross-sectional plane (e.g., the XZ and YZ planes) for the S / D top surface (e.g., S / D top surface 116t). In some embodiments, for a W-shaped or concave cross-sectional profile of the S / D top surface extending between adjacent nanostructure channel regions, the edge of the S / D top surface may rise above the top surface of the topmost nanostructure channel region (e.g., the topmost nanostructure channel region 108A), and the middle portion of the S / D top surface may have a convex or concave profile. In some embodiments, during the etching process, the thickness of the extended S / D portion may be reduced from a first thickness of about 4 nm to about 12 nm (e.g., thickness T8) to a second thickness of about 2 nm to about 8 nm (e.g., thickness T2). This reduction in the thickness of the extended S / D portion can reduce the parasitic capacitance between the S / D region and the gate structure by about 2% to about 3%. In some embodiments, reducing the thickness of the extended S / D portion may also facilitate the formation of a gate structure with a shorter height (e.g., height H1), which facilitates the miniaturization of GAA FETs to meet the growing demand for small and portable semiconductor devices.

[0051] In some embodiments, the etching process may subsequently form an etch control layer (e.g., etch control layer 124) on the top surface of the S / D region and on the top surface of the ESL (e.g., ESL 120A) and ILD layer (e.g., ILD layer 122A) disposed on the S / D region. The etch control layer may maintain the integrity of the edge profile of the S / D top surface during subsequent processes on the S / D region. In some embodiments, the etch control layer may also facilitate the formation of deep contact openings (e.g., contact opening 1038) in the S / D region while preventing the ESL and ILD layers from being over-etched during the formation of the contact openings. Thus, the contact structure (e.g., contact structure 128) on the S / D region may be formed with a contact area larger than that of the S / D region, and the portion of the contact structure on the ESL and ILD layers may have a shallower depth than if formed without a barrier layer on the S / D region. In some embodiments, due to this shallow depth of the contact structure, the parasitic capacitance between the S / D region and the portion of the contact structure on the ESL and ILD layers may be reduced from about 1% to about 4%. Therefore, the total parasitic capacitance of the GAA FET can be reduced by approximately 3% to approximately 7%.

[0052] In some embodiments, the method includes: forming a superlattice structure having a nanostructure layer and a sacrificial nanostructure layer on a substrate structure on a substrate; forming a polycrystalline silicon structure on the superlattice structure; and forming a S / D region in the superlattice structure. The S / D portion of the S / D region extends over the nanostructure layer. The method further includes: modifying the thickness of the S / D portion; depositing a dielectric layer on the modified S / D portion; and replacing the polycrystalline silicon structure and the sacrificial nanostructure layer with a gate structure.

[0053] In some embodiments, the method includes: forming a stack of a nanostructure layer and a sacrificial nanostructure layer on a substrate structure on a substrate; forming a polysilicon structure surrounding the stack of the nanostructure layer and the sacrificial nanostructure layer; epitaxially growing an S / D region adjacent to the nanostructure layer; modifying the cross-sectional profile of the S / D portion of the S / D region extending above the nanostructure layer; and replacing the polysilicon structure and the sacrificial nanostructure layer with a gate structure.

[0054] In some embodiments, the semiconductor device includes: a substrate; a nanostructured channel region disposed on the substrate; and an S / D region disposed adjacent to the nanostructured channel region. An S / D portion of the S / D region extends over the nanostructured layer, and the top surface of the S / D portion includes a W-shaped or concave cross-sectional profile. The semiconductor device further includes: a first dielectric layer disposed on the sidewalls of the S / D region; and a second dielectric layer disposed on the top surface of the S / D portion and the first dielectric layer. The first dielectric layer and the second dielectric layer are made of different materials.

[0055] Some embodiments of this application provide a method for forming a semiconductor device, comprising: forming a superlattice structure having a nanostructure layer and a sacrificial nanostructure layer on a substrate structure on a substrate; forming a polycrystalline silicon structure on the superlattice structure; forming a source / drain region in the superlattice structure, wherein the source / drain portion of the source / drain region extends over the nanostructure layer; modifying the thickness of the source / drain portion; depositing a dielectric layer on the modified source / drain portion; and replacing the polycrystalline silicon structure and the sacrificial nanostructure layer with a gate structure.

[0056] In some embodiments, modifying the thickness of the source / drain portion includes performing an etching process on the source / drain portion. In some embodiments, modifying the thickness of the source / drain portion includes reducing the thickness of the source / drain portion. In some embodiments, the method further includes depositing an etch stop layer on the source / drain region before modifying the thickness of the source / drain portion. In some embodiments, modifying the thickness of the source / drain portion includes etching the etch stop layer to expose the source / drain portion. In some embodiments, depositing the dielectric layer includes depositing a silicon nitride layer on the modified source / drain portion. In some embodiments, modifying the thickness of the source / drain portion includes modifying the cross-sectional profile of the top surface of the source / drain portion. In some embodiments, the method further includes forming a silicide layer in the source / drain region, wherein the silicide layer includes: a W-shaped cross-sectional profile along a first cross-sectional plane; and a U-shaped cross-sectional profile along a second cross-sectional plane. In some embodiments, the method further includes: performing a first etching process on the source / drain to form a contact opening in the source / drain region; and performing a second etching process on the source / drain to increase the depth of the contact opening in the source / drain region. In some embodiments, the method further includes: forming a silicide layer in the contact opening after the second etching process; and depositing a conductive layer on the silicide layer.

[0057] Other embodiments of this application provide a method for forming a semiconductor device, comprising: forming a stack of a nanostructure layer and a sacrificial nanostructure layer on a substrate structure on a substrate; forming a polysilicon structure surrounding the stack of the nanostructure layer and the sacrificial nanostructure layer; epitaxially growing a source / drain region adjacent to the nanostructure layer; modifying the cross-sectional profile of the source / drain portion of the source / drain region extending above the nanostructure layer; and replacing the polysilicon structure and the sacrificial nanostructure layer with a gate structure.

[0058] In some embodiments, modifying the cross-sectional profile of the source / drain portion includes changing the top surface of the source / drain portion from a convex cross-sectional profile to a W-shaped or concave cross-sectional profile. In some embodiments, modifying the cross-sectional profile of the source / drain portion includes performing an etching process on the source / drain portion. In some embodiments, the method further includes: forming a contact opening having a first opening in the source / drain region and a second opening in the source / drain region; forming a silicide layer in the second opening; and depositing a conductive layer in the first opening and the second opening. In some embodiments, the method further includes: forming a dielectric layer along the sidewall of the first opening before forming the silicide layer. In some embodiments, the method further includes: depositing a nitride layer on the modified cross-sectional profile of the source / drain portion before replacing the polysilicon structure and the sacrificial nanostructure layer.

[0059] Some embodiments of this application provide a semiconductor device, including: a substrate; a nanostructured channel region disposed on the substrate; a source / drain region disposed adjacent to the nanostructured channel region, wherein a source / drain portion of the source / drain region extends over the nanostructured channel region, and wherein the top surface of the source / drain portion includes a W-shaped or concave cross-sectional profile; a first dielectric layer disposed on the sidewall of the source / drain region; and a second dielectric layer disposed on the top surface of the source / drain portion and the first dielectric layer, wherein the materials of the first dielectric layer and the second dielectric layer are different from each other.

[0060] In some embodiments, the semiconductor device further includes a silicide layer disposed in the source / drain region, wherein the silicide layer includes a W-shaped cross-sectional profile along a first cross-sectional plane and a U-shaped cross-sectional profile along a second cross-sectional plane. In some embodiments, the semiconductor device further includes a contact structure including a first contact portion disposed in the source / drain region and a second contact portion disposed in the source / drain region; and a third dielectric layer surrounding the second contact portion. In some embodiments, the semiconductor device further includes an etch stop layer surrounding the third dielectric layer.

[0061] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a base to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and modifications can be made to them herein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A method for forming a semiconductor device, comprising: A superlattice structure with nanostructured layers and sacrificial nanostructured layers is formed on a substrate structure on a substrate. A polycrystalline silicon structure is formed on the superlattice structure; Source / drain regions are formed in the superlattice structure, wherein the source / drain portions of the source / drain regions extend over the nanostructure layer; Modify the thickness of the source / drain portions; Deposit a dielectric layer on the modified source / drain portions; and Replace the polysilicon structure and the sacrificial nanostructure layer with a gate structure.

2. The method according to claim 1, wherein, Modifying the thickness of the source / drain portion includes performing an etching process on the source / drain portion.

3. The method according to claim 1, wherein, Modifying the thickness of the source / drain portion includes reducing the thickness of the source / drain portion.

4. The method of claim 1, further comprising depositing an etch stop layer on the source / drain region before modifying the thickness of the source / drain portion.

5. The method according to claim 4, wherein, Modifying the thickness of the source / drain portion includes etching the etch stop layer to expose the source / drain portion.

6. The method according to claim 1, wherein, Depositing the dielectric layer includes depositing a silicon nitride layer on the modified source / drain portions.

7. The method according to claim 1, wherein, Modifying the thickness of the source / drain portion includes modifying the cross-sectional profile of the top surface of the source / drain portion.

8. The method of claim 1, further comprising forming a silicide layer in the source / drain region, wherein, The silicide layer includes: The W-shaped cross-sectional profile along the plane of the first cross-section; and The U-shaped cross-sectional profile along the second cross-sectional plane.

9. A method for forming a semiconductor device, comprising: A stack of nanostructured layers and sacrificial nanostructured layers is formed on a substrate structure on a substrate. A polycrystalline silicon structure is formed around the stack of the nanostructure layer and the sacrificial nanostructure layer; Epitaxial growth of source / drain regions adjacent to the nanostructure layer; Modify the cross-sectional profile of the source / drain portion of the source / drain region extending above the nanostructure layer; as well as Replace the polysilicon structure and the sacrificial nanostructure layer with a gate structure.

10. A semiconductor device, comprising: Substrate; A nanostructured channel region is disposed on the substrate; A source / drain region is disposed adjacent to the nanostructured channel region, wherein the source / drain portion of the source / drain region extends above the nanostructured channel region, and wherein the top surface of the source / drain portion includes a W-shaped or concave cross-sectional profile. A first dielectric layer is disposed on the sidewall of the source / drain region; and A second dielectric layer is disposed on the top surface of the source / drain portion and the first dielectric layer, wherein the materials of the first dielectric layer and the second dielectric layer are different from each other.

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