Semiconductor structure and forming method thereof

Abstract

Semiconductor structures and methods of forming the same are provided. The semiconductor structure includes a plurality of first nanostructures formed over the substrate in a first direction and a plurality of second nanostructures formed adjacent to the first nanostructures. The semiconductor structure includes a first gate structure formed on the first nanostructure in the second direction, and the first gate structure includes a first gate dielectric layer. The semiconductor structure includes a second gate structure formed on the second nanostructure. The semiconductor structure includes a dielectric wall structure between the first gate structure and the second gate structure in the first direction. The dielectric wall structure has a top portion and a bottom portion, and the bottom portion is wider than the top portion.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor structures and methods of forming the same. Background Technology

[0002] The electronics industry is experiencing a growing demand for smaller and faster electronic devices capable of implementing a greater number of increasingly complex and sophisticated functions. Consequently, there is a persistent trend in the semiconductor industry towards manufacturing low-cost, high-performance, and low-power integrated circuits (ICs). To date, these goals have been largely achieved by shrinking the size of semiconductor ICs (e.g., the smallest component size), thereby improving production efficiency and reducing associated costs. However, this miniaturization introduces greater complexity into semiconductor manufacturing processes. Therefore, continued advancements in semiconductor ICs and devices require similar advancements in semiconductor manufacturing processes and technologies.

[0003] Recently, multi-gate devices have been introduced in an attempt to improve gate control by increasing gate-channel coupling, reducing off-state current, and minimizing short-channel effect (SCE). However, the integration of multi-gate devices in fabrication can be challenging. Summary of the Invention

[0004] Some embodiments of this application provide a semiconductor structure including: a plurality of first nanostructures formed above a substrate along a first direction; a plurality of second nanostructures formed adjacent to the first nanostructures; a first gate structure formed on the first nanostructures along a second direction, wherein the first gate structure includes a first gate dielectric layer; a second gate structure formed on the second nanostructures; and a dielectric wall structure located between the first gate structure and the second gate structure along the first direction, wherein the dielectric wall structure has a top portion and a bottom portion, and the bottom portion is wider than the top portion.

[0005] Other embodiments of this application provide a semiconductor structure including: a plurality of first nanostructures formed above a substrate; a plurality of second nanostructures formed adjacent to the first nanostructures; a first gate structure formed on the first nanostructures; a second gate structure formed on the second nanostructures; and a dielectric wall structure located between the first gate structure and the second gate structure, wherein the dielectric wall structure has a top portion and a bottom portion, a first distance is located between the sidewall surface of the top portion and the sidewall surface of the topmost first nanostructure, a second distance is located between the sidewall surface of the bottom portion and the sidewall surface of the topmost first nanostructure, and the first distance is greater than the second distance.

[0006] Some embodiments of this application provide a method for forming a semiconductor structure, comprising: forming a first fin structure and a second fin structure over a substrate, wherein the first fin structure includes alternating stacked first semiconductor material layers and second semiconductor material layers, and the second fin structure includes alternating stacked first semiconductor material layers and second semiconductor material layers; forming a first dummy gate structure over the first fin structure and the second fin structure, wherein the first dummy gate structure includes a first dummy gate dielectric layer and a first dummy gate electrode layer; replacing the first semiconductor material layer with a dummy dielectric layer such that the dummy dielectric layer and the second semiconductor material layer are alternately stacked; removing a portion of the first dummy gate electrode layer to form an opening; forming a pad layer in the opening; forming a dielectric wall material in the opening; removing another portion of the first dummy gate electrode layer; removing a portion of the pad layer; removing a portion of the first dummy gate dielectric layer and a portion of the dielectric wall material to form a dielectric wall structure, wherein the remaining portion of the pad layer and the remaining portion of the first dummy gate dielectric layer are located directly below the dielectric wall structure; removing the dummy dielectric layer to form a gap; and forming a first gate structure in the gap. Attached Figure Description

[0007] Various aspects of the embodiments of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figures 1A to 1F A perspective view of an intermediate stage in the fabrication of a semiconductor structure according to some embodiments is shown.

[0009] Figure 2 A top view representation of a semiconductor structure according to some embodiments is shown.

[0010] Figures 3A-1 to 3N-1 Manufacturing process according to some embodiments is shown. Figure 1F neutralization Figure 2 The line A-A' in the figure represents the cross-sectional representation of various stages of the semiconductor structure.

[0011] Figures 3A-2 to 3N-2 Manufacturing process according to some embodiments is shown. Figure 1F neutralization Figure 2 The line B-B' in the figure represents the cross-sectional representation of various stages of the semiconductor structure.

[0012] Figures 3A-3 to 3N-3 Manufacturing process according to some embodiments is shown. Figure 1F neutralization Figure 2 The line C-C' in the figure represents the cross-sectional representation of various stages of the semiconductor structure.

[0013] Figure 4 A top view representation of a semiconductor structure after the opening is formed, according to some embodiments, is shown.

[0014] Figure 5 A top view representation of a semiconductor structure after the formation of a first gate structure and a second gate structure, according to some embodiments, is shown.

[0015] Figure 6A A top view representation of a semiconductor structure after the formation of a dielectric wall structure is shown according to some embodiments.

[0016] Figure 6B The following are shown according to some embodiments. Figure 6A The cross-sectional representation of the semiconductor structure is shown by line D-D' in the figure.

[0017] Figure 7A A top view representation of a semiconductor structure after the formation of a dielectric wall structure is shown according to some embodiments.

[0018] Figure 7B The following are shown according to some embodiments. Figure 7A The lines B-B' and E-E' in the figure show a cross-sectional representation of the semiconductor structure.

[0019] Figure 8 A cross-sectional representation of a semiconductor structure according to some embodiments is shown.

[0020] Figure 9 A cross-sectional representation of a semiconductor structure according to some embodiments is shown. Detailed Implementation

[0021] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0022] Some variations of the embodiments are described. Throughout the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. It should be understood that additional operations may be provided before, during, and after the method, and that some of the described operations may be replaced or eliminated for other embodiments of the method.

[0023] The gate-all-around (GAA) transistor structure described below can be patterned using any suitable method. For example, the structure can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, smaller pitches than that achievable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0024] The fins described below can be patterned using any suitable method. For example, the fins can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with a pitch, for example, smaller than that achievable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins.

[0025] Embodiments of semiconductor structures and methods for forming the same are provided. The semiconductor structure may include a first nanostructure and a second nanostructure along a first direction (e.g., the x-axis). A first gate structure is formed over the first nanostructure, and a second gate structure is formed over the second nanostructure. A dielectric wall structure is located between the first and second gate structures. A first S / D structure is adjacent to the first gate structure, and a second S / D structure is adjacent to the second gate structure. The dielectric wall structure extends from the gate region to the S / D region. The dielectric wall structure has an inverted T-shaped structure, so that the gate contact structure is formed on the first gate structure and does not contact the dielectric wall structure, thus providing more contact windows. Furthermore, the first gate structure fills the gap between the dielectric wall structure and the nanostructure to further reduce capacitance. Therefore, the performance of the semiconductor structure is improved. The source / drain (S / D) structure or region may refer to the source or drain, individually or collectively, depending on the context.

[0026] Figures 1A to 1F A perspective view of an intermediate stage in the fabrication of a semiconductor structure 100a according to some embodiments is shown. Figure 1A As shown, a first semiconductor material layer 106 and a second semiconductor material layer 108 are formed above a substrate 102.

[0027] Substrate 102 may be a semiconductor wafer, such as a silicon wafer. Optionally or additionally, substrate 102 may include elemental semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. Elemental semiconductor materials may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP.

[0028] In some embodiments, a first semiconductor material layer 106 and a second semiconductor material layer 108 are alternately stacked over a substrate 102. In some embodiments, the first semiconductor material layer 106 and the second semiconductor material layer 108 are made of different semiconductor materials. In some embodiments, the first semiconductor material layer 106 is made of SiGe, and the second semiconductor material layer 108 is made of silicon. It should be noted that although three first semiconductor material layers 106 and three second semiconductor material layers 108 are formed, the semiconductor structure may include more or fewer first semiconductor material layers 106 and second semiconductor material layers 108. For example, the semiconductor structure may include two to five of the first semiconductor material layers 106 and second semiconductor material layers 108.

[0029] The first semiconductor material layer 106 and the second semiconductor material layer 108 can be formed using low-pressure chemical vapor deposition (LPCVD), epitaxial growth processes, another suitable method, or a combination thereof. In some embodiments, the epitaxial growth process includes molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), or vapor phase epitaxy (VPE).

[0030] After that, as Figure 1B As shown, according to some embodiments, after the first semiconductor material layer 106 and the second semiconductor material layer 108 are formed as a semiconductor material stack above the substrate 102, the semiconductor material stack is patterned to form a first fin structure 104a and a second fin structure 104b. In some embodiments, each of the first fin structure 104a and the second fin structure 104b includes a base fin structure 105 and a semiconductor material stack of the first semiconductor material layer 106 and the second semiconductor material layer 108.

[0031] In some embodiments, the patterning process includes: forming a mask structure 110 over a semiconductor material stack; and etching the semiconductor material stack and the underlying substrate 102 through the mask structure 110. In some embodiments, the mask structure 110 is a multilayer structure including a pad oxide layer 112 and a nitride layer 114 formed over the pad oxide layer 112. The pad oxide layer 112 may be made of silicon oxide and formed by thermal oxidation or chemical vapor deposition (CVD), and the nitride layer 114 may be made of silicon nitride and formed by chemical vapor deposition (CVD), such as low-temperature chemical vapor deposition (LPCVD) or plasma-enhanced CVD (PECVD).

[0032] Next step, such as Figure 1C As shown, according to some embodiments, after the first fin structure 104a and the second fin structure 104b are formed, an isolation structure 116 is formed around the first fin structure 104a and the second fin structure 104b, and the mask structure 110 is removed.

[0033] According to some embodiments, the isolation structure 116 is configured as an active region of an electrically isolated semiconductor structure 100a (e.g., a first fin structure 104a and a second fin structure 104b), and is also referred to as a shallow trench isolation (STI) component.

[0034] The isolation structure 116 can be formed by depositing an insulating layer over the substrate 102 and recessing the insulating layer such that the first fin structure 104a and the second fin structure 104b protrude from the isolation structure 116. In some embodiments, the isolation structure 116 is made of silicon oxide, silicon nitride, silicon oxynitride (SiON), another suitable insulating material, or a combination thereof. In some embodiments, a dielectric pad (not shown) is formed prior to the formation of the isolation structure 116, and the dielectric pad is made of silicon nitride, and the isolation structure formed over the dielectric pad is made of silicon oxide.

[0035] After that, as Figure 1D As shown, according to some embodiments, a mask layer 117 is formed on the isolation structure 116. When trenches are formed from the back side of the substrate 102, the mask layer 117 serves as an etch stop layer. In addition, the mask layer 117 serves as a protective layer to protect the isolation structure 116.

[0036] In some embodiments, the mask layer 117 is composed of silicon nitride (SiN) and silicon oxide (SiO). x Silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), silicon carbonitride (SiCO), silicon carbide (SiC), and high-k dielectric materials (HfO or AlO) xIt may be made of a chemical vapor deposition (CVD), ALD, other application methods, or a combination thereof. In some embodiments, the mask layer 117 is formed by chemical vapor deposition (CVD), ALD, other application methods, or combinations thereof.

[0037] After that, as Figure 1E As shown, according to some embodiments, after the mask layer 117 is formed, a first dummy gate structure 118a and a second dummy gate structure 118b are formed across the first fin structure 104a and the second fin structure 104b, extending over the isolation structure 116. The first dummy gate structure 118a and the second dummy gate structure 118b can be used to define the source / drain (S / D) region and the channel region of the resulting semiconductor structure 100a.

[0038] In some embodiments, each of the first dummy gate structure 118a and each of the second dummy gate structure 118b includes a dummy gate dielectric layer 120 and a dummy gate electrode layer 122. In some embodiments, the dummy gate dielectric layer 120 is made of one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride (SiON), HfO2, HfZrO, HfSiO, HfTiO, HfAlO, or combinations thereof. In some embodiments, the dummy gate dielectric layer 120 is formed using thermal oxidation, chemical vapor deposition (CVD), atomic vapor deposition (ALD), physical vapor deposition (PVD), another suitable method, or combinations thereof.

[0039] In some embodiments, the conductive material includes polycrystalline silicon (poly-Si), polycrystalline silicon germanium (poly-SiGe), metal nitrides, metal silicides, metals, or combinations thereof. In some embodiments, the dummy gate electrode layer 122 is formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), or combinations thereof.

[0040] In some embodiments, a hard mask layer 124 is formed over the dummy gate structure 118. In some embodiments, the hard mask layer 124 comprises multiple layers, such as an oxide layer and a nitride layer. In some embodiments, the oxide layer is silicon oxide and the nitride layer is silicon nitride.

[0041] The formation of the dummy gate structure 118 may include conformally forming a dielectric material as a dummy gate dielectric layer 120. Subsequently, a conductive material may be formed over the dielectric material as a dummy gate electrode layer 122, and a hard mask layer 124 may be formed over the conductive material. Next, the dielectric and conductive materials may be patterned using the hard mask layer 124 to form the dummy gate structure 118.

[0042] Next step, such as Figure 1FAs shown, according to some embodiments, after forming the dummy gate structure 118, a gate spacer layer 126 covering the opposite sidewalls of the dummy gate structure 118 is formed along the opposite sidewalls of the dummy gate structure 118, and a fin spacer layer 128 covering the opposite sidewalls of the source / drain regions of the fin structure 104 is formed along the opposite sidewalls of the source / drain regions of the fin structure 104.

[0043] The gate spacer layer 126 can be configured to separate the source / drain (S / D) structure from the first pseudo-gate structure 118a and the second pseudo-gate structure 118b, and support the first pseudo-gate structure 118a and the second pseudo-gate structure 118b. The fin spacer layer 128 can be configured to restrict the lateral growth of the subsequently formed source / drain structure, and support the first fin structure 104a and the second fin structure 104b.

[0044] In some embodiments, the gate spacer layer 126 and the fin spacer layer 128 are made of dielectric materials such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), and / or combinations thereof. The formation of the gate spacer layer 126 and the fin spacer layer 128 may include: conformally depositing dielectric material covering the first dummy gate structure 118a, the second dummy gate structure 118b, the first fin structure 104a, the second fin structure 104b, and the isolation structure 116 over a substrate 102; and performing an anisotropic etching process, such as dry plasma etching, to remove the dielectric layer on the top surface covering portions of the first dummy gate structure 118a, the second dummy gate structure 118b, the first fin structure 104a, the second fin structure 104b, and the isolation structure 116.

[0045] Figure 2 A top view representation of a semiconductor structure 100a according to some embodiments is shown. Figure 2 As shown, substrate 102 has a first region 11 and a second region 12. The first region 11 is a gate region, and the second region 12 is an S / D region. A first fin structure 104a is formed along a first direction (e.g., the X-axis), and a second fin structure 104b is formed along the first direction (e.g., the X-axis). A first dummy gate structure 118a and a second dummy gate structure 118b are formed along a second direction (e.g., the Y-axis). The second direction (e.g., the Y-axis) is orthogonal to the first direction (e.g., the X-axis). The first dummy gate structure 118a and the second dummy gate structure 118b are located in the first region 11. The first dummy gate structure 118a and the second dummy gate structure 118b are formed across the first fin structure 104a and the second fin structure 104b. An S / D structure (formed later) will be formed in the second region 12 (S / D region).

[0046] Figures 3A-1 to 3N-1 Manufacturing process according to some embodiments is shown. Figure 1F neutralization Figure 2 The cross-sectional representation of each stage of the semiconductor structure 100a shown by line A-A' in the figure. Figures 3A-2 to 3N-2 Manufacturing process according to some embodiments is shown. Figure 1F neutralization Figure 2 The cross-sectional representation of each stage of the semiconductor structure 100a shown by line B-B' in the figure. Figures 3A-3 to 3N-3 Manufacturing process according to some embodiments is shown. Figure 1F neutralization Figure 2 The line C-C' in the figure represents the cross-sectional representation of each stage of the semiconductor structure 100a.

[0047] More specifically, Figure 3A-1 It shows along Figure 1F and Figure 2 The cross section shown by line A-A' in the diagram is represented. Figure 3A-2 The following are shown according to some embodiments. Figure 1F and Figure 2 The cross section shown by line B-B' in the diagram is represented. Figure 3A-3 It shows along Figure 1F neutralization Figure 2 The cross section represented by line C-C' in the figure is shown.

[0048] Next step, such as Figure 3B-1 , Figure 3B-2 and Figure 3B-3 As shown, after forming the gate spacer layer 126 and the fin spacer layer 128, the source / drain (S / D) region of the fin structure 104 is recessed to form a source / drain (S / D) recess 130, as shown in some embodiments. More specifically, according to some embodiments, the first semiconductor material layer 106 and the second semiconductor material layer 108 not covered by the dummy gate structure 118 and the gate spacer layer 126 are removed. Furthermore, according to some embodiments, some portions of the base fin structure 105 are also recessed to form a curved top surface, as shown in some embodiments. Figure 3B-1 As shown in the image.

[0049] In some embodiments, a portion of the first fin structure 104a and a portion of the second fin structure 104b are recessed by performing an etching process. The etching process may be an anisotropic etching process, such as dry plasma etching, and the first dummy gate structure 118a, the second dummy gate structure 118b, and the gate spacer layer 126 are used as an etching mask during the etching process. In some embodiments, the fin spacer layer 128 is also recessed to form a lowered fin spacer layer 128'.

[0050] After that, as Figure 3C-1 , Figure 3C-2 and Figure 3C-3As shown, according to some embodiments, after the S / D groove 130 is formed, the first semiconductor material layer 106 is removed to form the groove 131. The groove 131 is exposed by the S / D groove 130.

[0051] Next step, such as Figure 3D-1 , Figure 3D-2 and Figure 3D-3 As shown, according to some embodiments, a dummy dielectric layer 132 is formed in the recess 131. The dummy dielectric layer 132 is used to replace the first semiconductor material layer 106. Therefore, the second semiconductor material layer 108 and the dummy dielectric layer 132 are stacked alternately. The dummy dielectric layer 132 is also called a disposable interposer, which will be removed in the following steps and replaced with the first gate structure 142a and the second gate structure 142b. Figure 3N-2 and Figure 3N-3 (as shown in the image) Replace.

[0052] The pseudo-dielectric layer 132 is made of silicon oxide (SiO2), silicon oxynitride (SiON), aluminum oxide (Al2O3), or another suitable material. In some embodiments, the pseudo-dielectric layer 132 is formed by ALD (atomic layer deposition), flowable CVD, or another application process. The advantage of the ALD process is that it forms a uniform and conformal film in the narrow groove 131.

[0053] After that, as Figure 3E-1 , Figure 3E-2 and Figure 3E-3 As shown, according to some embodiments, after the pseudo dielectric layer 132 is formed, the pseudo dielectric layer 132 exposed by the S / D groove 130 is laterally recessed to form a groove 133.

[0054] In some embodiments, during the etching process, the second semiconductor material layer 108 has a larger etching rate (or etching amount) than the dummy dielectric layer 132, thereby forming a groove 133 between adjacent dummy dielectric layers 132. In some embodiments, the etching process is isotropic etching, such as dry chemical etching, remote plasma etching, wet chemical etching, another suitable technique, and / or a combination thereof.

[0055] Next step, such as Figure 3F-1 , Figure 3F-2 and Figure 3F-3 As shown, according to some embodiments, an internal spacer 134 is formed in a slot 133 between the second semiconductor material layers 108. According to some embodiments, the internal spacer 134 is configured to separate the source / drain (S / D) structure and the gate structure formed in a subsequent manufacturing process.

[0056] In some embodiments, the internal spacer 134 is made of a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), or combinations thereof. In some embodiments, the internal spacer 134 is formed by a deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), another suitable process, or combinations thereof.

[0057] After that, as Figure 3G-1 , Figure 3G-2 and Figure 3G-3 As shown, according to some embodiments, after the internal spacer 134 is formed, a first source / drain (S / D) structure 136a and a second S / D structure 136b are formed in the S / D groove 130.

[0058] In some embodiments, the first source / drain (S / D) structure 136a and the second S / D structure 136b are formed using epitaxial growth processes, such as molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), vapor phase epitaxy (VPE), other suitable epitaxial growth processes, or combinations thereof. In some embodiments, the first source / drain (S / D) structure 136a and the second S / D structure 136b are made of any suitable material, such as Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, SiC, SiCP, or combinations thereof.

[0059] In some embodiments, the first source / drain (S / D) structure 136a and the second S / D structure 136b are doped in situ during the epitaxial growth process. For example, the first source / drain (S / D) structure 136a and the second S / D structure 136b may be boron (B)-doped epitaxially grown SiGe. For example, the first source / drain (S / D) structure 136a and the second S / D structure 136b may be carbon-doped to form a silicon:carbon (Si:C) source / drain device, phosphorus-doped to form a silicon:phosphorus (Si:P) source / drain device, or carbon and phosphorus-doped to form a silicon-carbon-phosphorus (SiCP) source / drain device. In some embodiments, the first source / drain (S / D) structure 136a and the second S / D structure 136b are doped in one or more implantation processes following the epitaxial growth process.

[0060] After that, as Figure 3H-1 , Figure 3H-2 and Figure 3H-3As shown, according to some embodiments, a conformally formed contact etch stop layer (CESL) 138 is formed to cover the first S / D structure 136a and the second S / D structure 136b, and an interlayer dielectric (ILD) layer 140 is formed over the contact etch stop layer 138.

[0061] In some embodiments, the contact etch stop layer 138 is made of a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, another suitable dielectric material, or a combination thereof. The dielectric material used for the contact etch stop layer 138 can be conformally deposited over the semiconductor structure by performing chemical vapor deposition (CVD), ALD, other application methods, or a combination thereof.

[0062] The ILD layer 140 may comprise a multilayer made of a variety of dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BPSG), and / or other suitable low-k dielectric materials. The ILD layer 140 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes.

[0063] According to some embodiments, after depositing the contact etch stop layer 138 and the ILD layer 140, a planarization process such as CMP or etch-back can be performed until the gate electrode layer 120 of the dummy gate structure 118 is exposed, such as... Figure 3I-3 As shown in the image.

[0064] After that, as Figure 3I-1 , Figure 3I-2 and Figure 3I-3 As shown, according to some embodiments, a portion of the dummy gate electrode layer 122 of the first dummy gate structure 118a is removed to form an opening 21. Therefore, a portion of the dummy gate dielectric layer 120 is exposed by the opening 21. The opening 21 is formed by a photolithography process and an etching process. The photolithography process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, and drying (e.g., hard baking). The etching process includes a dry etching process or a wet etching process.

[0065] A portion of the dummy gate electrode layer 122 of the first dummy gate structure 118a is removed by performing the first etching process 51. Furthermore, a portion of the ILD layer 140 is also removed by the first etching process 51. Therefore, the opening 21 extends from the first region 11 (gate region) to the second region 12 (S / D region).

[0066] In some embodiments, when the dummy gate electrode layer 122 is polysilicon, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution can be used to selectively remove the dummy gate electrode layer 122.

[0067] In some embodiments, the opening 21 has a rectangular structure with a uniform thickness from top to bottom. In some embodiments, the top portion of the opening 21 has a width W1 along a second direction (e.g., the y-axis). Although the ILD layer 140 is removed, the amount of ILD layer 140 removed is less than the amount of dummy gate electrode layer 122 removed. Because the ILD layer 140 has etch selectivity relative to the dummy gate electrode layer 122, the ILD layer 140 is etched less than the dummy gate electrode layer 122. In other words, the ILD layer 140 is difficult to remove relative to the dummy gate electrode layer 122. Therefore, the depth of the opening 21 in the S / D region ( Figure 3I-1 (as shown) is less than the depth of the opening 21 in the gate region ( Figure 3I-2 (as shown in the image).

[0068] The term "selectivity" or "etch selectivity" is defined as the ratio of the etching rate of one material (reference material) to that of another material (material of interest). Increased etch selectivity means that the selected material or material of interest is more difficult to etch. Decreased etch selectivity means that the selected material is easier to etch.

[0069] Next step, such as Figure 3J-1 , Figure 3J-2 and Figure 3J-3 As shown, according to some embodiments, the sidewall portion of the dummy gate electrode layer 122 is further removed to form an opening 23. The opening 23 has a T-shaped structure with a top portion and a bottom portion, and the top portion is wider than the bottom portion. In the S / D region ( Figure 3J-1 As shown), the opening 21 is not enlarged. In the gate region ( Figure 3J-2 As shown in the diagram, opening 23 is wider than opening 21. The top portion of opening 23 has a width W2, and the second width W2 is greater than the first width W1.

[0070] The opening 23 is formed by photolithography and etching processes. The photolithography process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, and drying (e.g., hard baking). The etching process includes dry etching or wet etching.

[0071] The sidewall portion of the dummy gate electrode layer 122 of the first dummy gate structure 118a is removed by performing a second etching process 53. In the second etching process 53, the ILD layer 140 has high etching selectivity relative to the dummy gate electrode layer 122, and the ILD layer 140 is not etched when removing the sidewall portion of the dummy gate electrode layer 122.

[0072] Figure 4 A top view representation of a semiconductor structure 100a after the formation of opening 23 is shown according to some embodiments.

[0073] like Figure 4 As shown, in the first region 11 (gate region), the opening 23 has a second width W2 along the second direction (e.g., the Y-axis). In the second region 12 (S / D region), the opening 21 has a first width W1 along the second direction (e.g., the Y-axis). In some embodiments, the second width W2 is greater than the first width W1.

[0074] Next, as Figure 3K-1 , Figure 3K-2 and Figure 3K-3 shown, according to some embodiments, a liner layer 14 and a dielectric wall material 16 are formed in the opening 21 and the opening 23. Next, a portion of the liner layer 14 and a portion of the dielectric wall material 16 are removed by a polishing process (such as CMP or an etch-back process).

[0075] The liner layer 14 and the dielectric wall material 16 are made of different materials. In some embodiments, the liner layer 14 is made of SiN, SiCN, SiOC, SiOCN, or a suitable material. In some embodiments, the dielectric wall material 16 is made of SiN, SiCN, SiOC, SiOCN, or a suitable material. In some embodiments, the liner layer 14 is made of SiO x1 C y1 N z1 and the dielectric wall material 16 is made of SiO x2 C y2 N z2 where y1 < Y2 and Z1 < Z2. The nitrogen ratio of the dielectric wall material 16 is greater than the nitrogen ratio of the liner layer 14. The dielectric wall material 16 has a high etch selectivity relative to the liner layer 14. When the liner layer 14 is removed, the dielectric wall material 16 is difficult to remove.

[0076] After that, as Figure 3L-1 , Figure 3L-2 and Figure 3L-3 shown, according to some embodiments, the remaining pseudo-gate electrode layer 122 of the first pseudo-gate structure 118a is removed, and then the liner layer 14 and the pseudo-gate dielectric layer 120 are removed. According to some embodiments, the first pseudo-gate structure 118a and the second pseudo-gate structure 118b are removed to form a trench 141.

[0077] The removal process may include one or more etching processes. For example, when the pseudo-gate electrode layer 122 is polysilicon, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution can be used to selectively remove the pseudo-gate electrode layer 122. After that, a plasma dry etching, a dry chemical etching, and / or a wet etching can be used to remove the pseudo-gate dielectric layer 120.

[0078] Furthermore, when the dummy gate dielectric layer 120 is removed, the dummy dielectric layer 132 is also removed to form a nanostructure 108' (or channel layer 108') using the second semiconductor material layer 108. When the dummy gate dielectric layer 120 is removed, the top portion of the dielectric wall material 16 is also removed. Therefore, the top portion of the dielectric wall material 16 is removed to form a dielectric wall structure 18. After the removal process, the dielectric wall structure 18 has an inverted T-shaped structure.

[0079] In some embodiments, such as Figure 3L-2 As shown, the dielectric wall structure 18 has sidewall surfaces, and the sidewall surfaces have a top vertical portion 18V1, a horizontal portion 18h, and a bottom vertical portion 18V2. The horizontal portion 18h is located between the top vertical portion 18V1 and the bottom vertical portion 18V2. In some embodiments, the horizontal portion 18h of the dielectric wall structure 18 is higher than the top surface of the nanostructure 108'. After the removal process, the top surface of the dielectric wall structure 18 has a third width W3. In some embodiments, the third width W3 is smaller than the second width W2. In some embodiments, the third width W3 is smaller than the first width W1. In some other embodiments, the third width W3 is equal to the first width W1. In some embodiments, the third width W3 of the top surface of the dielectric wall structure 18 is smaller than the width of the nanostructure 108'. In some embodiments, the third width W3 of the top surface of the dielectric wall structure 18 is larger than the width of the nanostructure 108'.

[0080] like Figure 3L-1 As shown, the dielectric wall structure 18 has an extension 18e located between the first S / D structure 136a and the second S / D structure 136b. The bottom surface of the extension 18e is higher than the top surface of the first S / D structure 136a and the top surface of the second S / D structure 136b.

[0081] It should be noted that a portion of the pad layer 14 is located directly beneath the dielectric wall structure 18 and is not removed; therefore, the remaining pad layer 14 remains directly beneath the dielectric wall structure 18. Furthermore, the remaining portion of the dummy gate dielectric layer 120, located directly beneath the pad layer 14, is also left. The sidewall surfaces of the remaining pad layer 14 are substantially aligned with the sidewall surfaces of the remaining dummy gate dielectric layer 120.

[0082] like Figure 3L-1 As shown, the top portion of the padding layer 14 and the top portion of the dielectric wall material 16 are slightly removed. This results in the top surface of the padding layer 14 and the top portion of the dielectric wall material 16 being recessed.

[0083] Next step, such as Figure 3M-1 , Figure 3M-2 and Figure 3M-3As shown, according to some embodiments, after forming the nanostructure 108', a first gate structure 142a and a second gate structure 142b are formed to surround the nanostructure 108'.

[0084] An interface layer 144, a gate dielectric layer 146, and a gate electrode layer 148 are formed around the nanostructure 108', and a planarization process such as CMP or etch-back can then be performed until the ILD layer 140 is exposed. Thus, a first gate structure 142a and a second gate structure 142b are formed between the dielectric wall structures 18. In some embodiments, the first gate structure 142a includes the interface layer 144, the gate dielectric layer 146, and the gate electrode layer 148. In some embodiments, the second gate structure 142b includes the interface layer 144, the gate dielectric layer 146, and the gate electrode layer 148.

[0085] The first gate structure 142a and the second gate structure 142b are formed to enclose the nanostructure 108'. According to some embodiments, the first gate structure 142a and the second gate structure 142b enclose the nanostructure 108' to form an all-around gate transistor structure.

[0086] In some embodiments, the interface layer 144 is an oxide layer formed around the nanostructure 108' and on top of the base fin structure 105. In some embodiments, the interface layer 144 is formed by performing a thermal process.

[0087] In some embodiments, a gate dielectric layer 146 is formed over an interface layer 144 such that the nanostructure 108' is surrounded (e.g., wrapped) by the gate dielectric layer 146. Furthermore, according to some embodiments, the gate dielectric layer 146 also covers the sidewalls of the gate spacer 126 and the inner spacer 134. In some embodiments, the gate dielectric layer 146 is made of one or more layers of dielectric material, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloy, another suitable high-k dielectric material, or combinations thereof. In some embodiments, the gate dielectric layer 146 is formed using chemical vapor deposition (CVD), atomic layer deposition (ALD), another suitable method, or combinations thereof.

[0088] In some embodiments, the gate electrode layer 148 is made of one or more layers of conductive material, such as aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, or combinations thereof. In some embodiments, the gate electrode layer 148 is formed using chemical vapor deposition (CVD), atomic layer deposition (ALD), electroplating, other suitable methods, or combinations thereof.

[0089] Other conductive layers, such as work function metal layers, may also be formed in the first gate structure 142a and the second gate structure 142b, but they are not shown in the figures. In some embodiments, the n-work function layer includes tungsten (W), copper (Cu), titanium (Ti), silver (Ag), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), titanium aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr), or combinations thereof. In some embodiments, the p-work function layer includes titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), molybdenum nitride, tungsten nitride (WN), ruthenium (Ru), or combinations thereof.

[0090] After that, as Figure 3N-1 , Figure 3N-2 and Figure 3N-3 As shown, according to some embodiments, an etch stop layer 150 is formed over the first gate structure 142a and the second gate structure 142b, and a dielectric layer 152 is formed over the etch stop layer 150.

[0091] In some embodiments, the etch stop layer 150 is made of a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, another suitable dielectric material, or a combination thereof. The dielectric material used for the etch stop layer 150 can be conformally deposited over the semiconductor structure by performing chemical vapor deposition (CVD), ALD, other application methods, or a combination thereof.

[0092] The dielectric layer 152 may comprise a multilayer made of a variety of dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BPSG), and / or other suitable low-k dielectric materials. The dielectric layer 152 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes.

[0093] Next, according to some embodiments, a silicide layer 154 and an S / D contact structure 156 are formed over the first S / D structure 136a and the second S / D structure 136b, and a gate contact structure 168 is formed over the first gate structure 142a and the second gate structure 142b. The gate contact structure 168 is electrically connected to the first gate structure 142a.

[0094] In some embodiments, contact openings can be formed through the contact etch stop layer 138, the interlayer dielectric layer 140, the etch stop layer 150, and the dielectric layer 152 to expose the top surfaces of the first S / D structure 136a and the second S / D structure 136b, and then the silicide layer 154 and the S / D contact structure 156 can be formed in the contact openings. The contact openings can be formed using photolithography and etching processes. Furthermore, some portions of the first S / D structure 136a and the second S / D structure 136b exposed by the contact openings can also be etched during the etching process.

[0095] The silicide layer 154 can be formed by: forming a metal layer over the top surfaces of the first S / D structure 136a and the second S / D structure 136b; and annealing the metal layer such that the metal layer reacts with the first S / D structure 136a and the second S / D structure 136b to form the silicide layer 154. After the silicide layer 154 is formed, any unreacted metal layer can be removed.

[0096] The S / D contact structure 156 may include a barrier layer and a conductive layer. In some other embodiments, the S / D contact structure 156 does not include a barrier layer. In some embodiments, the barrier layer is made of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or another suitable material. In some embodiments, the barrier layer is formed using a process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), plasma-enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other suitable deposition process. In some embodiments, the conductive layer is made of tungsten (W), ruthenium (Ru), molybdenum (Mo), etc. In some embodiments, the conductive layer is formed by performing a deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes.

[0097] In some embodiments, the gate contact structure 168 is made of a conductive material, such as tungsten (W), ruthenium (Ru), molybdenum (Mo), etc. In some embodiments, the gate contact structure 168 is formed by performing a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes.

[0098] like Figure 3N-2As shown, the dielectric wall structure 18 has a top portion and a bottom portion, with the bottom portion being wider than the top portion. The dielectric wall structure 18 has an inverted T-shaped structure. In some embodiments, the dielectric wall structure 18 has sidewall surfaces, and the sidewall surfaces have a top vertical portion 18V1, a horizontal portion 18h, and a bottom vertical portion 18V2. The horizontal portion 18h is located between the top vertical portion 18V1 and the bottom vertical portion 18V2. In some embodiments, the horizontal portion 18h of the dielectric wall structure 18 is higher than the topmost surface of the nanostructure 108'.

[0099] Furthermore, the dielectric wall structure 18 has a top portion and a bottom portion, with a first distance D1 existing between the sidewall surface of the top portion and the sidewall surface of the topmost nanostructure 108'. A second distance D2 exists between the sidewall surface of the bottom portion and the sidewall surface of the topmost nanostructure 108'. In some embodiments, the first distance D1 is greater than the second distance D2. In some embodiments, the first distance D1 is in the range from about 4 nm to about 8 nm. When the first distance D1 is within the aforementioned range, the unwanted capacitance of the semiconductor structure 100a is reduced.

[0100] The top portion of the dielectric wall structure 18 has a first height H1. In some embodiments, the first height H1 is in the range of about 10 nm to about 15 nm. In some embodiments, the third width W3 of the topmost surface of the dielectric wall structure 18 is in the range of about 15 nm to about 45 nm. The horizontal portion 18h of the sidewall surface of the dielectric wall structure 18 has a fourth width W4. In some embodiments, the fourth width W4 is in the range of about 5 nm to about 30 nm.

[0101] Because the dielectric wall structure 18 is formed before the first gate structure 142a is formed, the gate dielectric layer 146 of the first gate structure 142a is in contact with the sidewall surfaces of the bottom portion and the top portion of the dielectric wall structure 18. Furthermore, the pad layer 14 is located directly below the dielectric wall structure 18, and the gate dielectric layer 146 of the first gate structure 142a is in contact with the sidewall surface of the pad layer 14. The dummy gate dielectric layer 120 is also located directly below the dielectric wall structure 18 and the pad layer 14, and the gate dielectric layer 146 of the first gate structure 142a is in contact with the sidewall surface of the dummy gate dielectric layer 120.

[0102] like Figure 3N-2As shown, a mask layer 117 is formed on an isolation structure 116, and a pad layer 14 is located on the mask layer 117. A dielectric wall structure 18 is located on the mask layer 117. The pad layer 14 is located between the mask layer 117 and the dielectric wall structure 18. The mask layer 17 is separated from the dielectric wall structure 18 by the pad layer 14 and a dummy gate dielectric layer 120. The mask layer 117 is located between the isolation structure 116 and the dielectric wall structure 18. The dummy dielectric layer 120 is located between the pad layer 14 and the mask layer 117.

[0103] It should be noted that because the top portion of the dielectric wall structure 18 is removed or trimmed, the top width of the top surface of the dielectric wall structure 18 is reduced, and therefore more spacing will be available for forming the gate contact structure 168. The gate contact structure 168 is formed on the first gate structure 142a and does not contact the dielectric wall structure 18. Therefore, the gate contact structure 168 has more contact windows.

[0104] Furthermore, because there is a gap between the sidewall surface of the bottom portion of the dielectric wall structure 18 and the sidewall surface of the topmost nanostructure 108' (in Figure 3N-2 The middle is marked as the second distance D2), so in Figure 3L-2 The pseudo dielectric layer 132 can be easily removed during the process, preventing the problem of residual pseudo dielectric layer 132.

[0105] Furthermore, the dielectric wall structure 18 has an inverted T-shaped structure, and the first gate structure 142a fills the gap between the dielectric wall structure 18 and the nanostructure 108' to further reduce capacitance. Therefore, the performance of the semiconductor structure 100a is improved.

[0106] Figure 5 A top view representation of a semiconductor structure 100a after the formation of a first gate structure 142a and a second gate structure 142b, according to some embodiments, is shown.

[0107] like Figure 5 As shown, the dielectric wall structure 18 is located between the first gate structure 142a and the second gate structure 142b. The first gate structure 142a is separated from the second gate structure 142b by the dielectric wall structure 18. The longitudinal direction of the dielectric wall structure 18 is along a first direction (e.g., the x-axis). The longitudinal direction of the dielectric wall structure 18 is parallel to the longitudinal direction of the first fin structure 104a and the second fin structure 104b.

[0108] The dielectric wall structure 18 extends from the first region 11 (gate region) to the second region 12 (S / D region). The dielectric wall structure 18 has a first width W1 in the second region 12 (S / D region) and a third width W3 in the first region 11 (gate region). In some embodiments, the third width W3 is smaller than the first width W1.

[0109] Figure 6A A top view representation of a semiconductor structure 100b after the formation of a dielectric wall structure is shown according to some embodiments. Figure 6B The following are shown according to some embodiments. Figure 6A The cross-section of semiconductor structure 100b is shown by line D-D'. Figure 6A and Figure 6B The semiconductor structure 100b includes similar semiconductor structures. Figure 3N-2 and Figure 5 The semiconductor structure 100a of the element or related Figure 3N-2 and Figure 5 The semiconductor structure 100a has the same components as the components. Figure 6A and Figure 6B and Figure 3N-2 and Figure 5 The difference is that the length of the dielectric wall structure 18' along the first direction (e.g., the x-axis) is less than the length of the dielectric wall structure 18 along the first direction (e.g., the x-axis).

[0110] like Figure 6A and Figure 6B As shown, the main portion of the dielectric wall structure 18' is located in the first region 11 (gate region). The remaining portion of the dielectric wall structure 18' is located in the second region 12 (S / D region). In some embodiments, the dielectric wall structure 18' has a first width W1 in the second region 12 (S / D region) and a third width W3 in the first region 11 (gate region). In some embodiments, the third width W3 is equal to the first width W1.

[0111] Figure 7A A top view representation of a semiconductor structure 100c after the formation of a dielectric wall structure is shown according to some embodiments. Figure 7B The following are shown according to some embodiments. Figure 7A The lines B-B' and E-E' in the figure represent the cross-section of the semiconductor structure 100c. Figure 7A and Figure 7B The semiconductor structure 100c includes similar Figure 3N-2 and Figure 5 The semiconductor structure 100a of the element or related Figure 3N-2 and Figure 5 The semiconductor structure 100a has the same components as the components. Figure 7A and Figure 7B and Figure 3N-2 and Figure 5 The difference lies in the fact that the width Wa of the nanostructure 108' in the first sub-region 10 is greater than the width Wb of the nanostructure 108' in the second sub-region 20. The widths Wa and Wb are measured along a second direction (e.g., the Y-axis).

[0112] In the first sub-region 10, the dielectric wall structure 18a has a first width W1 in the second region 12 (S / D region) and a third width W3 in the first region 11 (gate region). In some embodiments, the third width W3 is smaller than the first width W1.

[0113] In the second sub-region 20, the dielectric wall structure 18b has a seventh width W7 in the second region 12 (S / D region) and a ninth width W9 in the first region 11 (gate region). In some embodiments, the ninth width W9 is smaller than the seventh width W7.

[0114] like Figure 7A As shown, a first distance D1 exists between the sidewall surface of the top portion of the dielectric wall structure 18a and the sidewall surface of the topmost nanostructure 108'. A third distance D3 exists between the sidewall surface of the top portion of the dielectric wall structure 18b and the sidewall surface of the topmost nanostructure 108'. In some embodiments, the first distance D1 is substantially equal to the third distance D3. In some embodiments, the third distance D3 is in the range of about 4 nm to about 8 nm.

[0115] like Figure 7B As shown, dielectric wall structures 18a and 18b have an inverted T-shaped structure. Therefore, the first gate structure 142a fills the gap between the dielectric wall structure 18a and the nanostructure 108' to further reduce capacitance. Furthermore, a gate contact structure 168 is formed on the first gate structure 142a and does not contact the dielectric wall structure 18a. Therefore, the gate contact structure 168 has more contact windows. Thus, the performance of the semiconductor structure 100c is improved.

[0116] Figure 8 A cross-sectional representation of a semiconductor structure 100d according to some embodiments is shown. Figure 8 The semiconductor structure 100d includes similar Figure 3N-2 The semiconductor structure 100a of the element or related Figure 3N-2 The semiconductor structure 100a has the same components as the components. Figure 8 and Figure 3N-2 The difference is that the horizontal portion 18h of the dielectric wall structure 18 is lower than the top surface of the nanostructure 108'.

[0117] Figure 9 A cross-sectional representation of a semiconductor structure 100e according to some embodiments is shown. Figure 9 The semiconductor structure 100e includes similar Figure 3N-2 The semiconductor structure 100a of the element or related Figure 3N-2 The semiconductor structure 100a has the same components as the components. Figure 9 and Figure 3N-2 The difference lies in that the rounded portion 18r is located between the top vertical portion 18V1 and the bottom vertical portion 18V2 of the dielectric wall structure 18. The rounded portion 18r has a curved surface.

[0118] The dielectric wall structure 18 of semiconductor structures 100a-100e has an inverted T-shaped structure, so the gate contact structure 168 is formed on the first gate structure 142a and does not contact the dielectric wall structure 18, thus providing more contact windows. Furthermore, the first gate structure 142a fills the gap between the dielectric wall structure 18 and the nanostructure 108' to further reduce unwanted capacitance. Therefore, the performance of semiconductor structures 100a-100e is improved.

[0119] It should be understood that the semiconductor structures 100a to 100e described above, which have an inverted T-shaped dielectric wall structure 118 between the first gate structure 142a and the second gate structure 142b, can also be applied to FinFET structures, but are not shown in the figures.

[0120] It should be pointed out that, Figures 1A to 9 The same elements in the same document can be represented by the same reference numerals, and can include similar or identical materials, and can be formed by similar or identical processes; therefore, for the sake of brevity, such redundant details have been omitted. Furthermore, although... Figures 1A to 9 It is described in relation to the method, but it should be understood that... Figures 1A to 9 The structures disclosed are not limited to methods, but can exist independently of methods. Similarly, Figures 1A to 9 The methods shown are not limited to the disclosed structures, but can exist independently of the structures. Furthermore, according to some embodiments, the nanostructures described above may include nanowires, nanosheets, or other suitable nanostructures.

[0121] Furthermore, while the disclosed methods are shown and described below as a series of steps or events, it should be understood that in some other embodiments, the order of such steps or events may be varied. For example, some steps may occur in a different order and / or simultaneously with other steps or events besides those shown and / or described above. Moreover, not all steps shown may be necessary to implement one or more aspects or embodiments described above. Furthermore, one or more of the steps depicted above may be performed in one or more separate steps and / or stages.

[0122] Furthermore, the terms “approximately,” “basically,” “essentially,” and “about” described above take into account minor variations and can vary across different technologies and within the range of deviations understood by those skilled in the art. For example, when used in conjunction with an event or situation, the terms can refer to instances where the event or situation occurred precisely or instances where the event or situation was very close to occurring.

[0123] Embodiments for forming semiconductor structures can be provided. The semiconductor structure includes a first nanostructure and a second nanostructure formed above a substrate along a first direction (e.g., the x-axis). A first gate structure is formed above the first nanostructure, and a second gate structure is formed above the second nanostructure. A dielectric wall structure is located between the first and second gate structures. A first S / D structure is adjacent to the first gate structure, and a second S / D structure is adjacent to the second gate structure. The dielectric wall structure extends from the gate region to the S / D region. The dielectric wall structure has an inverted T-shaped structure, so that the gate contact structure is formed on the first gate structure and does not contact the dielectric wall structure, thus providing more contact windows. Furthermore, the first gate structure fills the gap between the dielectric wall structure and the nanostructure to further reduce capacitance. Therefore, the performance of the semiconductor structure is improved.

[0124] In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a plurality of first nanostructures formed along a first direction over a substrate and a plurality of second nanostructures formed adjacent to the first nanostructures. The semiconductor structure includes a first gate structure formed along a second direction on the first nanostructures, and the first gate structure includes a first gate dielectric layer. The semiconductor structure includes a second gate structure formed on the second nanostructures. The semiconductor structure includes a dielectric wall structure located along the first direction between the first gate structure and the second gate structure. The dielectric wall structure has a top portion and a bottom portion, and the bottom portion is wider than the top portion. The semiconductor structure includes a pad layer located beneath the dielectric wall structure, and the first gate dielectric layer is formed on the sidewall surface of the pad layer and the sidewall surface of the dielectric wall structure.

[0125] In some embodiments, a semiconductor structure is provided. The semiconductor structure includes: a plurality of first nanostructures formed above a substrate; and a plurality of second nanostructures formed adjacent to the first nanostructures. The semiconductor structure includes: a first gate structure formed on the first nanostructures; and a second gate structure formed on the second nanostructures. A dielectric wall structure is located between the first gate structure and the second gate structure. The dielectric wall structure has a top portion and a bottom portion, a first distance being located between the sidewall surface of the top portion and the sidewall surface of the topmost first nanostructure, and a second distance being located between the sidewall surface of the bottom portion and the sidewall surface of the topmost first nanostructure. The first distance is greater than the second distance.

[0126] In some embodiments, a method for forming a semiconductor structure is provided. The method includes: forming a first fin structure and a second fin structure over a substrate, wherein the first fin structure includes alternately stacked first and second semiconductor material layers, and the second fin structure includes alternately stacked first and second semiconductor material layers. The method includes: forming a first dummy gate structure over the first and second fin structures, wherein the first dummy gate structure includes a first dummy gate dielectric layer and a first dummy gate electrode layer. The method includes: replacing the first semiconductor material layer with a dummy dielectric layer, such that the dummy dielectric layer and the second semiconductor material layer are alternately stacked. The method includes: removing a portion of the first dummy gate electrode layer to form an opening; and forming a pad layer in the opening. The method includes: forming a dielectric wall material in the opening; and removing another portion of the first dummy gate electrode layer. The method includes: removing a portion of the pad layer; and removing a portion of the first dummy gate dielectric layer and a portion of the dielectric wall material to form a dielectric wall structure. The remaining portion of the pad layer and the remaining portion of the first dummy gate dielectric layer are located directly below the dielectric wall structure. The method includes: removing the dummy dielectric layer to form a gap; and forming a first gate structure in the gap.

[0127] Some embodiments of this application provide a semiconductor structure including: a plurality of first nanostructures formed above a substrate along a first direction; a plurality of second nanostructures formed adjacent to the first nanostructures; a first gate structure formed on the first nanostructures along a second direction, wherein the first gate structure includes a first gate dielectric layer; a second gate structure formed on the second nanostructures; and a dielectric wall structure located between the first gate structure and the second gate structure along the first direction, wherein the dielectric wall structure has a top portion and a bottom portion, and the bottom portion is wider than the top portion.

[0128] In some embodiments, the dielectric wall structure has an inverted T-shaped structure. In some embodiments, the semiconductor structure further includes: a pad layer located below the dielectric wall structure, wherein the first gate dielectric layer is formed on the sidewall surface of the pad layer and the sidewall surface of the dielectric wall structure; and a dummy gate dielectric layer located below the pad layer, wherein the first gate dielectric layer is formed on the sidewall surface of the dummy gate dielectric layer. In some embodiments, the semiconductor structure further includes: an isolation structure formed on the substrate; and a mask layer formed on the isolation structure, wherein the mask layer is located between the isolation structure and the dielectric wall structure. In some embodiments, the pad layer is located between the mask layer and the dielectric wall structure. In some embodiments, the dielectric wall structure has sidewall surfaces, and the sidewall surfaces have a top vertical portion, a horizontal portion, and a bottom vertical portion, the horizontal portion being located between the top vertical portion and the bottom vertical portion, and the horizontal portion being higher than the topmost surface of the first nanostructure. In some embodiments, the semiconductor structure further includes: a gate contact structure formed on the first gate structure, wherein the gate contact structure is electrically connected to the first gate structure. In some embodiments, the semiconductor structure further includes: a first source / drain structure formed adjacent to the first gate structure; and a second source / drain structure formed adjacent to the second gate structure, wherein the dielectric wall structure has an extension portion located between the first source / drain structure and the second source / drain structure. In some embodiments, the bottom surface of the extension portion of the dielectric wall structure is higher than the top surface of the first source / drain structure.

[0129] Other embodiments of this application provide a semiconductor structure including: a plurality of first nanostructures formed above a substrate; a plurality of second nanostructures formed adjacent to the first nanostructures; a first gate structure formed on the first nanostructures; a second gate structure formed on the second nanostructures; and a dielectric wall structure located between the first gate structure and the second gate structure, wherein the dielectric wall structure has a top portion and a bottom portion, a first distance is located between the sidewall surface of the top portion and the sidewall surface of the topmost first nanostructure, a second distance is located between the sidewall surface of the bottom portion and the sidewall surface of the topmost first nanostructure, and the first distance is greater than the second distance.

[0130] In some embodiments, the first gate structure includes a first gate dielectric layer, and the first gate dielectric layer contacts the sidewall surface of the bottom portion of the dielectric wall structure. In some embodiments, the semiconductor structure further includes: a first source / drain structure formed adjacent to the first gate structure; and a second source / drain structure formed adjacent to the second gate structure, wherein the dielectric wall structure has an extension portion located between the first source / drain structure and the second source / drain structure. In some embodiments, the semiconductor structure further includes: an isolation structure formed on the substrate; and a mask layer formed on the isolation structure, wherein the mask layer is separated from the dielectric wall structure by a pad layer. In some embodiments, the semiconductor structure further includes: the pad layer formed under the dielectric wall structure; and a dielectric layer formed under the pad layer. In some embodiments, the sidewall surface of the pad layer is aligned with the sidewall surface of the dielectric wall structure. In some embodiments, the dielectric wall structure has a sidewall surface, and the sidewall surface has a top vertical portion, a horizontal portion, and a bottom vertical portion, the horizontal portion being located between the top vertical portion and the bottom vertical portion, and the horizontal portion being lower than the topmost surface of the first nanostructure.

[0131] Some embodiments of this application provide a method for forming a semiconductor structure, comprising: forming a first fin structure and a second fin structure over a substrate, wherein the first fin structure includes alternating stacked first semiconductor material layers and second semiconductor material layers, and the second fin structure includes alternating stacked first semiconductor material layers and second semiconductor material layers; forming a first dummy gate structure over the first fin structure and the second fin structure, wherein the first dummy gate structure includes a first dummy gate dielectric layer and a first dummy gate electrode layer; replacing the first semiconductor material layer with a dummy dielectric layer such that the dummy dielectric layer and the second semiconductor material layer are alternately stacked; removing a portion of the first dummy gate electrode layer to form an opening; forming a pad layer in the opening; forming a dielectric wall material in the opening; removing another portion of the first dummy gate electrode layer; removing a portion of the pad layer; removing a portion of the first dummy gate dielectric layer and a portion of the dielectric wall material to form a dielectric wall structure, wherein the remaining portion of the pad layer and the remaining portion of the first dummy gate dielectric layer are located directly below the dielectric wall structure; removing the dummy dielectric layer to form a gap; and forming a first gate structure in the gap.

[0132] In some embodiments, the method of forming the semiconductor structure further includes: forming a dielectric layer on the first dummy gate structure; and removing a portion of the dielectric layer when the portion of the first dummy gate electrode layer is removed. In some embodiments, the method of forming the semiconductor structure further includes: forming an isolation structure on the substrate; and forming a mask layer on the isolation structure, wherein the mask layer is separated from the dielectric wall structure by the pad layer. In some embodiments, the method of forming the semiconductor structure further includes: forming a first source / drain structure adjacent to the first dummy gate structure, wherein the dielectric wall structure has an extension adjacent to the first source / drain structure, and the bottom surface of the extension of the dielectric wall structure is higher than the top surface of the first source / drain structure.

[0133] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a base to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and modifications can be made to them herein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A semiconductor structure, comprising: Multiple first nanostructures are formed above the substrate along a first direction; Multiple second nanostructures are formed adjacent to the first nanostructure; A first gate structure is formed on the first nanostructure along a second direction, wherein the first gate structure includes a first gate dielectric layer; A second gate structure is formed on the second nanostructure; and A dielectric wall structure is located between the first gate structure and the second gate structure along the first direction, wherein the dielectric wall structure has a top portion and a bottom portion, and the bottom portion is wider than the top portion.

2. The semiconductor structure according to claim 1, wherein, The dielectric wall structure has an inverted T-shaped structure.

3. The semiconductor structure according to claim 1, further comprising: A pad layer, located beneath the dielectric wall structure, wherein the first gate dielectric layer is formed on the sidewall surface of the pad layer and the sidewall surface of the dielectric wall structure; and A dummy gate dielectric layer is located beneath the pad layer, wherein the first gate dielectric layer is formed on the sidewall surface of the dummy gate dielectric layer.

4. The semiconductor structure according to claim 3, further comprising: An isolation structure is formed on the substrate; as well as A mask layer is formed on the isolation structure, wherein the mask layer is located between the isolation structure and the dielectric wall structure.

5. The semiconductor structure according to claim 4, wherein, The padding layer is located between the mask layer and the dielectric wall structure.

6. The semiconductor structure according to claim 1, wherein, The dielectric wall structure has a sidewall surface, and the sidewall surface has a top vertical portion, a horizontal portion and a bottom vertical portion, the horizontal portion being located between the top vertical portion and the bottom vertical portion, and the horizontal portion being higher than the top surface of the first nanostructure.

7. The semiconductor structure according to claim 1, further comprising: A gate contact structure is formed on the first gate structure, wherein the gate contact structure is electrically connected to the first gate structure.

8. The semiconductor structure according to claim 1, further comprising: The first source / drain structure is formed adjacent to the first gate structure; as well as A second source / drain structure is formed adjacent to the second gate structure, wherein the dielectric wall structure has an extension located between the first source / drain structure and the second source / drain structure.

9. A semiconductor structure, comprising: Multiple first nanostructures are formed on the substrate; Multiple second nanostructures are formed adjacent to the first nanostructure; A first gate structure is formed on the first nanostructure; A second gate structure is formed on the second nanostructure; as well as A dielectric wall structure is located between the first gate structure and the second gate structure, wherein the dielectric wall structure has a top portion and a bottom portion, a first distance is located between the sidewall surface of the top portion and the sidewall surface of the topmost first nanostructure, a second distance is located between the sidewall surface of the bottom portion and the sidewall surface of the topmost first nanostructure, and the first distance is greater than the second distance.

10. A method for forming a semiconductor structure, comprising: A first fin structure and a second fin structure are formed on the substrate, wherein the first fin structure includes alternating stacked first semiconductor material layers and second semiconductor material layers, and the second fin structure includes alternating stacked first semiconductor material layers and second semiconductor material layers. A first dummy gate structure is formed above the first fin structure and the second fin structure, wherein the first dummy gate structure includes a first dummy gate dielectric layer and a first dummy gate electrode layer. The first semiconductor material layer is replaced with a pseudo dielectric layer, thereby causing the pseudo dielectric layer and the second semiconductor material layer to be stacked alternately. Remove a portion of the first dummy gate electrode layer to form an opening; A liner layer is formed in the opening; A dielectric wall material is formed in the opening; Remove another portion of the first dummy gate electrode layer; Remove a portion of the liner layer; A portion of the first dummy gate dielectric layer and a portion of the dielectric wall material are removed to form a dielectric wall structure, wherein the remaining portion of the pad layer and the remaining portion of the first dummy gate dielectric layer are located directly below the dielectric wall structure; Remove the pseudo-dielectric layer to form a gap; and A first gate structure is formed in the gap.

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