Electrostatic discharge protection device and chip
By introducing a parasitic capacitance and resistance coupling structure into the electrostatic discharge protection device, the problem of insufficient discharge current capability of GGNMOS is solved, achieving faster conduction speed and higher discharge current capability, enhancing anti-latch-up capability, and improving the effect of electrostatic discharge protection.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-22
- Publication Date
- 2026-03-24
AI Technical Summary
Existing GGNMOS electrostatic discharge protection devices have limited discharge current capacity, low holding current, and high trigger voltage, making them unable to effectively protect integrated circuits.
In electrostatic discharge protection devices, a parasitic capacitance and resistance coupling structure is introduced. This is achieved by setting a second P-type doped region between the gate and the second N-type doped region, connecting the gate and the second P-type doped region together, adding an N-type region on the P-type region side, and setting a third N-type doped region and a third P-type doped region within the N-type region. This forms a parasitic capacitance and resistance coupling, reducing the trigger voltage and increasing the holding current.
It achieves faster conduction speed and higher discharge current capability, enhances anti-latch-up capability, and improves the effect of electrostatic discharge protection.
Smart Images
Figure CN121568436B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and in particular to an electrostatic discharge protection device and chip. Background Technology
[0002] Electrostatic discharge (ESD) protection is a crucial aspect of integrated circuit (IC) design. ESD protection devices are connected to the integrated circuit via a positive (anode) and a negative (cathode) terminal to provide ESD protection. As process nodes shrink, the requirements for ESD protection in integrated circuits become increasingly stringent.
[0003] Commonly used electrostatic discharge protection devices include diodes, metal-oxide-semiconductor field-effect transistors (MOSFETs), bipolar junction transistors (BJTs), and silicon controlled rectifiers (SCRs). Among them, gate-grounded N-type metal-oxide-semiconductor (GGNMOS) is widely used in electrostatic discharge protection circuits due to its good CMOS process compatibility, simple process, and excellent snapback characteristics.
[0004] However, existing GGNMOS has limited discharge current capability, low holding current (Ih), and high trigger voltage. Summary of the Invention
[0005] The purpose of this invention is to provide an electrostatic discharge protection device and chip that can reduce the trigger voltage and improve the ability to discharge electrostatic discharge current.
[0006] To solve the above-mentioned technical problems, according to a first aspect of the present invention, an electrostatic discharge protection device is provided, comprising:
[0007] Substrate;
[0008] The P-type region is located within the substrate;
[0009] An N-type region is located within the substrate, and the N-type region is disposed adjacent to the P-type region.
[0010] The first N-type doped region is located in the P-type region;
[0011] The second N-type doped region is located in the P-type region, and the second N-type doped region is located on the side of the first N-type doped region away from the N-type region;
[0012] A first P-type doped region is located in the P-type region, and the first P-type doped region is located on the side of the second N-type doped region away from the N-type region;
[0013] The second P-type doped region is located in the P-type region, and the second P-type doped region is located between the first N-type doped region and the second N-type doped region;
[0014] The third N-type doped region is located in the N-type region;
[0015] The third P-type doped region is located in the N-type region, and the third P-type doped region is located on the side of the third N-type doped region away from the P-type region;
[0016] The gate is located above the region between the first N-type doped region and the second P-type doped region;
[0017] The gate is connected to the second P-type doped region, the second N-type doped region is connected to the first P-type doped region as the negative electrode of the electrostatic discharge protection device, and the first N-type doped region, the third N-type doped region, and the third P-type doped region are connected as the positive electrode of the electrostatic discharge protection device.
[0018] Optionally, the gate, the first N-type doped region, and the second N-type doped region constitute a GGNMOS, with the first N-type doped region serving as the drain of the GGNMOS, the second N-type doped region serving as the source of the GGNMOS, and the gate serving as the gate of the GGNMOS.
[0019] Optionally, the third P-type doped region, the N-type region, and the P-type region constitute a first parasitic transistor, the third P-type doped region serves as the emitter of the first parasitic transistor, the N-type region serves as the base of the first parasitic transistor, and the P-type region serves as the collector of the first parasitic transistor.
[0020] Optionally, the second N-type doped region, the P-type region, and the N-type region constitute a second parasitic transistor, with the second N-type doped region serving as the emitter of the second parasitic transistor, the P-type region serving as the base of the second parasitic transistor, and the N-type region serving as the collector of the second parasitic transistor.
[0021] Optionally, an N-type resistor exists within the N-type region, with one end of the N-type resistor connected to the emitter of the first parasitic transistor and the other end connected to the base of the first parasitic transistor; a P-type resistor exists within the P-type region, with one end of the P-type resistor connected to the base of the second parasitic transistor and the other end connected to the emitter of the second parasitic transistor.
[0022] Optionally, there is a parasitic capacitance between the gate and the P-type region, and there is a doped region resistance within the second P-type doped region.
[0023] Optionally, when the electrostatic discharge pulse reaches the positive terminal of the device and the negative terminal of the device is grounded, the voltage is coupled to the gate of the GGNMOS, and the GGNMOS is turned on; the current flowing through the doped region resistor raises the voltage of the GGNMOS gate, and the voltage drop of the P-type region resistor causes the emitter junction of the second parasitic transistor to be forward biased, and the second parasitic transistor is turned on; the current flowing through the N-type region resistor causes a voltage drop, which causes the emitter junction of the first parasitic transistor to be forward biased, and the first parasitic transistor is turned on. The SCR circuit composed of the first parasitic transistor and the second parasitic transistor is turned on, and the electrostatic discharge current is discharged.
[0024] Optionally, it also includes multiple isolation regions, wherein the isolation region is disposed between the first P-type doped region and the second N-type doped region, the isolation region is disposed between the second N-type doped region and the second P-type doped region, and the isolation region is disposed between the third N-type doped region and the third P-type doped region.
[0025] Optionally, the doping concentrations of the first N-type doped region, the second N-type doped region, and the third N-type doped region are all greater than the doping concentration of the N-type region; the doping concentrations of the first P-type doped region, the second P-type doped region, and the third P-type doped region are all greater than the doping concentration of the P-type region.
[0026] To solve the above-mentioned technical problems, according to a second aspect of the present invention, a chip is provided, including the electrostatic discharge protection device as described above.
[0027] In summary, the electrostatic discharge protection device and chip provided by the present invention include: a substrate; a P-type region located within the substrate; an N-type region located within the substrate, the N-type region and the P-type region being disposed adjacent to each other; a first N-type doped region located within the P-type region; a second N-type doped region located within the P-type region, the second N-type doped region being located on the side of the first N-type doped region away from the N-type region; a first P-type doped region located within the P-type region, the first P-type doped region being located on the side of the second N-type doped region away from the N-type region; and a second P-type doped region located within the P-type region, the second P-type doped region being located within the first N-type doped region. Between the first N-type doped region and the second P-type doped region; a third N-type doped region, located within the N-type region; a third P-type doped region, located within the N-type region, the third P-type doped region being located on the side of the third N-type doped region away from the P-type region; a gate, located above the region between the first N-type doped region and the second P-type doped region; wherein, the gate is connected to the second P-type doped region, the second N-type doped region is connected to the first P-type doped region as the negative electrode of the electrostatic discharge protection device, and the first N-type doped region, the third N-type doped region, and the third P-type doped region are connected as the positive electrode of the electrostatic discharge protection device. The unexpected effect of this invention is that a second P-type doped region is set between the gate and the second N-type doped region, and the gate and the second P-type doped region are connected together. At the same time, an N-type region adjacent to the P-type region is added on one side of the P-type region. A third N-type doped region and a third P-type doped region are set in the N-type region. The second N-type doped region and the first P-type doped region are connected as the negative electrode of the electrostatic discharge protection device, and the first N-type doped region, the third N-type doped region and the third P-type doped region are connected as the positive electrode of the electrostatic discharge protection device. The electrostatic discharge protection device thus formed has parasitic capacitance and resistance. The coupling between resistance and capacitance can reduce the trigger voltage of the device and increase the holding current.
[0028] An unexpected benefit of this invention is that it combines the advantages of GGNMOS and SCR, giving it a faster turn-on speed, higher discharge current capability, and enhanced anti-latch-up capability. Attached Figure Description
[0029] Figure 1 This is a schematic diagram of the structure of a traditional electrostatic discharge protection device.
[0030] Figure 2 yes Figure 1 The equivalent circuit diagram of the electrostatic discharge protection device is shown.
[0031] Figure 3 This is a schematic diagram of the electrostatic discharge protection device provided in an embodiment of the present invention.
[0032] Figure 4 yes Figure 3 The equivalent circuit diagram of the electrostatic discharge protection device is shown.
[0033] Figure 5 This is a comparison chart of the current-voltage curves of an electrostatic discharge protection device provided in an embodiment of the present invention and a traditional electrostatic discharge protection device during electrostatic discharge.
[0034] Explanation of reference numerals in the attached figures:
[0035] 10 - Substrate; 20 - P-type region; 21 - First N-type doped region; 22 - Second N-type doped region; 23 - First P-type doped region; 24 - Gate; 25 - Second P-type doped region; 30 - N-type region; 31 - Third N-type doped region; 32 - Third P-type doped region; 33 - Isolation region. Detailed Implementation
[0036] Figure 1 This is a schematic diagram of the structure of a traditional electrostatic discharge protection device. Figure 2 yes Figure 1 The equivalent circuit diagram of the electrostatic discharge protection device is shown below. Please refer to it. Figure 1 and Figure 2 As shown, the electrostatic discharge protection device is a GGNMOS, which includes: a substrate 10; a P-type region 20 located within the substrate 10; a first N-type doped region 21 located within the P-type region 20; a second N-type doped region 22 located within the P-type region 20; a first P-type doped region 23 located within the P-type region 20; and the second N-type doped region 22 located between the first P-type doped region 23 and the first N-type doped region 21; it also includes a gate 24 located above the region between the first N-type doped region 21 and the second N-type doped region 22.
[0037] The first N-type doped region 21, the second N-type doped region 22, and the gate 24 constitute a GGNMOS. The first N-type doped region 21 serves as the drain of the GGNMOS, the second N-type doped region 22 serves as the source of the GGNMOS, and the gate 24 serves as the gate of the GGNMOS. The first P-type doped region 23 serves as the body region.
[0038] Wherein, the first N-type doped region 21 serves as the positive electrode (±V) of the electrostatic discharge protection device. ESDThe second N-type doped region 22, the first P-type doped region 23, and the gate 24 are connected to serve as the negative electrode (GND) of the electrostatic discharge protection device. For example, the substrate 10 is a P-type substrate (P-sub), the P-type region 20 is a P-well (PW), the first N-type doped region 21 and the second N-type doped region 22 are N+, and the first P-type doped region 23 is P+.
[0039] Please refer to Figure 2 As shown, when the electrostatic discharge pulse reaches the positive terminal (±V) of the device ESD When the negative terminal (GND) of the device is grounded, the GGNMOS turns on to discharge the electrostatic discharge current. However, the discharge current capacity of this electrostatic discharge protection device is limited, the holding voltage (Ih) is too low, and the trigger voltage is too high, so it cannot play a good role in electrostatic discharge protection.
[0040] To address the aforementioned problems, this invention adds a second P-type doped region within the P-type region between the gate and the second N-type doped region, and connects the gate and the second P-type doped region together. Simultaneously, an N-type region adjacent to the P-type region is added to one side of the P-type region. A third N-type doped region and a third P-type doped region are disposed within the N-type region. The second N-type doped region is connected to the first P-type doped region as the negative electrode of the electrostatic discharge protection device, and the first N-type doped region, the third N-type doped region, and the third P-type doped region are connected as the positive electrode of the electrostatic discharge protection device. The electrostatic discharge protection device thus formed has parasitic capacitance and resistance. The coupling between resistance and capacitance can reduce the trigger voltage of the device and increase the holding current.
[0041] Specifically, the present invention provides an electrostatic discharge protection device, comprising: a substrate; a P-type region located within the substrate; an N-type region located within the substrate, the N-type region and the P-type region being disposed adjacent to each other; a first N-type doped region located within the P-type region; a second N-type doped region located within the P-type region, the second N-type doped region being located on the side of the first N-type doped region away from the N-type region; a first P-type doped region located within the P-type region, the first P-type doped region being located on the side of the second N-type doped region away from the N-type region; and a second P-type doped region located within the P-type region, the second P-type doped region being located within the first N-type doped region. Between the first N-type doped region and the second P-type doped region; a third N-type doped region, located within the N-type region; a third P-type doped region, located within the N-type region, the third P-type doped region being located on the side of the third N-type doped region away from the P-type region; a gate, located above the region between the first N-type doped region and the second P-type doped region; wherein, the gate is connected to the second P-type doped region, the second N-type doped region is connected to the first P-type doped region as the negative electrode of the electrostatic discharge protection device, and the first N-type doped region, the third N-type doped region, and the third P-type doped region are connected as the positive electrode of the electrostatic discharge protection device.
[0042] Accordingly, the present invention provides a chip including the electrostatic discharge protection device as described above.
[0043] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.
[0044] As used herein, the singular forms “a,” “an,” and “the” include plural objects unless otherwise expressly indicated. As used herein, the term “or” is generally used to include “and / or” unless otherwise expressly indicated. As used herein, the term “a number” is generally used to include “at least one” unless otherwise expressly indicated. As used herein, the term “at least two” is generally used to include “two or more” unless otherwise expressly indicated. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature.
[0045] The semiconductor terminology used in this invention consists of technical terms commonly used by those skilled in the art. For example, for P-type and N-type impurities, to distinguish doping concentration, P+ type represents heavily doped P-type, P type represents moderately doped P-type, P- represents lightly doped P-type, N+ type represents heavily doped N-type, N type represents moderately doped N-type, and N- represents lightly doped N-type.
[0046] Figure 3 This is a schematic diagram of the structure of an electrostatic discharge protection device provided in an embodiment of the present invention. Figure 4 yes Figure 3 The equivalent circuit diagram of the electrostatic discharge protection device is shown below. Please refer to it. Figure 3 and Figure 4 As shown, the electrostatic discharge protection device provided in this embodiment includes: a substrate 10; a P-type region 20 located within the substrate 10; an N-type region 30 located within the substrate 10, the N-type region 30 being adjacent to the P-type region 20; a first N-type doped region 21 located within the P-type region 20; a second N-type doped region 22 located within the P-type region 20, the second N-type doped region 22 being located on the side of the first N-type doped region 21 away from the N-type region 30; and a first P-type doped region 23 located within the P-type region 20, the first P-type doped region 23 being located on the side of the second N-type doped region 30 away from the N-type region 30. The doped region 22 is located on the side away from the N-type region 30; the second P-type doped region 25 is located in the P-type region 20, and the second P-type doped region 25 is located between the first N-type doped region 21 and the second N-type doped region 22; the third N-type doped region 31 is located in the N-type region 30; the third P-type doped region 32 is located in the N-type region 30, and the third P-type doped region 32 is located on the side of the third N-type doped region 31 away from the P-type region 20; the gate 24 is located above the region between the first N-type doped region 21 and the second P-type doped region 25.
[0047] In this configuration, the gate 24 is connected to the second P-type doped region 25, the second N-type doped region 22 is connected to the first P-type doped region 23 as the negative electrode (GND) of the electrostatic discharge protection device, and the first N-type doped region 21, the third N-type doped region 31, and the third P-type doped region 32 are connected as the positive electrode (±V) of the electrostatic discharge protection device. ESD The positive electrode (±V) of the electrostatic discharge protection device. ESD The negative terminal (GND) of the electrostatic discharge protection device serves as the electrical connection point for the positive pulse input of electrostatic discharge, and the negative terminal (GND) of the electrostatic discharge protection device serves as the electrical connection point for the electrostatic discharge pulse output of the electrostatic discharge protection device.
[0048] In one embodiment, the substrate 10 is a P-type substrate (P-sub), the P-type region 20 is a P-well (PW), the N-type region 30 is an N-well (NW), the first N-type doped region 21, the second N-type doped region 22 and the third N-type doped region 31 are all N+, that is, heavily doped N-type, and the first P-type doped region 23, the second P-type doped region 25 and the third P-type doped region 32 are all P+, that is, heavily doped P-type.
[0049] The gate 24, the first N-type doped region 21 and the second N-type doped region 22 constitute a GGNMOS, the first N-type doped region 21 serves as the drain of the GGNMOS, the second N-type doped region 22 serves as the source of the GGNMOS, and the gate 24 serves as the gate of the GGNMOS.
[0050] The third P-type doped region 32, the N-type region 30, and the P-type region 20 constitute a first parasitic transistor T1. The third P-type doped region 32 serves as the emitter of the first parasitic transistor T1, the N-type region 30 serves as the base of the first parasitic transistor T1, and the P-type region 20 serves as the collector of the first parasitic transistor T1. The first parasitic transistor T1 is a PNP transistor.
[0051] The second N-type doped region 22, the P-type region 20, and the N-type region 30 constitute the second parasitic transistor T2. The second N-type doped region 22 serves as the emitter of the second parasitic transistor T2, the P-type region 20 serves as the base of the second parasitic transistor T2, and the N-type region 30 serves as the collector of the second parasitic transistor T2. The second parasitic transistor T2 is an NPN transistor.
[0052] An N-type resistor Rnwell exists within the N-type region 30. One end of the N-type resistor Rnwell is connected to the emitter of the first parasitic transistor T1, and the other end is connected to the base of the first parasitic transistor T1. A P-type resistor Rpwell exists within the P-type region 20. One end of the P-type resistor Rpwell is connected to the base of the second parasitic transistor T2, and the other end is connected to the emitter of the second parasitic transistor T2.
[0053] There is a parasitic capacitance Cp between the gate 24 and the P-type region 20, and there is a doped region resistance Rp in the second P-type doped region 25.
[0054] In this embodiment, the turn-on voltage of the GGNMOS is lower than that of the SCR, so the GGNMOS will turn on first. Due to the resistance Rp in the doped region, the voltage at point A will increase. Since points A and B are at the same potential, the voltage at point B will also increase. When the voltage at point B rises to a set value, for example, >0.7V, the second parasitic transistor T2 will turn on, and consequently, the PNPN path will also turn on, thereby improving its ability to discharge electrostatic discharge current. This invention combines the advantages of GGNMOS and SCR, giving it a faster turn-on speed, higher discharge current capability, and enhanced anti-latch-up capability.
[0055] Figure 5 This is a comparison chart of the current-voltage curves of an electrostatic discharge protection device provided in an embodiment of the present invention and a traditional electrostatic discharge protection device during electrostatic discharge. Figure 5 The solid line in the middle represents Figure 3 The diagram shows the current-voltage curve of the electrostatic discharge protection device during electrostatic discharge. The dashed line represents... Figure 1 The diagram shows the current-voltage curve of the electrostatic discharge protection device during electrostatic discharge.
[0056] Please refer to Figure 4 and Figure 5 ( Figure 5 As shown by the solid line in the diagram, when an electrostatic discharge pulse reaches the positive terminal of the electrostatic discharge protection device and the negative terminal of the device is grounded, i.e., when an electrostatic discharge event occurs, the voltage can be quickly coupled to the gate of the GGNMOS, causing the GGNMOS to conduct. Figure 5 The trigger point (Vt1, It1); current flows through the doped region resistor Rp, raising the voltage of the GGNMOS gate (i.e., raising the voltage at point A). The voltage drop across the P-type region resistor Rpwell causes the emitter junction of the second parasitic transistor T2 to be forward biased, and the second parasitic transistor T2 is turned on, corresponding to... Figure 5 The trigger point (Vt1′, It1′); the current flowing through the N-type region resistor Rnwell causes a voltage drop, making the emitter junction of the first parasitic transistor T1 forward biased. The first parasitic transistor T1 conducts, and the PNPN SCR circuit formed by the first parasitic transistor T1 and the second parasitic transistor T2 conducts, thereby discharging the electrostatic discharge current. Voltage hysteresis causes the voltage of the electrostatic discharge protection device to drop to the holding voltage Vh, corresponding to... Figure 5 The trigger point (Vh, Ih). As the electrostatic discharge pulse increases, most of the electrostatic discharge current is rapidly discharged by the SCR until the electrostatic discharge protection device reaches the secondary breakdown point (Vt2, It2).
[0057] The electrostatic discharge protection device provided in this embodiment contains parasitic capacitance and resistance. The coupling between the resistance and capacitance can reduce the trigger voltage Vt1 of the device and increase the holding current Ih. Please refer to... Figure 5As shown, comparing the electrostatic discharge protection device of this embodiment with the conventional electrostatic discharge protection device, the trigger voltage Vt1 of the device in this embodiment is greater than the trigger voltage Vt1 of the conventional device, and the holding current Ih of the device in this embodiment is greater than the holding current Ih of the conventional device.
[0058] In one embodiment of the present invention, please refer to Figure 3 As shown, the electrostatic discharge protection device further includes multiple isolation regions 33. The isolation region 33 is disposed between the first P-type doped region 23 and the second N-type doped region 22, between the second N-type doped region 22 and the second P-type doped region 25, and between the third N-type doped region 31 and the third P-type doped region 32. The isolation region 33 can be a shallow trench isolation structure or a field oxygen isolation region; this invention does not limit the specific type of isolation region.
[0059] In one embodiment of the present invention, the doping concentrations of the first N-type doped region 21, the second N-type doped region 22, and the third N-type doped region 31 are all greater than the doping concentration of the N-type region 30; the doping concentrations of the first P-type doped region 23, the second P-type doped region 25, and the third P-type doped region 32 are all greater than the doping concentration of the P-type region 20.
[0060] The electrostatic discharge protection device provided in this embodiment of the invention includes a substrate 10; a P-type region 20 located within the substrate 10; an N-type region 30 located within the substrate 10, the N-type region 30 being adjacent to the P-type region 20; a first N-type doped region 21 located within the P-type region 20; a second N-type doped region 22 located within the P-type region 20, the second N-type doped region 22 being located on the side of the first N-type doped region 21 away from the N-type region 30; a first P-type doped region 23 located within the P-type region 20, the first P-type doped region 23 being located on the side of the second N-type doped region 22 away from the N-type region 30; and a second P-type doped region 25 located within the P-type region 20, the second P-type doped region 25 being located within the first N-type doped region. Between the first N-type doped region 21 and the second N-type doped region 22; a third N-type doped region 31, located in the N-type region 30; a third P-type doped region 32, located in the N-type region 30, the third P-type doped region 32 being located on the side of the third N-type doped region 31 away from the P-type region 20; a gate 24, located above the region between the first N-type doped region 21 and the second P-type doped region 25; wherein, the gate 24 is connected to the second P-type doped region 25, the second N-type doped region 22 is connected to the first P-type doped region 23 as the negative electrode of the electrostatic discharge protection device, and the first N-type doped region 21, the third N-type doped region 31, and the third P-type doped region 32 are connected as the positive electrode of the electrostatic discharge protection device.
[0061] An unexpected effect of this invention is that a second P-type doped region 25 is provided between the gate 24 and the second N-type doped region 22, and the gate 24 and the second P-type doped region 25 are connected together. At the same time, an N-type region 30 is added on one side of the P-type region 20, adjacent to the P-type region 20. A third N-type doped region 31 and a third P-type doped region 32 are provided in the N-type region 20. The second N-type doped region 22 is connected to the first P-type doped region 23 as the negative electrode of the electrostatic discharge protection device, and the first N-type doped region 21, the third N-type doped region 31 and the third P-type doped region 32 are connected as the positive electrode of the electrostatic discharge protection device. The electrostatic discharge protection device thus formed has parasitic capacitance and resistance. The coupling between resistance and capacitance can reduce the trigger voltage of the device and increase the holding current.
[0062] An unexpected benefit of this invention is that it combines the advantages of GGNMOS and SCR, giving it a faster turn-on speed, higher discharge current capability, and enhanced anti-latch-up capability.
[0063] Accordingly, the present invention also provides a chip including the electrostatic discharge protection device as described above.
[0064] In summary, the electrostatic discharge protection device and chip provided by the present invention include: a substrate; a P-type region located within the substrate; an N-type region located within the substrate, the N-type region being adjacent to the P-type region; a first N-type doped region located within the P-type region; a second N-type doped region located within the P-type region, the second N-type doped region being located on the side of the first N-type doped region away from the N-type region; a first P-type doped region located within the P-type region, the first P-type doped region being located on the side of the second N-type doped region away from the N-type region; and a second P-type doped region located within the P-type region, the second P-type doped region being located on the side of the first N-type doped region away from the N-type region. Between the first N-type doped region and the second N-type doped region; a third N-type doped region located within the N-type region; a third P-type doped region located within the N-type region, the third P-type doped region being located on the side of the third N-type doped region away from the P-type region; a gate located above the region between the first N-type doped region and the second P-type doped region; wherein the gate is connected to the second P-type doped region, the second N-type doped region and the first P-type doped region are connected to the negative electrode of the electrostatic discharge protection device, and the first N-type doped region, the third N-type doped region and the third P-type doped region are connected to the positive electrode of the electrostatic discharge protection device. The unexpected effect of this invention is that a second P-type doped region is set between the gate and the second N-type doped region, and the gate and the second P-type doped region are connected together. At the same time, an N-type region adjacent to the P-type region is added on one side of the P-type region. A third N-type doped region and a third P-type doped region are set in the N-type region. The second N-type doped region and the first P-type doped region are connected as the negative electrode of the electrostatic discharge protection device, and the first N-type doped region, the third N-type doped region and the third P-type doped region are connected as the positive electrode of the electrostatic discharge protection device. The electrostatic discharge device thus formed has parasitic capacitance and resistance. The coupling between resistance and capacitance can reduce the trigger voltage of the device and increase the holding current.
[0065] An unexpected benefit of this invention is that it combines the advantages of GGNMOS and SCR, giving it a faster turn-on speed, higher discharge current capability, and enhanced anti-latch-up capability.
[0066] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.
Claims
1. An electrostatic discharge protection device, characterized in that, include: Substrate; The P-type region is located within the substrate; An N-type region is located within the substrate, and the N-type region is disposed adjacent to the P-type region. The first N-type doped region is located in the P-type region; The second N-type doped region is located in the P-type region, and the second N-type doped region is located on the side of the first N-type doped region away from the N-type region; A first P-type doped region is located in the P-type region, and the first P-type doped region is located on the side of the second N-type doped region away from the N-type region; The second P-type doped region is located in the P-type region, and the second P-type doped region is located between the first N-type doped region and the second N-type doped region; The third N-type doped region is located in the N-type region; The third P-type doped region is located in the N-type region, and the third P-type doped region is located on the side of the third N-type doped region away from the P-type region; The gate is located above the region between the first N-type doped region and the second P-type doped region; The gate is connected to the second P-type doped region, the second N-type doped region is connected to the first P-type doped region as the negative electrode of the electrostatic discharge protection device, and the first N-type doped region, the third N-type doped region, and the third P-type doped region are connected as the positive electrode of the electrostatic discharge protection device.
2. The electrostatic discharge protection device according to claim 1, characterized in that, The gate, the first N-type doped region, and the second N-type doped region constitute a GGNMOS, with the first N-type doped region serving as the drain of the GGNMOS, the second N-type doped region serving as the source of the GGNMOS, and the gate serving as the gate of the GGNMOS.
3. The electrostatic discharge protection device according to claim 2, characterized in that, The third P-type doped region, the N-type region, and the P-type region constitute a first parasitic transistor. The third P-type doped region serves as the emitter of the first parasitic transistor, the N-type region serves as the base of the first parasitic transistor, and the P-type region serves as the collector of the first parasitic transistor.
4. The electrostatic discharge protection device according to claim 3, characterized in that, The second N-type doped region, the P-type region, and the N-type region constitute a second parasitic transistor. The second N-type doped region serves as the emitter of the second parasitic transistor, the P-type region serves as the base of the second parasitic transistor, and the N-type region serves as the collector of the second parasitic transistor.
5. The electrostatic discharge protection device according to claim 4, characterized in that, An N-type resistor exists within the N-type region, with one end of the N-type resistor connected to the emitter of the first parasitic transistor and the other end connected to the base of the first parasitic transistor; a P-type resistor exists within the P-type region, with one end of the P-type resistor connected to the base of the second parasitic transistor and the other end connected to the emitter of the second parasitic transistor.
6. The electrostatic discharge protection device according to claim 5, characterized in that, There is a parasitic capacitance between the gate and the P-type region, and there is a doped region resistance in the second P-type doped region.
7. The electrostatic discharge protection device according to claim 6, characterized in that, When an electrostatic discharge pulse reaches the positive terminal of the device and the negative terminal is grounded, voltage is coupled to the gate of the GGNMOS, and the GGNMOS turns on. Current flows through the doped region resistor, raising the voltage of the GGNMOS gate. The voltage drop across the P-type region resistor causes the emitter junction of the second parasitic transistor to be forward biased, and the second parasitic transistor turns on. Current flows through the N-type region resistor, causing a voltage drop that causes the emitter junction of the first parasitic transistor to be forward biased, and the first parasitic transistor turns on. The SCR circuit formed by the first parasitic transistor and the second parasitic transistor is turned on, allowing the electrostatic discharge current to be discharged.
8. The electrostatic discharge protection device according to any one of claims 1 to 7, characterized in that, It also includes multiple isolation regions, with the isolation region disposed between the first P-type doped region and the second N-type doped region, the isolation region disposed between the second N-type doped region and the second P-type doped region, and the isolation region disposed between the third N-type doped region and the third P-type doped region.
9. The electrostatic discharge protection device according to any one of claims 1 to 7, characterized in that, The doping concentrations of the first N-type doped region, the second N-type doped region, and the third N-type doped region are all greater than the doping concentration of the N-type region; the doping concentrations of the first P-type doped region, the second P-type doped region, and the third P-type doped region are all greater than the doping concentration of the P-type region.
10. A chip, characterized in that, Includes the electrostatic discharge protection device as described in any one of claims 1 to 9.
Citation Information
Patent Citations
Electrostatic discharge protecting equipment and manufacturing method thereof
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