Implementation method of ultrathin semiconductor and heat dissipation method based on ultrathin semiconductor

Abstract

The invention discloses an ultrathin semiconductor implementation method, which comprises the following steps of: enabling a device layer of a semiconductor substrate of which a functional structure is manufactured to face a slide glass and be combined with the slide glass, so that a substrate (10) of the semiconductor substrate (J1) is exposed; the semiconductor substrate further comprises a corrosion barrier layer and a semiconductor layer which are stacked with the substrate in sequence, and the semiconductor layer comprises a buffer layer and a device layer; the buffer layer is used for preventing the device layer from being influenced by the change of a work function before and after the substrate is thinned and removed and assisting to overcome the charge accumulation problem of the semiconductor layer during dry etching; and corroding the exposed substrate by adopting a first corrosion method to obtain the thinned ultrathin semiconductor, wherein the corrosion barrier layer is used for preventing the semiconductor layer from being corroded. According to the invention, the thickness of the substrate can be reduced as a whole, and even the thinning capability that the thickness is less than 1 [mu] m can be realized; the problems of stress influence, poor uniformity, scratches, particle pollution and the like of a traditional grinding and thinning process are well solved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor thinning technology, and more specifically, to a method for realizing an ultra-thin semiconductor and a heat dissipation method based on an ultra-thin semiconductor. Background Technology

[0002] Currently, the adoption of three-dimensional stacking integration is a consensus in the semiconductor industry, and obtaining more stacking layers and thinner chips is an urgent need in the industry; in addition, with the increase in the number of transistors in chips and the significant increase in computing power, it is necessary to solve the heat dissipation problem through thinner chips.

[0003] However, current thinning methods mainly involve grinding and improvements around grinding. The main problems with current methods include stress effects, difficulty in achieving a thickness of 25μm to reach mass production levels (for large chip particles), poor uniformity (e.g., ±1μm), scratches, and particle contamination. Further improvements are becoming increasingly difficult, especially for ultra-flat wafers with extremely low particle contamination required for future direct bonding methods. Summary of the Invention

[0004] The present invention was proposed in view of the above-mentioned problems.

[0005] According to one aspect of the present invention, a method for realizing an ultrathin semiconductor is provided, the method comprising the following steps: bonding the device layer (32) of a semiconductor substrate (J1) with completed functional structure fabrication to a carrier wafer (Z1), thereby exposing the substrate (10) of the semiconductor substrate (J1); wherein the semiconductor substrate (J1) comprises a substrate (10), an etching barrier layer (20), and a semiconductor layer (30) stacked sequentially, the semiconductor layer (30) comprising a buffer layer (31) and a device layer (32); wherein only the device layer (32) has completed the semiconductor device functional structure fabrication of an integrated circuit or device; the buffer layer (31) is used to prevent the device layer (32) from being affected by changes in work function before and after the substrate (10) is thinned and removed; The exposed substrate (10) is etched away using the first etching method to obtain a thinned ultrathin semiconductor. The etching barrier layer (20) is used to prevent the etchant used in the first etching method from etching the semiconductor layer (30). The lower surface of the carrier (Z1) is resistant to the etchant of the first etching method.

[0006] In one embodiment, the corrosion barrier layer (20) is made of an insulating material.

[0007] In one embodiment, after the step of etching away the exposed substrate (10) using the first etching method, the method further includes: etching away the exposed etching barrier layer (20) using the second etching method.

[0008] In one embodiment, the substrate (10) and semiconductor layer (30) of the semiconductor substrate (J1) to be thinned are electrically connected at edge and / or internal locations.

[0009] In one embodiment, the material through which the substrate (10) and the semiconductor layer (30) are electrically connected is homogeneous with the semiconductor layer (30), non-homogeneous, or only partially non-homogeneous.

[0010] In one embodiment, the portion of the non-homogeneous material is fabricated by first etching away the electrically connected material of the homogeneous material before deposition.

[0011] In one embodiment, the carrier wafer includes one or more composites of the semiconductor substrate (J1), silicon / germanium / compound semiconductor bare wafer, silicon / germanium / compound semiconductor with completed functional structure fabrication, diamond, silicon dioxide, glass, ceramic, blue film, carrier tape, and protective adhesive.

[0012] In one embodiment, the substrate (Z1) further includes one or more layers of ultrathin semiconductors implemented using the above-described ultrathin semiconductor implementation method; wherein, the ultrathin semiconductors of the multiple layers have different functions or at least two layers are the same.

[0013] In one embodiment, the lower surface of the substrate (Z1) is provided with at least one of a protective layer, a protective film, and an adhesive coating, so that the lower surface of the substrate (Z1) can withstand corrosion by the corrosive agent of the first corrosion method.

[0014] In one embodiment, the first etching method employs at least one of liquid-phase, gas-phase, and plasma methods. In one embodiment, the substrate (10) is a single layer or a composite layer of at least two layers; and / or the buffer layer (31) is a single layer or a composite layer of at least two layers.

[0015] In one embodiment, at least one of the composite layers of the substrate (10) or the buffer layer (31) is low-resistivity.

[0016] In one embodiment, the corrosion barrier layer (20) is a single layer or a composite layer of at least two layers; the composite layer of the corrosion barrier layer (20) includes at least a barrier layer compatible with the semiconductor layer (30), and the barrier layer compatible with the semiconductor layer (30) is connected to the semiconductor layer (30).

[0017] In one embodiment, the substrate (10) and the semiconductor layer (30) are electrically connected through the substrate (10) and the buffer layer (31).

[0018] In one embodiment, the fabrication of the functional structure of the semiconductor substrate (J1) includes the fabrication of at least one functional structure in an integrated circuit, electronic device, optical device, electronic circuit, optical path, microfluidic path, detector, and MEMS system.

[0019] In one embodiment, prior to the step of placing the semiconductor substrate (J1) with the completed functional structure fabrication onto the carrier (Z1) and bonding it thereto, the method further includes: pre-processing the semiconductor substrate (J1); the pre-processing includes one or more of pre-thinning, pre-dicing, planarization, cleaning, and bonding layer activation.

[0020] In one embodiment, after the step of placing the semiconductor substrate (J1) with the completed functional result on the carrier (Z1) and bonding it thereto, and before the step of etching away the exposed substrate (10) to obtain the thinned ultrathin semiconductor using a first etching method, the embodiment further includes: further processing the semiconductor substrate (J1) to be thinned; The further processing includes one or more of the pre-thinning, cleaning, and edge corrosion protection; only one of the further processing and the pre-processing includes the pre-thinning; the edge corrosion protection refers to the protective treatment of the edge of the semiconductor substrate (J1) to be thinned against corrosion by the corrosive agent of the first corrosion method.

[0021] In one embodiment, the ultrathin semiconductor undergoes post-processing; the post-processing includes at least one of the following steps: growing material, cleaning, coating with resist, photolithography, developing, etching holes, fabricating lines, removing resist, removing etched edge residue, passivating etched edges, removing the barrier layer, growing a low bonding temperature insulating layer, removing substrate edges, activating the bonding layer, bonding with other wafers, and separating the wafers.

[0022] In one embodiment, the post-processing is used to achieve electrical and / or optical connections between the substrate (Z1) and the ultrathin semiconductor.

[0023] In one embodiment, the carrier (Z1) is electrically connected to the ultrathin semiconductor through a conductive material or a composite material formed of at least two materials; the composite material includes at least one conductive material.

[0024] In one embodiment, the composite material in which the carrier (Z1) is electrically connected to the ultrathin semiconductor includes an adhesive layer; and / or, the composite material in which the carrier (Z1) is electrically connected to the ultrathin semiconductor includes an insulating layer, the insulating material being used to achieve electrical connection and semiconductor isolation.

[0025] In one embodiment, the present invention also provides a heat dissipation method based on an ultrathin semiconductor, wherein a heat dissipation structure is mounted on the back side of the ultrathin semiconductor implemented using the above-described ultrathin semiconductor implementation method.

[0026] In one embodiment, the heat dissipation structure is electrically connected to the ultrathin semiconductor.

[0027] The above technical solution utilizes an etching barrier layer to block the influence of etchants on the semiconductor layer during the substrate etching process, while a buffer layer prevents the device layer from being affected by changes in the work function before and after substrate removal. Therefore, it can be understood that the ultrathin semiconductor obtained after etching achieves overall thinning by removing the substrate thickness. Furthermore, the etching barrier layer can be removed even after the substrate is etched away, thus achieving significant thinning, even reaching thicknesses of less than 1 μm. This provides ultrathin semiconductors for 3D chip integration. Simultaneously, the buffer layer is electrically connected to both the substrate and the semiconductor layer, effectively addressing the issue when the etching barrier layer is an insulating layer (such as an insulator). The method addresses the charge accumulation problem in silicon (S) semiconductor layers during dry etching, demonstrating good process compatibility with traditional semiconductor processes (such as bulk silicon processes) in integrated circuit and other semiconductor fabrication. Due to the etching method, it effectively solves problems such as stress effects, poor uniformity, scratches, and particle contamination inherent in traditional grinding and thinning processes, and overcomes the severe challenge of ultra-flat wafers with extremely low particle contamination required for methods like direct bonding. The heat dissipation method based on ultra-thin semiconductors provided in this solution offers a 1-2 order of magnitude improvement in heat dissipation capacity compared to conventional methods. Furthermore, the shorter electrical connection length helps resolve power supply issues. Overall, the ultra-thin semiconductor implementation method provided in this solution effectively addresses the challenges of 3D chip integration and heat dissipation.

[0028] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and in order to make the above and other objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description

[0029] The above and other objects, features, and advantages of the present invention will become more apparent from the more detailed description of the embodiments of the invention in conjunction with the accompanying drawings. The drawings are provided to further illustrate the embodiments of the invention and form part of the specification. They are used together with the embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings, the same reference numerals generally represent the same parts or steps.

[0030] Figure 1 A flowchart illustrating an ultrathin semiconductor implementation method according to an embodiment of the present invention; Figure 2 for Figure 1 A schematic diagram of the semiconductor substrate; Figure 3 To execute Figure 1 A schematic diagram following step S1; Figure 4 To execute Figure 1 A schematic diagram following step S2; Figure 5 The effect of back gate (substrate) bias (Vb) on the characteristics of FDSOI devices; Figure 6 and Figure 7 Two schematic diagrams illustrating the electrical connection between the substrate and the semiconductor layer; Figure 8 Another flowchart of the ultrathin semiconductor implementation method provided in the embodiments of the present invention; Figures 9(a) and 9(b) are schematic diagrams of two types of pre-cut strips; Figures 10(a) to 10(d) are several schematic diagrams of the three-dimensional stacked structure of two-layer integrated circuits; Figure 11 This is a schematic diagram of a three-dimensional stacked structure of a three-layer integrated circuit; Figure 12(a) and Figure 12(b) show two schematic diagrams of the electrical connection between the back electrode and the semiconductor layer; Figure 13 A flowchart illustrating an ultrathin semiconductor implementation method according to another embodiment of the present invention; Figure 14 To complete Figure 13 A schematic diagram following step S3; Figure 15 A schematic diagram of a heat dissipation method based on ultrathin semiconductors provided in an embodiment of the present invention; Figures 16(a) to 16(c) show several schematic diagrams of the heat dissipation structure and the electrical connection of the ultra-thin semiconductor. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of the present invention more apparent, exemplary embodiments according to the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are merely a part of the embodiments of the present invention, and not all of the embodiments of the present invention. It should be understood that the present invention is not limited to the exemplary embodiments described herein. Based on the embodiments of the present invention described herein, all other embodiments obtained by those skilled in the art without inventive effort should fall within the protection scope of the present invention. Example 1

[0032] Figure 1 A flowchart illustrating an embodiment of an ultrathin semiconductor implementation method provided by the present invention; Figure 2 for Figure 1 A schematic diagram of the semiconductor substrate; Figure 3 To execute Figure 1 A schematic diagram following step S1; Figure 4 To execute Figure 1 The diagram following step S2 is shown below. Please refer to it as well. Figures 1-4 The ultra-thin semiconductor implementation method provided in this embodiment belongs to the field of semiconductor packaging thinning process methods, and the ultra-thin semiconductor implementation method includes the following steps: Step S1: The device layer (32) of the semiconductor substrate J1 with the completed functional structure is oriented toward the carrier Z1 and bonded to it, so that the substrate (10) of the semiconductor substrate (J1) is exposed; wherein, the semiconductor substrate J1 also includes an etching barrier layer 20 and a semiconductor layer 30 stacked sequentially with the substrate 10, the semiconductor layer 30 including a buffer layer 31 and the device layer 32; the semiconductor device functional structure of the integrated circuit or device is completed only on the device layer 32; the buffer layer 31 is used to prevent the device layer 32 from being affected by the change in work function before and after the substrate 10 is thinned and removed.

[0033] The function of buffer layer 31 is explained in detail below. Please refer to [link / reference needed]. Figure 5 ,exist Figure 5 The image shows a semiconductor substrate without a buffer layer 31, which can be called an FDSOI substrate (Fully Depleted Silicon On Insulator). This substrate has only one device layer 32 as the FDSOI layer; therefore, the device is fabricated on the FDSOI layer. Figure 5 The diagram illustrates multiple variations of the threshold voltage (Vth) of an FDSOI device at temperature T and various back gate (substrate) biases (Vb). As can be seen from the diagram, the characteristic threshold voltage Vth of the FDSOI device is significantly affected by temperature. Removing substrate 10 causes a change in the work function, similar to a change in substrate bias, which significantly affects device characteristics. Since integrated circuits contain hundreds of billions of transistors, this effect requires strict control. Therefore, in this embodiment, a buffer layer 31 is used to isolate this effect.

[0034] In step S1, the semiconductor substrate J1 and the carrier Z1 can be combined by any one or at least two of the following methods: bonding, adhesive bonding, and wax bonding.

[0035] Step S2: The substrate 10 on the semiconductor substrate J1 to be thinned on the carrier Z1 is etched away using the first etching method to obtain the thinned ultrathin semiconductor.

[0036] The corrosion barrier layer 20 is used to prevent the corrosive agent used in the first corrosion method from corroding the semiconductor layer 30; the lower surface of the substrate Z1 is resistant to corrosion by the corrosive agent of the first corrosion method.

[0037] In this embodiment, to avoid the first etching method in step S2 affecting the lower surface of the substrate Z1, the lower surface of the substrate Z1 is resistant to the corrosion by the corrosive agent of the first etching method. Preferably, the substrate Z1 is made of a material resistant to the corrosion by the corrosive agent of the first etching method, such as ceramic. Of course, in practical applications, materials that are inherently susceptible to corrosion can also be selected. In this case, preferably, at least one of the following methods can be used: forming a protective layer, applying a protective film, and applying an adhesive to the lower surface of the substrate Z1, thereby making the lower surface of the substrate Z1 resistant to the corrosion by the corrosive agent of the first etching method. More preferably, in practical applications, the surface of the outer edge of the substrate Z1 can also be treated, so that the surface of the outer edge of the substrate Z1 can also be resistant to the corrosion by the corrosive agent of the first etching method, thereby further protecting the substrate Z1.

[0038] In this embodiment, the first etching method in step S2 can be a liquid-phase method, a gas-phase method, a plasma method, or a combination of at least two methods. More specifically, using a combination of at least two methods can specifically mean: sequentially performing multiple etching operations or multiple etching operations at corresponding etching locations such as etching chambers, tanks, or turntables, or performing multiple etching operations at the same etching location using different etching components. Further specifically, when the substrate 10 is made of silicon, the liquid-phase method can be one or more of KOH and TMAH, and the gas-phase method can be one or more of TMAH gas and XeF2 gas mixed together.

[0039] In the above, the ultrathin semiconductor referred to in this embodiment refers to the semiconductor substrate J1 obtained after the substrate 10 is etched. Therefore, the thickness of the ultrathin semiconductor refers to the thickness of the semiconductor substrate J1 after etching. More specifically, the thickness of the ultrathin semiconductor includes the thickness of the etching barrier layer 20 + the thickness of the semiconductor layer 30 and the functional structures further fabricated thereon.

[0040] In summary, in this embodiment, by using the steps S1-S2 described above, the etching barrier layer 20 can block the influence of the etchant on the semiconductor layer 30 during the etching process of removing the substrate 10. The buffer layer 31 prevents the device layer 32 from being affected by the change in work function before and after substrate removal. Therefore, the ultrathin semiconductor obtained after etching can reduce the overall thickness of the substrate 10. Furthermore, the etching barrier layer 20 can be removed even after the substrate 10 is etched away, thereby achieving further thinning. Ultimately, it can even achieve a thinning capability of less than 1 μm for the ultrathin semiconductor, providing ultrathin semiconductors for the three-dimensional integration of chips. In addition, due to the use of etching, the problems of stress influence, poor uniformity, scratches, and particle contamination in traditional grinding thinning processes can be effectively overcome.

[0041] In this embodiment, preferably, the etching barrier layer 20 is made of an insulating material, that is, the semiconductor substrate J1 is a semiconductor on an insulator. In this case, it is even more preferably that the substrate 10 and the semiconductor layer 30 in the semiconductor substrate J1 to be thinned are electrically connected, so as to avoid the problem of charge accumulation in the semiconductor substrate J1 during dry etching.

[0042] The following describes in detail how to implement the substrate 10 and the semiconductor layer 30. Specifically, (1) an electrical connection is implemented at the edge of the semiconductor substrate J1, and (2) an electrical connection is implemented inside the semiconductor substrate J1. In practical applications, either (1) or (2) can be used, or both (1) and (2) can be used.

[0043] Please see Figure 6 , specifically, Figure 6 A schematic diagram illustrating the electrical connection between the substrate and the semiconductor layer; please refer to [link / reference]. Figure 6 ,in, Figure 6 The right-hand figure shows that the substrate 10 and the semiconductor layer 30 are electrically connected at positions 46 and 47 at the edge of the semiconductor substrate J1 (46 and 47 can be specifically conductive thin films). Figure 6 The left side of the diagram shows the electrical connection between substrate 10 and semiconductor layer 30 at 41 and 42 within semiconductor substrate J1. Although Figure 6 The diagram shows that either the electrical connection between the substrate 10 and the semiconductor layer 30 is achieved at the edge, or it is achieved by internal fabrication. Of course, in practical applications, the electrical connection between the substrate 10 and the semiconductor layer 30 can also be achieved by both edge fabrication and internal fabrication.

[0044] Because the plasma in dry etching is charged, the charge accumulated in bulk silicon processes can be effectively conducted away through the bulk silicon and chuck structure. However, in semiconductor-on-insulator (STI) processes, the lack of electrical connection between the substrate 10 and the semiconductor layer 30 prevents this pathway. Alternatively, the absence of the buffer layer 31 can lead to widespread semiconductor islands in the device layer 32 under the STI structure. Consequently, the charge accumulation characteristics during dry etching differ from those of traditional bulk silicon processes, resulting in different micro-loading / loading effects and making compatibility with traditional semiconductor processes difficult. Therefore, in this embodiment, the structure of electrically connecting the substrate 10 and the semiconductor layer 30 through this invention achieves electrical connection between the single-crystal silicon substrate and the silicon on the insulator. Combined with the buffer layer 31, this effectively overcomes the charge accumulation problem of silicon on the insulator during dry etching when the barrier layer is an insulating layer, thus achieving compatibility with traditional bulk silicon processes. Therefore, overall, this invention can effectively achieve mass production of ultrathin semiconductors.

[0045] In this embodiment, the material that enables the electrical connection between the substrate (10) and the semiconductor layer (30) is a homogeneous material, a non-homogeneous material, or only a portion of a non-homogeneous material with the semiconductor layer (30). That is, the materials of 41, 42, 46, and 47 that electrically connect the substrate 10 and the semiconductor layer 30 are homogeneous materials, non-homogeneous materials, or only a portion of a non-homogeneous material with the semiconductor layer 30.

[0046] Among them, homogeneous materials refer to materials with the same chemical composition as the main material, and it is not limited to whether the doping components or concentrations are the same or consistent; heterogeneous materials refer to materials with different chemical compositions as the main material, and it is not limited to whether the doping components or concentrations are the same or consistent.

[0047] The homogeneous materials of the substrate (10) and the semiconductor layer (30) include polycrystalline, amorphous, or single-crystal materials of homogeneous composition; the polycrystalline, amorphous, or single-crystal materials of homogeneous composition are formed by epitaxy and / or deposition. More specifically, the homogeneous materials form the electrical connection between the substrate 10 and the semiconductor layer 30 through doping or self-leakage; the non-homogeneous materials include at least one of semiconductors, silicides, conductive oxides, and metallic materials of different compositions.

[0048] To further clarify, only a portion of the above refers to non-homogeneous materials, which are fabricated by first etching away the electrically connected homogeneous materials before deposition. To explain in more detail... Figure 6 The left-hand scheme is explained below. 41 and 42 are initially formed using a material homologous to semiconductor layer 30. During the fabrication of functional structures, such as dry etching, the upper portions of 41 and 42 are etched away (i.e.,...). Figure 7 (The locations of 411 and 412 in the middle), to form 411 and 412 by redepositing a material of different nature from the semiconductor layer 30. This different material can be a metal or other material, and the final result is as follows: Figure 7 As shown, this approach avoids the contamination and other impacts that can occur when using heterogeneous materials such as metals as electrical connection materials from the outset, which could lead to the fabrication of subsequent functional structures. Although in Figure 7 In this process, only the upper part of 41 and 42 is etched away, and then a material different from the semiconductor layer 30 is deposited. In practical applications, the entire 41 and 42 can also be etched away according to actual needs, and then a non-homogeneous material can be deposited.

[0049] Although Figure 6 All of these are achieved through 41, 41, 46, and 47, which realize the electrical connection between the substrate 10 and the semiconductor layer 30. Figure 7 The electrical connection between the substrate 10 and the semiconductor layer 30 is achieved through 411 and 41, as well as 412 and 42. However, in practical applications, the electrical connection between the substrate 10 and the semiconductor layer 30 can also be achieved through the electrical connection between the substrate 10 and the buffer layer 31. That is to say, 411 and 412 can also be insulating materials.

[0050] It should be noted that in step S1, the fabrication of functional structures includes the fabrication of at least one functional structure in integrated circuits, electronic devices, optical devices, electronic circuits, optical pathways, microfluidic pathways, detectors, and MEMS systems. In other words, the fabrication of functional structures includes the fabrication of semiconductor functional structures completed in device layer 32. These semiconductor device functional structures include structures such as wells, sources, or drains.

[0051] In this embodiment, the substrate 10 is a single layer or a composite layer of at least two layers, and / or the buffer layer 31 is a single layer or a composite layer of at least two layers. The composite layer of at least two layers can refer to layers with the same main chemical composition but different doping components and / or doping concentrations; it can also refer to layers with different main chemical compositions, where the doping components or doping concentrations are not specifically limited. More preferably, at least one layer in the composite layer of the substrate 10 and the buffer layer is low-resistivity.

[0052] The following examples will be used to illustrate this further: (Example 1) The substrate 10 includes a first layer and a low-resistivity layer, which is located between the first layer and the etch barrier layer 20; (Example 2) The buffer layer 31 includes a first layer and a low-resistivity layer, the low-resistivity layer being located between the corrosion barrier layer 20 and the second layer, or the low-resistivity layer being located between the first layer and the device layer 32. (Example 3) The substrate 10 includes a first layer and a first low-resistivity layer, and the buffer layer includes a second layer and a second low-resistivity layer, wherein the first low-resistivity layer is located between the first layer and the etch barrier layer 20, and the second low-resistivity layer is located between the etch barrier layer 20 and the second layer.

[0053] In this embodiment, the corrosion barrier layer 20 is a single layer or a composite layer of at least two layers; the composite layer includes at least a barrier layer compatible with the semiconductor layer 30, and the barrier layer compatible with the semiconductor layer 30 is connected to the semiconductor layer 30.

[0054] The following examples will be used to illustrate this further: (Example 4) The corrosion barrier layer 20 includes a first layer and a barrier layer, with the barrier layer located between the first layer and the semiconductor layer 30; (Example 5) The etching barrier layer 20 includes a first layer and a barrier layer, and the buffer layer 31 includes a second layer and a low-resistivity layer. The barrier layer is located between the first layer and the low-resistivity layer, and the first layer is located between the substrate and the barrier layer. The low-resistivity layer is located between the barrier layer and the second layer, and the second layer is located between the low-resistivity layer and the device layer 32.

[0055] It should be noted that, in this embodiment, the thickness of the buffer layer 31 is any one of 50nm~800nm ​​or 1μm~150μm. The specific thickness is based on the basic requirement that the work function of the device layer 32 is not affected by the thinning and removal of the substrate 10. Other thicknesses can be selected according to actual needs and are not specifically limited.

[0056] In this embodiment, the semiconductor layer 30 is a type of silicon, germanium, or compound semiconductor; the substrate 10 and the semiconductor layer 30 are either homogeneous or non-homogeneous, and the definitions of homogeneous and non-homogeneous can be found above.

[0057] In this embodiment, the carrier wafer includes one or more composites selected from the following: a semiconductor substrate J1, a silicon / germanium / compound semiconductor bare die, a silicon / germanium / compound semiconductor with a completed functional structure fabrication, diamond, silicon dioxide, glass, ceramic, blue film, carrier tape, and protective adhesive. When the carrier wafer uses protective adhesive, the adhesive is bonded to the semiconductor substrate (J1) by coating. The silicon / germanium / compound semiconductor bare die refers to a silicon / germanium / compound semiconductor without a functional structure fabrication. The functional structure fabrication includes the fabrication of at least one functional structure in integrated circuits, electronic devices, optical devices, electronic circuits, optical pathways, microfluidic pathways, detectors, and MEMS systems.

[0058] The carrier Z1 also includes one or more layers of ultrathin semiconductors implemented by the ultrathin semiconductor implementation method provided in the embodiments of the present invention, and / or one or more layers of ultrathin semiconductors further processed to obtain reprocessed ultrathin semiconductors, wherein the functions of each layer of the multilayer ultrathin semiconductor are different or at least two layers are the same. Example 2

[0059] Figure 8 A flowchart illustrating the ultrathin semiconductor implementation method provided in this embodiment of the invention; please refer to [link / reference]. Figure 8Compared with Embodiment 1 above, this embodiment of the invention also includes steps S1 to S2. Please refer to Embodiment 1 above for the content of steps S1 to S2, which will not be repeated here. The following only describes the differences between this embodiment and the above embodiment.

[0060] In this embodiment, before step S1, step S0 is further included: pre-processing the semiconductor substrate J1; the pre-processing includes one or more of pre-thinning, pre-dicing, planarization, cleaning, and bonding layer activation.

[0061] After step S1 and before step S2, step S12 is also included: further processing of the semiconductor substrate J1 to be thinned.

[0062] Step S2 is followed by step S5: post-processing of the ultrathin semiconductor.

[0063] In this embodiment, pre-dicing can also be called pre-cutting, which can be understood as using a laser or dicing blade to cut the semiconductor substrate J1 as required in advance. Typically, the cutting is done on the front side of the semiconductor substrate J1 without penetrating the substrate 10 of the semiconductor substrate J1.

[0064] Please refer to Figures 9(a) and 9(b). In Figures 9(a) and 9(b), the pre-scribes are directly scribed onto the substrate 10 but do not penetrate it. During cutting, grooves 81, 82, 83, and 84 are formed. After this, the chip separation effect can be achieved by thinning. Since this invention uses chemical etching, if the substrate 10 and the semiconductor 30 are made of the same material, the etchant may penetrate the semiconductor 30 on the insulator after reaching the grooves of the pre-scribe. Therefore, in order to protect the chips 71, 72, and 73, as shown in Figure 9(a), a deep trench 22 can be used to isolate and prevent the etchant from penetrating the chips 71, 72, and 73; and / or, as shown in Figure 9(b), after pre-scribe, a protective material 26 can be grown around the scribe lines by deposition or other methods to prevent the etchant from penetrating the chips 71, 72, and 73. Using the method shown in Figure 9(b), since additional material 26 is grown and reaches the substrate 10, the material 26 usually remains after the substrate 10 is removed, so it needs to be cleaned by means of etching or polishing.

[0065] Of course, in practical applications, the pre-diced die may not penetrate the insulating layer 20, such as only reaching the buffer layer 31, or the pre-diced die may only reach the insulating layer 20. In reality, due to the difficulty in controlling the dicing accuracy, it may partially reach the buffer layer 31 and partially reach the insulating layer 20. The insulating layer is used to prevent the etching solution from penetrating the chips 71, 72, and 73. After etching is completed, the chip is further separated by dicing.

[0066] In this embodiment, in order to facilitate the bonding of the semiconductor substrate J1 with the carrier Z1, the bonding layer can be activated by wet activation, plasma activation, or gas phase compound activation. Of course, in practical applications, multiple activation methods can be used in combination.

[0067] Further processing includes one or more of pre-thinning, cleaning, and edge corrosion protection; only one of the further processing and pre-processing includes pre-thinning; edge corrosion protection refers to the protective treatment of the edge of the semiconductor substrate J1 to be thinned against corrosion by the etchant of this first corrosion method.

[0068] Post-processing includes at least one of the following steps: growing materials, cleaning, coating, photolithography, developing, etching holes, fabricating lines, removing resist, removing etched edge residue, passivating etched edges, removing barrier layers, growing low bonding temperature insulating layers, removing substrate edges, activating bonding layers, bonding with other wafers, and separating wafers.

[0069] In this embodiment, post-processing steps are used to achieve electrical and / or optical connections between the carrier Z1 and the ultrathin semiconductor. Specifically, as shown in Figures 10(a) to 10(d), when the carrier and the semiconductor substrate on the insulator are silicon-based integrated circuits and are electrically connected, the single-layer integrated circuit C1, acting as the carrier Z1, is combined with the ultrathin semiconductor C2 to achieve a two-layer integrated circuit three-dimensional stacked structure. In Figure 10(a), the insulating layer 260 is used to further isolate the adverse effects of connection lines (such as 911) and external electrical connections (such as 921, 922) on the chip 72. This approach is a preferred solution when the buffer layer of the ultrathin semiconductor C2 is relatively thin. The passivation layer 27 is used to protect internal electrical connections (such as 911) and other structures, as well as to prevent moisture and metal ions from contaminating the chip 72, thus improving the chip's lifespan after stacking. It should be noted that the passivation layer 27 often uses a composite layer structure (such as silicon dioxide + silicon nitride).

[0070] More specifically, Figures 10(b) and 10(d) use a tight-fitting method (such as bonding) to make inter-chip electrical connections (such as 931, 932, 941, 942), and then make electrical connections (such as 904, 906, 907, 908) through the original electrical connection structure or through etching, through-hole fabrication, etc. The newly made electrical connection structure (such as 923, 924) forms an electrical connection with the outside. The electrical connection structure with the outside (such as 923, 924) can be made on C1 as a carrier, as shown in Figure 10(d); or it can be made on the ultrathin semiconductor C2, that is, the ultrathin semiconductor C2 as a carrier Z1, as shown in Figure 10(b).

[0071] Figures 10(a) and 10(c) show the use of etching to create through-holes for inter-chip electrical connections (e.g., 904, 906, 903, 905); and further fabrication of connecting lines, electrical connections between C1 and C2 (e.g., 911) and electrical connections between C1, C2 and the outside (e.g., 921, 922); the electrical connections between C1 and C2 (e.g., 911) and the electrical connection structures between C1, C2 and the outside (e.g., 923, 924) can be fabricated on C1 as a carrier, as shown in Figure 10(a); or they can be fabricated on the ultrathin semiconductor C2, as shown in Figure 10(c). Figure 11 A schematic diagram of a three-dimensional stacked structure of a three-layer integrated circuit is shown, such as... Figure 11 As shown, the method involves using the ultrathin semiconductor C2 on the already thinned C1 as a carrier for the ultrathin semiconductor C3. The specific method is described in Figures 10(a) to 10(d) above, and will not be repeated here.

[0072] The aforementioned electrical connections can be formed by one material or multiple composite materials, and / or by connecting one material or multiple composite materials together. When using a direct bonding method, the electrical connection materials of each integrated circuit layer are not required to be the same; each integrated circuit layer is shown as C1 and C2 in Figures 10(a) to 10(d). The electrical connection materials used to form three-dimensional integration, one material or multiple composite materials, contain at least one conductive material.

[0073] The composite material for electrically connecting the aforementioned carrier Z1 to the ultrathin semiconductor includes an adhesive layer and / or an insulating layer, which isolates the electrical connection from the semiconductor. Similar to the schematic diagrams of the back electrode and semiconductor layer electrical connection shown in Figures 12(a) and 12(b), a metal layer 90 is first formed on the corrosion barrier layer 20 as the back electrode. The chip 71 is electrically connected to the metal layer 90 on the back side through electrical connection structures 903, 904, 901, and 902. In Figure 12(a), 261 and 262 are adhesive materials to ensure the electrical connection lifespan; 263 and 264 are insulating materials, with the adhesive material surrounding the conductive material; the insulating material surrounds the adhesive material. Of course, in practical applications, the composite material may only include an adhesive layer and not an insulating layer, as shown in Figure 12(b); or, the composite material may include an insulating layer but not an adhesive layer. Both methods fulfill at least one of multiple functions, including insulation, prevention of metal ion diffusion, and adhesive layer function. The specific composite layer may be one, two, or more layers, depending on the actual requirements of the semiconductor layer 30 and the electrical connection conductive material, and will not be elaborated on one by one.

[0074] It should be noted that, in practical applications, the corresponding preprocessing steps can be selected in step S0, and / or, the corresponding further processing steps can be selected in step S12, and / or, the corresponding post-processing steps can be selected in step S5, depending on the actual needs. Example 3

[0075] Figure 13 This is a flowchart illustrating an ultrathin semiconductor implementation method according to another embodiment of the present invention. Figure 14 To execute Figure 13 Please refer to the diagram following step S3. Figure 13 and Figure 14 The ultrathin semiconductor implementation method provided in this embodiment also includes the above steps S1 to S2. Please refer to Embodiment 1 above for the content of steps S1 to S2, which will not be repeated here. The following only describes the differences between this embodiment and the above embodiment.

[0076] In this embodiment, preferably, after step S2, the method further includes step S3, in which the exposed corrosion barrier layer 20 is removed by etching using a second etching method. Specifically, in step S3, different etchants can be used to etch the corrosion barrier layer 20, that is, both the substrate 10 and the corrosion barrier layer 20 are etched using the same etching method, but the etchants used are different.

[0077] Therefore, in this embodiment, the thickness of the ultrathin semiconductor only includes the thickness of the semiconductor layer 20 and the functional structures further fabricated thereon, such as... Figure 14 As shown.

[0078] In this embodiment, since the thermal conductivity of the etching barrier layer 20 is poor (by 1 to 2 orders of magnitude), the etching barrier layer 20 is further removed by step S3, which not only helps to achieve ultra-thin semiconductor thickness but also helps to dissipate heat from the chip.

[0079] The ultrathin semiconductor implementation method provided in this embodiment, compared with Embodiment 1, after thinning and removing the thickness of the substrate 10, further removes the etching barrier layer 20 by step S3, thereby achieving a greater degree of thinning and better heat dissipation. When removing the etching barrier layer 20 in step S3, since a different etchant than the etching substrate is used, the buffer layer 31 itself is usually resistant to the etchant corrosion of the etching barrier layer 20.

[0080] It should be noted that in this embodiment, steps S0, S12 and S5 in embodiment 2 above can also be included. Step S0 is located before S1, step S12 is located between step S1 and step S2, and S5 can be located after step S3. Example 4

[0081] Figure 15Please refer to several schematic diagrams illustrating the heat dissipation method based on ultra-thin semiconductors provided in embodiments of the present invention. Figure 15 The heat dissipation method based on ultrathin semiconductors provided herein is used to dissipate heat from an ultrathin semiconductor implemented using the ultrathin semiconductor implementation method described in the above embodiments. The heat dissipation method includes mounting a heat dissipation structure on the back side of the ultrathin semiconductor.

[0082] like Figure 15 As shown, a heat dissipation structure D01 is mounted on the back side of the thinned ultrathin semiconductor, and one side of the integrated circuit 71 of the ultrathin semiconductor is mounted on a PCB board or a rigid carrier board; the ultrathin semiconductor uses the method described in the above embodiment to etch away both the substrate 10 and the etching barrier layer 20, therefore, in this Figure 15 The heat dissipation structure D01 can be directly installed on the exposed buffer layer 31. At this time, the heat dissipation structure D01 is less than 1μm away from the chip 71, and there is no influence from the corrosion barrier layer 20. It can have a super heat dissipation capacity (up to 1 to 2 orders of magnitude higher than the existing conventional heat dissipation methods).

[0083] Of course, in practical applications, ultrathin semiconductors use the method described in the above embodiment to remove only the substrate 10 by etching. In this case, the heat dissipation structure D01 can be installed on the etching barrier layer 20, especially on the etching barrier layer 20 of the composite layer. In particular, the etching barrier layer 20 also takes into account the thermal conductivity of the composite layer (such as using a thin silicon dioxide + silicon nitride / aluminum nitride composite material for silicon-based semiconductors), taking into account heat dissipation, insulation and prevention of metal ion contamination.

[0084] The aforementioned heat dissipation structure D01 can be an air-cooled or liquid-cooled heat dissipation structure; preferably, the liquid cooling liquid is a low-temperature liquid that can directly contact the ultra-thin semiconductor for heat conduction.

[0085] In practical applications, the heat dissipation structure is electrically connected to the ultrathin semiconductor. Specifically, as shown in Figures 16(a) to 16(c), after obtaining the ultrathin semiconductor, the semiconductor substrate on the insulator of the integrated circuit or device fabricated after substrate removal is further processed. First, a metal layer 90 is formed on the etching barrier layer 20, as shown in Figure 16(a). Then, the heat dissipation structure D01 is installed on the metal layer 90, and the chip 71 is electrically connected to the metal layer 90 on the back side through electrical connection structures 903, 904, 901, and 902. The heat dissipation structure D01 is electrically connected to the outside through conductive materials E02 and E01, as shown in Figure 16(b). To ensure the connection effect, E02 can also be further strengthened to the metal layer 90 through the E03 electrical connection structure, as shown in Figure 16(c). It should be noted that the electrical connection structures 903, 904, 901, and 902 are usually good conductors of heat, which is also important for balancing the heat dissipation effect of the etching barrier layer 20.

[0086] In this embodiment, the heat dissipation structure D01 is electrically connected to the ultra-thin semiconductor via a ground electrode connection. The specific connection will depend on actual requirements.

[0087] The heat dissipation method based on ultrathin semiconductors provided in this invention can achieve excellent heat dissipation of ultrathin semiconductors, with a heat dissipation capacity that is 1 to 2 orders of magnitude higher than that of conventional heat dissipation methods; at the same time, it can also provide good power supply capability.

[0088] Although exemplary embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above exemplary embodiments are merely illustrative and are not intended to limit the scope of the invention thereto. The listed values ​​are generally central values ​​and may be varied as necessary within the spirit of the invention (e.g., 15%) depending on actual needs. Various changes and modifications can be made therein by those skilled in the art without departing from the scope and spirit of the invention. All such changes and modifications are intended to be included within the scope of the invention as claimed in the appended claims.

[0089] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0090] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed.

[0091] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0092] Similarly, it should be understood that, in order to streamline the invention and aid in understanding one or more of the various aspects of the invention, features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof in the description of exemplary embodiments of the invention. However, this approach should not be construed as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as reflected in the corresponding claims, its inventive point lies in solving the corresponding technical problem with fewer features than all of those in a single disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of the invention.

[0093] Those skilled in the art will understand that, apart from the mutual exclusion of features, all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or elements of any method or apparatus so disclosed may be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature that serves the same, equivalent, or similar purpose.

[0094] Furthermore, those skilled in the art will understand that although some embodiments herein include certain features included in other embodiments but not others, combinations of features from different embodiments are intended to be within the scope of the invention and form different embodiments. For example, in the claims, any of the claimed embodiments can be used in any combination.

[0095] It should be noted that the above embodiments are illustrative of the invention and not restrictive, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

[0096] The above are merely specific embodiments or descriptions of the present invention, and the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. The scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for realizing ultrathin semiconductors, characterized in that, The method includes the following steps: The device layer (32) of the semiconductor substrate (J1) with the completed functional structure is bonded to the carrier (Z1), so that the substrate (10) of the semiconductor substrate (J1) is exposed; wherein, the semiconductor substrate (J1) also includes an etching barrier layer (20) and a semiconductor layer (30) stacked sequentially with the substrate (10), the semiconductor layer (30) including a buffer layer (31) and the device layer (32); only the device layer (32) has the semiconductor device functional structure of the integrated circuit or device completed; the buffer layer (31) is used to prevent the device layer (32) from being affected by the change in work function before and after the substrate (10) is thinned and removed; The exposed substrate (10) is etched away using the first etching method to obtain the thinned ultrathin semiconductor; The corrosion barrier layer (20) is used to prevent the corrosive agent used in the first corrosion method from corroding the semiconductor layer (30); the lower surface of the carrier (Z1) is resistant to corrosion by the corrosive agent of the first corrosion method.

2. The method for realizing ultrathin semiconductors according to claim 1, characterized in that, The corrosion barrier layer (20) is made of an insulating material.

3. The method for realizing ultrathin semiconductors according to claim 1, characterized in that, After the step of etching away the exposed substrate (10) using the first etching method, the method further includes: The exposed corrosion barrier layer (20) is removed by a second corrosion method.

4. The method for realizing ultrathin semiconductors according to claim 2, characterized in that, The substrate (10) and semiconductor layer (30) of the semiconductor substrate (J1) to be thinned are electrically connected at edge and / or internal locations.

5. The method for realizing ultrathin semiconductors according to claim 4, characterized in that, The material that enables the electrical connection between the substrate (10) and the semiconductor layer (30) is a homogeneous material, a non-homogeneous material, or only a portion thereof is a non-homogeneous material.

6. The method for realizing ultrathin semiconductors according to claim 5, characterized in that, The portion of the homogeneous material is fabricated by first etching away the electrically connected material of the homogeneous material and then depositing it.

7. The method for realizing ultrathin semiconductors according to claim 1, characterized in that, The carrier includes one or more composites of the semiconductor substrate (J1), silicon / germanium / compound semiconductor bare die, silicon / germanium / compound semiconductor with completed functional structure fabrication, diamond, silicon dioxide, glass, ceramic, blue film, carrier tape and protective adhesive.

8. The method for realizing ultrathin semiconductors according to claim 7, characterized in that, The carrier (Z1) further includes one or more layers of ultrathin semiconductors implemented using the ultrathin semiconductor implementation method of claim 1 or 3, wherein the ultrathin semiconductors of each layer of the multilayer ultrathin semiconductor have different functions or at least two layers are the same.

9. The method for realizing ultrathin semiconductors according to claim 1, characterized in that, The lower surface of the substrate (Z1) is provided with at least one of the following: a protective layer, a protective film, and an adhesive coating, so that the lower surface of the substrate (Z1) can resist corrosion by the corrosive agent of the first corrosion method.

10. The method for realizing an ultrathin semiconductor according to claim 1, characterized in that, The first corrosion method employs at least one of liquid phase, gas phase, and plasma methods.

11. The method for realizing ultrathin semiconductors according to claim 1, characterized in that, The substrate (10) is a single layer or a composite layer of at least two layers; and / or The buffer layer (31) is a single layer or a composite layer of at least two layers.

12. The method for realizing ultrathin semiconductors according to claim 11, characterized in that, At least one layer of the composite layer is low-resistivity.

13. The method for realizing ultrathin semiconductors according to claim 1, characterized in that, The corrosion barrier layer (20) is a single layer or a composite layer of at least two layers; the composite layer includes at least a barrier layer compatible with the semiconductor layer (30), and the barrier layer compatible with the semiconductor layer (30) is connected to the semiconductor layer (30).

14. The method for realizing ultrathin semiconductors according to claim 4, characterized in that, The electrical connection between the substrate (10) and the semiconductor layer (30) is achieved by the electrical connection between the substrate (10) and the buffer layer (31).

15. The method for realizing ultrathin semiconductors according to claim 1, characterized in that, The fabrication of the functional structure of the semiconductor substrate (J1) includes the fabrication of at least one functional structure in integrated circuits, electronic devices, optical devices, electronic circuits, optical pathways, microfluidic pathways, detectors, and MEMS systems.

16. The method for realizing ultrathin semiconductors according to claim 1, characterized in that, Before the step of placing the semiconductor substrate (J1) with the completed functional structure on the carrier (Z1) and bonding it thereto, the method further includes: pre-processing the semiconductor substrate (J1); The pretreatment includes one or more of the following: pre-thinning, pre-slicing, planarization, cleaning, and bonding layer activation.

17. The method for realizing ultrathin semiconductors according to claim 1, characterized in that, After the step of placing the semiconductor substrate (J1) with the completed functional structure on the carrier (Z1) and bonding it thereto, and before the step of etching away the exposed substrate (10) using the first etching method to obtain the thinned ultrathin semiconductor, the method further includes: further processing the semiconductor substrate (J1) to be thinned. The further processing includes one or more of the pre-thinning, cleaning, and edge corrosion protection; only one of the further processing and the pre-processing includes the pre-thinning; the edge corrosion protection refers to the protective treatment of the edge of the semiconductor substrate (J1) to be thinned against corrosion by the corrosive agent of the first corrosion method.

18. The method for realizing ultrathin semiconductors according to claim 1 or 3, characterized in that, The ultrathin semiconductor is subjected to post-processing; the post-processing includes at least one of the following steps: growing material, cleaning, coating, photolithography, developing, etching holes, fabricating lines, removing resist, removing etched edge residue, etched edge passivation, removing barrier layer, growing low bonding temperature insulating layer, substrate edge removal, bonding layer activation, bonding with other wafers, and wafer separation.

19. The method for realizing an ultrathin semiconductor according to claim 18, characterized in that, The post-processing is used to achieve electrical and / or optical connections between the substrate (Z1) and the ultrathin semiconductor.

20. The method for realizing an ultrathin semiconductor according to claim 19, characterized in that, The carrier (Z1) is electrically connected to the ultrathin semiconductor through a conductive material or a composite material formed of at least two materials; the composite material includes at least one conductive material.

21. The method for realizing an ultrathin semiconductor according to claim 20, characterized in that, The composite material in which the carrier (Z1) is electrically connected to the ultrathin semiconductor includes an adhesive layer; and / or The composite material in which the carrier (Z1) is electrically connected to the ultrathin semiconductor includes an insulating layer for achieving electrical connection and semiconductor isolation.

22. A heat dissipation method based on ultrathin semiconductors, characterized in that, A heat dissipation structure is mounted on the back of the ultrathin semiconductor implemented using the ultrathin semiconductor implementation method according to any one of claims 1 to 21.

23. The heat dissipation method based on ultrathin semiconductors according to claim 22, characterized in that, The heat dissipation structure is electrically connected to the ultrathin semiconductor.

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