Test layout and test structure for CESL characteristic test

Abstract

The invention provides a test layout and a test structure for CESL characteristic test, and the test layout comprises an isolation structure pattern, at least two gate ring patterns which are located in the isolation structure pattern and are sequentially sleeved, and two groups of contact hole patterns which are located at the inner sides of all the gate ring patterns and are arranged at intervals, and the self-aligned barrier layer pattern covers all the gate ring patterns, and the self-aligned barrier layer pattern is arranged on the outer side of the contact hole pattern. The test layout for CESL characteristic test provided by the invention is arranged on a product wafer and is formed in a cutting channel or a virtual pattern area of the product wafer, so that a test structure for CESL characteristic test can be directly integrated on the product wafer; therefore, in-situ and accurate monitoring of the CESL conduction characteristics can be directly realized on a product wafer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a test layout and test structure for CESL characteristic testing. Background Technology

[0002] In the manufacturing process of very large-scale integrated circuits (ICs), contact etch stop layers (CESLs) are widely used. This thin film layer is mainly located above the transistor gate and source / drain regions. One of its core functions is to act as an etch stop layer in subsequent contact etching processes to protect the underlying critical device structures (such as lightly doped drain regions (LDDs), silicides, etc.) from over-etching damage, thereby improving device performance and reliability.

[0003] However, existing CESL technology faces a significant technical challenge. For example... Figure 1 As shown, CESL films readily adsorb hydrogen ions (H⁺) generated during subsequent process steps (such as chemical mechanical polishing and dielectric deposition). These adsorbed H⁺ bonds can be distributed on the device surface, potentially inducing leakage channels and leading to transistor performance degradation, such as increased off-state current (Ioff), which directly affects chip yield and reliability.

[0004] To monitor the film quality and electrical properties (such as conductivity) of CESL, the current industry practice is to deposit CESL films on dedicated control wafers and then perform testing. This offline monitoring method has inherent limitations: First, the control wafer itself is not an actual product chip; its structure, thermal budget, and process environment differ from those of the product chip, resulting in test data that cannot accurately reflect the actual state of the CESL on the product chip. Second, this method cannot effectively characterize the cumulative impact of front-end (e.g., CESL deposition) and back-end (e.g., interlayer dielectric deposition, metal interconnects) processes on the conductivity of CESL. Therefore, existing technologies lack an effective means to directly and accurately monitor the electrical properties of CESL on actual product chips. This leads to blind spots in process monitoring and optimization, making it difficult to fundamentally prevent and resolve device performance and yield issues caused by variations in CESL characteristics. Summary of the Invention

[0005] The purpose of this invention is to provide a test layout and test structure for CESL characteristic testing, which can directly achieve in-situ and accurate monitoring of CESL conductivity characteristics on the product chip.

[0006] To address the above technical problems, the present invention provides a test layout for CESL characteristic testing, comprising an isolation structure pattern, at least two gate ring patterns nested sequentially within the isolation structure pattern, two sets of spaced contact hole patterns located inside all the gate ring patterns, and a self-aligned barrier layer pattern covering all the gate ring patterns, wherein the self-aligned barrier layer pattern is disposed outside the contact hole patterns.

[0007] In some embodiments, the gate ring pattern is rectangular and all the gate ring patterns are sequentially nested within the isolation structure pattern.

[0008] In some embodiments, the spacing between two adjacent gate ring patterns is 450nm ± 20nm.

[0009] In some embodiments, two metal block patterns are also included, each of which covers a set of contact hole patterns.

[0010] On the other hand, the present invention also provides a test structure for CESL characteristic testing, including a shallow trench isolation structure formed in a semiconductor substrate, at least two gate ring structures located on the shallow trench isolation structure and sequentially nested thereon, a self-aligned barrier layer is disposed on the surface of the gate ring structure, a gap groove is formed between two adjacent gate ring structures on which the self-aligned barrier layer is disposed, a contact hole etch stop layer is disposed on the surface of the semiconductor substrate, the contact hole etch stop layer covers the self-aligned barrier layer, and a break ring is formed at the bottom of at least one of the gap grooves, and two sets of contact holes are disposed at intervals on the contact hole etch stop layer inside the self-aligned barrier layer, the two sets of contact holes penetrate the contact hole etch stop layer and stop in the shallow trench isolation structure.

[0011] In some embodiments, the shallow trench isolation structure is located on the dicing or virtual pattern area of ​​the semiconductor substrate.

[0012] In some embodiments, the gate ring structure includes a polysilicon gate ring and sidewalls located on both sides of the polysilicon gate ring; the self-aligned barrier layer is disposed on the upper surface of the polysilicon gate ring and the outer surface of the sidewalls.

[0013] In some embodiments, the aspect ratio of the gap groove is greater than 1.5.

[0014] In some embodiments, the spacing between two adjacent polysilicon gate rings is a designed spacing of 450nm ± 20nm, and the total thickness of the polysilicon gate ring and the self-aligned barrier layer thereon is 4800Å ± 400Å.

[0015] In some embodiments, two metal blocks are formed on the contact hole, and the two metal blocks are respectively in contact with a set of contact holes.

[0016] Compared with the prior art, the present invention has the following unexpected technical effects:

[0017] This invention provides a test layout and test structure for CESL characteristic testing. The test layout includes an isolation structure pattern, at least two gate ring patterns nested sequentially within the isolation structure pattern, two sets of spaced contact hole patterns located inside all the gate ring patterns, and a self-aligned barrier layer pattern covering all the gate ring patterns, with the self-aligned barrier layer pattern disposed outside the contact hole patterns. The test layout for CESL characteristic testing provided by this invention is disposed on a product wafer and formed in the dicing track or virtual pattern area of ​​the product wafer. This allows the test structure for CESL characteristic testing to be directly integrated onto the product wafer, thereby enabling in-situ and accurate monitoring of CESL conductivity characteristics directly on the product wafer. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of a CESL film causing leakage.

[0019] Figure 2 This is a schematic diagram of a test layout provided in an embodiment of the present invention.

[0020] Figure 3 This is a schematic diagram of a test structure provided in an embodiment of the present invention.

[0021] Figure label:

[0022] 1-CESL thin film; 10-Isolation structure pattern; 20-Gate ring pattern; 21-Inner ring gate ring pattern; 22-Middle ring gate ring pattern; 23-Outer ring gate ring pattern; 30-Self-aligned barrier layer pattern; 40-Contact hole pattern; 50-Metal block pattern; 100-Semiconductor substrate; 101-Shallow trench isolation structure; 210-Polysilicon gate ring; 220-Sidewall; 230-Self-aligned barrier layer; 300-Contact hole etch stop layer; 400-Contact hole; 500-Metal block. Detailed Implementation

[0023] The following will provide a more detailed description of a test layout and test structure for CESL characteristic testing according to the present invention. The invention will now be described in more detail with reference to the accompanying drawings, which illustrate preferred embodiments of the invention. It should be understood that those skilled in the art can modify the invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit the invention.

[0024] For clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not detailed in detail, as they would obscure the invention with unnecessary detail. It should be understood that in the development of any actual embodiment, numerous implementation details must be made to achieve the developer's specific objectives, such as changes from one embodiment to another according to limitations related to the system or business. Furthermore, it should be understood that such development work may be complex and time-consuming, but is merely routine work for those skilled in the art.

[0025] To make the objectives and features of the present invention more apparent and understandable, the specific embodiments of the present invention will be further described below with reference to the accompanying drawings. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, and are only used to conveniently and clearly assist in illustrating the objectives of the embodiments of the present invention.

[0026] Figure 2 This is a schematic diagram of a test layout provided in this embodiment. Figure 2 As shown, this embodiment provides a test layout for CESL characteristic testing, including an isolation structure pattern 10, at least two gate ring patterns 20 nested in the isolation structure pattern 10, two sets of spaced contact hole patterns 40 located inside all the gate ring patterns 20, and a self-aligned barrier layer pattern 30 covering all the gate ring patterns 20, wherein the self-aligned barrier layer pattern 30 is disposed outside the contact hole pattern 40.

[0027] The test layout for CESL characteristic testing provided in this embodiment is set on the product wafer and will be formed in the dicing channel or virtual graphic area of ​​the product wafer. This allows the test structure for CESL characteristic testing to be directly integrated on the product wafer, thereby enabling in-situ and accurate monitoring of CESL conductivity characteristics directly on the product wafer.

[0028] The isolation structure pattern 10 is used to define the formation location and shape of the shallow trench isolation structure 101, so that it can be set on the dicing track or virtual graphic area of ​​the product wafer. The isolation structure pattern 10 can be a regular shape, such as a rectangle.

[0029] The gate ring pattern 20 is rectangular and all gate ring patterns 20 are sequentially nested within the isolation structure pattern 10. Furthermore, all gate ring patterns 20 are concentrically nested within the isolation structure pattern 10. Adjacent gate ring patterns 20 can be spaced at equal intervals, for example, 450nm ± 20nm. This spacing ensures that the aspect ratio of the gap between adjacent gate structures in the formed test structure is greater than 1.5. This facilitates the formation of a CESL film on the gate structure via PECVD (Physical Vapor Deposition) to break at the gap due to the PECVD loading effect, forming a fracture ring and thus creating independent test islands within all fracture rings.

[0030] The number of gate ring patterns 20 can be two, three, or more. In this embodiment, there are three gate ring patterns 20, namely an inner ring gate ring pattern 21, a middle ring gate ring pattern 22, and an outer ring gate ring pattern 23. The inner ring gate ring pattern 21, the middle ring gate ring pattern 22, and the outer ring gate ring pattern 23 are concentrically nested from the inside to the outside. The long side of the gate ring pattern 20 is parallel to the long side of the isolation structure pattern 10. All the gate ring patterns 20 have a central axis in the direction of the long side. The central axis is parallel to the long side and the distance from the long side of the same gate ring pattern 20 on both sides is the same.

[0031] The contact hole pattern 40 is disposed inside all the inner ring gate ring patterns 21 and spaced apart from the gate ring patterns 20. In this embodiment, two sets of spaced contact hole patterns 40 are spaced apart along the long side of the isolation structure pattern 10 and are respectively located at both ends of the long side of the long side of the isolation structure pattern 10 inside all the gate ring patterns 20. Further, the two sets of contact hole patterns 40 are placed vertically on the central axis A of all the gate ring patterns 20. Each set of contact hole patterns 40 includes at least one contact hole pattern 40, for example, three contact hole patterns 40, which are spaced apart perpendicular to the central axis A.

[0032] A metal block pattern 50 is placed on each group of contact hole patterns 40, and each metal block pattern 50 covers the corresponding group of contact hole patterns 40.

[0033] The self-aligned barrier layer pattern 30 is in the shape of a rectangular ring, located in the isolation structure pattern 10, with the outer ring located outside all the gate ring patterns 20 and the inner ring located inside all the gate ring patterns 20 and outside the two metal block patterns 50, so as to expose the metal block patterns 50.

[0034] Figure 3This is a schematic diagram of a test structure provided in this embodiment. Figure 3 As shown, this embodiment also provides a test structure for CESL characteristic testing, including a shallow trench isolation structure 101 formed in a semiconductor substrate 100, and at least two gate ring structures located on the shallow trench isolation structure 101 and sequentially nested thereon. A self-aligned barrier layer 230 is disposed on the surface of the gate ring structure, and a gap groove is formed between two adjacent gate ring structures on which the self-aligned barrier layer 230 is disposed. A contact hole etch stop layer 300 is disposed on the surface of the semiconductor substrate 100. The contact hole etch stop layer 300 covers all the shallow trench isolation structures 101 inside and outside the gate structures, and also covers the self-aligned barrier layer 230. It is broken at the bottom of at least one of the gap grooves to form a fracture ring. Two sets of contact holes are disposed at intervals on the contact hole etch stop layer 300 inside the self-aligned barrier layer 230. The two sets of contact holes penetrate the contact hole etch stop layer 300 and stop in the shallow trench isolation structure 101.

[0035] In the test structure for CESL characteristic testing provided in this embodiment, the contact hole etch stop layer 300 has at least one fracture ring, which makes the contact hole etch stop layer 300 inside the gate ring structure form a test island. This allows the test structure for CESL characteristic testing to be directly integrated on the product wafer, thereby enabling in-situ and accurate monitoring of CESL conductivity characteristics directly on the product wafer.

[0036] In this embodiment, the semiconductor substrate 100 is, for example, a wafer-level semiconductor substrate 100 used to form a product wafer. The semiconductor substrate 100 provides an operating platform for subsequent processes and can be any substrate known to those skilled in the art for carrying semiconductor integrated circuit components. It can be a bare die or a wafer processed by epitaxial growth. Specifically, the semiconductor substrate 100 can be, for example, a silicon-on-insulator (SOI) substrate, a bulk silicon substrate, a germanium substrate, a germanium-silicon substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator substrate, etc.

[0037] A shallow trench isolation structure 101 is formed on the dicing or virtual pattern area of ​​the semiconductor substrate 100. The shallow trench isolation structure 101 is fabricated by the isolation structure pattern 10 in the test layout.

[0038] At least two gate ring structures are formed on the shallow trench isolation structure 101, and all the gate ring structures are sequentially nested. Each gate ring structure includes a polysilicon gate ring 210 and sidewalls 220 located on both sides of each polysilicon gate ring 210. Each polysilicon gate ring 210 is fabricated using a corresponding gate ring pattern 20. The spacing between two adjacent polysilicon gate rings 210 is a designed spacing, for example, 450nm ± 20nm. The spacing between any two adjacent polysilicon gate rings 210 can be the same or different. This can be set according to actual needs. In this embodiment, the spacing between any two adjacent polysilicon gate rings 210 is the same.

[0039] A self-aligned barrier layer 230 is provided on the surface of the gate ring structure (i.e., the upper surface of the polysilicon gate ring 210 and the outer surface of the sidewall 220). The self-aligned barrier layer 230 is formed by the self-aligned barrier layer pattern 30. The self-aligned barrier layer 230 covers the surface of all the gate ring structures, and even covers the surface of the shallow trench isolation structure 101 between two adjacent gate ring structures, so that there is a gap between two adjacent gate ring structures covered by the self-aligned barrier layer 230.

[0040] The total thickness of the polysilicon gate ring 210 and the self-aligned barrier layer 230 thereon is, for example, 4800 Å ± 400 Å, so that the aspect ratio of the resulting gap will be greater than 1.5.

[0041] A contact hole etch stop layer 300 is formed on the surface of the semiconductor substrate 100. The formation of this contact hole etch stop layer 300 does not require an etching process; it can be formed directly by a PECVD process. Therefore, this step does not require a photomask. During the PECVD process, due to the PECVD process loading effect, the contact hole etch stop layer 300 is not covered in the gaps (at least the bottom wall of the gaps) with an aspect ratio greater than 1.5. Thus, the contact hole etch stop layer 300 breaks at the bottom wall of the gap to form a fracture ring. Consequently, the contact hole etch stop layers 300 inside all fracture rings form test islands.

[0042] A dielectric layer (not shown) is formed on the semiconductor substrate 100. The dielectric layer covers the contact hole etch stop layer 300 and the shallow trench isolation structure 101, and fills the gap trench. Two sets of contact holes 400 are formed in the dielectric layer. The contact holes 400 are located inside the gate ring structure, penetrating the dielectric layer and the contact hole etch stop layer 300, and stopping in the shallow trench isolation structure 101. All the contact holes 400 are formed by a contact hole pattern 40. Therefore, each set of contact holes 400 is located on the central axis A of the rectangular ring-shaped gate ring structure on its long side, and is located near both ends of the innermost gate ring structure. The line connecting all the contact holes 400 in each set is perpendicular to the central axis.

[0043] A metal layer is disposed on the dielectric layer, the metal layer comprising metal blocks 500, each of the metal blocks 500 being connected to a set of contact holes 400. The metal blocks 500 serve as pads for use as external measurement ports.

[0044] This embodiment also provides a method for preparing a test structure, including the following steps:

[0045] Step S1: Provide a semiconductor substrate, and form a shallow trench isolation structure in the semiconductor substrate using a first mask, wherein the first mask includes the isolation structure pattern;

[0046] Step S2: A gate ring structure is formed on the shallow trench isolation structure using a second mask template, wherein the second mask template includes the gate ring pattern;

[0047] Step S3: A self-aligned barrier layer is formed on the surface of the gate ring structure using a third mask template. A gap groove is formed between two adjacent gate ring structures on which the self-aligned barrier layer is provided. The third mask template includes the pattern of the self-aligned barrier layer.

[0048] Step S4: A contact hole etch stop layer is formed on the semiconductor substrate by PECVD process, wherein the contact hole etch stop layer is broken at the bottom of at least one of the gap trenches to form a fracture ring;

[0049] Step S5: Using a fourth mask template, two sets of contact holes are formed on the shallow trench isolation structure inside the gate ring structure. The contact holes penetrate the contact hole etch stop layer and stop in the shallow trench isolation structure. The fourth mask template includes the contact hole pattern.

[0050] Please see Figure 2-3In step S2, a second mask with at least two gate ring patterns 20 is first used to form corresponding polysilicon gate rings 210; then, sidewalls 220 are formed on both sides of each polysilicon gate ring 210 through deposition, etching, and other processes, thereby forming at least two gate ring structures. The spacing between two adjacent polysilicon gate rings 210 is 450nm ± 20nm, and the total thickness of the polysilicon gate ring 210 and the self-aligned barrier layer 230 located thereon is, for example, 4800Å ± 400 Å, so that the aspect ratio of the resulting gap trench will be greater than 1.5.

[0051] In step S4, since the aspect ratio of the gap groove is greater than 1.5, the PECVD process load effect is severe, and the contact hole etching stop layer 300 breaks at the bottom wall of the gap groove to form a fracture ring. As a result, an independent test island is formed on the shallow trench isolation structure 101 and located within the innermost fracture ring of the contact hole etching stop layer 300.

[0052] In this embodiment, the test structure is tested by applying a fixed voltage to one metal block 500 and grounding the other metal block 500. The corresponding resistance is calculated by measuring the current flowing through the two metal blocks 500, thereby monitoring the CESL conductivity characteristics on the product wafer and accurately characterizing the process on the product wafer.

[0053] In summary, this invention provides a test layout and test structure for CESL characteristic testing. The test layout includes an isolation structure pattern, at least two gate ring patterns nested sequentially within the isolation structure pattern, two sets of spaced-apart contact hole patterns located inside all the gate ring patterns, and a self-aligned barrier layer pattern covering all the gate ring patterns, with the self-aligned barrier layer pattern disposed outside the contact hole patterns. The test layout for CESL characteristic testing provided by this invention is disposed on a product wafer and formed in the dicing track or virtual pattern area of ​​the product wafer. This allows the test structure for CESL characteristic testing to be directly integrated onto the product wafer, thereby enabling in-situ and accurate monitoring of CESL conductivity characteristics directly on the product wafer.

[0054] Furthermore, it should be noted that, unless otherwise specified or indicated, the terms "first" and "second" in the specification are used only to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical or sequential relationships between the various components, elements, steps, etc.

[0055] It is understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A test layout for CESL feature testing, characterized in that, The device includes an isolation structure pattern, at least two gate ring patterns nested within the isolation structure pattern, two sets of spaced contact hole patterns located inside all the gate ring patterns, and a self-aligned barrier layer pattern covering all the gate ring patterns, wherein the self-aligned barrier layer pattern is disposed outside the contact hole patterns.

2. The test layout as described in claim 1, characterized in that, The gate ring pattern is rectangular and all the gate ring patterns are sequentially nested within the isolation structure pattern.

3. The test layout as described in claim 1, characterized in that, The spacing between two adjacent gate ring patterns is 450nm ± 20nm.

4. The test layout as described in claim 1, characterized in that, It also includes two metal block patterns, each of which covers a set of contact hole patterns.

5. A test structure for CESL characteristic testing, characterized in that, The device includes a shallow trench isolation structure formed in a semiconductor substrate, at least two gate ring structures located on the shallow trench isolation structure and sequentially nested thereon, a self-aligned barrier layer disposed on the surface of the gate ring structure, a gap groove formed between two adjacent gate ring structures with the self-aligned barrier layer disposed on their surfaces, a contact hole etch stop layer disposed on the surface of the semiconductor substrate, the contact hole etch stop layer covering the self-aligned barrier layer, and a break ring formed at the bottom of at least one of the gap grooves, and two sets of contact holes disposed at intervals on the contact hole etch stop layer inside the self-aligned barrier layer, the two sets of contact holes penetrating the contact hole etch stop layer and stopping in the shallow trench isolation structure.

6. The test structure as described in claim 5, characterized in that, The shallow trench isolation structure is located on the dicing or virtual pattern area of ​​the semiconductor substrate.

7. The test structure as described in claim 5, characterized in that, The gate ring structure includes a polysilicon gate ring and sidewalls located on both sides of the polysilicon gate ring; the self-aligned barrier layer is disposed on the upper surface of the polysilicon gate ring and the outer surface of the sidewalls.

8. The test structure as described in claim 7, characterized in that, The aspect ratio of the gap groove is greater than 1.

5.

9. The test structure as described in claim 7, characterized in that, The spacing between two adjacent polysilicon gate rings is designed to be 450nm ± 20nm, and the total thickness of the polysilicon gate ring and the self-aligned barrier layer located thereon is 4800Å ± 400Å.

10. The test structure as described in claim 7, characterized in that, Two metal blocks are formed on the contact hole, and the two metal blocks are respectively in contact with a set of contact holes.

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