Chip packaging structure and method

Abstract

The invention relates to the technical field of chip packaging, and discloses a chip packaging structure, which comprises a core plate frame and a power device, and is characterized in that the core plate frame is an integral metal plate without glass fibers, and a first space and a second space which are not communicated with each other are arranged in the core plate frame; the power device is arranged in the first space; the third metal layer and the fourth metal layer are connected to the upper surface and the lower surface of the power device respectively, the second metal layer and the third metal layer are arranged at an interval and located on the side, away from the power device, of the third metal layer, and the fifth metal layer and the fourth metal layer are arranged at an interval and located on the side, away from the power device, of the fourth metal layer; a metal column is connected between the second metal layer and the fifth metal layer, the metal column is arranged in the second space and is not in contact with the core plate frame, and a resin layer is filled between the metal column and the core plate frame in the second space. Through the synergistic effect of different metal layers, rapid and balanced distribution of heat is achieved, and performance degradation or damage caused by local overheating is effectively prevented.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and in particular to a chip packaging structure and method. Background Technology

[0002] The manufacturing process of integrated circuit chips mainly includes: chip design, chip fabrication, chip packaging, and chip testing. With the continuous advancement of integrated circuit chip manufacturing processes, electronic products are rapidly developing towards higher speeds, higher integration, and higher reliability, placing increasingly higher demands on integrated circuit manufacturing processes. Currently, the packaging process for power chips includes: Step 1: Perform double-sided laser drilling on the double-sided copper-clad board to form through-holes in the shape of X-shaped holes; Step 2: Electroplating process fills the through holes to form conductive copper pillars, and simultaneously thickens the upper and lower metal layers; Step 3: Through the pattern transfer process of film application → exposure → etching → film removal, the circuit pattern is etched on the metal layer to form the third wiring layer and the fourth wiring layer. Step 4: Laser cutting is used to process the through slots, high-temperature tape is applied to convert the through slots into blind slots, and a high-precision chip mounter is used to fix the power chip in the blind slots; Step 5: Multiple high-temperature pressing, namely: first, a prepreg containing glass fiber and copper foil are superimposed on the third wiring layer and pressed to form a five-layer structure; after the high-temperature tape is removed, the pressing is repeated on the fourth wiring layer to form a seven-layer structure; subsequently, dielectric and metal layers are added through pressing to finally form an eleven-layer semi-finished board. Step 6: After pattern transfer etching to create windows, laser ablation is used to form blind holes. Electroplating is used to fill the blind holes and thicken the metal layer. Pattern transfer is performed again to form the outer wiring layer. After solder mask printing, exposure, development, and post-curing, the solder assembly layer is formed. After immersion nickel-palladium-gold treatment, the smallest unit substrate is obtained by UV laser cutting.

[0003] However, the inventors found that power chips packaged using conventional processes have the following drawbacks: 1. Existing double-sided copper-clad laminates and prepregs used for lamination both contain fiberglass cloth. However, fiberglass cloth inherently suffers from uneven density distribution during weaving (such as localized fiber splicing or sparse areas). This causes nonlinear expansion and contraction deformation of the semi-finished board during high-temperature lamination and pattern transfer processes due to differences in fiber density. Specifically, densely fiberglass areas exhibit low shrinkage rates, while sparsely fiberglass areas show high shrinkage rates, leading to loss of overall dimensional accuracy of the substrate. This deformation directly causes hole position deviations during subsequent blind via fabrication, resulting in laser-ablated blind vias failing to accurately align with the conductive copper pillars of the underlying wiring layer. This leads to cross-layer conductivity failure, ultimately resulting in substrate scrap and significantly increasing production costs. 2. In the packaged power chip, the cross-layer conductivity of the second to fifth wiring layers relies on a composite conductive copper pillar structure formed by blind vias, X-shaped vias, and blind vias. This structure requires multiple drilling, electroplating, and pattern transfer processes, making the manufacturing process cumbersome and difficult to control. At the same time, since the composite conductive copper pillar is close to the metal layer of the double-sided copper-clad laminate, if there is over-etching during the etching process or interlayer misalignment during lamination, it is very easy for the conductive copper pillar to come into direct contact with the metal layer, thereby causing a short circuit fault. 3. The heat generated by the packaged power chip needs to pass through the fourth conductive copper pillar, the fifth wiring layer, the fifth conductive copper pillar, and the sixth wiring layer in sequence before it can be dissipated. Since there is contact thermal resistance at each interface, and the sequential transfer of multiple wiring layers and copper pillars will further amplify the thermal resistance, the heat will accumulate around the chip, making the heat dissipation capacity of the chip package structure unable to meet the requirements, which can easily lead to overheating failure of the power chip. Summary of the Invention

[0004] To solve the above-mentioned technical problems, or at least partially solve them, this application provides a chip packaging structure and method.

[0005] In a first aspect, this application provides a chip packaging structure, including: The core board frame is a single metal plate without glass fiber, and the core board frame is provided with a first space and a second space that are arranged in a first direction, and the first space and the second space are not connected to each other. A power device is disposed within the first space and is bonded and fixed to the core board frame by an adhesive. A second metal layer, a third metal layer, a fourth metal layer, and a fifth metal layer, wherein the third and fourth metal layers are respectively connected to the upper and lower surfaces of the power device in the first direction; the second metal layer is spaced apart from the third metal layer in the first direction and is located on the side of the third metal layer away from the power device; the fifth metal layer is spaced apart from the fourth metal layer in the first direction and is located on the side of the fourth metal layer away from the power device; and... A metal pillar is connected between the second metal layer and the fifth metal layer. The metal pillar is arranged in the second space and does not contact the core board frame. A resin layer is filled between the metal pillar and the core board frame in the second space.

[0006] In one embodiment, a fiber-free resin layer is filled between the second metal layer and the third metal layer, the fourth metal layer and the fifth metal layer, and between the second metal layer and the fifth metal layer.

[0007] In one embodiment, the thickness of the core board frame is D, and 50μm≤D≤500μm.

[0008] In one embodiment, the packaging structure further includes a first metal layer and a sixth metal layer, wherein the first metal layer and the second metal layer are spaced apart in the first direction and located on the side of the second metal layer away from the power device, and the sixth metal layer and the fifth metal layer are spaced apart in the first direction and located on the side of the fifth metal layer away from the power device; and... A fiber-free resin layer is filled between the first metal layer and the sixth metal layer.

[0009] In one embodiment, the outer edge of the encapsulation structure is provided with a resin layer that covers at least the second metal layer, the core board frame, and the fifth metal layer, wherein the resin layer is a fiberless resin layer.

[0010] Secondly, this application provides a method for preparing a packaging structure, the method comprising at least the following steps: Copper foil without glass fiber was selected as the core board frame; The core board frame is subjected to graphic transfer processing to form a first space and a second space that are not connected to each other within the core board frame. The power devices are assembled into the first space to form a three-layer semi-finished board; The pressed sheet and copper foil are sequentially covered on the top of the three-layer structure semi-finished plate, so that the pressed sheet and copper foil cover the corresponding areas of the first space and the second space, and the corresponding pressed sheet and copper foil are pressed together to form the second metal layer, and the resin of the pressed sheet at least fills part of the second space. The pressed sheet and copper foil are sequentially covered under the power device, so that the pressed sheet and copper foil cover the corresponding areas of the first space and the second space, and the corresponding pressed sheet and copper foil are pressed together to form the fifth metal layer, and a five-layer structure semi-finished board is obtained. The five-layer semi-finished board is subjected to pattern transfer processing, so that the second metal layer and the fifth metal layer form windows in the regions corresponding to the power device and the second space, and the windows are subjected to ablation processing to form through holes between the second metal layer and the power device, between the fifth metal layer and the power device, and between the second metal layer and the fifth metal layer, respectively. The five-layer semi-finished board is electroplated to fill the through holes, thereby forming the metal pillars in the area where the through holes are located. The metal pillars can then be used to electrically connect the second metal layer, the fifth metal layer and the power device.

[0011] In one embodiment, the laminated sheet is a fiber-free laminated sheet.

[0012] In one embodiment, the method further includes at least the following steps: The five-layer semi-finished plate with the metal pillars is subjected to graphic transfer processing to form lines on the second metal layer and the fifth metal layer; The pressed sheet and copper foil are sequentially covered to cover the second metal layer and the fifth metal layer, so that the pressed sheet and copper foil cover the area corresponding to the circuit, and the corresponding pressed sheet and copper foil are pressed together to form the first metal layer and the sixth metal layer, and a nine-layer structure semi-finished board is obtained. The final product is formed by processing the nine-layer semi-finished board.

[0013] Thirdly, this application provides a plate separation method based on the preparation method described above, the method comprising at least the following steps: Copper foil without glass fiber is selected as the core board frame, and multiple encapsulation areas are divided within the core board frame; The core board frame is subjected to pattern transfer processing to form a first space and a second space that are not connected to each other in the multiple encapsulation areas, and at least a portion of the cutting channel area between adjacent encapsulation areas is etched so that adjacent encapsulation areas are connected by connecting ribs. The five-layer semi-finished plate is subjected to graphic transfer processing, so that the second metal layer and the fifth metal layer form windows in the area corresponding to the connecting rib, and the windows are subjected to ablation processing to hollow out the cutting area covered by the connecting rib. The pressed sheet and copper foil are sequentially covered to cover the second metal layer and the fifth metal layer, respectively, so that the pressed sheet and copper foil cover the area corresponding to the circuit, and the corresponding pressed sheet and copper foil are pressed together to form the first metal layer and the sixth metal layer, and the cutting area is filled with resin. The core board frame is cut along the cutting area to form multiple sealing structures.

[0014] This application also provides an etching compensation method for preparing the first space of the above-described packaging structure, the method comprising at least the following steps: Based on the dimensions of the power device, the dimensions of the initial through slot are set, wherein the cross-section of the initial through slot is rectangular, and the side of the initial through slot is spaced apart from the side of the power device by a distance d1. A first compensation hole is set with the first base point as the center and the distance d2 as the diameter, and the first compensation hole is positioned at the four corners of the initial through slot. The first base point is located near the corner of the rectangle and is spaced d3 away from the two sides of the initial through slot. A second compensation hole is set with the second base point as the center and the distance d4 as the diameter, and the second compensation hole is positioned at the four corners of the initial through slot, wherein the second base point is located at the end of the rectangle; The intersection area of ​​the first compensation hole and the second compensation hole is leveled to obtain an etched pattern; Based on the etched pattern, a pattern transfer process is performed on the core board frame to form the first space.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows: Using a fiberglass-free monolithic metal plate as the core board frame eliminates the risk of nonlinear expansion and contraction due to the absence of fiberglass density variations, effectively preventing cross-layer conductivity failure caused by hole misalignment. Simultaneously, the core board frame exhibits a stable and uniform coefficient of thermal expansion. Heat from the power devices is conducted to the core board frame via the third and fourth metal layers. These layers further transfer some heat to the second and fifth metal layers, forming a multi-path, three-dimensional heat dissipation system. This not only increases the heat dissipation area but also achieves rapid and even heat distribution through the synergistic effect between different metal layers. Even under high-load operation of the power devices, it ensures that temperature differences across the packaging structure are kept within a minimal range, effectively preventing performance degradation or damage caused by localized overheating.

[0016] Furthermore, the metal pillars are located within the second space, and the second space is not connected to the first aperture, thereby preventing short circuits caused by contact between the metal pillars and power devices or the third and fourth metal layers in the first space. At the same time, the gap between the metal pillars and the inner wall of the second space is filled with resin, thereby forming an electrical barrier. Even if the metal pillars undergo slight displacement due to vibration, they will not conduct electricity with the core board frame, thereby further reducing the probability of short circuit failure and improving the electrical reliability of the package. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a chip packaging structure provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of a chip packaging structure provided in another embodiment of the present invention; Figure 3 This is a schematic flowchart of a method for fabricating a chip packaging structure according to an embodiment of the present invention; Figure 4This is a schematic diagram of an embodiment of the present invention providing image transfer processing of a core board frame; Figure 5 This is a schematic diagram of the process of assembling a power device into a first space according to an embodiment of the present invention; Figure 6 This is a schematic diagram of pressing a three-layer semi-finished plate according to an embodiment of the present invention; Figure 7 This is another schematic diagram of pressing a three-layer semi-finished plate according to an embodiment of the present invention; Figure 8 This is a schematic diagram of a five-layer semi-finished board with hole opening process provided in an embodiment of the present invention; Figure 9 A schematic diagram of electroplating treatment of a five-layer semi-finished board according to an embodiment of the present invention; Figure 10 A schematic diagram of the preparation of a nine-layer structured semi-finished board according to an embodiment of the present invention; Figure 11 A schematic diagram of graphic transfer processing for a five-layer semi-finished board provided in an embodiment of the present invention; Figure 12 An embodiment of the present invention provides a flowchart of an etching compensation method for a first space of a chip package structure; Figure 13 This is a schematic diagram of etching compensation of the first space of the chip packaging structure according to an embodiment of the present invention; Figure 14 A flowchart illustrating a plate-splitting method according to an embodiment of the present invention; Figure 15 A schematic diagram of a chip packaging structure being separated using a separate board method according to an embodiment of the present invention.

[0018] In the diagram: 10, core board frame; 10a, first space; 10b, second space; 20, power device; 30, third metal layer; 40, fourth metal layer; 50, second metal layer; 60, fifth metal layer; 70, metal pillar; 80, first metal layer; 90, second metal layer; 100, high-temperature tape. Detailed Implementation

[0019] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples. The following examples are for illustrative purposes only and are not intended to limit the scope of the invention.

[0020] In the description of this invention, it should be understood that when an element is referred to as "fixed to" or "set on" another element, it can be directly on or indirectly on the other element. When an element is referred to as "connected to" another element, it can be directly connected to or indirectly connected to the other element. The terms "mounted," "connected," and "attached" should be interpreted broadly, for example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two elements or the interaction between two elements. Those skilled in the art will understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0021] In the description of this invention, it should be understood that the terms "height," "upper," "lower," "vertical," "horizontal," "top," "bottom," "inner," and "outer" used in this invention to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings are used only for the convenience of describing this invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0022] In the description of this invention, it should be understood that the terms "first," "second," etc., used in this invention are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature.

[0023] The following explains and describes the relevant terms involved in the embodiments of this application.

[0024] The first direction refers to the vertical direction of the chip board frame, distinguished by the top and bottom sides of the chip packaging structure during normal use. For details, please refer to... Figure 1 X-rays in the middle.

[0025] like Figure 1 As shown, a chip packaging structure according to an embodiment of the present invention includes a chip frame, a power device 20, a metal pillar 70, and a second metal layer 50, a third metal layer 30, a fourth metal layer 40, and a fifth metal layer 60.

[0026] The core board frame 10 is a single metal plate without glass fibers. Because copper foil is a homogeneous metallic material with a stable and uniform coefficient of thermal expansion, it avoids the localized expansion and contraction differences caused by uneven glass fiber density. Furthermore, copper foil possesses excellent chemical etching properties, resulting in high edge precision and no burrs during etching, thus meeting the high-precision processing requirements of through-grooves. Therefore, copper foil is preferably used for the core board frame 10 in this embodiment, but it is not limited to this.

[0027] The core board frame 10 has a first space 10a and a second space 10b that extend along a first direction. The first space 10a and the second space 10b are not interconnected. The power device 20 is disposed in the first space 10a and is bonded to the core board frame 10 with an adhesive. It should be noted that the adhesive here can be a substance formed by melting resin in a pressed sheet after heating, flowing into the gap between the power device 20 and the inner wall of the first space 10a, and then curing the resin. Preferably, the pressed sheet is a fiber-free pressed sheet, such as a pure epoxy resin pressed sheet, a polyimide-based pressed sheet, or a resin-ceramic composite pressed sheet.

[0028] The third metal layer 30 and the fourth metal layer 40 are respectively connected to the upper and lower surfaces of the power device 20 in the first direction. The second metal layer 50 is spaced apart from the third metal layer 30 in the first direction and is located on the side of the third metal layer 30 away from the power device 20. The fifth metal layer 60 is spaced apart from the fourth metal layer 40 in the first direction and is located on the side of the fourth metal layer 40 away from the power device 20. A metal pillar 70 is connected between the second metal layer 50 and the fifth metal layer 60. The metal pillar 70 is arranged in the second space 10b and does not contact the core board frame 10. A resin layer is filled between the metal pillar 70 and the core board frame 10 in the second space 10b.

[0029] In other words, by providing a third metal layer 30 and a fourth metal layer 40 on the upper and lower surfaces of the power device 20 in the first direction, and by providing a second metal layer 50 and a fifth metal layer 60 at intervals on the side of the third metal layer 30 and the fourth metal layer 40 away from the power device 20, and then connecting the second metal layer 50 and the fifth metal layer 60 with metal pillars 70, the transmission path of electrical signals from the power device 20 to the outer layer (third metal layer 30 → second metal layer 50, and fourth metal layer 40 → fifth metal layer 60) is shortened, parasitic inductance is reduced, and problems such as signal delay and crosstalk are reduced.

[0030] The heat from the power device 20 can be diffused to the second metal layer 50 and the fifth metal layer 60 through the third metal layer 30 and the fourth metal layer 40, respectively, and then conducted to the external heat sink or air by the second metal layer 50 and the fifth metal layer 60. At the same time, the core board frame 10 is an integral metal plate without glass fiber, so the heat from the power device 20 can also be conducted to the core board frame 10 through the third metal layer 30 and the fourth metal layer 40. This forms a heat dissipation system of main heat dissipation of the core board frame 10 + auxiliary heat dissipation of multiple metal layers, which can significantly improve the heat dissipation effect of the entire packaging structure, reduce the junction temperature difference of the packaging structure, and further extend the service life of the packaging structure.

[0031] In summary, the chip packaging structure of this application uses a fiberglass-free integral metal plate as the core frame 10. The absence of uneven fiberglass density prevents nonlinear expansion and contraction deformation, effectively avoiding cross-layer conductivity failure caused by hole misalignment. Simultaneously, the core frame 10 has a stable and uniform coefficient of thermal expansion. Heat from the power device 20 is conducted to the core frame 10 via the third metal layer 30 and the fourth metal layer 40. Furthermore, the third and fourth metal layers 30 and 40 conduct some heat to the second metal layer 50 and the fifth metal layer 60, forming a multi-path, three-dimensional heat dissipation system. This not only increases the heat dissipation area but also achieves rapid and balanced heat distribution through the synergistic effect between different metal layers. Even under high load operation of the power device 20, the temperature difference between different parts of the packaging structure can be kept within a minimal range, effectively preventing performance degradation or damage caused by localized overheating.

[0032] Furthermore, the metal pillar 70 is disposed within the second space 10b, and the second space 10b is not connected to the first aperture, thereby preventing the metal pillar 70 from contacting the power device 20 or the third metal layer 30 and the fourth metal layer 40 in the first space 10a and causing a short circuit. At the same time, the gap between the metal pillar 70 and the inner wall of the second space 10b is filled with resin layer, thereby forming an electrical barrier. In this way, even if the metal pillar 70 undergoes a slight displacement due to vibration, it will not conduct with the core board frame 10, thereby further reducing the probability of short circuit failure and improving the electrical reliability of the package.

[0033] In traditional packaging processes, the dielectric layer between metal layers often uses a prepreg containing fiberglass cloth. However, uneven density of the fiberglass cloth can lead to localized expansion and contraction differences in the dielectric layer during high-temperature lamination, causing metal layer misalignment, substrate warping, and consequently, hole position deviations or insufficient chip mounting accuracy in subsequent drilling. To address this, in one embodiment, a fiberglass-free resin layer is filled between the second metal layer 50 and the third metal layer 30, the fourth metal layer 40 and the fifth metal layer 60, and the second metal layer 50 and the fifth metal layer 60. This prevents localized expansion and contraction differences in the dielectric layer during high-temperature lamination and curing, significantly reducing interlayer thermal stress.

[0034] In addition, the fiberless resin layer has good insulation properties. It fills the spaces between the second metal layer 50 and the third metal layer 30, the fourth metal layer 40 and the fifth metal layer 60, and between the second metal layer 50 and the fifth metal layer 60. It can act as an insulating medium to block direct contact between different metals, avoid short circuits caused by contact between adjacent metal layers, and also prevent accidental conduction between the cross-layer metal pillar 70 and the core board frame 10, resulting in leakage or signal crosstalk.

[0035] The core frame 10 has a thickness of D, where 50 μm ≤ D ≤ 500 μm. In other words, limiting the thickness of the core frame 10 to this range not only ensures sufficient rigidity to prevent deformation during subsequent etching of the first space 10a, the second space 10b, and drilling, but also ensures that the cross-sectional area of ​​the core frame 10 is sufficient to guarantee low thermal resistance, achieving a balance between rapid heat absorption and rapid heat conduction, thus allowing for rapid heat dissipation. Preferably, the thickness D of the core frame is 105 μm.

[0036] Reference Figure 2 In one embodiment, the packaging structure further includes a first metal layer 80 and a sixth metal layer 90. The first metal layer 80 is spaced apart from the second metal layer 50 in a first direction and is located on the side of the second metal layer 50 away from the power device 20. The sixth metal layer 90 is spaced apart from the fifth metal layer 60 in a first direction and is located on the side of the fifth metal layer 60 away from the power device 20. That is, the first metal layer 80 and the sixth metal layer 90 can serve as the outermost wiring layers of the chip packaging structure. Furthermore, more pin solder points can be etched onto the first metal layer 80 and the sixth metal layer 90 through pattern transfer, enabling multi-channel connections between the power device 20 and the external circuit board without occupying wiring space in the internal metal layers, thus avoiding signal delays caused by internal wiring congestion. In addition, the first metal layer 80 and the sixth metal layer 90 can directly contact the external heat dissipation structure, reducing heat accumulation in the internal metal layers.

[0037] Furthermore, a fiber-free resin layer is filled between the first metal layer 80 and the sixth metal layer 90. The excellent insulation properties of the fiber-free resin layer are used to form a gapless insulation barrier between the first metal layer 80 and the sixth metal layer 90, thus eliminating the risk of short circuits even in high-voltage or humid environments.

[0038] In one embodiment, the outer edge of the chip package structure is provided with a resin layer that covers at least the second metal layer 50, the core board frame 10, and the fifth metal layer 60. The resin layer is a fiberless resin layer. That is, a resin layer is arranged on the outer edge of the chip package structure to wrap the second metal layer 50, the core board frame 10, and the fifth metal layer 60. Because the fiberless resin layer has a certain degree of toughness, it can absorb the impact energy when the edge of the package structure is impacted, preventing the edges of the second metal layer 50 and the fifth metal layer 60 from cracking or the core board frame 10 from deforming. At the same time, it can also block external hard objects from scratching the edges, preventing scratches on the surfaces of the second metal layer 50 and the fifth metal layer 60.

[0039] Reference Figure 3 This application provides a method for preparing a packaging structure, the method comprising at least the following steps: S10. Select copper foil without glass fiber as the core board frame 10.

[0040] The core board frame 10 is made of fiber-free copper foil. This ensures that the fiber-free density is uniform, preventing nonlinear expansion and contraction deformation. Furthermore, the stable and uniform thermal expansion coefficient of copper foil accelerates heat dissipation from the power device 20. Additionally, the copper foil possesses excellent chemical etching properties, resulting in high edge precision and burr-free etching during the etching process, meeting the high-precision processing requirements of through-slots. Specifically, the copper foil thickness is 115 μm, and the roughness of both the upper and lower surfaces is ≤0.5 μm.

[0041] S20. Perform graphic transfer processing on the core board frame 10 to form a first space 10a and a second space 10b that are not connected to each other within the core board frame 10.

[0042] Reference Figure 4 Image transfer processing includes processes such as lamination, development, exposure, etching, and lamination removal. Specifically, it can employ the following steps: (1) Core board pretreatment: Surface treatment of copper foil without glass fiber; (2) Film application: A layer of photosensitive dry film is uniformly applied to the surface of the copper foil; (3) Development: A mask with the target pattern (such as wiring lines, slot shape) is placed on top of the photosensitive dry film. The mask is irradiated with ultraviolet light. At this time, the patterned area on the mask will block the ultraviolet light, and the photosensitive dry film below will not be cured. However, the transparent area without the pattern on the mask allows ultraviolet light to penetrate, and the dry film below will be cross-linked and cured; (4) Exposure: The exposed copper foil is rinsed with a specific chemical developer. The uncured photosensitive dry film will be dissolved and removed by the developer, leaving only the cured photosensitive dry film. At this time, the surface of the copper foil will show the area covered by the cured dry film and the exposed metal area; (5) Etching: The developed copper foil is then etched into the copper foil. The copper foil is placed in a chemical etching solution (such as an acidic etching solution for copper metal layers). The etching solution will react chemically with the exposed metal area, corroding and removing the metal in that area. The metal area covered by the cured dry film will not be etched due to the protection of the dry film. After the etching reaches the preset depth, the copper foil is taken out and cleaned. At this time, a metal structure (such as wiring lines, rectangular through-holes, and circular through-holes) that is completely consistent with the target pattern will be left on the copper foil. (6) Film removal: The etched copper foil is rinsed with film removal solution to completely peel off the remaining cured dry film. After peeling, only the metal lines or through-hole structures formed by etching are retained. At this point, the pattern transfer process is completed. The functional structure (wiring layer or through-hole) that meets the design requirements is formally formed on the copper foil, providing a foundation for subsequent lamination, electroplating, chip mounting and other processes. The above image transfer process steps are only an example, but are not limited to this.

[0043] S30. Assemble the power device 20 into the first space 10a to form a three-layer semi-finished board.

[0044] Reference Figure 5 Specifically, the core board frame 10 formed in step S200 is browned and a high-temperature tape 100 is attached to its lower surface. The adhesive side of the high-temperature tape 100 is turned into a blind groove facing the through groove. Then, a high-precision pick and place machine is used to mount the power device 20 into the blind groove. At this time, the power device 20 is fixed in the blind groove under the adhesive action of the high-temperature tape 100.

[0045] S40. The pressed sheet and copper foil are sequentially covered on the top of the three-layer structure semi-finished plate, so that the pressed sheet and copper foil cover the corresponding areas of the first space 10a and the second space 10b, and the corresponding pressed sheet and copper foil are pressed together to form the second metal layer 50, and the resin of the pressed sheet at least fills part of the second space 10b.

[0046] Reference Figure 6Specifically, on the three-layer semi-finished product board formed in step S300, a press-fit sheet and a layer of copper foil are stacked on top of the blind groove (i.e., the first space 10a and the second space 10b) in sequence. Then, high-temperature pressing is performed so that the resin in the press-fit sheet is heated and melted and flows into the gap between the power device 20 and the wall of the blind groove. After the resin is cured, a second dielectric layer is formed. At this time, the power device 20 is stably embedded in the core board frame 10, and the covering copper foil forms a second metal layer 50.

[0047] S50. The pressed sheet and copper foil are sequentially covered under the power device 20, so that the pressed sheet and copper foil cover the corresponding areas of the first space 10a and the second space 10b, and the corresponding pressed sheet and copper foil are pressed together to form the fifth metal layer 60, and a five-layer structure semi-finished board is obtained.

[0048] Reference Figure 7 Specifically, the high-temperature tape 100 in step S400 is removed, and a pressing sheet and copper foil are sequentially stacked under the three-layer semi-finished board to cover the corresponding areas of the first space 10a and the second space 10b. Then, high-temperature pressing is performed so that the resin in the pressing sheet melts when heated. After the resin solidifies, a fifth dielectric layer is formed. At this time, the copper foil is fixed under the three-layer semi-finished board under the action of the resin to form a fifth metal layer 60, thereby obtaining a five-layer semi-finished board.

[0049] S60. Perform pattern transfer processing on the five-layer semi-finished board to form windows in the regions corresponding to the power device 20 and the second space 10b of the second metal layer 50 and the fifth metal layer 60, and perform ablation processing at the windows to form through holes between the second metal layer 50 and the power device 20, between the fifth metal layer 60 and the power device 20, and between the second metal layer 50 and the fifth metal layer 60, respectively.

[0050] Reference Figure 8 Specifically, by performing pattern transfer on the five-layer semi-finished board, the areas between the second metal layer 50 and the power device 20, the fifth metal layer 60 and the power device 20, and the areas between the second metal layer 50 and the fifth metal layer 60 are etched away, thereby forming φ70μm and φ90μm circular openings. Laser drilling is then used to perform laser ablation on the openings, thereby forming φ70μm blind vias between the second metal layer 50 and the power device 20, and between the fifth metal layer 60 and the power device 20, and forming φ90μm X-shaped through-holes between the second metal layer 50 and the fifth metal layer 60. It should be noted that the image processing steps for the five-layer semi-finished board are the same as the pattern transfer steps for the core board frame 10 described above, and will not be repeated here.

[0051] S70. Electroplating is performed on the five-layer semi-finished board to fill the through holes, thereby forming the metal pillar 70 in the area where the through holes are located, and the second metal layer 50, the fifth metal layer 60 and the power device 20 can be electrically connected by the metal pillar.

[0052] Reference Figure 9 Specifically, the five-layer semi-finished board undergoes electroplating to fill the φ70μm blind vias and φ90μm X-shaped through-holes, thereby forming φ70μm frustum-shaped copper pillars and φ90μm hourglass-shaped copper pillars. Simultaneously, the second metal layer 50 and the fifth metal layer 60 are thickened. The φ70μm frustum-shaped copper pillars electrically connect the second metal layer 50 and the power device 20, and the fifth metal layer 60 and the power device 20, while the φ90μm hourglass-shaped copper pillars electrically connect the second metal layer 50 and the fifth metal layer 60, thus achieving electrical connectivity between the second metal layer 50, the fifth metal layer 60, and the power device 20. In this way, the metal pillars formed by the through-holes create a complete conductive path between the second metal layer, the fifth metal layer, and the power device, ensuring that the power device can receive electricity or output signals without requiring additional complex wiring structures. This design is suitable for the compact design of the five-layer semi-finished board and reduces space occupation.

[0053] In one embodiment, the preparation method further includes at least the following steps: S80. Perform graphic transfer processing on the five-layer structure semi-finished plate with the metal pillar 70 to form lines on the second metal layer 50 and the fifth metal layer 60.

[0054] Reference Figure 10 After the circuitry is formed on the second metal layer 50 and the fifth metal layer 60, the five-layer semi-finished board undergoes a browning treatment, forming a browning film on the surface of the circuitry on the second metal layer 50 and the fifth metal layer 60. This browning film is a copper-metallic organic complex with a molecular-level thickness, characterized by a large specific surface area, high surface tension, and polarity. It significantly increases the bonding force between buried vias and the circuitry surface and the via / gap filling resin, improving product reliability. It should be noted that the circuit layout pattern on the surface of the second metal layer 50 and the circuit layout pattern on the surface of the fifth metal layer 60 can be the same image, or different patterns can be set according to actual needs.

[0055] S90. The pressed sheet and copper foil are sequentially covered with the second metal layer 50 and the fifth metal layer 60, so that the pressed sheet and copper foil cover the area corresponding to the circuit, and the corresponding pressed sheet and copper foil are pressed together to form the first metal layer 80 and the sixth metal layer 90, and a nine-layer structure semi-finished board is obtained.

[0056] S100. Process the nine-layer semi-finished board to form the final product.

[0057] Reference Figure 11 Specifically, the nine-layer semi-finished board undergoes pattern transfer to etch away the areas between the first metal layer 80 and the second metal layer 50, and between the sixth metal layer 90 and the fifth metal layer 60, to form φ70μm circular openings. Laser drilling is then used to ablate these openings, creating φ70μm blind vias between the first metal layer 80 and the second metal layer 50, and between the sixth metal layer 90 and the fifth metal layer 60. The nine-layer semi-finished board is then electroplated to fill the φ70μm blind vias, forming φ70μm frustum-shaped copper pillars. Simultaneously, the first metal layer 80 and the sixth metal layer 90 are thickened, and pattern transfer is performed on the first metal layer 80 and the sixth metal layer 90 to create wiring. Finally, the nine-layer semi-finished board undergoes solder mask silkscreening, solder mask exposure, solder mask development, and post-curing to form a solder mask layer. Finally, an immersion nickel-palladium gold plating process is applied to form the final product.

[0058] It should be noted that the pressing sheet used in the above steps is a glass fiber-free pressing sheet. This ensures that the formed dielectric layer has no uneven glass fiber density and will not produce nonlinear expansion and contraction deformation, which can effectively avoid cross-layer conductivity failure caused by pore position deviation.

[0059] In practical applications, when the etching solution corrodes the upper and lower surfaces of the core board frame 10, it will laterally etch to both sides, resulting in an actual linewidth narrower than the design value. For example, if the thickness of the core board frame 10 is 35 μm, the lateral etching amount is about 8-10 μm; if the thickness of the core board frame 10 is 105 μm, the lateral etching amount can reach 18-20 μm. Without compensation, the actual linewidth will deviate significantly from the design value, affecting impedance and soldering performance. Therefore, this application also provides an etching compensation method for preparing the first space 10a of the chip packaging structure described above, to counteract the lateral etching generated during the etching process and ensure that the designed linewidth is consistent with the actual production linewidth.

[0060] Reference Figure 12 and 13 The etching compensation method includes at least the following steps: S11. Based on the dimensions of the power device 20, the dimensions of the initial through slot are set, wherein the cross-section of the initial through slot is rectangular, and the side of the initial through slot is spaced by a distance d1 from the side of the power device 20. S12. Set a first compensation circular hole with the first base point as the center and a distance d2 as the diameter, and place the first compensation circular hole at the four corners of the initial through slot; wherein, the first base point is near the corner of the rectangle and is spaced d3 away from the two sides of the initial through slot. S13. Set a second compensation hole with the second base point as the center and a distance d4 as the diameter, and place the second compensation hole at the four corners of the initial through slot; wherein the second base point is located at the end of the rectangle; S14. Flatten the intersection area of ​​the first compensation hole and the second compensation hole to obtain an etching pattern; S15. Based on the etching pattern, perform a pattern transfer process on the core board frame 10 to form the first space 10a.

[0061] This etching compensation method adds a first compensation circular hole and a second compensation circular hole at the four corners of the initial through slot. The first compensation circular hole and the second compensation circular hole are used as compensation structures to effectively offset the corner deviation during the etching process. Then, the intersecting area is further flattened so that the final etched first space 10a size is consistent with the design value. This ensures that when the power device 20 is subsequently attached, the four corners of the power device 20 will not hit the four corners of the first space 10a, thereby avoiding affecting the mounting accuracy or even chip breakage.

[0062] Reference Figure 14 and Figure 15 This application provides a plate separation method based on the preparation method described above, the method comprising at least the following steps: S21. Select a copper foil without glass fiber as the core board frame 10, and divide the core board frame 10 into multiple encapsulation areas.

[0063] S22. Perform pattern transfer processing on the core board frame 10 to form a first space 10a and a second space 10b that are not interconnected in the multiple encapsulation areas, and etch at least a portion of the cutting channel area between adjacent encapsulation areas so that adjacent encapsulation areas are connected by connecting ribs.

[0064] Specifically, after dividing the core board frame 10 into multiple packaging areas, a portion of the cutting groove area is directly etched between adjacent packaging areas to predefine the baseline for board separation, avoiding damage to the packaging areas due to inaccurate positioning during subsequent cutting. In addition, because only a portion of the cutting groove is etched, the remaining connecting ribs connect all packaging areas into a complete core board frame 10, ensuring that the core board frame 10 has no risk of chip breakage in subsequent processes.

[0065] S23. Perform graphic transfer processing on the five-layer semi-finished plate to form windows in the area corresponding to the connecting ribs of the second metal layer 50 and the fifth metal layer 60, and perform ablation processing on the windows to hollow out the cutting area covered by the connecting ribs.

[0066] S24. The pressed sheet and copper foil are sequentially covered with the second metal layer 50 and the fifth metal layer 60, so that the pressed sheet and copper foil cover the area corresponding to the circuit, and the corresponding pressed sheet and copper foil are pressed together to form the first metal layer 80 and the sixth metal layer 90, and the cutting area is filled with resin. S25. Cut the core board frame 10 along the cutting area to form a plurality of the sealing structures.

[0067] In other words, the board separation method in this embodiment ensures that when using thick copper foil as the core board frame 10, the cutting paths between effective substrate units are all copper-free full substrate areas. This can effectively avoid different copper layers being exposed on the sides after cutting, causing short circuits between different copper layers when the subsequent substrate works in a humid environment.

[0068] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and substitutions can be made without departing from the technical principles of the present invention, and these improvements and substitutions should also be considered within the scope of protection of the present invention.

Claims

1. A chip packaging structure, characterized in that, include: The core board frame is a single metal plate without glass fiber, and the core board frame is provided with a first space and a second space that are arranged in a first direction, and the first space and the second space are not connected to each other. A power device is disposed within the first space and is bonded and fixed to the core board frame by an adhesive. A second metal layer, a third metal layer, a fourth metal layer, and a fifth metal layer, wherein the third and fourth metal layers are respectively connected to the upper and lower surfaces of the power device in the first direction; the second metal layer is spaced apart from the third metal layer in the first direction and is located on the side of the third metal layer away from the power device; the fifth metal layer is spaced apart from the fourth metal layer in the first direction and is located on the side of the fourth metal layer away from the power device; and... A metal pillar is connected between the second metal layer and the fifth metal layer. The metal pillar is arranged in the second space and does not contact the core board frame. A resin layer is filled between the metal pillar and the core board frame in the second space.

2. The chip packaging structure according to claim 1, characterized in that, A fiber-free resin layer is filled between the second metal layer and the third metal layer, the fourth metal layer and the fifth metal layer, and between the second metal layer and the fifth metal layer.

3. The packaging substrate structure according to claim 1, characterized in that, The thickness of the core board frame is D, and 50μm≤D≤500μm.

4. The chip packaging structure according to claim 1, characterized in that, The packaging structure further includes a first metal layer and a sixth metal layer, wherein the first metal layer and the second metal layer are spaced apart in the first direction and located on the side of the second metal layer away from the power device, and the sixth metal layer and the fifth metal layer are spaced apart in the first direction and located on the side of the fifth metal layer away from the power device; and... A fiber-free resin layer is filled between the first metal layer and the sixth metal layer.

5. The chip packaging structure according to claim 1, characterized in that, The outer edge of the chip packaging structure is provided with a resin layer that covers at least the second metal layer, the core board frame, and the fifth metal layer. The resin layer is a fiberless resin layer.

6. A method for preparing the chip packaging structure according to any one of claims 1-5, characterized in that, The method includes at least the following steps: Copper foil without glass fiber was selected as the core board frame; The core board frame is subjected to graphic transfer processing to form a first space and a second space that are not connected to each other within the core board frame. The power devices are assembled into the first space to form a three-layer semi-finished board; The pressed sheet and copper foil are sequentially covered on the top of the three-layer structure semi-finished plate, so that the pressed sheet and copper foil cover the corresponding areas of the first space and the second space, and the corresponding pressed sheet and copper foil are pressed together to form the second metal layer, and the resin of the pressed sheet at least fills part of the second space. The pressed sheet and copper foil are sequentially covered under the power device, so that the pressed sheet and copper foil cover the corresponding areas of the first space and the second space, and the corresponding pressed sheet and copper foil are pressed together to form the fifth metal layer, and a five-layer structure semi-finished board is obtained. The five-layer semi-finished board is subjected to pattern transfer processing, so that the second metal layer and the fifth metal layer form windows in the regions corresponding to the power device and the second space, and the windows are subjected to ablation processing to form through holes between the second metal layer and the power device, between the fifth metal layer and the power device, and between the second metal layer and the fifth metal layer, respectively. The five-layer semi-finished board is electroplated to fill the through holes, thereby forming the metal pillars in the area where the through holes are located. The metal pillars can then be used to electrically connect the second metal layer, the fifth metal layer and the power device.

7. The preparation method according to claim 6, characterized in that, The laminated sheet is a fiber-free laminated sheet.

8. The preparation method according to claim 6, characterized in that, The method further includes at least the following steps: The five-layer semi-finished plate with the metal pillars is subjected to graphic transfer processing to form lines on the second metal layer and the fifth metal layer; The pressed sheet and copper foil are sequentially covered to cover the second metal layer and the fifth metal layer, so that the pressed sheet and copper foil cover the area corresponding to the circuit, and the corresponding pressed sheet and copper foil are pressed together to form the first metal layer and the sixth metal layer, and a nine-layer structure semi-finished board is obtained. The final product is formed by processing the nine-layer semi-finished board.

9. A plate separation method based on the preparation method according to any one of claims 6-8, characterized in that, The method includes at least the following steps: Copper foil without glass fiber is selected as the core board frame, and multiple encapsulation areas are divided within the core board frame; The core board frame is subjected to pattern transfer processing to form a first space and a second space that are not connected to each other in the multiple encapsulation areas, and at least a portion of the cutting channel area between adjacent encapsulation areas is etched so that adjacent encapsulation areas are connected by connecting ribs. The five-layer semi-finished plate is subjected to graphic transfer processing, so that the second metal layer and the fifth metal layer form windows in the area corresponding to the connecting rib, and the windows are subjected to ablation processing to hollow out the cutting area covered by the connecting rib. The pressed sheet and copper foil are sequentially covered to cover the second metal layer and the fifth metal layer, respectively, so that the pressed sheet and copper foil cover the area corresponding to the circuit, and the corresponding pressed sheet and copper foil are pressed together to form the first metal layer and the sixth metal layer, and the cutting area is filled with resin. The core board frame is cut along the cutting area to form multiple sealing structures.

10. A method for etching compensation of the first space in preparing the packaging structure according to any one of claims 1-5, characterized in that, It should include at least the following steps: Based on the dimensions of the power device, the dimensions of the initial through slot are set, wherein the cross-section of the initial through slot is rectangular, and the side of the initial through slot is spaced apart from the side of the power device by a distance d1. A first compensation hole is set with the first base point as the center and the distance d2 as the diameter, and the first compensation hole is positioned at the four corners of the initial through slot. The first base point is located near the corner of the rectangle and is spaced d3 away from the two sides of the initial through slot. A second compensation hole is set with the second base point as the center and the distance d4 as the diameter, and the second compensation hole is positioned at the four corners of the initial through slot, wherein the second base point is located at the end of the rectangle; The intersection area of ​​the first compensation hole and the second compensation hole is leveled to obtain an etched pattern; Based on the etched pattern, a pattern transfer process is performed on the core board frame to form the first space.

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