Managing address spaces in register banks of system base chip

Abstract

Examples include managing an address space in a register bank of a system base chip. An apparatus includes a bus slave and a system base chip. The system base chip includes a register block, an access controller that limits a range of the bus slave device to a selected address set of the register block, and an address space manager that sets the selected address set of the register block.

Description

Priority Statement

[0001] This application claims priority to International Patent Application Serial No. PCT / CN2023 / 107648, filed on July 17, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The example sets generally involve the 10SPE physical layer (PHY). Some example sets involve the system base chip implementing the transceiver of the 10SPE PHY and the microcontroller implementing the controller of the 10SPE PHY. Some example sets involve the system base chip managing the address space in the register set of the system base chip. Background Technology

[0003] Integrated circuits (ICs) are used in a variety of operating environments and may be subjected to a variety of stresses. Attached Figure Description

[0004] To facilitate the identification of any particular element or action in the discussion, the most important number in the figure labels refers to the figure number of the element when it was first introduced.

[0005] Figure 1 It is a block diagram of a system base chip (SBC) designed to manage register access and extend the address space of a 10BASE-T1S transceiver, based on one or more examples.

[0006] Figure 2 It is a block diagram of a system including a system base chip and a microcontroller, based on one or more examples.

[0007] Figure 3 It is a schematic diagram illustrating example formats of MDIO bit streams and I2C bit streams received at an MDIO slave device and an I2C slave device with address space management, respectively, based on one or more examples.

[0008] Figure 4 It is a schematic diagram depicting an example of a purpose-specific register based on one or more examples.

[0009] Figure 5A It is a schematic diagram depicting a register set or a portion thereof in an example environment based on one or more examples.

[0010] Figure 5B This is a schematic diagram that further illustrates the structure of the register group in the example environment.

[0011] Figure 6Example procedures are illustrated, based on one or more examples, to represent the behavior of access control logic that enables modification of address allocations within the system base chip or its address controller.

[0012] Figure 7 It is a flowchart illustrating the process of adding a non-native register address to the address allocation of an MDIO slave device, thereby expanding the accessible register space, based on one or more examples.

[0013] Figure 8 It is a flowchart illustrating the process of verifying address access requests based on one or more examples to ensure that they fall within an authorized address allocation.

[0014] Figure 9 This illustrates one aspect of the subject based on one or more examples.

[0015] Figure 10 It is a block diagram of a circuit that can be used in some examples to implement the various functions, operations, actions, processes or methods disclosed herein. Detailed Implementation

[0016] In the following detailed description, reference is made to the accompanying drawings, which form part of this disclosure, and specific examples of embodiments in which this disclosure may be practiced are shown by way of example. These examples have been described in sufficient detail to enable those skilled in the art to practice this disclosure. However, other examples may be utilized, and changes in structure, materials, and processes may be made without departing from the scope of this disclosure.

[0017] The illustrations presented herein are not intended to be actual views of any particular method, system, device, or structure, but are merely idealized representations used to describe the examples described herein. The accompanying drawings are not necessarily drawn to scale. For the reader's convenience, similar structures or components in the various drawings may retain the same or similar numbering; however, similarity in numbering does not imply that the structure or component must be identical in size, composition, configuration, or any other property.

[0018] The following description may include examples to help enable those skilled in the art to practice the disclosed examples. The use of the terms “exemplary,” “for example,” and “e.g.” means that the description is illustrative, and while the scope of this disclosure is intended to cover examples and legal equivalents, the use of such terms is not intended to limit the examples or the scope of this disclosure to the specified components, steps, features, functions, etc.

[0019] It should be readily understood that the components of the examples, as generally described herein and illustrated in the accompanying drawings, can be arranged and designed in a variety of different configurations. Therefore, the following description of various examples is not intended to limit the scope of this disclosure, but rather to represent various examples only. While various aspects of the examples may be presented in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0020] Furthermore, the specific embodiments shown and described are merely examples and should not be construed as the only way to implement this disclosure unless otherwise indicated herein. Components, circuits, and functions may be shown in block diagram form so as not to obscure this disclosure with unnecessary detail. Rather, the specific embodiments shown and described are merely exemplary and should not be construed as the only way to implement this disclosure unless otherwise indicated herein. Additionally, block definitions and logical partitioning between blocks are examples of specific embodiments. It will be apparent to those skilled in the art that this disclosure can be practiced with many other partitioning solutions. In most cases, details regarding timing considerations, etc., have been omitted, where such details do not require a full understanding of this disclosure and are within the capabilities of those skilled in the art.

[0021] Those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and methods. For clarity of presentation and description, some figures may illustrate a signal as a single signal. It should be understood by those skilled in the art that a signal may represent a signal bus, wherein the bus may have multiple bit widths, and this disclosure can be implemented on any number of data signals, including a single data signal.

[0022] The various exemplary logic blocks, modules, and circuits described in conjunction with the examples disclosed herein may be implemented or performed using a general-purpose processor, a special-purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic components, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor (which may also be referred to herein as a host processor or simply host) may be a microprocessor, but in alternative embodiments, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. A general-purpose computer including a processor is considered a special-purpose computer when executing computational instructions (e.g., software code, but not limited thereto) related to the examples described herein.

[0023] Examples can be described based on processes depicted as flowcharts, schematic diagrams, structural diagrams, or block diagrams. While a flowchart may describe operable actions as a continuous process, many of these actions may be performed in another sequence, in parallel, or substantially concurrently. Furthermore, the order of actions can be rearranged. A process may correspond to a method, thread, function, procedure, subroutine, or subroutine, but is not limited to these. Moreover, the methods disclosed herein can be implemented in hardware, software, or both. If implemented in software, functions may be stored or transmitted as one or more instructions or code onto a computer-readable medium. Computer-readable media includes both computer storage media and communication media, which includes any medium that facilitates the transfer of a computer program from one location to another.

[0024] Any reference to elements in this document using names such as “first”, “second”, etc., does not limit the number or order of those elements unless such limitation is explicitly stated. Rather, these names may be used herein as a convenient way to distinguish between two or more elements or instances of elements. Thus, referring to a first element and a second element does not imply that only two elements can be used there, or that the first element must somehow precede the second element. Furthermore, unless otherwise specified, a group of elements may include one or more elements.

[0025] As used herein, the term "substantially" refers to and includes the degree to which a given parameter, attribute, or condition is satisfied with a small degree of variance, such as, for example, within acceptable manufacturing tolerances, as would be understood by one of ordinary skill in the art. For example, depending on whether a particular parameter, attribute, or condition is substantially satisfied, it may be satisfied with at least 90%, at least 95%, or even at least 99%.

[0026] As used herein, any relational terms (such as "above", "below", "on", "under", "upper", "lower", etc., but not limited thereto) are used for clarity and convenience in understanding this disclosure and the accompanying drawings, and such relational terms do not imply or depend on any particular preference, orientation or order unless the context clearly indicates otherwise.

[0027] In this description, the term "coupled" and its derivatives may be used to indicate that two elements cooperate or interact with each other. When an element is described as "coupled" to another element, the element may be in direct physical or electrical contact, or an intermediary element or layer may be present. In contrast, when an element is described as "directly coupled" to another element, no intermediary element or layer is present. The term "connection" is used interchangeably with the term "coupled" in this specification and has the same meaning unless otherwise expressly indicated or the context will otherwise indicate to a person skilled in the art.

[0028] As used herein, the terms “assert,” “deassert,” and their derivatives used with respect to the pin and the component are referred to respectively to assert or deassert the signal associated with the pin (e.g., a signal specifically assigned to or to the pin, but not limited thereto).

[0029] A system base chip (SBC) is an integrated circuit (IC) that combines multiple functions for operating an electronic system. SBCs typically integrate a variety of different functions into a single chip. These functions, as non-limiting examples, include: power management functions for managing the power supply to the system, such as, but not limited to, voltage regulators, power switches, or protection circuits; communication interfaces, such as, but not limited to, CAN (Controller Area Network), LIN (Local Interconnect Network), SPI (Serial Peripheral Interface), or I2C (Internal Integrated Circuit); embedded systems for controlling and coordinating tasks, such as, but not limited to, state machines or microprocessors; analog functions, such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), temperature sensors, and other signal conditioning circuitry; and diagnostic and safety functions, such as monitoring and reporting voltage levels, temperature, or fault conditions, but not limited to these.

[0030] SBCs exist in a variety of operating environments, including automotive and industrial applications. A non-limiting example of an automotive application of SBCs is in 10SPE (i.e., 10 Mbps single-pair Ethernet) networks (also known as "10BASE-T1S networks"). 10SPE is a network technology specified in IEEE 802.3 clauses 147 and 148. 10SPE can be used to provide collision-free deterministic transmission over multipoint networks.

[0031] In some cases, as a non-limiting example, the transceiver (xcvr) and controller of a 10SPE physical layer device (PHY) may reside on different dies, thus subjecting the dies to different processing conditions. This architecture is referred to herein as a “split PHY” architecture. The digital block of the PHY controller, which is susceptible to damage during high-voltage temperature processes, resides on a first die that does not undergo such processes. The analog and digital blocks of the PHY transceiver (which are not susceptible to damage during high-voltage temperature processes, or where such high-voltage temperature processes are required) reside on a second die that does undergo such high-voltage temperature processes.

[0032] The 10SPE transceiver interface standard, currently being developed and standardized by Open Consortium Technical Committee 14 (hereinafter referred to as "TC14"), defines a hardware interface (specifically, a 3-pin hardware interface) for communication between the PHY transceiver and the PHY controller in a discrete PHY architecture.

[0033] In 10SPE, the microcontroller (MCU) implements the PHY controller function, and the SBC implements the PHY transceiver function. In 10SPE, the SBC's non-transceiver responsibilities include regulating power delivery, observability / control in the high-voltage domain, and functional safety mechanisms to enable the MCU to reach a safe state. Therefore, in addition to transceiver functions, the SBC also implements electronic system functions such as power management, watchdog circuits, monitors, and general-purpose input / output (GPIO), but is not limited to these.

[0034] TC14 describes the low-power (sleep-wake) behavior of PHY transceivers for partial networking. Partial networking refers to the feature of enabling selective power management and communication capabilities within a network. Partial networking allows certain network nodes or devices to enter a low-power state or sleep state while still maintaining basic communication functionality. In Ethernet networks, partial networking is used to optimize power consumption, particularly in automotive or industrial applications. Allowing selected devices to enter a low-power state or sleep state can reduce overall power consumption, extend battery life, or improve energy efficiency, but is not limited to these.

[0035] The System Base Chip (SBC) contains a 10BASE-T1S transceiver. Due to the limited number of vendor-specific registers defined by the Open Alliance (OA) specification, extended register space is necessary. The OA specification allows access to 32 registers via the Management Data Input / Output (MDIO) interface, of which only 15 are available for vendor-specific use. Additional registers may sometimes be desired for (such as in non-limiting examples) tuning, testing, eFuse, and debugging, but are not limited to these.

[0036] One or more examples in general involve managing the address space within the register set of the SBC that implements the 10BASE-T1S transceiver. The SBC that implements the 10BASE-T1S transceiver is able to extend the register space associated with the 10BASE-T1S transceiver beyond the 32 registers defined by the OA specification, and manage indirect access to other register spaces within the SBC.

[0037] In one or more examples, the SBC utilizes at least two of the 15 vendor-specific registers as control / address and data registers, thereby allowing access to an extended register space beyond the 32 registers specified in the OA specification. One of the at least two registers is used as a control register and includes fields for reading / writing control and an address for the extended configuration register. The other of the at least two registers is used as a data register and holds data to be written to or read from the extended register specified by the control register.

[0038] In one or more examples, the SBC includes register sets that are partitioned (e.g., logically partitioned, physically partitioned, or both, but not limited to) into at least two groups: a first group of registers accessible by the MDIO driver and a distinct second group of registers accessible by the I2C driver. The MDIO driver handles access to registers in a transceiver-specific address space, and the I2C driver utilizes a separate register space (e.g., a register space different from the transceiver-specific address space) to manage access to registers used for non-transceiver functions such as power delivery and watchdog features.

[0039] In some cases, the corresponding firmware for the MDIO and I2C drivers may have a list of resources that the firmware can utilize, including register addresses. However, in other cases, the firmware may be customizable and therefore potentially subject to breaches due to unauthorized access. In one or more examples, the SBC includes hardware locking to ensure that cross-access between the MDIO and I2C-accessible register spaces is prevented during normal operation, maintaining security and integrity. Attempting to access the wrong resource triggers a breach, and the hardware at the SBC will prevent the access from completing. In this way, SBC-specific registers are inaccessible via the MDIO driver, and transceiver-specific registers are inaccessible via I2C.

[0040] In one or more examples, as a non-limiting example, a specific set or series of cryptographic keys (“access keys”) can be used to temporarily disable hardware lockout. As a non-limiting example, it may be desirable to disable hardware lockout for debugging, testing, or programming, but is not limited to these purposes. Access keys disable hardware lockout, thereby unlocking cross-access to registers by the MDIO driver and I2C driver.

[0041] Figure 1 It is a block diagram of the system base chip (SBC) and architecture designed to manage register access and extend the address space of the 10BASE-T1S transceiver, based on one or more examples.

[0042] System 100 includes a system base chip (SBC) 102 and one or more bus slave devices 112. System base chip 102 includes an address space manager 104, an access controller 106, and a register set 110. Access controller 106 includes access control logic 108.

[0043] Bus slave device 112 is a device that operates as a peripheral device or slave device of a bus master device in a computer or electronic communication system.

[0044] In a bus-based architecture, electronic communication systems, data, and control signals can be transmitted using the bus between corresponding bus slave devices in bus slave device 112 (via bit streams) and between bus slave device 112 and bus master device. Bus slave device 112 monitors the bus (e.g., MDIO or I2C) to receive commands or requests addressed to the bus, processes the received data or instructions, and provides the requested information or performs the requested action. One or more bus slave devices in bus slave device 112 can be implemented as needed at system base chip (SBC) 102 or another device.

[0045] One or more of the bus slave devices in bus slave device 112 may be MDIO (Management Data Input / Output) bus slave devices. Non-limiting examples of MDIO bus slave devices include physical layer (PHY) transceivers, Ethernet switches (e.g., Gigabit Ethernet switches, but not limited to), network interface cards (NICs), Ethernet media converters, and Ethernet routers and gateways.

[0046] One or more bus slave devices in bus slave device 112 may be I2C (Internal Integrated Circuit) bus slave devices. Non-limiting examples of I2C bus slave devices include sensors, memory chips, or peripheral devices. One or more bus slave devices in bus slave device 112 may be a PCI (Peripheral Component Interconnect) bus system. Non-limiting examples of PCI bus slave devices include network interface cards (NICs), sound cards, or peripheral devices. Bus slave device 112 monitors the bus to receive commands or requests addressing the bus, processes received data or instructions, and provides requested information or performs requested actions.

[0047] Address space manager 104 dynamically manages the accessibility of one or more bus pairs to register group 110. Address space manager 104 operates by adding or removing addresses from a selected set of addresses in register group 110. The selected set of addresses corresponds to a selected portion of the address space of the register group that a bus (e.g., an MDIO bus or an I2C bus, without emulation) can interact with. In one or more examples, address space manager 104 manages the accessibility of one or more bus pairs to register group 110 in response to address space expansion request 114. Address space expansion request 114 may identify a bus slave device (e.g., one of bus slave devices in bus slave device 112, but not limited thereto) and includes an indication of the desired address space expansion (e.g., the number of additional registers or addresses or the amount of additional memory space, but not limited thereto). For example, address space expansion request 114 requesting an expansion of a transceiver-specific address space may identify an 10BASET1S transceiver and indicate the number of additional registers. In some cases, it may be desirable to reduce the extended address space of a bus slave device (e.g., to free up space for another bus slave device, but not limited thereto), so the address space extension request 114 may also identify the bus slave device and include an identifier of the desired address space subtraction (e.g., the number of registers or addresses to be subtracted or the amount of memory space to be subtracted, but not limited thereto). In one or more examples, the address space manager 104 will not reduce the address space below the bus native address space (e.g., the minimum number of addresses or registers specified in the specification, but not limited thereto).

[0048] In this way, the address space manager 104 effectively controls the range of registers in register set 110 that the bus (or bus slave device) has the right to read or write, thereby providing flexibility and ensuring efficient use of register set resources. As a non-limiting example, the address space manager 104 adjusts the range of accessible addresses in response to address space expansion request 114, thereby effectively controlling which parts of the register set the bus can interact with. This ensures flexibility and efficient use of register set resources.

[0049] Access controller 106 restricts the scope of the bus to selected addresses within register set 110, which correspond to selected portions of the address space of register set 110. Access controller 106 enforces interaction boundaries within register set 110 of a given bus. It does this by preventing any attempt to interact with addresses outside the set of selected addresses falling within the address space of the register set. As a non-limiting example, this ensures that a given bus can only read from or write to the allocated address range, thus protecting the integrity of other addresses within the register set.

[0050] Access control logic 108 of access controller 106 (“access ctrl logic 108”) serves as a security mechanism for expanding the selected address set of the address space of register set 110. In one or more examples, if the correct set of access keys is provided, access ctrl logic 108 only permits address space manager 104 to add or remove addresses from the selected address set. This key-based verification process ensures secure and controlled expansion of the accessible address space, preventing unauthorized or unintentional modification. Therefore, for a specific address space or portion of the register set, access ctrl logic 108 knows the predefined sequence or set of digital keys that authorize any changes to the address space. Access ctrl logic 108 also knows the current state of the corresponding address space, including which addresses are currently part of the selected set.

[0051] A bus native address is an address that can be directly accessed by the corresponding bus master device (e.g., an address in a bus slave device, such as the address of a register in register set 110, but not limited to this). As used herein, the term "direct access" (and its derivatives) refers to access using a single access operation (e.g., a single read or write operation, but not limited to this), and the term "directly accessible" refers to access using a single access operation. A non-limiting example of a directly accessible address is that the address is placed on an address line, decoded at the register set, and data is read from or written to a data line. This direct approach allows for uniform firmware driver operation. In contrast to a native address, a scalable address is an address that requires access to more than a single access operation (e.g., the address of a register in register set 110, but not limited to this). Scalable addresses are not directly accessible in a single step and involve additional stages, such as using registers as temporary registers.

[0052] Figure 2 This is a block diagram of system 200. System 200 includes a system base chip 202 and a microcontroller 214. System base chip 202 includes an MDIO slave device 204 with address space management, access Ctrl logic 206, an I2C slave device 208, an access controller 210, and a register set 212. Microcontroller 214 includes an MDIO master device 216 and an I2C master device 218.

[0053] The MDIO slave device 204 with address space management is an MDIO bus slave device and address space manager (e.g., Figure 1 The address space manager (104). Accessing Ctrl logic (206) is... Figure 1 This is a non-restrictive example of access Ctrl logic 108. Access controller 210 is... Figure 1 A non-limiting example of access controller 106. Register group 212 is Figure 1 A non-restrictive example of register group 110.

[0054] The system base chip 202 integrates both register set 212 and PHY transceiver (xcvr logic or finite state machine not depicted) and provides a flexible address space allocation mechanism. Initially, different portions of the address space of register set 212 are dedicated to the MDIO bus / PHY transceiver, and different portions of the address space of register set 212 are dedicated to I2C slave device 208. The system base chip 202 provides dynamic address space management (including, but not limited to, adding or subtracting address spaces from a selected address space set).

[0055] This allows I2C to allocate the address space from device 208 (in Figure 2 Some or all of the address space (referred to as "extreg addr") in the MDIO slave device (which may include some or all of the address space of the SBC used for non-PHY transceiver-specific functions) can be accessed by the MDIO slave device, thereby expanding the address range that the MDIO can interact with. The allocation process is controlled by an address space manager (e.g., address space manager 104, but not limited thereto), which is integrated with the MDIO slave device, but it can also be a separate logic block (e.g., not integrated with the MDIO slave device, but not limited thereto). The allocation process is regulated by access ctrl logic 206 to maintain secure and controlled access to the resources of register set 212 for the purpose of expanding or reducing the address space. Access ctrl logic 206 ensures secure and controlled access to the register set by verifying the provided key and validating the address space modification. A signal line for an unlock indication (UNLOCK) is shown between access ctrl logic 206 and access controller 210. The unlock signal is used to control the modification of the address allocation. In one or more examples, as a non-limiting example, address assignments may be maintained at the address domain table or extended domain table of the MDIO slave device. Accessing ctrl logic 206 requires the correct set of keys to generate an unlock signal. Once verified, the unlock signal enables the MDIO slave device 204 (part of the MDIO slave device) with address space management to modify the address space, such as adding or removing addresses. In various examples, a first value of the unlock signal may enable modification of the address assignments, and a different second value of the unlock signal (different from the first value) may disable modification of the address assignments.

[0056] As a non-limiting example, adjusting address allocation may include updating control registers or tables (e.g., expanding registers for control and data). Figure 1This can be represented as "EXTN CTRL&DATA" (but is not limited to) to include a new address within an MDIO allocation. Adjusting an address allocation may also include updating control registers or tables to set registers as temporary registers to access one or more extended registers, as discussed below. Adjusting an address allocation may also include updating (optionally including) control registers or tables to remove an address from an I2C allocation.

[0057] The MDIO slave device 204 with address space management is responsible for managing the register space accessible via the MDIO interface. As discussed above, this may include transceiver-specific address spaces. Address and data signal lines are shown between the MDIO slave device 204 with address space management and access controller 210, and between the I2C slave device 208 and access controller 210. Signals on the address lines specify the address of a register to be accessed (read from or written to) in register set 212, and signals on the data lines carry the actual data to be written to or read from the specified register address. In the hypothetical example, the MDIO slave device 204 with address space management or the I2C slave device 208 receives address information from the MDIO master device 216 or the I2C master device 218 and uses this signal to identify a specific register in register set 110.

[0058] This architecture provides a high degree of flexibility and efficiency in managing the address space of the register set, making it adaptable to changing requirements of the system base chip operation or the operation of MDIO slave devices.

[0059] Register set 212 includes several purpose-specific registers: a command register and a lock control register, whose bits are used to control access to and allocation of portions of the address space of register set 212. This setup allows for flexible, controlled, and secure access to and manipulation of registers within the set, especially for extended or indirect access scenarios.

[0060] Figure 3 It is a schematic diagram illustrating example formats of MDIO bit stream 300 and I2C bit stream 302 received at an MDIO slave device and an I2C slave device 208 having address space management 204, respectively, based on one or more examples.

[0061] MDIO and I2C each have a corresponding data line and a clock line (clock line not shown). Because they each have a corresponding data line, data is received as a bit stream in the format of MDIO bit stream 300 and I2C bit stream 302.

[0062] Switching to MDIO bitstream 300, bits #1 through #8 are preamble bits, i.e., the sequence of bits prepared for incoming data from the MDIO slave device. Bit #9 is the start sequence, signaling the start of an MDIO frame. Bits #11 and #12 specify the operation type, such as read or write. The next four bits (bits #13 through #16) represent the physical address, identifying which MDIO device the command is intended for. The next five bits (bits #17 through #21) are the register address within the target device. The remaining bits are the data payload used for the operation.

[0063] Proceeding to I2C bit stream 302, the I2C bit stream begins with a start bit indicating the start of communication. Following the start bit is a 7-bit address field, which specifies the I2C slave device address. The next bit indicates the operation type (read or write). The next bit is an acknowledgment bit sent by the I2C slave device to confirm receipt of the address. The following bits contain the data payload to be transmitted (reading from or writing to the I2C slave device). The last bit of I2C bit stream 302 is a stop bit, marking the end of communication.

[0064] Both the MDIO driver and the I2C driver utilize bit streams for data transfer, thereby ensuring synchronous communication via a single data line and an accompanying clock line (not shown). MDIO bit stream 300 and I2C bit stream 302, their respective formats and bit values, allow access to and management of the register space within the SBC, enabling precise control and data transfer to and from MDIO and I2C slave devices.

[0065] Figure 4 It is a schematic diagram depicting one or more examples of 400.

[0066] Figure 4 The structure and function of example purpose-specific register 400 within the SBC are illustrated, including control registers, extended control registers, and data temporary registers. These registers manage the extended address space and ensure secure and flexible access to register set resources. The control register handles key-based security mechanisms, the extended control register manages read / write operations on the extended address space, and the data temporary register facilitates indirect data access.

[0067] Control Register 408: This register includes three key-related fields: a first key bit, a second key bit, and an enable bit. The first key bit indicates whether the first key (key1) has been received. Except when key2 is written, the first key bit is reset (or cleared) whenever any write is made to a specific register named SFTR. The second key bit indicates that the second key (key2) has been received. When both key1 and key2 are "1", the second key bit allows write access to the SFTR register. This bit is also reset whenever any write is made to another specific register, SFIRm. The enable bit serves as a control signal for firmware (FW) access to all Control Status Register (CSR) bits in the indirection domain. When set to "1", the enable bit enables FW access, and when set to "0", it disables FW access. Before enabling or disabling this bit, a specific key value needs to be written to the SFTR register: as a non-limiting example, SFTR key1 (16'h4149), followed by SFTR key2 (16'h4155). SFTR and SFTRm are not shown.

[0068] Extended Control Register 402: This register includes several fields, including an extended address field, a read Ctrl, and a write Ctrl. The extended register address field stores the address as part of a selected portion of the address space of the register set. The read Ctrl acts as a control signal. When this bit is set to "1", data stored in extended register 406, referenced by the extended register address stored in extended control register 402, can be read from data temporary register 404. The write Ctrl works similarly. When this bit is set to "1", data stored in data temporary register 404 is written to extended register 406 associated with the current extended address.

[0069] The data temporary register 404 may be a memory-mapped register. In one or more examples, the system base chip 202 or a peripheral device (not shown) maps a specific address in register set 212 (the extended address space of register set 212) to various registers, thereby allowing direct access to these registers via standard memory read and write operations. As a non-limiting example, an address decoding mechanism is provided to map a unique address to a specific register in register set 212.

[0070] The illustration of the “Reserved” field is to illustrate that not all fields in a purpose-specific register must be used exclusively for the address space allocation and access control discussed in this article, but they can also be used.

[0071] Figure 5A It is a schematic diagram of register group 502 or a portion thereof in a depiction example environment based on one or more examples.

[0072] Register set 502 includes the allocated MDIO native address space 512 and the expandable address space 514. The MDIO native address space 512 includes various key register addresses used to manage MDIO operations and secure access. In this particular example, the MDIO native address space 512 includes MDIO register address 504, lock ctrl register address 506, expand ctrl register address 508, and data buffer register address 510.

[0073] Register set 502 is the main memory area for configuration and operation registers within the System Base Chip (SBC). The MDIO native address space 512 is a portion of the register set dedicated to addresses natively accessible via the MDIO interface. MDIO register address 504 is the standard address used for typical MDIO operations, such as configuration and status monitoring. The lock ctrl register address 506 is used to control access permissions and lock or unlock specific portions of the register set. The extended ctrl register address 508 manages the extension of the address space, including controlling read and write operations to extended addresses. The data buffer register address 510 acts as an intermediary for data transfers, buffering data read from or written to the extended register space. The expandable address 514 is initially outside the native MDIO address space but can be dynamically allocated to it.

[0074] Following the address allocation process, the extended data register address 516 logically becomes part of the MDIO native address space 512 and is accessible via the data temporary register address 510. The extended ctrl register address 508 and the lock ctrl register address 506 allow for managed access to and secure modification of the register set's address space. The data temporary register address 510 facilitates indirect access to the extended address, thereby ensuring seamless data transfer between the extended address space and the native address space.

[0075] It should be noted that the expandable address 514 includes the extended data register address 516. After the address allocation process, the extended data register address is now logically part of the MDIO native address space 512 because it can be accessed via the data temporary register address 510.

[0076] Figure 5B This is a schematic diagram that further illustrates the structure of register group 502 in the example environment. Figure 5B It is highlighted that once the scalable address 514 is allocated, it is integrated into the MDIO native address space 512, becoming accessible as part of the entire register space managed by the System Base Chip (SBC). The same part number has the same description, such as... Figure 5BAs described above. Note that the expandable address 514, initially outside the native address space, can be reallocated to expand the MDIO addressable space. Furthermore, after reallocation, the extended data register address 516 is integrated into the MDIO native address space 512, making them accessible via the data temporary register address 510.

[0077] Figure 6 Example process 600, according to one or more examples, is illustrated to represent the behavior of access control logic that enables modification of address allocations within a system base chip or its address controller. Although example process 600 depicts a particular sequence of operations, this sequence can be changed without departing from the scope of this disclosure. For example, some of the depicted operations may be performed in parallel or in a different order that does not substantially affect the functionality of process 600. In other examples, different components of the example device or system implementing process 600 may perform functions substantially simultaneously or in a specific order. As a non-limiting example, one or more operations of process 600 may be performed by access control access ctrl logic 108, access ctrl logic 206, access controller 106, access controller 210, system base chip (SBC) 102, system base chip 202, system 100, or system 200.

[0078] The system initiates process 600 with hardware locking enabled, thereby preventing unauthorized changes to address allocations.

[0079] According to one or more examples, process 600 may include receiving keys at the unlock logic in operation 602. The SBC receives a set of keys at the unlock logic. These keys, if verified, are used to authorize changes to the requester's address space.

[0080] Depending on one or more examples, process 600 may include verifying the received key at operation 604. In one or more examples, the unlock logic verifies the received key to ensure it matches the expected value. Process 600 can only proceed to enable modification if the key is correct and valid.

[0081] If the key is not verified (e.g., verification fails, but not limited to this), hardware locking remains enabled, and address allocation cannot be modified. The SBC's address controller continues to prevent unauthorized changes, thereby maintaining the integrity and security of the register set's address space. Optionally, in one or more examples, an error handling mechanism may be present to log failed attempts or trigger security alerts. This ensures that any unauthorized attempts to modify the address space are logged and can be handled appropriately.

[0082] According to one or more examples, process 600 may include at operation 606 enabling modification of the address allocation at the address controller of the system base chip. Upon successful key verification, unlocking logic signals to the address controller. The address controller can then modify the address allocation, thereby allowing secure changes to the address space within the register set.

[0083] In one or more examples, a key can be received within one or more cycles as needed. As a specific, non-limiting example, the unlocking logic can proceed through two check states: Lock 1 and Lock 2. When key 1 is written, the unlocking logic transitions from Lock 1 to Lock 2, and when key 2 is written, the unlocking logic transitions from Lock 2 to unlock. If the key is not written or is not written within a predetermined number of clock cycles, the finite state machine of the unlocking logic transitions from Lock 2 to Lock 1. Procedure 600 may optionally perform this behavior each time a read or write is initiated, or perform this behavior once and then remain in the unlocked state until a reset is received.

[0084] Figure 7 This is a flowchart illustrating a process of adding a non-native register address to the address allocation of an MDIO slave device, thereby expanding the accessible register space, according to one or more examples. Although example process 700 depicts a specific order of operations, this order can be changed without departing from the scope of this disclosure. For example, some of the depicted operations may be performed in parallel or in a different order that does not substantially affect the functionality of process 700. In other examples, different components of the example device or system implementing process 700 may perform functions substantially simultaneously or in a specific order. As a non-limiting example, one or more operations of process 700 may be performed by access control access ctrl logic 108, access ctrl logic 206, address space manager 104, MDIO slave device 204 with address space management, access controller 106, access controller 210, system base chip (SBC) 102, system base chip 202, system 100, or system 200.

[0085] According to one or more examples, process 700 may include selecting N non-native register addresses at operation 702 to add to the address allocation for the MDIO slave device. In operation 702, process 700 selects a set of N non-native register addresses to be added to the address allocation for the MDIO slave device. N is an integer greater than or equal to 1.

[0086] According to one or more examples, procedure 700 may include requesting permission to modify the address allocation of the MDIO slave device at operation 704. The request obtains the necessary permission to modify the address allocation. This step ensures that only authorized modifications are made to the address space of the MDIO slave device.

[0087] In some cases, requests to modify address allocations can be rejected. If a request to modify address allocations is rejected, no changes are made to the address space. The integrity and security of the existing address space are preserved, preventing unauthorized or accidental modifications. Optionally, an error handling mechanism can log failed attempts or trigger notifications. This ensures that any unauthorized or failed attempts to modify the address space are logged and appropriately handled.

[0088] According to one or more examples, process 700 may include, at operation 706, adding n non-native register addresses to the address allocation of the MDIO slave device when granting permission to modify the address allocation of the MDIO slave device, making them extended register addresses of the MDIO slave device. If the request to modify the address allocation is approved, the selected non-native register addresses are added to the address allocation of the MDIO slave device. These addresses become extended register addresses of the MDIO slave device, thereby expanding its accessible register space.

[0089] As a non-limiting example, modifying an address allocation may include updating a control register or table to include a new address within the MDIO allocation. Modifying an address allocation may also include updating (optionally including) a control register or table to remove an address from the I2C allocation.

[0090] Figure 8 This is a flowchart of process 800, which describes the verification of address access requests to ensure they fall within an authorized address allocation, based on one or more examples. Although example 800 depicts a specific sequence of operations, this sequence may be changed without departing from the scope of this disclosure. For example, some of the depicted operations may be performed in parallel or in a different order without substantially affecting the functionality of 800. In other examples, different components of the example device or system implementing 800 may perform functions substantially simultaneously or in a specific order. As a non-limiting example, one or more operations of 800 may be performed by access control access ctrl logic 108, access ctrl logic 206, address space manager 104, MDIO slave device 204 with address space management, access controller 106, access controller 210, system base chip (SBC) 102, system base chip 202, system 100, or system 200.

[0091] According to some examples, the method includes receiving the requested address at the address controller of the system base chip at operation 802. The address controller of the SBC receives the request containing the address that the requester intends to access.

[0092] According to some examples, the method includes determining at operation 804 whether the requested address is in the requester's address allocation. The address controller checks whether the requested address is within the address allocation assigned to the requester. This step ensures that only authorized addresses can be accessed.

[0093] According to some examples, the method includes blocking access at operation 806 if it is determined that the requested address is not in the requester's address allocation. Access is blocked if the requested address is not in an authorized address allocation. This prevents unauthorized access to protected registers.

[0094] According to some examples, the method includes blocking access at operation 808 if it is determined that the requested address is in the requester's address allocation. If the requested address is in an authorized address allocation, access is permitted. The requester can then read from or write to the specified address according to the permission.

[0095] Figure 9 It is a block diagram depicting a system, which is a specific, non-limiting example of system 200.

[0096] Those skilled in the art will understand that the functional elements (e.g., functions, operations, actions, processes, or methods) of the examples disclosed herein can be implemented in any suitable hardware, software, firmware, or a combination thereof. Figure 10 Non-limiting examples of specific implementations of the functional elements disclosed herein are illustrated. In some examples, some or all portions of the functional elements disclosed herein may be executed by hardware capable of performing the functional elements.

[0097] Figure 10This is a block diagram of circuitry 1000, which in some examples can be used to implement the various functions, operations, actions, processes, or methods disclosed herein. Circuitry 1000 includes one or more processors 1002 (sometimes referred to herein as "processor 1002") operatively coupled to one or more data storage devices 1004 (sometimes referred to herein as "storage device 1004"). Storage device 1004 includes machine-executable code 1006 stored thereon, and processor 1002 includes logic circuitry 1008. Machine-executable code 1006 describes functional elements that can be implemented (e.g., executed) by logic circuitry 1008. Logic circuitry 1008 is adapted to implement (e.g., execute) the functional elements described by machine-executable code 1006. When executing the functional elements described by machine-executable code 1006, circuitry 1000 should be considered as dedicated hardware for executing the functional elements disclosed herein. In some examples, processor 1002 may execute the functional elements described by machine-executable code 1006 sequentially, simultaneously (e.g., on one or more different hardware platforms), or in one or more parallel process flows.

[0098] When implemented by the logic circuitry 1008 of the processor 1002, the machine-executable code 1006 adapts the processor 1002 to perform the operations of the examples disclosed herein. As a non-limiting example, the machine-executable code 1006 may adapt the processor 1002 to perform some or all of the operations of a procedure for managing the address space in the register set of a system underlying chip.

[0099] Additionally, by way of non-limiting examples, machine-executable code 1006 may adapt processor 1002 to perform some or all of the features, functions or operations disclosed herein to manage or utilize the address space in the system base chip register set.

[0100] Processor 1002 may include a general-purpose processor, special-purpose processor, central processing unit (CPU), microcontroller, programmable logic controller (PLC), digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic unit, discrete hardware component, other programmable device, or any combination thereof, designed to perform the functions disclosed herein. A general-purpose computer including a processor is considered a special-purpose computer when it executes functional elements corresponding to machine-executable code 1006 (e.g., software code, firmware code, hardware description) relevant to the examples discussed herein. It should be noted that the general-purpose processor (also referred to herein as a host processor or simply host) may be a microprocessor, but in alternative embodiments, processor 1002 may include any conventional processor, controller, microcontroller, or state machine. Processor 1002 may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0101] In some examples, storage device 1004 includes volatile data storage devices (e.g., random access memory (RAM)), non-volatile data storage devices (e.g., flash memory, hard disk drive, solid-state drive, erasable programmable read-only memory (EPROM), but not limited thereto). In some examples, processor 1002 and storage device 1004 may be implemented as a single device (e.g., semiconductor device product, system-on-a-chip (SoC), but not limited thereto). In some examples, processor 1002 and storage device 1004 may be implemented as independent devices.

[0102] In some examples, the machine-executable code 1006 may include computer-readable instructions (e.g., software code, firmware code). As a non-limiting example, the computer-readable instructions may be stored in storage device 1004, directly accessed by processor 1002, and executed by processor 1002 using at least logic circuitry 1008. Also as a non-limiting example, the computer-readable instructions may be stored on storage device 1004, passed to storage device (not shown) for execution, and executed by processor 1002 using at least logic circuitry 1008. Therefore, in some examples, logic circuitry 1008 includes electrically configurable logic circuitry 1008.

[0103] In some examples, machine-executable code 1006 may describe hardware (e.g., circuitry) that will be implemented in logic circuitry 1008 to perform functional elements. This hardware can be described at any of a range of abstraction levels, from low-level transistor layout to high-level description languages. At high-level abstractions, hardware description languages ​​(HDLs), such as the IEEE standard hardware description language (HDL), can be used. With the aid of non-limiting examples, Verilog, SystemVerilog, or VLSI hardware description language (VHDL) can be used.

[0104] HDL descriptions can be converted into descriptions at any of a variety of other levels of abstraction as needed. As a non-limiting example, a high-level description can be converted into a logic-level description, such as Register Transfer Language (RTL), Gate-level (GL) description, layout-level description, or mask-level description. As a non-limiting example, micro-operations to be performed by the hardware logic circuitry (e.g., gates, flip-flops, registers, but not limited to) of logic circuitry 1008 can be described in RTL and subsequently converted into a GL description by a synthesis tool, and the GL description can be converted into a layout-level description by a placement and routing tool, which corresponds to the physical layout of an integrated circuit, discrete gate or transistor logic, discrete hardware components, or combinations thereof of a programmable logic device. Therefore, in some examples, machine-executable code 1006 may include HDL, RTL, GL descriptions, mask-level descriptions, other hardware descriptions, or any combination thereof.

[0105] In an example where machine-executable code 1006 includes a hardware description (at any level of abstraction), the system (not shown, but including storage device 1004) implements the hardware description described by machine-executable code 1006. As a non-limiting example, processor 1002 may include a programmable logic device (e.g., an FPGA or PLC), and logic circuitry 1008 may be electrically controlled to implement circuitry corresponding to the hardware description into logic circuitry 1008. Similarly, as a non-limiting example, logic circuitry 1008 may include hardwired logic manufactured by a manufacturing system (not shown, but including storage device 1004) according to the hardware description of machine-executable code 1006.

[0106] Regardless of whether the machine-executable code 1006 includes computer-readable instructions or a hardware description, the logic circuit 1008 is adapted to execute the functional elements described by the machine-executable code 1006 when implementing the functional elements of the machine-executable code 1006. It should be noted that although the hardware description may not directly describe the functional elements, it indirectly describes the functional elements that the hardware elements described by the hardware description can execute.

[0107] As used in this disclosure, the terms "module" or "component" can refer to a specific hardware implementation that performs actions of a module or component and / or software object or software routine that can be stored on and / or executed by general-purpose hardware of a computing system (e.g., computer-readable media, processing apparatus, but not limited thereto). In some examples, the different components, modules, engines, and services described in this disclosure may be implemented as objects or processes (e.g., as separate threads) that execute on a computing system. While some of the systems and methods described in this disclosure are generally described as being implemented in software (stored on and / or executed by general-purpose hardware), specific hardware implementations or combinations of software and specific hardware implementations are also possible and contemplated.

[0108] As used in this disclosure, the term "combination" referring to multiple elements can include any combination of all elements or any combination of various different sub-combinations of certain elements. For example, the phrase "A, B, C, D or combinations thereof" can refer to any one of A, B, C, or D; a combination of each of A, B, C, and D; and any sub-combination of A, B, C, or D, such as A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0109] The terminology used in this disclosure, and particularly in the appended claims (e.g., the body of the appended claims, but not limited thereto), is generally intended to be “open-ended” terms (e.g., the term “including” should be interpreted as “including but not limited to”, the term “having” should be interpreted as “having at least”, and the term “include” should be interpreted as “including but not limited to”, but not limited thereto). As used herein, the term “each” means “some or all”. As used herein, the term “each and every” means “all”.

[0110] Furthermore, if a specific number of introduced claim statements are anticipated, this intention will be explicitly stated in the claims, and without such a statement, this intention does not exist. For example, as an aid to understanding, the appended claims may contain the use of the introductory phrases “at least one” and “one or more” to introduce claim statements. However, the use of such phrases should not be construed as implying that a claim statement introduced by the indefinite article “a” or “an” limits any particular claim containing such an introduced claim statement to an example containing only one such statement, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an” (e.g., “a” and / or “an” can be interpreted as referring to “at least one” or “one or more”, but is not limited thereto); the same applies to the use of definite articles to introduce claim statements.

[0111] Furthermore, even when a specific number of the introduced claims are explicitly stated, those skilled in the art will recognize that such a statement should be interpreted as intended to represent at least the number stated (e.g., the unmodified statement "two statements" means, without other modifying elements, at least two statements, or two or more statements, but not limited thereto). Additionally, in instances where conventions such as "at least one of A, B, and C, but not limited thereto" or "one or more of A, B, and C, but not limited thereto" are used, this construction is generally intended to include, but is not limited to, a single A, a single B, a single C, A and B together, A and C together, B and C together, or A, B, and C together.

[0112] Furthermore, any separate word or phrase presenting two or more alternative terms in the specification, claims, or drawings should be understood to include the possibility of including one term, any one term, or both terms. For example, the phrase "A or B" should be understood to include the possibility of including "A" or "B" or "A and B".

[0113] Additional non-limiting embodiments include:

[0114] Example 1: An apparatus comprising: a bus slave device; a system base chip, the system base chip comprising: a register set; an access controller configured to restrict the scope of the bus slave device to a selectable address set of the register set; and an address space manager configured to set the selectable address set of the register set.

[0115] Example 2: According to the apparatus of Example 1, in order to set the selected address set of the register group, the address space manager is used to: change the address within the selected address set of the register group.

[0116] Example 3: The apparatus according to any one of Examples 1 and 2, wherein, in order to change the address within the selected address set of the register group, the address space manager is configured to: add an address to or remove an address from the selected address set of the register group.

[0117] Example 4: An apparatus according to any one of Examples 1 to 3, wherein, in order to limit the scope of the bus slave device to the selected address set of the register group, the access controller is configured to: allow the bus slave device to interact with registers of the register group corresponding to the selected address set of the register group; and prevent the bus slave device from interacting with registers of the register group corresponding to addresses outside the selected address set of the register group.

[0118] Example 5: The apparatus according to any one of Examples 1 to 4, wherein the bus slave device is a management data input / output bus slave device.

[0119] Example 6: The apparatus according to any one of Examples 1 to 5, wherein the set of selected addresses of the register group includes the local address of the bus slave device.

[0120] Example 7: An apparatus according to any one of Examples 1 to 6, wherein the access controller is configured to: permit the address space manager to change the selected address set of the register group at least in part in response to a key-based authentication process.

[0121] Example 8: An apparatus according to any one of Examples 1 to 7, the apparatus comprising: an additional bus slave device, wherein the access controller is configured to: limit the scope of the additional bus slave device to an additional set of selectable addresses of the register set.

[0122] Example 9: The apparatus according to any one of Examples 1 to 8, wherein the registers of the register group include a first key field, a second key field and an enable field, wherein the first key field is used to indicate whether a first key has been received and verified, wherein the second key field is used to indicate whether a second key has been received and verified, and wherein the enable field is used to indicate whether the firmware can access all bits of the control status register of the system base chip.

[0123] Example 10: The apparatus according to any one of Examples 1 to 9, wherein the registers of the register group include an extended address field, a read field, and a write field, wherein the extended address field is used to store an extended address in the selected address set of the register group, the extended address being associated with an extended register; wherein the read field is used to indicate whether data can be read from the extended register via a data temporary register; and wherein the read field is used to indicate whether data can be written to the extended register via a data temporary register.

[0124] Example 11: The apparatus according to any one of Examples 1 to 10, wherein the extended register is a memory-mapped register.

[0125] Example 12: The apparatus according to any one of Examples 1 to 11, wherein the address space manager, in response to the debug state of the system base chip, sets the selected address set of the register group to include the entire address space of the register group.

[0126] Example 13: An apparatus according to any one of Examples 1 to 12, the apparatus comprising: a physical layer transceiver, wherein the access controller is configured to: limit the scope of the physical layer transceiver to an additional set of selectable addresses of the register set, wherein the set of selectable addresses is different from the additional set of selectable addresses.

[0127] Example 14: A method comprising: selecting N non-native register addresses to add to the address allocation of an MDIO slave device; requesting permission to modify the address allocation of the MDIO slave device; and, upon granting permission to modify the address allocation of the MDIO slave device, adding the N non-native register addresses to the address allocation of the MDIO slave device, such that they become extended register addresses of the MDIO slave device.

[0128] While this disclosure describes the invention with respect to certain illustrative examples, those skilled in the art will recognize and understand that the invention is not limited thereto. Rather, many additions, deletions, and modifications may be made to the illustrative examples and the examples themselves without departing from the scope of the invention as claimed below and its legal equivalents. Furthermore, features from one example may be combined with features from another example while still being included within the scope of the invention as contemplated by the inventors.

Claims

1. An apparatus, the apparatus comprising: Bus slave device; The system base chip includes: Register set; An access controller, configured to restrict the range of the bus slave device to a selectable set of addresses of the register set; and An address space manager is used to set the selected address set of the register group.

2. The apparatus of claim 1, wherein, in order to set the selection address set of the register group, the address space manager is configured to: Change the address within the selected address set of the register group.

3. The apparatus of claim 2, wherein, in order to change the address within the selected address set of the register group, the address space manager is configured to: Add or remove addresses from the selected address set of the register group.

4. The apparatus of claim 2, wherein, in order to limit the range of the bus slave device to the selected address set of the register group, the access controller is configured to: Allowing the bus slave device to interact with registers in the register group corresponding to the selected address set of the register group; and Prevent the bus slave device from interacting with registers in the register group that correspond to addresses outside the selected address set of the register group.

5. The apparatus of claim 1, wherein the bus slave device is a management data input / output bus slave device.

6. The apparatus of claim 1, wherein the set of selectable addresses of the register group includes the native address of the bus slave device.

7. The apparatus of claim 1, wherein the access controller is configured to: The address space manager is permitted to modify the selected address set of the register group, at least in part, in response to a key-based authentication process.

8. The apparatus according to claim 1, wherein the apparatus comprises: Other bus slave devices, The access controller is used for: This restricts the range of the additional bus from the device to an additional set of selectable addresses of the register set.

9. The apparatus of claim 1, wherein the registers of the register group include a first key field, a second key field, and an enable field. The first key field is used to indicate whether the first key has been received and verified. The second key field is used to indicate whether the second key has been received and verified. The enable field indicates whether the firmware can access all bits of the control status register of the system base chip.

10. The apparatus of claim 1, wherein the registers of the register group include an extended address field, a read field, and a write field. The extended address field is used to store the extended address in the selected address set of the register group, and the extended address is associated with the extended register; The read field is used to indicate whether data can be read from the extended register via the data temporary register; and The read field indicates whether data can be written to the extended register via the data temporary register.

11. The apparatus of claim 10, wherein the extended register is a memory-mapped register.

12. The apparatus of claim 1, wherein the address space manager, in response to a debug state of the system base chip, sets the selected address set of the register group to include the entire address space of the register group.

13. The apparatus of claim 1, wherein the apparatus comprises: Physical layer transceiver, The access controller is used for: This limits the range of the physical layer transceiver to an additional set of selectable addresses within the register set. The set of selected addresses mentioned therein is different from the other set of selected addresses.

14. A method, the method comprising: Select N non-native register addresses to add to the address allocation of the MDIO slave device; Request modification of the permissions for the address allocation of the MDIO slave device; as well as When granting permission to modify the address allocation of the MDIO slave device, the N non-native register addresses are added to the address allocation of the MDIO slave device, making them extended register addresses of the MDIO slave device.

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