Task recovery method, memory management unit, processor, electronic equipment and system
By adding an access restriction unit to the memory management unit, using cached data to detect data line anomalies and repeatedly performing address translation, the problem of slow task recovery in GPU computing clusters is solved, achieving fast task recovery and improved processor performance.
Patent Information
- Application Number
- CN202511746810.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-25
- Publication Date
- 2026-02-27
AI Technical Summary
In GPU computing clusters, high-speed interconnect links are susceptible to electromagnetic interference and temperature changes, which can lead to performance degradation or interruption of data lines. Existing task recovery solutions are time-consuming, affecting the recovery time of computing tasks.
By adding an access restriction unit to the memory management unit (MMU), cached data is used to determine data line anomalies. The virtual address to physical address translation operation is repeatedly performed until the line is normal. When the line is restored, the computing task is sent, avoiding explicit operations at the software level.
It enables rapid recovery of computing tasks in the event of data line failure, thereby improving the reliability of GPU computing clusters and the processing performance of processors.
Smart Images
Figure CN121579253A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of electronic technology, specifically relating to a task recovery method, a memory management unit, a processor, an electronic device, and a computing system. Background Technology
[0002] In computing clusters such as GPU (Graphics Processing Unit) computing clusters, multiple GPU cards need to interact with each other through interconnect systems such as PCIe (Peripheral Component Interconnect Express) switches to complete large-scale parallel computing.
[0003] However, these high-speed interconnect links (data lines) are susceptible to environmental factors such as electromagnetic interference and temperature changes during operation, leading to performance degradation or even interruption. Existing solutions typically rely on management software: when the management software detects an anomaly in the data line (including performance degradation or failure), it proactively stops the user's computing tasks using that data line, saves a snapshot of the task, and then re-establishes the connection on the faulty data line. Once the data line is restored, the task is restarted and resumes operation from the snapshot point. This process involves a series of software operations, including stopping the task, saving the snapshot, and restarting the task, and the overall process is time-consuming, resulting in less than ideal recovery time for interrupted computing tasks. Therefore, a technical solution capable of enabling rapid task recovery is needed to improve the reliability and operating efficiency of GPU computing clusters. Summary of the Invention
[0004] Therefore, the purpose of this application is to provide a task recovery method, a memory management unit, a processor, an electronic device, and a computing system to improve the current problem of slow task recovery speed, which affects the performance of the processor.
[0005] The embodiments of this application are implemented as follows: In a first aspect, embodiments of this application provide a task recovery method applied to a first processor. The method includes: when completing the virtual address to physical address conversion in a computing task, determining whether the data line to which the physical address belongs is abnormal based on cached data in the cache, wherein the data line to which the physical address belongs is the data line between the first processor and a communication object, and the cached data includes a range of physical addresses corresponding to abnormal or normal data lines; when the data line to which the physical address belongs is abnormal, repeatedly executing the virtual address to physical address conversion operation in the computing task until the data line to which the physical address belongs is normal; when the data line to which the physical address belongs is normal, sending the computing task that has completed the address conversion out via the data line to which the physical address belongs.
[0006] In the above scheme, when completing the virtual address to physical address translation in the computing task, before sending the completed computing task through the data line of the physical address, the system first determines whether the data line of the physical address is abnormal based on the cached data. If the data line is found to be abnormal, the system no longer performs explicit operations on the computing task at the software level (such as stopping the computing task or saving a task snapshot). Instead, it reuses the retry-page fault mechanism of the Memory Management Unit (MMU) to repeatedly execute the virtual address to physical address translation operation in the computing task until the data line is normal. When the data line is normal, the completed computing task can be sent through the data line, thereby achieving the goal of quickly restoring the computing task when the abnormal data line is restored to normal, thus improving the processing efficiency of the task and improving the processing performance of the processor.
[0007] In one possible implementation of the first aspect embodiment, determining whether the data line to which the physical address belongs is abnormal based on cached data in the cache includes: checking whether the physical address hits the physical address range corresponding to the abnormal data line in the cache; if the physical address hits the physical address range corresponding to the abnormal data line, determining that the data line to which the physical address belongs is abnormal.
[0008] In the above scheme, if the cached data in the cache includes the physical address range corresponding to the abnormal data line, it is possible to determine whether the data line to which the physical address belongs is abnormal by checking whether the physical address hits the physical address corresponding to the abnormal data line in the cache. This allows for a quick determination of whether the data line to which the physical address belongs is abnormal.
[0009] In one possible implementation of the first aspect embodiment, the physical address range corresponding to the abnormal data line in the cache is: saved to the cache when the health information of the data line indicates that the data line is abnormal, and removed from the cache when the data line is normal.
[0010] In the above scheme, when the health information of the data line indicates an anomaly, the physical address range corresponding to the abnormal data line is stored in a cache to restrict the execution of computing tasks. When the data line is normal, it is removed from the cache, thereby removing the restriction and achieving the goal of quickly restoring the computing tasks. In a possible implementation of the first aspect embodiment, determining whether the data line to which the physical address belongs is abnormal based on cached data includes: checking whether the physical address hits the physical address range corresponding to a normal data line in the cache; if the physical address does not hit the physical address range corresponding to the normal data line, it is determined that the data line to which the physical address belongs is abnormal.
[0011] In the above scheme, if the cached data in the cache includes the physical address range corresponding to the normal data line, then the abnormality of the data line to which the physical address belongs can be determined by checking whether the physical address hits the physical address corresponding to the normal data line in the cache. For example, if the physical address does not hit the physical address range corresponding to the normal data line, then it is determined that the data line to which the physical address belongs is abnormal. In this way, it is possible to quickly find out whether the data line to which the physical address belongs is abnormal.
[0012] In one possible implementation of the first aspect embodiment, the physical address range corresponding to the normal data line in the cache is: saved to the cache when the health information of the data line indicates that the data line is normal, and removed from the cache when the data line is abnormal.
[0013] In the above scheme, when the health information of the data line indicates that the data line is normal, the physical address range corresponding to the normal data line is stored in the cache to restrict the execution of computing tasks. When the data line is abnormal, it is removed from the cache to remove the restriction and achieve the purpose of quickly restoring computing tasks.
[0014] Secondly, this application also provides a task recovery method applied to a second processor. The method includes: acquiring health information of a data line between a first processor and a communication object; when the health information indicates that the data line is abnormal, configuring cached data in the cache of the first processor so that when the first processor completes the virtual address to physical address conversion in a computing task, it determines whether the data line to which the physical address belongs is abnormal based on the cached data; and when the data line to which the physical address belongs is abnormal, repeatedly executing the virtual address to physical address conversion operation in the computing task until the data line to which the physical address belongs is normal, and sending the computing task with completed address conversion through the data line to which the physical address belongs; wherein, the cached data includes a range of physical addresses corresponding to the abnormal data line or the normal data line; performing a re-establishment operation on the abnormal data line to restore the abnormal data line to normal; and updating the cached data when the abnormal data line is restored to normal, the updated cached data being used to inform the first processor that the data line to which the physical address belongs is normal.
[0015] In the above scheme, by monitoring the health information of the data lines in real time, when the health information indicates that the data line is abnormal, the cached data in the cache of the first processor is configured. This is so that when the virtual address to physical address translation in the computing task is completed, and the computing task that has completed the address translation is about to be sent out through the data line to which the physical address belongs, the cached data in the cache will be used to determine whether the data line to which the physical address belongs is abnormal, so as to restrict the continued execution of the computing task. At the same time, the abnormal data line is re-established to restore the abnormal data line to normal. When the abnormal data line is restored to normal, the cached data is updated to remove the restriction and achieve the purpose of quickly restoring the computing task.
[0016] Thirdly, embodiments of this application also provide a memory management unit, including: an address translation unit, a cache, and an access restriction unit; the address translation unit is used to perform the translation of virtual addresses to physical addresses in a computing task; the cache is used to store cached data, the cached data being used to determine whether the data line to which the physical address belongs is abnormal, the cached data including a range of physical addresses corresponding to abnormal or normal data lines, wherein the data line to which the physical address belongs is the data line between the processor to which the memory management unit belongs and the communication object; the access restriction unit is used to determine whether the data line to which the physical address belongs is abnormal based on the cached data, and when the data line to which the physical address belongs is abnormal, instruct the address translation unit to repeatedly perform the virtual address to physical address translation operation in the computing task until the data line to which the physical address belongs is normal; and when the data line to which the physical address belongs is normal, send the computing task that has completed the address translation out through the data line to which the physical address belongs.
[0017] In the above scheme, by adding an access restriction unit to the memory management unit and cooperating with the management software, a hardware-software collaborative solution is adopted to circumvent the existing management process's handling of computing tasks on abnormal data lines (which involves a series of software operations such as stopping tasks, saving task snapshots, and restarting tasks), thereby achieving the goal of quickly restoring computing tasks.
[0018] Fourthly, embodiments of this application also provide a processor, including the memory management unit provided in the third aspect of the embodiments described above.
[0019] Fifthly, embodiments of this application also provide an electronic device, including the processor provided in the fourth aspect of the embodiments described above.
[0020] In a sixth aspect, embodiments of this application also provide an electronic device, including: a memory and a processor, the processor being connected to the memory; the memory being used to store a program; the processor being used to invoke the program stored in the memory to perform a method as provided in any possible implementation of the first aspect embodiment and / or in combination with the first aspect embodiment, or to perform a method as provided in the second aspect embodiment.
[0021] In a seventh aspect, embodiments of this application also provide a computing system, including: a first processor and a second processor; the first processor is configured to, when performing a virtual address to physical address conversion in a computing task, determine whether the data line to which the physical address belongs is abnormal based on cached data in a cache, wherein the data line to which the physical address belongs is a data line between the first processor and a communication object, and the cached data includes a range of physical addresses corresponding to abnormal or normal data lines; when the data line to which the physical address belongs is abnormal, repeatedly perform the virtual address to physical address conversion operation in the computing task until the data line to which the physical address belongs is normal, and then send the computing task with completed address conversion through the data line to which the physical address belongs; the second processor is configured to obtain health information of the data line to which the physical address belongs, configure the cached data in the cache of the first processor when the health information indicates that the data line to which the physical address belongs is abnormal; and perform a re-establishment operation on the abnormal data line to restore the abnormal data line to normal; and update the cached data when the abnormal data line is restored to normal, wherein the updated cached data is used to inform the first processor that the data line to which the physical address belongs is normal.
[0022] In one possible implementation of the seventh aspect embodiment, when the first processor determines whether the data line to which the physical address belongs is abnormal based on cached data in the cache, it is specifically used to check whether the physical address hits the physical address range corresponding to the abnormal data line in the cache; if the physical address hits the physical address range corresponding to the abnormal data line, it is determined that the data line to which the physical address belongs is abnormal; the second processor is specifically used to store the physical address range corresponding to the abnormal data line in the cache when the health information indicates that the data line to which the physical address belongs is abnormal.
[0023] In one possible implementation of the seventh aspect embodiment, when the first processor determines whether the data line to which the physical address belongs is abnormal based on cached data in the cache, it is specifically used to check whether the physical address hits the physical address range corresponding to the normal data line in the cache; if the physical address does not hit the physical address range corresponding to the normal data line, it is determined that the data line to which the physical address belongs is abnormal; the second processor is specifically used to store the physical address range corresponding to the normal data line in the cache when the health information indicates that the data line to which the physical address belongs is normal.
[0024] In one possible implementation of the seventh aspect embodiment, the communication object is a switch, and the computing system further includes: the switch, through which a plurality of the first processors are connected.
[0025] The technical effects of any of the implementation methods in aspects four through seven can be found in the technical effects of the same or similar implementation methods in aspects one through three, and will not be repeated here.
[0026] Other features and advantages of this application will be set forth in the following description. The objectives and other advantages of this application can be realized and obtained through the structures specifically pointed out in the written description and the accompanying drawings. Attached Figure Description
[0027] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the accompanying drawings used in the embodiments will be briefly described below. Obviously, the drawings described below are only some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. The above and other objects, features, and advantages of this application will become clearer through the accompanying drawings.
[0028] Figure 1 This illustration shows an interaction diagram between a processor and a communication object provided in an embodiment of this application.
[0029] Figure 2 A schematic diagram of a computing system provided in an embodiment of this application is shown.
[0030] Figure 3 A schematic diagram illustrating the principle of the task recovery method for a computing system provided in an embodiment of this application is shown.
[0031] Figure 4 A flowchart illustrating a task recovery method provided in an embodiment of this application is shown.
[0032] Figure 5 A flowchart illustrating another task recovery method provided in an embodiment of this application is shown.
[0033] Figure 6 A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown. Detailed Implementation
[0034] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. The following embodiments are provided as examples to more clearly illustrate the technical solutions of this application, and should not be used to limit the scope of protection of this application. Those skilled in the art will understand that, without conflict, the following embodiments and features can be combined with each other.
[0035] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, relational terms such as "first," "second," etc., in the description of this application are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.
[0036] Furthermore, the term "and / or" in this application is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.
[0037] In the description of the embodiments of this application, unless otherwise expressly specified and limited, the technical term "connection" can be a direct connection or an indirect connection through an intermediate medium.
[0038] Given the current problem of slow task recovery speed affecting processor performance, this application adopts a hardware-software collaborative solution to circumvent the existing management process's handling of user computing tasks (hereinafter referred to as computing tasks) on abnormal data lines (this process involves a series of software operations such as stopping the task, saving task snapshots, and restarting the task). This allows users to be unaware of the re-establishment process of abnormal data lines, accelerating the recovery of computing tasks. When completing the virtual address to physical address translation in the computing task, this application determines whether the data line to which the physical address belongs is abnormal based on the cached data in the cache. If the data line is determined to be abnormal, the computing task is not stopped or task snapshots are not saved. Instead, the virtual address to physical address translation operation in the computing task is repeatedly executed until the data line is normal. When the data line is normal, the computing task with completed address translation can be sent out through the data line, thereby achieving the purpose of quickly recovering the computing task.
[0039] To achieve this objective, this application can add an access restriction unit to the memory management unit (MMU) and work in conjunction with management software. The following describes how... Figure 1 The memory management unit provided in the embodiments of this application will be described. This memory management unit includes an address translation unit, a cache (also referred to as an access restriction cache), and an access restriction unit. In some possible implementations, the cache may be integrated within the access restriction unit.
[0040] The address translation unit (ATU) is primarily used to translate virtual addresses (VAs) to physical addresses (PAs) in computational tasks. In some possible implementations, the ATU may include a Translation Lookaside Buffer (TLB), a Translation WalkUnit (TWU), and page table checking. When the MMU receives a computational task containing a VA address, it first queries the TLB. If the TLB hits, the PA address can be obtained directly. If the TLB misses, the MMU activates the TWU to perform page table traversal to obtain the corresponding page table, and then finds the PA address corresponding to the VA address based on the page table. During the page table traversal, page table checks are performed, such as verifying permissions and the validity of page table entries. After page table traversal, the PA address corresponding to the VA address can be found.
[0041] The cache stores cached data, primarily used to determine whether the data line corresponding to a physical address is abnormal. This data line can be the data line between the processor of the memory management unit (including but not limited to the first processor mentioned below) and the communication object (including but not limited to a switch). The cached data can be configured by the second processor (e.g., adding, deleting, modifying, etc.). There can be multiple data lines between the processor and the communication object, each with its own memory access physical address range; for example, each data line may be pre-assigned a specific memory access physical address range. The computational task of completing PA address translation needs to be sent through the data line responsible for accessing that PA address.
[0042] In some possible implementations, the cached data can be whitelisted or blacklisted data. For example, the cached data can include the physical address range corresponding to abnormal data lines, or it can include the physical address range corresponding to normal data lines. In this application, the physical address range corresponding to a data line refers to the memory access physical address range corresponding to that data line, and each data line is pre-assigned a specific memory access physical address range. If a physical address (e.g., PA1) falls within the physical address range corresponding to a data line (e.g., Lane1), then that data line (Lane1) is the data line to which the physical address (PA1) belongs.
[0043] When cached data includes the physical address range corresponding to abnormal data lines, the physical address range corresponding to the abnormal data lines in the cache can be: saved to the cache when the health information of the data line indicates that the data line is abnormal, and removed from the cache when the data line is normal. In this implementation, when determining whether the data line to which the physical address belongs is abnormal based on the cached data, the process can be: check whether the physical address hits the physical address range corresponding to the abnormal data line in the cache; if the physical address hits the physical address range corresponding to the abnormal data line, it is determined that the data line to which the physical address belongs is abnormal; otherwise, if it does not hit, it indicates that the data line to which the physical address belongs is normal.
[0044] By adding an access restriction unit to the MMU, when the PA address of the VA translation is detected to hit the set restricted access PA address range, the retry-page fault function of the MMU is triggered, which actively puts the computing task into a VA to PA translation loop (the computing task must wait for the PA translation to be completed before it can continue the task), without affecting the execution of other normal computing tasks in the MMU.
[0045] When the cached data includes the physical address range corresponding to normal data lines, the physical address range corresponding to normal data lines in the cache can be: saved to the cache when the health information of the data line indicates that the data line is normal, and removed from the cache when the data line is abnormal. In this implementation, when determining whether the data line to which the physical address belongs is abnormal based on the cached data, the process can be: check whether the physical address hits the physical address range corresponding to normal data lines in the cache; if the physical address does not hit the physical address range corresponding to normal data lines, it is determined that the data line to which the physical address belongs is abnormal. Conversely, if it hits, it indicates that the data line to which the physical address belongs is normal.
[0046] By adding an access restriction unit to the MMU, when it is detected that the PA address translated from VA does not hit the set allowed PA address range, the retry-page fault function of the MMU is triggered, which actively puts the computing task into a cyclic state of VA to PA translation (the computing task must wait for the PA translation to be completed before it can continue the task), without affecting the execution of other normal computing tasks in the MMU.
[0047] For example, in one possible implementation, the cached data in the cache can be as shown in Table 1 below.
[0048] Table 1
[0049] In Table 1, Lane represents the data line identifier (id). Valid indicates whether the data line is abnormal; for example, valid = 0 indicates a normal data line, and valid = 1 indicates an abnormal data line. Conversely, valid = 1 indicates a normal data line, and valid = 0 indicates an abnormal data line. The PA address range in Table 1 represents the memory access PA address range corresponding to the data line.
[0050] After the address translation unit completes the virtual address to physical address translation in the computation task, the access restriction unit determines whether the data line to which the physical address belongs is abnormal based on the cached data in the cache. If the data line to which the physical address belongs is abnormal, the address translation unit is instructed to repeat the virtual address to physical address translation operation in the computation task until the data line to which the physical address belongs is normal. And when the data line to which the physical address belongs is normal, the computation task with completed address translation is sent out through the data line to which the physical address belongs.
[0051] Whether the aforementioned data lines are abnormal can be detected by the management software. For example, the management software periodically acquires and checks the health information of the data lines. If it detects that a data line is in an abnormal state, it configures the cached data in the MMU's cache. This allows the computing task to be suspended at the current task access point without explicit operation on the computing task, preventing data interaction through the abnormal data line. Afterward, a re-establishment operation is performed on the abnormal data line. Once the link re-establishment is complete, the PA (Parent Access Restriction) configuration in the MMU is cleared, achieving the goal of quickly recovering the task.
[0052] The health information can include Correctable Error (CE) and / or Figure of Merit (FOM). An increase in CE is an early signal of deterioration in the physical condition of the link, while a decrease in FOM directly quantifies the degradation of link quality. When the health information exceeds the warning indicator value, for example, when CE is greater than a first threshold (configurable) and / or FOM value (configurable) is less than a second threshold, the data line can be considered abnormal.
[0053] This application also provides a processor that includes the memory management unit described above. This processor can be either the first processor or the second processor described in this application.
[0054] For example, a processor includes, but is not limited to, a Central Processing Unit (CPU), a Network Processor (NP), a Graphics Processing Unit (GPU), an Accelerated Processing Unit (ACCU), a Multimedia Application Processor (MAP), and a microprocessor. Furthermore, a processor can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Alternatively, the processor can be any other conventional processor.
[0055] This application also provides a computing system, which will be described below in conjunction with... Figure 2 The computing system described in this application includes a first processor and a second processor, which are connected together.
[0056] In this application, the first processor and the second processor can be different processors. For example, the first processor can be a GPU, and the second processor can be a CPU. In the following examples, we will mainly use a GPU as the first processor and a CPU as the second processor for illustration. It is understood that the first processor in this application can also be a processor other than a GPU, and similarly, the second processor can also be a processor other than a CPU.
[0057] The first processor, when performing the virtual address to physical address conversion in a computing task, determines whether the data line to which the physical address belongs is abnormal based on cached data in the cache. The data line to which the physical address belongs is the data line between the first processor and the communication object (such as a switch). When the data line to which the physical address belongs is abnormal, the virtual address to physical address conversion operation in the computing task is repeatedly executed until the data line to which the physical address belongs is normal. Then, the computing task with completed address conversion is sent out through the data line to which the physical address belongs.
[0058] The second processor is used to obtain the health information of the data line to which the physical address belongs; when the health information indicates that the data line to which the physical address belongs is abnormal, it configures the cached data in the cache of the first processor; and performs a re-establishment operation on the abnormal data line to restore the abnormal data line to normal; and updates the cached data when the abnormal data line is restored to normal, wherein the updated cached data is used to inform the first processor that the data line to which the physical address belongs has been restored to normal.
[0059] In one implementation, the second processor is specifically used to store the physical address range corresponding to the abnormal data line in a cache when the health information indicates that the data line to which the physical address belongs is abnormal. At this time, when the first processor determines whether the data line to which the physical address belongs is abnormal based on the cached data, it is specifically used to check whether the physical address hits the physical address range corresponding to the abnormal data line in the cache; if the physical address hits the physical address range corresponding to the abnormal data line, it is determined that the data line to which the physical address belongs is abnormal.
[0060] In one implementation, the second processor is specifically used to store the physical address range corresponding to the normal data line in a cache when the health information indicates that the data line to which the physical address belongs is normal. At this time, when the first processor determines whether the data line to which the physical address belongs is abnormal based on the cached data, it is specifically used to check whether the physical address hits the physical address range corresponding to the normal data line in the cache; if the physical address does not hit the physical address range corresponding to the normal data line, it is determined that the data line to which the physical address belongs is abnormal.
[0061] The aforementioned communication object can be a switch. In some possible implementations, the computing system further includes a switch, through which multiple first processors are connected. The multiple first processors connected by the switch can belong to the same device or different devices, such as belonging to at least two devices.
[0062] When multiple first processors connected to a switch belong to the same device, the number of second processors can be one. When the computing system is a heterogeneous computing system, the multiple first processors connected to the switch can belong to different devices, and in this case, the number of second processors can be multiple, with each device containing at least one second processor. For example... Figure 2 The two primary processors on the right side can belong to the same device and share a single secondary processor. For example... Figure 2 The two first processors on the left side can belong to two different devices, each containing a second processor.
[0063] In one possible implementation, taking a GPU as the first processor and a CPU as the second processor as an example, the principle of the task recovery method shown in this application can be as follows: Figure 3 As shown, its principle is as follows: 1. The management software in the CPU periodically checks the health information of the high-speed interconnect lines between the GPU and the CPU; 2. The management software detects that the health information in step 1 has reached the warning value, indicating that the corresponding data line is abnormal; 3. Configure the cache in the GPU's MMU using the management software. For example, configure the cached data in the cache to set PA limit conversion settings for GPU cards involved in abnormal data lines. 4. If the GPU card's computing task is suspended at the PA switching point due to the abnormal data line, data access on the abnormal data line will stop. 5. The management software can re-establish links for abnormal data lines without requiring explicit operations on user computing tasks (such as snapshot saving, task termination, task restart, etc.). 6. After the link is established, update the cached data in the cache to restore the PA limit conversion settings; 7. User computing tasks will resume running immediately.
[0064] This application also provides a task recovery method applied to a first processor, which is described below in conjunction with... Figure 4 Explain it.
[0065] S1: When the virtual address to physical address translation in the computing task is completed, determine whether the data line to which the physical address belongs is abnormal based on the cached data in the cache.
[0066] In one possible implementation, the process of determining whether a data line to which a physical address belongs is abnormal based on cached data in the cache can be as follows: check whether the physical address matches the physical address range corresponding to the abnormal data line in the cache; if the physical address matches the physical address range corresponding to the abnormal data line, it is determined that the data line to which the physical address belongs is abnormal. In this implementation, the physical address range corresponding to the abnormal data line in the cache is defined as follows: it is saved to the cache when the health information of the data line indicates that the data line is abnormal, and it is removed from the cache when the data line is normal.
[0067] In one possible implementation, the process of determining whether a physical address belongs to an abnormal data line based on cached data in the cache can be as follows: check whether the physical address hits the physical address range corresponding to normal data lines in the cache; if the physical address does not hit the physical address range corresponding to normal data lines, determine that the data line to which the physical address belongs is abnormal. In this implementation, the physical address range corresponding to normal data lines in the cache is defined as follows: the range of physical addresses that are saved to the cache when the health information of the data line indicates that the data line is normal, and are removed from the cache when the data line is abnormal.
[0068] S2: When the data line to which the physical address belongs is abnormal, repeat the virtual address to physical address conversion operation in the computing task until the data line to which the physical address belongs is normal.
[0069] S3: When the data line to which the physical address belongs is normal, the calculation task to complete the address translation will be sent out through the data line to which the physical address belongs.
[0070] This application also provides a task recovery method applied to a second processor, which is described below in conjunction with... Figure 5 Explain it.
[0071] S10: Obtain the health information of the data line between the first processor and the communication object.
[0072] S20: When the health information indicates an abnormal data line, configure the cached data in the cache of the first processor.
[0073] By configuring the cached data in the cache of the first processor, the first processor can determine whether the data line to which the physical address belongs is abnormal when performing the virtual address to physical address translation in the computing task. If the data line to which the physical address belongs is abnormal, the virtual address to physical address translation operation in the computing task is repeatedly executed until the data line to which the physical address belongs is normal, and then the computing task with completed address translation is sent out through the data line to which the physical address belongs.
[0074] S30: Re-establish the connection for the abnormal data line to restore it to normal.
[0075] S40: Update cached data when the abnormal data line is restored to normal.
[0076] The updated cached data is used to inform the first processor that the data line corresponding to the physical address is functioning normally. For example, by checking the updated cached data, the first processor can determine that the data line corresponding to the physical address is functioning normally, so that it can send the computation task that has completed the address translation out via the data line corresponding to the physical address.
[0077] The task recovery method provided in this application embodiment has the same implementation principle and technical effect as the aforementioned system embodiment. For the sake of brevity, any parts not mentioned in the method embodiment can be referred to the corresponding content in the aforementioned system embodiment.
[0078] This application also provides an electronic device that includes the processor described above. The processor may be either the first processor or the second processor described above. Alternatively, the processor may include both the first processor and the second processor described above.
[0079] The electronic devices provided in this application may include, but are not limited to, mobile phones, tablets, personal computers (PCs), netbooks, personal digital assistants (PDAs), wearable electronic devices, virtual reality devices, and other devices equipped with parallel processors.
[0080] In one possible implementation, the electronic device 200 includes a transceiver 210, a memory 220, a communication bus 230, and a processor 240. The transceiver 210, memory 220, and processor 240 are electrically connected directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses 230 or signal lines. The transceiver 210 is used to send and receive data. The memory 220 is used to store computer programs, which include at least one software functional module that can be stored in the memory 220 in the form of software or firmware or embedded in the operating system (OS) of the electronic device 200. The processor 240 is used to execute the software functional modules or computer programs stored in the memory 220. For example, the processor 240 is used to execute the aforementioned task recovery method.
[0081] The memory 220 may be, but is not limited to, random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), etc.
[0082] Processor 240 may be an integrated circuit chip with signal processing capabilities. The aforementioned processor can be a general-purpose processor, including a Central Processing Unit (CPU), Network Processor (NP), Graphics Processing Unit (GPU), Accelerated Processing Unit (ACCU), Multimedia Application Processor (MAP), microprocessor, etc.; it can also be a Digital Signal Processor (DSP), Application Specific Integrated Circuit (ASIC), Field Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. Alternatively, processor 240 can also be any conventional processor.
[0083] This application also provides a non-volatile computer-readable storage medium (hereinafter referred to as the storage medium) storing a computer program, which, when run by a computer such as the electronic device 200 described above, executes the task recovery method described above.
[0084] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.
[0085] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.
[0086] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.
[0087] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a computer-readable storage medium and includes several instructions to cause a computer device (which may be a personal computer, laptop, server, or electronic device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned computer-readable storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0088] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A task recovery method characterized by, The method applied to a first processor comprises: When completing virtual address to physical address conversion in a computing task, determining whether a data line to which the physical address belongs is abnormal according to cache data in a cache, wherein the data line to which the physical address belongs is a data line between the first processor and a communication object, and the cache data comprises physical address ranges corresponding to abnormal data lines or normal data lines; When the data line to which the physical address belongs is abnormal, repeatedly performing virtual address to physical address conversion in the computing task until the data line to which the physical address belongs is normal; When the data line to which the physical address belongs is normal, sending the computing task with completed address conversion out through the data line to which the physical address belongs.
2. The method of claim 1, wherein, The determining whether the data line to which the physical address belongs is abnormal according to the cache data in the cache comprises: checking whether the physical address hits a physical address range corresponding to an abnormal data line in the cache; if the physical address hits the physical address range corresponding to the abnormal data line, determining that the data line to which the physical address belongs is abnormal.
3. The method of claim 2, wherein the physical address range corresponding to the abnormal data line in the cache is saved to the cache when the health information of the data line indicates that the data line is abnormal, and is removed from the cache when the data line is normal. The determining whether the data line to which the physical address belongs is abnormal according to the cache data in the cache comprises:
4. The method of claim 1, wherein, checking whether the physical address hits a physical address range corresponding to a normal data line in the cache; if the physical address does not hit the physical address range corresponding to the normal data line, determining that the data line to which the physical address belongs is abnormal.
5. The method of claim 4, wherein the physical address range corresponding to the normal data line in the cache is saved to the cache when the health information of the data line indicates that the data line is normal, and is removed from the cache when the data line is abnormal. The method applied to a second processor comprises: obtaining health information of a data line between a first processor and a communication object; 6. A task recovery method characterized by, when the health information indicates that the data line is abnormal, configuring cache data in a cache of the first processor, so that the first processor, when completing virtual address to physical address conversion in a computing task, determines whether a data line to which the physical address belongs is abnormal according to the cache data, and when the data line to which the physical address belongs is abnormal, repeatedly performs virtual address to physical address conversion in the computing task until the data line to which the physical address belongs is normal, and then sends the computing task with completed address conversion out through the data line to which the physical address belongs; wherein the cache data comprises physical address ranges corresponding to abnormal data lines or normal data lines; performing re-linking operation on the abnormal data line to make the abnormal data line normal again; When the abnormal data line recovers, the cache data is updated, and the updated cache data is used to inform the first processor that the data line to which the physical address belongs is normal.
7. A memory management unit, comprising: The memory management unit comprises: an address conversion unit configured to perform virtual address to physical address conversion in a computing task; a cache configured to store cache data, the cache data being used to determine whether a data line to which the physical address belongs is abnormal, the cache data comprising a range of physical addresses corresponding to an abnormal data line or a normal data line, wherein the data line to which the physical address belongs is a data line between the processor to which the memory management unit belongs and a communication object; an access restriction unit configured to determine, according to the cache data, whether the data line to which the physical address belongs is abnormal, instruct the address conversion unit to repeatedly perform virtual address to physical address conversion in the computing task until the data line to which the physical address belongs is normal when the data line to which the physical address belongs is abnormal, and send the computing task with completed address conversion to the data line to which the physical address belongs when the data line to which the physical address belongs is normal.
8. A processor, comprising: The memory management unit comprises the memory management unit according to claim 7.
9. An electronic device, comprising: The processor comprises the processor according to claim 8.
10. An electronic device, comprising: The memory management unit comprises: a memory and a processor, the processor being connected to the memory; the memory is configured to store a program; the processor is configured to call the program stored in the memory to execute the method according to any one of claims 1-6.
11. A computing system, comprising: The memory management unit comprises: a first processor configured to determine, according to cache data in a cache, whether a data line to which a physical address belongs is abnormal when virtual address to physical address conversion in a computing task is completed, wherein the data line to which the physical address belongs is a data line between the first processor and a communication object, the cache data comprising a range of physical addresses corresponding to an abnormal data line or a normal data line, repeatedly perform virtual address to physical address conversion in the computing task until the data line to which the physical address belongs is normal when the data line to which the physical address belongs is abnormal, and send the computing task with completed address conversion to the data line to which the physical address belongs when the data line to which the physical address belongs is normal; a second processor configured to obtain health information of the data line to which the physical address belongs, configure cache data in the cache of the first processor when the health information indicates that the data line to which the physical address belongs is abnormal, perform re-linking operation on the abnormal data line to make the abnormal data line recover, and update the cache data when the abnormal data line recovers, wherein the updated cache data is used to inform the first processor that the data line to which the physical address belongs is normal.
12. The computing system of claim 11, wherein, The first processor is specifically configured to determine whether the data line to which the physical address belongs is abnormal according to the cache data in the cache, and specifically configured to check whether the physical address hits a physical address range corresponding to an abnormal data line in the cache; if the physical address hits the physical address range corresponding to the abnormal data line, it is determined that the data line to which the physical address belongs is abnormal; The second processor is specifically configured to save a physical address range corresponding to an abnormal data line in the cache when the health degree information indicates that the data line to which the physical address belongs is abnormal.
13. The computing system of claim 11, wherein, The first processor is specifically configured to determine whether the data line to which the physical address belongs is abnormal according to the cache data in the cache, and specifically configured to check whether the physical address hits a physical address range corresponding to a normal data line in the cache; if the physical address does not hit the physical address range corresponding to the normal data line, it is determined that the data line to which the physical address belongs is abnormal; The second processor is specifically configured to save a physical address range corresponding to a normal data line in the cache when the health degree information indicates that the data line to which the physical address belongs is normal.
14. The computing system of any of claims 11-13, wherein, The communication object is a switch, and the computing system further comprises the switch, and the plurality of first processors are connected through the switch.