Positioning detection method, device, equipment, medium and product of a computing module

Abstract

The application discloses a positioning detection method, device, equipment, medium and product of a computing module, comprising: in response to detecting a trigger signal of a positioning probe, obtaining a first in-place signal of a target computing module; identifying a target node of the target computing module in a server according to the first in-place signal, and sending the first in-place signal to a opposite connector of the target computing module based on the target node; performing loop processing on the first in-place signal based on the opposite connector to obtain a second in-place signal, and performing effectiveness detection on the target computing module according to the second in-place signal. The application positions the target computing module through the trigger signal of the positioning probe, and performs loop processing and effectiveness detection on the in-place signal of the target computing module. Therefore, the technical problem of how to position the computing module and detect the interconnection between nodes based on the architecture of the board-to-board blind plug cable can be solved, so as to improve the reliability and maintainability of the board-to-board blind plug cable architecture.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of positioning detection of computing modules, and in particular to a positioning detection method and device for computing modules, equipment, a medium and a product. BACKGROUND

[0002] Currently, the industry adopts a SW full-interconnection topology AI server constructed based on a PCIe Fabric. Such a server can support 16 standard PCIe double-wide GPUs to improve the point-to-point communication bandwidth between any two GPUs (Graphics Processing Unit) and reduce communication delay, thereby achieving a substantial improvement in model inference performance compared with a traditional 2-machine 8-card PCIe architecture. In hardware design, in order to simplify the structure and improve the board card reuse rate, modular design is generally adopted, that is, 16 GPUs are grouped into two groups of 8 GPUs each, and are integrated into two computing modules of a node to jointly constitute a server whole machine with a height of 8U or 10U.

[0003] In order to guarantee the quality of high-speed signals, the above-mentioned architecture adopts a board-to-board blind plug cable scheme to replace a traditional PCB (Printed Circuit Board) backplane. However, the board-to-board blind plug cable scheme has very high requirements for the precision and strength of the mechanical structure. In the production and assembly process, the contact between the connectors is easily poor due to tolerances or stress, thereby causing the high-speed link between the GPU chips to be interrupted or the performance to be degraded, which finally manifests as GPU card loss or communication rate reduction after the server is started, so that the entire system cannot be normally used, and the equipment reliability and usability are seriously affected. SUMMARY

[0004] The present application provides a positioning detection method and device for computing modules, equipment, a medium and a product to at least solve the problem of how to detect the positioning of computing modules and the interconnection between nodes based on the architecture of a board-to-board blind plug cable in related technologies.

[0005] The present application provides a positioning detection method for computing modules, applied to a server, wherein the server is configured with a positioning probe and at least one computing module of a node, and the method comprises the following steps:

[0006] In response to detecting a trigger signal of the positioning probe, a first in-place signal of a target computing module is acquired;

[0007] According to the first in-place signal, a target node of the target computing module in the server is identified, and the first in-place signal is sent to an opposite connector of the target computing module based on the target node;

[0008] The first in-situ signal is looped back based on the opposite end connector to obtain a second in-situ signal, and the target computing module is detected for effectiveness according to the second in-situ signal.

[0009] In an embodiment, the server is further configured with at least one positioning pin, and before obtaining the first in-situ signal of the target computing module in response to the trigger signal of the positioning probe, the method comprises:

[0010] In response to inserting the target computing module into the server, the positioning pin triggers the positioning probe.

[0011] In an embodiment, the server is further configured with at least one positioning device, and the positioning device comprises a limiting sheet for limiting the positioning probe in the positioning device.

[0012] The first in-situ signal of the target computing module is obtained in response to the trigger signal of the positioning probe, comprising:

[0013] In response to detecting the trigger signal of the positioning probe, the output electrode of the positioning probe is connected to the limiting sheet, and a high-level signal output by the output electrode is obtained.

[0014] The high-level signal is taken as the first in-situ signal of the target computing module.

[0015] In an embodiment, the first in-situ signal is sent to the opposite end connector of the target computing module based on the target node, comprising:

[0016] The first in-situ signal is converted into a first differential signal, and the first differential signal is sent to the self-end connector of the target computing module, wherein the self-end connector is located at the target node of the target computing module, the self-end connector is connected to the opposite end connector through a high-speed cable, and the opposite end connector is located at the opposite end node of the target computing module.

[0017] The first differential signal is sent to the opposite end connector through the high-speed cable.

[0018] In an embodiment, the first in-situ signal is converted into a first differential signal, and the first differential signal is sent to the self-end connector of the target computing module, comprising:

[0019] The first in-situ signal is sent to a control chip of the target computing module for level detection.

[0020] In response to detecting the high level of the first in-situ signal, sending the first in-situ signal to a first conversion chip for signal conversion to obtain a first differential signal;

[0021] Sending the first differential signal to a self-end connector of the target computing module.

[0022] In an embodiment, the loop processing of the first in-situ signal based on the opposite-end connector to obtain a second in-situ signal comprises:

[0023] Sending the first differential signal to the self-end connector based on the opposite-end connector;

[0024] Sending the first differential signal to a second conversion chip through the self-end connector for signal conversion to obtain a second in-situ signal.

[0025] In an embodiment, the detecting whether the target computing module is abnormal according to the second in-situ signal comprises:

[0026] Sending the second in-situ signal to a control chip of the target computing module;

[0027] Performing validity detection on the target computing module according to the second in-situ signal and the first in-situ signal in the control chip.

[0028] In an embodiment, the performing validity detection on the target computing module according to the second in-situ signal and the first in-situ signal in the control chip comprises:

[0029] Performing XOR calculation on the second in-situ signal and the first in-situ signal to obtain a difference result between the second in-situ signal and the first in-situ signal;

[0030] Comparing the difference result with a difference threshold value stored in the control chip, and taking the comparison result as a validity detection result of the target computing module.

[0031] In an embodiment, the performing XOR calculation on the second in-situ signal and the first in-situ signal to obtain a difference result between the second in-situ signal and the first in-situ signal comprises:

[0032] Performing XOR calculation on binary coded data of the first in-situ signal and binary coded data of the second in-situ signal to obtain a difference coding number between the first in-situ signal and the second in-situ signal;

[0033] Calculating a difference rate of the second in-situ signal compared with the first in-situ signal according to the difference coding number.

[0034] In an embodiment, the comparison of the difference result with the difference threshold stored in the control chip is used as the effectiveness detection result of the target computing module, including:

[0035] comparing the difference rate with the difference threshold stored in the control chip;

[0036] If the difference rate is less than or equal to the difference threshold, it is determined that the connection between the target node and the opposite node of the target computing module is normal; if the difference rate is greater than the difference threshold, it is determined that the connection between the target node and the opposite node is abnormal.

[0037] In an embodiment, the server is connected to a baseboard management controller through a bus, and the method further includes:

[0038] sending the effectiveness detection result to the baseboard management controller through the bus for recording to generate a corresponding detection log;

[0039] generating alarm information for the target computing module according to the detection log.

[0040] The application also provides a positioning detection device for a computing module, applied to a server, the server being configured with a positioning probe and at least one node computing module, the device including:

[0041] a triggering module for obtaining a first in-place signal of a target computing module in response to detecting a trigger signal of the positioning probe;

[0042] a positioning module for identifying a target node of the target computing module in the server according to the first in-place signal, and sending the first in-place signal to an opposite connector of the target computing module based on the target node;

[0043] a detection module for performing loop processing on the first in-place signal based on the opposite connector to obtain a second in-place signal, and performing effectiveness detection on the target computing module according to the second in-place signal.

[0044] The application also provides an electronic device including a memory for storing a computer program and a processor for executing the computer program to implement the steps of the positioning detection method of any one of the above computing modules.

[0045] The application also provides a computer readable storage medium having a computer program stored therein, wherein the computer program is executed by a processor to implement the steps of the positioning detection method of any one of the above computing modules.

[0046] The application further provides a computer program product comprising a computer program which, when executed by a processor, implements the steps of the positioning detection method of any one of the above computing modules.

[0047] According to the embodiments disclosed in the application, in response to the trigger signal of the positioning probe, the first in-place signal of the target computing module is acquired; the target node of the target computing module in the server is identified according to the first in-place signal, and the first in-place signal is sent to the opposite end connector of the target computing module based on the target node; the first in-place signal is looped back by the opposite end connector to obtain the second in-place signal, and the effectiveness of the target computing module is detected according to the second in-place signal. In the embodiment, the trigger signal of the positioning probe is used to position the target computing module, and the in-place signal of the target computing module is sent to the opposite end connector for looped back processing to detect the effectiveness of the target computing module, so that the communication link interruption or signal degradation problem caused by poor connector contact can be found in time. Therefore, the technical problem of how to position the computing module and detect the interconnection between nodes based on the architecture of the board-to-board blind plug cable can be solved, and the technical effect of improving the reliability and maintainability of the board-to-board blind plug cable architecture can be achieved. BRIEF DESCRIPTION OF DRAWINGS

[0048] In order to more clearly illustrate the embodiments of the application, the drawings needed in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0049] Figure 1 The flowchart of the positioning detection method of the computing module provided by the embodiments of the application is shown in the figure.

[0050] Figure 2 The schematic diagram of the mainframe box of the server provided by the embodiments of the application is shown in the figure.

[0051] Figure 3 The internal schematic diagram of the mainframe box of the server provided by the embodiments of the application is shown in the figure.

[0052] Figure 4 The structural schematic diagram of the positioning pin provided by the embodiments of the application is shown in the figure.

[0053] Figure 5 The structural schematic diagram of the positioning device provided by the embodiments of the application is shown in the figure.

[0054] Figure 6 Another flowchart of the positioning detection method of the computing module provided by the embodiments of the application is shown in the figure.

[0055] Figure 7A structural schematic diagram of a positioning detection device of a computing module provided by an embodiment of the present application is shown in the figure.

[0056] Figure 8 A structural schematic diagram of an electronic device provided by an embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0057] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without any creative work fall within the protection scope of the present application.

[0058] It should be noted that, in the description of the present application, the terms “comprise”, “contain” or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. The terms “first”, “second” and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0059] In order for those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0060] Currently, the industry adopts a SW full-interconnected topology AI server based on PCIe Fabric. Such a server can support 16 standard PCIe double-wide GPUs to improve the point-to-point communication bandwidth between any two GPUs (Graphics Processing Unit) and reduce communication delay, thereby achieving a substantial improvement in model inference performance compared with the traditional 2-machine 8-card PCIe architecture. In hardware design, in order to simplify the structure and improve the board card reuse rate, modular design is generally adopted, that is, 16 GPUs are grouped into two groups of 8 GPUs each, and integrated into two computing modules of a node, together constituting an 8U or 10U high server whole machine.

[0061] To ensure the quality of high-speed signals, the above architecture uses a board-to-board blind plug cable scheme to replace the traditional PCB (Printed Circuit Board) backplane. However, the board-to-board blind plug cable scheme has very high requirements for the precision and strength of the mechanical structure. In the production and assembly process, the contact between the connectors is easily poor due to tolerances or stress, thereby causing the high-speed link between GPU chips to be interrupted or the performance to be degraded. Ultimately, the server appears to have a GPU card lost or a communication rate decreased after starting, so that the entire system cannot be normally used, which seriously affects the reliability and usability of the equipment.

[0062] Based on this, the embodiment of the present application provides a positioning detection method of a computing module. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that here.

[0063] In this embodiment, a positioning detection method of a computing module is provided, which is applied to a server, and the server is configured with a positioning probe and at least one node computing module, Figure 1 The flowchart of the positioning detection method of the computing module according to the embodiment of the present application is shown in FIG. 1, which includes the following steps: Figure 1

[0064] Step S101, in response to detecting a trigger signal of the positioning probe, a first in-place signal of a target computing module is acquired.

[0065] Step S102, the target node of the target computing module in the server is identified according to the first in-place signal, and the first in-place signal is sent to the opposite end connector of the target computing module based on the target node.

[0066] Step S103, the first in-place signal is looped back by the opposite end connector to obtain a second in-place signal, and the effectiveness of the target computing module is detected according to the second in-place signal.

[0067] ​The positioning detection method of the computing module provided in the embodiment responds to the trigger signal of the positioning probe, acquires the first in-position signal of the target computing module, identifies the target node of the target computing module in the server according to the first in-position signal, and sends the first in-position signal to the opposite connector of the target computing module based on the target node. The opposite connector performs loop processing on the first in-position signal to obtain the second in-position signal, and performs effectiveness detection on the target computing module according to the second in-position signal. The embodiment positions the target computing module through the trigger signal of the positioning probe, and performs loop processing and effectiveness detection on the in-position signal of the target computing module. Therefore, the technical problem of how to position the computing module and detect the interconnection between nodes based on the board-to-board blind plug cable architecture can be solved, so as to improve the reliability and maintainability of the board-to-board blind plug cable architecture.

[0068] With reference to Figure 2 , a schematic diagram of a host box of a server is shown, the host box of the server contains at least one computing module, and each computing module corresponds to a node. As shown in the figure, the server can contain a first node computing module, a second node computing module, and a third node computing module. It is worth noting that the number of nodes in the figure is only schematic, and the present application does not limit this.

[0069] For the above step S101, the first in-position signal of the target computing module is acquired in response to the trigger signal of the positioning probe.

[0070] With reference to Figure 3 , a schematic diagram of the inside of the host box of the server is shown. As shown in the figure, the inside of the host box of the server is configured with multiple sub-boxes, wherein each sub-box corresponds to the computing module of a node, and each sub-box is configured with a positioning pin, a positioning device, a wire, a cable, a plurality of connectors, a control chip, and a PCB. Specifically, the control chip is on-board on the PCB, and the control chip can be a CPLD or an MCU. The wire led out from the positioning device is connected to the connector on the PCB and then sent to the control chip. The connectors are connected by cables. The sub-box of the first node and the sub-box of the second node each contain a connector connected to the positioning device and six blind plug connectors for interconnection. Among them, the connectors 2 and 4 have signal loops, and the sub-box of the third node has four blind plug connectors, and the four connectors each have a signal loop. In terms of interconnection, the connectors 1 and 6 in the first node and the second node are each interconnected to different connectors in the third node, and the connectors 3, 4, 5, 2 of the first node are respectively interconnected to the connectors 2, 3, 4, 5 of the second node one by one.

[0071] The server is also configured with at least one positioning pin, with reference to Figure 4, shows the structural schematic diagram of the positioning pin provided by the embodiment of the application, the positioning pin is fixed to the side wall of the main box body by riveting or welding. As shown in the top view of the positioning pin in Figure 4 , the positioning pin is a small slope trapezoidal structure, the height of the positioning pin needs to be slightly greater than three quarters of the length of the positioning probe, so as to facilitate the smooth lifting of the side wall positioning pin when the calculation module is pushed in and pulled out, and to avoid jamming. The installation position of the positioning pin has specific requirements, the positioning pin corresponding to the upper calculation module needs to be fixed to the lower position, corresponding to the positioning probe 2 shown in Figure 5 , and the positioning pin corresponding to the lower calculation module needs to be fixed to the upper position, corresponding to the positioning probe 1 shown in Figure 5 .

[0072] Referring to Figure 5 , shows the structural schematic diagram of the positioning device provided by the embodiment of the application, the positioning device at least includes a limiting sheet, a return spring, a positioning probe and a return key. As shown by the dashed line, the limiting sheet integrates two limiting hooks, which are used to hook and limit the positioning probe. The whole positioning device is locked by a fixing screw on the side wall of the sub-box body, the side wall of the sub-box body is designed with two guide holes, the positioning probe is outwardly probed from the guide hole, and under normal circumstances, three quarters of the probe are exposed outside the sub-box body, which is used to trigger the positioning pin of the main box body. The surface of the probe can be sprayed with different colors and marked with "up" and "down" to represent the characteristics of different calculation modules, for example, the positioning probe 1 is designed as yellow and marked with "up" to represent that its calculation module belongs to the upper node of the server main box, and the positioning probe 2 is designed as green and marked with "down" to represent that its calculation module belongs to the lower node of the server main box.

[0073] In the embodiment of the application, the calculation module refers to equal grouping of a plurality of GPUs in the server, and each group of GPUs serves as a calculation module. The server is configured with at least one positioning device, the positioning device includes a limiting sheet for limiting the positioning probe, and the positioning probe is located in the positioning device. In response to inserting the target calculation module into the server, the positioning pin triggers the positioning probe. Specifically, the positioning device internally integrates a large-capacity button cell to provide a 3V positive voltage, and the limiting sheet is made of conductive material, and the input electrode thereon is connected to the positive electrode of the button cell. The distal end of the positioning probe 1 and 2 has an output electrode, and the output electrode is connected to a wire. Therefore, when the positioning probe is triggered and pressed down, the corresponding output electrode will be in contact with the charged limiting sheet, and a 3V high level will be obtained on the corresponding wire, and the two wires correspond to the in-place condition of each calculation module, and a corresponding in-place signal is generated, and the processed in-place signal is sent to the control chip through the connector and the related circuit.

[0074] The positioning pin is a mechanical component fixed to the side wall of the main box by riveting or welding. During the process of inserting the computing module into the server slot, it interacts with the positioning probe in the case to trigger the probe. Specifically, the positioning pin changes the physical state of the positioning probe by applying pressure during the process of inserting the computing module into the sub-box of the server, thereby switching it from one steady state (such as the off state) to another steady state (such as the on state). For example, the positioning pin presses the button of the micro switch, so that the internal contact changes from normally open to closed.

[0075] The limiting sheet is a conductive metal sheet inside the positioning device, which limits the travel of the positioning probe and prevents it from moving too much or mispositioning. When the positioning probe is triggered, the output electrode at the end of the probe will physically contact the limiting sheet, thereby forming a complete current path. For example, after the probe is pressed down, the metal contact at the bottom of the probe closely adheres to the limiting sheet as a static sheet, and the current flows from the probe to the limiting sheet.

[0076] After the electrical path is established, the level state change of the circuit is detected, for example, the I / O pin connected to the limiting sheet is continuously monitored. When the level of the pin jumps from 0V (low level) to 3V (high level), the jump signal is obtained. The specific steps include:

[0077] In response to detecting the trigger signal of the positioning probe, the output electrode of the positioning probe is connected to the limiting sheet, and a high-level signal output by the output electrode is obtained; the high-level signal is taken as the first in-place signal of the target computing module.

[0078] The embodiment introduces a cooperative triggering structure composed of a positioning pin, a positioning probe, and a positioning device with a limiting sheet, which realizes accurate detection of the physical plugging state of the computing module and effectively solves the problem of uncertainty of the module in-place state caused by the inability to visually align in the board-to-board blind insertion architecture. Specifically, by linking the mechanical structure and the level signal, the physical in-place state of the computing module is converted into a clear electrical signal. At the same time, the limiting sheet ensures the stability of the electrical connection, avoids signal false triggering caused by vibration or tolerance, and significantly improves the accuracy and robustness of the detection result, fundamentally improving the production and assembly efficiency, system reliability, and maintainability of the blind insertion server architecture.

[0079] For step S102, the target node of the target computing module in the server is identified according to the first in-place signal, and the first in-place signal is sent to the opposite connector of the target computing module based on the target node.

[0080] Target node refers to the physical location or logical number of the target computing module inserted in the server chassis. Through backplane wiring or software configuration, the first in-place signal can be uniquely associated with a specific node slot. For example, a server has four computing module slots, which are defined as node 1, node 2, node 3 and node 4. When the target computing module is inserted into node 2, node 2 is taken as the target node corresponding to the target computing module.

[0081] Counter node refers to another node in the server that has a direct interconnection relationship with the target node, and the two form a communication pair through a high-speed cable. For example, in the server shown in FIG. 1, the first node and the second node are directly paired, so when the target node is the first node / second node, the counter node is the second node / first node. Figure 3

[0082] Self-end connector refers to a wire-to-wire blind-mate connector installed on the target computing module (i.e., the target node), which is the starting point or end point of the high-speed signal transmission of the target computing module to the outside.

[0083] Counter-end connector refers to a wire-to-wire blind-mate connector installed on the computing module of the counter node, which is paired with the self-end connector.

[0084] Specifically, after the target computing module is inserted into the sub-chassis of the server, the positioning pin on the side wall of the sub-chassis where the target computing module is inserted will lift the positioning probe, at which time the output electrode at the end of the positioning probe will come into contact with the electrified limit sheet. Then, a 3V high level (i.e., the first in-place signal) can be output on the wire connected to the output electrode, while the wire in the sub-chassis where the target computing module is not inserted is still at a low level. Therefore, the target node corresponding to the sub-chassis where the target computing module is currently inserted can be located according to the level detection result of the wire, that is, the target node of the target computing module in the server is identified according to the first in-place signal. For example, referring to FIGS. 1 and 2, if the target computing module is inserted into the first layer of the server main chassis, the positioning pin 1 will lift the positioning probe 2, at which time the output electrode 2 will come into contact with the electrified limit sheet, and a 3V high level can be output on the wire at this time, indicating that the current target computing module corresponds to the first node. If the target computing module is inserted into the second layer of the chassis, the positioning pin 2 will lift the positioning probe 1, at which time the output electrode 1 will come into contact with the electrified limit sheet, and a 3V high level can be output on the wire at this time, indicating that the current target computing module corresponds to the second node. Through the cooperation of the positioning device in each node and the positioning pin of the main chassis, the positioning of the target computing module is completed. Figure 4 Figure 5

[0085] ​​​After obtaining the first in-situ signal of the target computing module, the first in-situ signal is converted into a differential signal more suitable for long-distance transmission in a high-speed cable. The converted differential signal is routed to a self-end connector of the target node, and the self-end connector transmits the differential signal to a counter-end connector through the high-speed cable.

[0086] For example, it is confirmed through step S101 that the target computing module is located at the first node and the corresponding first in-situ signal is obtained. It is identified that the first in-situ signal originates from the first node. According to the preset node interconnection topology (such as the interconnection between the first node and the second node), it is determined that the counter-end node is the second node. The first in-situ signal indicating that the target computing module is located at the first node is converted into a first differential signal with stronger anti-interference capability, and the first differential signal is sent to a self-end connector on the first node, wherein the self-end connector is interconnected with a counter-end connector on the second node through a high-speed cable previously laid. Further, the first differential signal is sent to the connector in the second node (i.e., the counter-end connector of the first node) through the high-speed cable. Specifically, the following steps are included:

[0087] The first in-situ signal is converted into a first differential signal, and the first differential signal is sent to a self-end connector of the target computing module, wherein the self-end connector is located at a target node of the target computing module, and the self-end connector is connected to a counter-end connector through a high-speed cable, and the counter-end connector is located at a counter-end node of the target computing module; the first differential signal is sent to the counter-end connector through the high-speed cable.

[0088] In a specific embodiment, when the first in-situ signal is converted into the first differential signal and the first differential signal is sent to the self-end connector of the target computing module, the first in-situ signal is first sent to a control chip of the target computing module for level detection; in response to detecting a high level of the first in-situ signal, the first in-situ signal is sent to a first conversion chip for signal conversion to obtain the first differential signal; and the first differential signal is sent to the self-end connector of the target computing module.

[0089] Specifically, the first in-situ signal is subjected to level detection by a control chip loaded on a PCB in the first node. The control chip can be a complex programmable logic device (CPLD) or a microcontroller (MCU) and is integrated with general-purpose input / output (GPIO) pins. The control chip reads the voltage value of the first in-situ signal through the GPIO pins and analyzes it into a digital state of logic "1" (high level) or logic "0" (low level). For example, when the voltage is read as 3V, it is determined as a high level.

[0090] In combination with Figure 3 Table 1 specifically sets forth the level detection logic in the embodiments of the present application:

[0091] Table 1 Level detection logic table

[0092]

[0093] The first conversion chip is a high-speed DAC (Digital-to-Analog Converter) chip, which is a chip for converting discrete digital signals into continuous analog signals. The digital signal is input to the digital input port of the high-speed DAC chip, and the converter in the high-speed DAC chip converts the digital signal into an analog signal, which is then amplified and filtered by an amplifier and an output filter, and finally output as an analog signal. In this embodiment, the first in-place signal is input to the digital input port of the high-speed DAC chip, and the converter in the high-speed DAC chip converts the first in-place signal into a first differential signal, which is then amplified and filtered by an amplifier and an output filter, and finally output as a first differential signal.

[0094] In this embodiment, the control chip detects the level of the first in-place signal, reads the voltage of the pin, and confirms that it is a stable high level, which eliminates abnormal situations such as signal jitter or insufficient level caused by line interference or poor contact. In response to detecting a stable high level, the control chip determines that the in-place state of the target computing module is true. Then, the first in-place signal is sent to the first conversion chip for signal conversion, converting the input digital signal into an analog signal. This ensures that only valid in-place signals that have been verified can enter the opposite end node for loopback transmission, avoiding the occupation of the interconnection link by invalid signals, and effectively improving the accuracy and robustness of interconnection detection under the blind plug architecture.

[0095] For step S103, the opposite end connector processes the first in-place signal in a loopback manner to obtain a second in-place signal, and performs effectiveness detection on the target computing module based on the second in-place signal.

[0096] In one embodiment, loopback processing refers to guiding the transmitted signal back to the receiving end through a specific path, and verifying the integrity of the entire transmission link by comparing the characteristics of the transmitted and received signals. In this embodiment, it specifically refers to the process of sending the first differential signal to the opposite end connector and then returning to the self-end connector. The second conversion chip is a high-speed ADC (Analog-to-Digital Converter) chip, which is opposite to the first conversion chip and is used to convert the received analog signal back to a digital signal.

[0097] Specifically, after receiving the first differential signal from the high-speed cable, the opposite end connector routes the first differential signal directly or after simple buffering to its paired self-end connector. Further, the self-end connector sends the first differential signal (analog signal) to the second conversion chip for conversion into a second in-situ signal (digital signal). For example, referring to Figure 6 After the positioning device identifies the target node where the target computing module is located, it transmits the corresponding first in-situ signal to the control chip through the wire. After detecting the high level of the first in-situ signal representing the first node in-situ, the control chip sends the first in-situ signal to the high-speed DAC chip through the high-speed interface. After the DAC chip converts the first in-situ signal into the corresponding first differential signal, it is transmitted to the specific pins of the self-end connectors 1, 3, 5, and 6. After the first differential signal is transmitted to the opposite end connector through the high-speed cable between the self-end connector and the opposite end connector, it is again looped back to the high-speed cable through the corresponding pins and then returned to the self-end connectors 1, 3, 5, and 6. Further, the first differential signal is sent to the high-speed ADC chip, which converts the first differential signal into a second in-situ signal (digital signal) after collecting it and returns it to the control chip through the high-speed interface. The specific steps include:

[0098] Based on the opposite end connector sending the first differential signal to the self-end connector, the self-end connector sends the first differential signal to the second conversion chip for signal conversion to obtain the second in-situ signal.

[0099] This embodiment determines that the entire high-speed cable link from the target node to the opposite end node and back to the target node is also connected and functioning normally through the signal loopback mechanism. Further, by comparing the first in-situ signal with the second in-situ signal, the effectiveness of this interconnection link can be finally confirmed.

[0100] In one embodiment, the present embodiment evaluates whether the target computing module and its interconnection link are in the expected working state by analyzing the effectiveness of the in-situ signal through the loopback mechanism.

[0101] XOR calculation is a binary logic operation, with the specific rule being: when the two input bits are different, the output is "1" (true); when they are the same, the output is "0" (false). For example, XOR calculation on the binary sequence 10110011 of the first in-situ signal and the binary sequence 10111011 of the second in-situ signal will result in 00001000, where the "1" in the 4th bit from the right represents the difference between the first in-situ signal and the second in-situ signal at a specific bit position.

[0102] The difference coding number refers to the total number of bits with value "1" in the result of the XOR calculation, which quantifies the degree of inconsistency between the two signal sequences. For example, in the XOR result 00001000, only 1 bit is "1", so the difference coding number is 1.

[0103] The difference rate is the ratio between the difference coding number and the total number of bits in the signal sequence. In this embodiment, the difference rate between the first in-situ signal and the second in-situ signal is calculated to convert the difference degree into a percentage or ratio, which is convenient for comparison with the preset difference threshold. For example, if the total length of the signal is 8 bits and the difference coding number is 1, the difference rate is 12.5%. In this embodiment, the difference threshold is pre-stored in the control chip, which represents the maximum allowable error limit. For example, based on the system noise tolerance and link performance requirements, the difference threshold can be set to 5%, that is, as long as the difference rate of the loopback signal does not exceed 5%, the link quality is considered to be qualified.

[0104] Specifically, the XOR function is called in the control chip to calculate the first in-situ signal and the second in-situ signal, and the calculation result is stored in the register on the control chip. Then, the control chip needs to count the number of "1"s in the XOR result, and calculate the ratio between the number of "1"s in the XOR result and the total length (i.e. the total number of bits) of the first in-situ signal. For example, the XOR result in the register has 5 bits of "1", and assuming the total bit width is 64 bits, it calculates that the actual difference rate is about 7.8%.

[0105] Further, the control chip compares the calculated actual difference rate with the preset difference threshold read from the memory to determine whether the former is greater than the latter. If the difference rate is not greater than the difference threshold, the control chip determines that the connection between the target node and the opposite node is normal, otherwise, it determines that the connection between the target node and the opposite node is abnormal. Specifically, the following steps are included:

[0106] The second in-situ signal is sent to the control chip of the target computing module; and the control chip performs effectiveness detection on the target computing module according to the second in-situ signal and the first in-situ signal. Specifically, the second in-situ signal and the first in-situ signal are XOR calculated to obtain the difference result between the second in-situ signal and the first in-situ signal; the difference result is compared with the difference threshold stored in the control chip, and the comparison result is taken as the effectiveness detection result of the target computing module.

[0107] In a specific embodiment, the binary coded data of the first in-situ signal and the binary coded data of the second in-situ signal are subjected to an XOR calculation to obtain a difference encoding quantity between the first in-situ signal and the second in-situ signal; a difference rate of the second in-situ signal compared with the first in-situ signal is calculated according to the difference encoding quantity. The difference rate is compared with a difference threshold value stored in the control chip; if the difference rate is less than or equal to the difference threshold value, it is determined that the connection between the target node and the opposite end node of the target computing module is normal; if the difference rate is greater than the difference threshold value, it is determined that the connection between the target node and the opposite end node is abnormal.

[0108] The embodiment effectively combines the node built-in control chip, the high-speed DAC chip and the high-speed ADC chip, compares the difference before and after the high-speed digital signal is sent back, simulates and analyzes the loss of the high-speed differential signal after the connector, confirms whether the blind-mate connector exists false insertion, and further identifies whether the physical link exists a bad condition.

[0109] In another embodiment of the present application, the server is connected with the baseboard management controller through the bus, and after obtaining the validity detection result, the validity detection result is sent to the baseboard management controller through the bus for recording, so as to generate a corresponding detection log; further, the detection log is used to generate alarm information for the target computing module.

[0110] Specifically, the baseboard management controller is an independent microcontroller embedded on the server mainboard, which is used to monitor the hardware health status (such as temperature, voltage, fan speed) in the server and record logs. The baseboard management controller contains an independent processing core and a network interface, so that even if the main CPU (Central Processing Unit, CPU) of the server is not powered on or the operating system is not running, the baseboard management controller can work normally. The bus is a shared communication path connecting various main hardware components (such as CPU, baseboard management controller, various controllers) in the server.

[0111] Specifically, after the control chip completes the determination, the validity detection result representing “the connection between the target node and the opposite end node of the target computing module is normal” or “the connection between the target node and the opposite end node is abnormal” is packaged into a data packet according to the bus protocol, driven to the bus, and transmitted to the baseboard management controller. The baseboard management controller receives it and writes it as a key event item into its log database. For example, the control chip sends a byte of data (such as 0x00 representing normal and 0x01 representing abnormal) to the specified register address of the baseboard management controller through the I2C bus, and the baseboard management controller periodically polls the address, records the result in the log file after obtaining the result.

[0112] When the baseboard management controller identifies an event of a specific severity level in the log, an alarm generation process is triggered, such as when a connection between the target node and the opposite node is abnormal. For example, the alarm engine of the baseboard management controller generates specific alarm information according to the newly appearing abnormal record in the detection log. The alarm information can include alarm ID, severity level, occurrence location, recommended measures, and the like. The server user can learn the current log and alarm information through the RJ45 management network port, and then repair the located problem point.

[0113] The embodiment reports the effectiveness detection result to the baseboard management controller, so that a hidden physical failure such as a poor contact of the blind-mate connector can be converted into an explicit and recordable alarm event in real time, greatly improving the observability and traceability of the failure. Secondly, the baseboard management controller uniformly generates and publishes alarm information, realizes the centralization and automation of operation and maintenance management, and the administrator can master the health status of the interconnection link without logging into a single computing module, thereby improving the operation and maintenance efficiency of a large-scale server cluster.

[0114] Through the description of the above implementation, those skilled in the art can clearly understand that the method according to the above embodiment can be realized by means of software and the necessary general hardware platform, of course, it can also be realized by hardware, but in many cases the former is a better implementation.

[0115] The embodiment of the present application also provides a positioning detection device of a computing module, which is used to implement the above embodiment and preferred implementation, and will not be described again. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiment is preferably implemented in software, hardware, or a combination of software and hardware is also possible and is conceived.

[0116] The embodiment provides a positioning detection device of a computing module, as shown in Figure 7 The device is applied to a server, the server is configured with a positioning probe and at least one node computing module, and the device comprises:

[0117] The triggering module 701 is configured to acquire a first in-place signal of the target computing module in response to detecting a trigger signal of the positioning probe.

[0118] The positioning module 702 is configured to identify a target node of the target computing module in the server according to the first in-place signal, and send the first in-place signal to an opposite connector of the target computing module based on the target node.

[0119] The detection module 703 is configured to perform loop processing on the first in-place signal based on the opposite connector to obtain a second in-place signal, and perform effectiveness detection on the target computing module according to the second in-place signal.

[0120] In an embodiment, the server is further configured with at least one positioning pin, and the device comprises:

[0121] An insertion module is configured to trigger the positioning probe by the positioning pin in response to the insertion of the target computing module into the server.

[0122] In an embodiment, the server is further configured with at least one positioning device, and the positioning device comprises a limiting sheet for limiting the positioning probe in the positioning device; and the trigger module 701 is specifically configured to control the output electrode of the positioning probe to be connected with the limiting sheet in response to the detection of the trigger signal of the positioning probe, acquire the high-level signal output by the output electrode, and take the high-level signal as the first in-place signal of the target computing module.

[0123] In an embodiment, the positioning module 702 is specifically configured to convert the first in-place signal into a first differential signal and send the first differential signal to a self-end connector of the target computing module, wherein the self-end connector is located at a target node of the target computing module, and the self-end connector is connected with a counter-end connector through a high-speed cable, and the counter-end connector is located at a counter-end node of the target computing module; and the first differential signal is sent to the counter-end connector through the high-speed cable.

[0124] In an embodiment, the positioning module 702 is specifically configured to send the first in-place signal to a control chip of the target computing module for level detection; in response to the detection of the high level of the first in-place signal, send the first in-place signal to a first conversion chip for signal conversion to obtain a first differential signal; and send the first differential signal to the self-end connector of the target computing module.

[0125] In an embodiment, the detection module 703 is specifically configured to send the first differential signal to the self-end connector based on the sending of the first differential signal to the self-end connector by the counter-end connector; and send the first differential signal to a second conversion chip through the self-end connector for signal conversion to obtain a second in-place signal.

[0126] In an embodiment, the detection module 703 is specifically configured to send the second in-place signal to the control chip of the target computing module; and perform validity detection on the target computing module according to the second in-place signal and the first in-place signal in the control chip.

[0127] In an embodiment, the detection module 703 is specifically configured to perform exclusive OR calculation on the second in-place signal and the first in-place signal to obtain a difference result between the second in-place signal and the first in-place signal; compare the difference result with a difference threshold value stored in the control chip, and take the obtained comparison result as the validity detection result of the target computing module.

[0128] In an embodiment, the detection module 703 is specifically configured to perform XOR calculation on the binary coded data of the first in-position signal and the binary coded data of the second in-position signal to obtain a difference coding quantity between the first in-position signal and the second in-position signal; and calculate a difference rate of the second in-position signal compared with the first in-position signal according to the difference coding quantity.

[0129] In an embodiment, the detection module 703 is specifically configured to compare the difference rate with a difference threshold value stored in the control chip; if the difference rate is less than or equal to the difference threshold value, it is determined that the connection between the target node and the opposite node of the target computing module is normal; if the difference rate is greater than the difference threshold value, it is determined that the connection between the target node and the opposite node is abnormal.

[0130] In an embodiment, the server is connected with the baseboard management controller through a bus, and the apparatus further comprises:

[0131] The recording module is configured to send the validity detection result to the baseboard management controller through the bus for recording to generate a corresponding detection log.

[0132] The alarm module is configured to generate alarm information for the target computing module according to the detection log.

[0133] The features of the embodiments of the positioning detection apparatus of the computing module can be referred to the related descriptions of the embodiments of the positioning detection method of the computing module, which will not be repeated here.

[0134] The embodiments of the present application also provide an electronic device, as shown in the figure, comprising a memory 10, a processor 20 and a communication interface 30, the memory 10 stores a computer program, the processor 20 is configured to run the computer program to execute the steps in any of the above-mentioned embodiments of the positioning detection method of the computing module. Figure 8

[0135] The embodiments of the present application also provide a computer readable storage medium, which stores a computer program, wherein the computer program is configured to execute the steps in any of the above-mentioned embodiments of the positioning detection method of the computing module when running.

[0136] In an exemplary embodiment, the above-mentioned computer readable storage medium can include but is not limited to: U disk, read-only memory (Read-Only Memory, ROM for short), random access memory (Random Access Memory, RAM for short), mobile hard disk, magnetic disk or optical disk and various computer program storage media.

[0137] ​The embodiment of the present application further provides a computer program product, the computer program product comprising a computer program, the computer program being executed by a processor to implement the steps in the positioning detection method embodiments of any of the computing modules.

[0138] The embodiment of the present application further provides another computer program product, comprising a non-volatile computer readable storage medium, the non-volatile computer readable storage medium storing a computer program, the computer program being executed by a processor to implement the steps in the positioning detection method embodiments of any of the computing modules.

[0139] The skilled person can further realize that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be realized in electronic hardware, computer software or a combination of both. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been described in the above description in general terms. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0140] The positioning detection method, device, equipment, medium and product of the computing module provided by the present application are described in detail above. The principles and implementation modes of the present application are described by applying specific examples in this paper, and the above description of the examples is only applicable to help understand the method and core idea of the present application. It should be pointed out that, for ordinary skilled persons in the technical field, some improvements and modifications can be made to the present application without departing from the principles of the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A method for positioning and detecting a computing module, characterized in that, Applied to a server, the server being configured with a positioning probe and a computing module with at least one node, the method includes: In response to the detection of the trigger signal of the positioning probe, the first presence signal of the target computing module is acquired; The target node of the target computing module in the server is identified based on the first presence signal, and the first presence signal is sent to the peer connector of the target computing module based on the target node. Based on the peer connector, the first in-situ signal is looped back to obtain the second in-situ signal, and the target computing module is validated based on the second in-situ signal.

2. The method according to claim 1, characterized in that, The server is also configured with at least one positioning pin, and before acquiring a first presence signal of the target computing module in response to detecting a trigger signal from a positioning probe, the method includes: In response to inserting the target computing module into the server, the positioning pin triggers the positioning probe.

3. The method according to claim 2, characterized in that, The server is also equipped with at least one positioning device, which includes a limiting piece for limiting the positioning probe, which is located in the positioning device. The step of acquiring the first presence signal of the target computing module in response to the detection of the trigger signal of the positioning probe includes: In response to the detection of a trigger signal from the positioning probe, the output electrode of the positioning probe is connected to the limiting plate to obtain a high-level signal output by the output electrode; The high-level signal is used as the first in-situ signal of the target computing module.

4. The method according to claim 1, characterized in that, The step of sending the first in-situ signal to the peer connector of the target computing module based on the target node includes: The first in-situ signal is converted into a first differential signal and sent to the self-end connector of the target computing module, wherein the self-end connector is located at the target node of the target computing module, and the self-end connector is connected to the peer connector via a high-speed cable, wherein the peer connector is located at the peer node of the target computing module. The first differential signal is transmitted to the opposite connector via the high-speed cable.

5. The method according to claim 4, characterized in that, The step of converting the first in-situ signal into a first differential signal and sending the first differential signal to the self-end connector of the target computing module includes: The first in-situ signal is sent to the control chip of the target computing module for level detection; In response to detecting a high level of the first presence signal, the first presence signal is sent to the first conversion chip for signal conversion to obtain a first differential signal; The first differential signal is sent to the self-end connector of the target computing module.

6. The method according to claim 4, characterized in that, The step of performing loopback processing on the first in-situ signal based on the peer connector to obtain the second in-situ signal includes: The first differential signal is sent to the self-end connector based on the peer connector; The first differential signal is sent to the second conversion chip through the self-terminal connector for signal conversion to obtain the second in-situ signal.

7. The method according to claim 1, characterized in that, The step of detecting whether the target computing module is abnormal based on the second in-situ signal includes: The second in-situ signal is sent to the control chip of the target computing module; The control chip performs validity detection on the target computing module based on the second presence signal and the first presence signal.

8. The method according to claim 7, characterized in that, The step of performing validity detection on the target computing module in the control chip based on the second presence signal and the first presence signal includes: Perform an XOR operation on the second in-situ signal and the first in-situ signal to obtain the difference between the second in-situ signal and the first in-situ signal; The difference result is compared with the difference threshold stored in the control chip, and the comparison result is used as the validity detection result of the target computing module.

9. The method according to claim 8, characterized in that, The step of performing an XOR operation on the second in-situ signal and the first in-situ signal to obtain the difference between the second in-situ signal and the first in-situ signal includes: XOR the binary encoded data of the first in-situ signal and the binary encoded data of the second in-situ signal to obtain the number of difference codes between the first in-situ signal and the second in-situ signal; The difference rate between the second in-situ signal and the first in-situ signal is calculated based on the number of difference codes.

10. The method according to claim 9, characterized in that, The step of comparing the difference result with the difference threshold stored in the control chip, and using the comparison result as the validity detection result of the target computing module, includes: The difference rate is compared with the difference threshold stored in the control chip; If the difference rate is less than or equal to the difference threshold, the connection between the target node and the peer node of the target computing module is determined to be normal; if the difference rate is greater than the difference threshold, the connection between the target node and the peer node is determined to be abnormal.

11. The method according to claim 9, characterized in that, The server is connected to the baseboard management controller via a bus, and the method further includes: The validity detection results are sent to the baseboard management controller via the bus for recording, thereby generating a corresponding detection log; Based on the detection logs, alarm information is generated for the target computing module.

12. A positioning detection device for a computing module, characterized in that, Applied to a server, the server being configured with a positioning probe and a computing module with at least one node, the device includes: The trigger module is used to acquire the first presence signal of the target computing module in response to the detection of the trigger signal of the positioning probe; The positioning module is used to identify the target node of the target computing module in the server based on the first presence signal, and to send the first presence signal to the peer connector of the target computing module based on the target node. The detection module is used to perform loopback processing on the first in-situ signal based on the peer connector to obtain a second in-situ signal, and to perform validity detection on the target computing module based on the second in-situ signal.

13. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the positioning and detection method of the computing module as described in any one of claims 1 to 11 when executing the computer program.

14. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, it implements the steps of the positioning and detection method of the computing module as described in any one of claims 1 to 11.

15. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the positioning and detection method of the computing module as described in any one of claims 1 to 11.

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