Processing method and device of circuit board model mesh hole, and storage medium

Abstract

A circuit board model grid hole processing method and device and storage medium are disclosed. The method comprises: obtaining geometric information of a circuit board model, determining a contour boundary and a target hole boundary of the circuit board model; determining at least three continuous feature points on the target hole boundary according to a vertex direction representing an inside direction of the target hole boundary; dividing a plurality of first grid units in the contour boundary based on the geometric information and a preset grid shape; searching for second grid units adjacent to the feature points in the plurality of first grid units; determining a seed grid unit inside the target hole boundary from the plurality of second grid units according to the inside direction; traversing the plurality of first grid units in the contour boundary based on a region growing algorithm from the seed grid unit as a starting point, and determining a plurality of third grid units inside the target hole boundary; and deleting the plurality of third grid units to form a hole of the circuit board model. The application can improve the processing efficiency of the circuit board model grid hole.

Description

Technical Field

[0001] This disclosure relates to the field of electronic design automation technology, and in particular to a method, apparatus, and storage medium for processing grid holes in a circuit board model. Background Technology

[0002] Electronic Design Automation (EDA) is a core supporting technology for integrated circuit and printed circuit board design and manufacturing. In the electromagnetic simulation process for high-frequency electronic devices, the finite element method (FEM) typically requires mesh generation of the model. For non-computational areas such as pads and anti-pads commonly found in PCB design, the mesh generation process must handle the holes. However, as electronic product designs trend towards miniaturization and high density, complex structures containing numerous dense holes pose significant challenges to existing mesh generation technologies. Current techniques typically involve generating a global mesh and then performing traversal deletion, or relying on complex pre-marking of inner and outer boundaries to handle holes. These methods often suffer from high computational complexity, cumbersome preprocessing, and insufficient reliability in densely holed regions. Therefore, improving the efficiency and automation of mesh hole handling in complex structures is a pressing issue in the field of electromagnetic simulation for electronic design automation. Summary of the Invention

[0003] In view of this, the present disclosure provides a method, apparatus, and storage medium for processing grid holes in a circuit board model, in order to improve the processing efficiency of grid holes in a circuit board model.

[0004] In a first aspect, a method for processing mesh holes in a circuit board model is provided, comprising: acquiring geometric information of the circuit board model, determining the outline boundary of the circuit board model and the boundary of the target hole; determining at least three consecutive feature points on the boundary of the target hole based on the vertex orientation representing the inner direction of the boundary of the target hole; dividing the outline boundary into multiple first mesh units based on the geometric information and a preset mesh shape; searching for second mesh units adjacent to the feature points in the multiple first mesh units; determining seed mesh units located inside the boundary of the target hole from the multiple second mesh units based on the inner direction; traversing the multiple first mesh units within the outline boundary based on a region growing algorithm, starting from the seed mesh unit, and determining multiple third mesh units within the boundary of the target hole; deleting the multiple third mesh units to form the holes in the circuit board model.

[0005] The above method for processing mesh holes in circuit board models determines the outline boundary of the circuit board model and the boundary of the target hole. It identifies feature points based on the vertex orientation of the target hole boundary and searches for second mesh units adjacent to the feature points in the multiple first mesh units. It then determines seed mesh units by combining the target hole boundary. Subsequently, it performs region growth and strictly restricts it to the inside of the hole, avoiding invalid traversal and calculation of the massive number of external mesh units, greatly reducing computational complexity, and further improving the speed of mesh generation and processing.

[0006] Optionally, the geometric information includes a discrete set of points and a set of boundary edges of the circuit board model; determining the contour boundary and target hole boundary of the circuit board model includes: identifying closed external contours as contour boundaries based on the set of boundary edges, and identifying closed internal contours as target hole boundaries.

[0007] Optionally, the vertex representing the inner direction of the target hole boundary is oriented in a counterclockwise direction; at least three consecutive feature points are determined, including: extracting at least three consecutive vertices as feature points in a counterclockwise direction on the target hole boundary.

[0008] Optionally, the preset mesh shape is a triangle; based on geometric information and the preset mesh shape, multiple first mesh units are formed within the contour boundary, including: using discrete point sets as vertices and connecting them based on the triangular mesh shape to form multiple first mesh units within the contour boundary; wherein, the boundary of the target hole overlaps with the edge of some of the first mesh units.

[0009] Optionally, searching for a second grid cell adjacent to the feature point includes: using the middle feature point among the feature points as the center point, searching among a plurality of first grid cells for a grid cell directly connected to the center point, and using it as the second grid cell.

[0010] Optionally, starting from a seed grid cell, multiple first grid cells are traversed within the contour boundary based on a region growing algorithm, and multiple third grid cells are determined within the target hole boundary. This includes: marking multiple seed grid cells as third grid cells; searching for neighboring grid cells adjacent to the seed grid cells; determining whether the neighboring grid cells cross the target hole boundary; when the neighboring grid cells do not cross the target hole boundary, marking the neighboring grid cells as third grid cells; and continuing the search from the newly marked third grid cells until all grid cells in the target hole boundary have been marked.

[0011] Optionally, it also includes: performing topology optimization on the remaining first mesh units in the circuit board model, the topology optimization including at least one of edge swapping operation and vertex smoothing operation; determining whether the size of the first mesh unit not marked as the third mesh unit within the contour boundary conforms to the preset size standard based on the preset size standard; if it does not conform, inserting Steiner points in the first mesh unit, and performing meshing on the first mesh unit based on the Steiner points and geometric information.

[0012] Optionally, the target hole boundary includes: a first hole boundary and a second hole boundary, wherein the first hole boundary forms a first hole region, the second hole boundary forms a second hole region, and the first hole region is within the second hole region; determining seed grid cells located inside the target hole boundary according to the inner direction further includes: determining seed grid cells in the region within the second hole region and outside the first hole region; determining multiple third grid cells within the target hole boundary further includes: searching for neighboring grid cells adjacent to the seed grid cells in the second hole region; determining whether the neighboring grid cells cross the first hole boundary and the second hole boundary; when the neighboring grid cells do not cross the first hole boundary and the second hole boundary, marking the neighboring grid cells as third grid cells.

[0013] Secondly, a processing apparatus for mesh holes in a circuit board model is provided, comprising: a boundary determination unit for acquiring geometric information of the circuit board model and determining the outline boundary and target hole boundary of the circuit board model; a feature point determination unit for determining at least three consecutive feature points on the target hole boundary based on the vertex orientation representing the inner direction of the target hole boundary; a subdivision unit for dividing the outline boundary into multiple first mesh units based on geometric information and a preset mesh shape; a search unit for searching for second mesh units adjacent to the feature points among the multiple first mesh units; and determining seed mesh units located inside the target hole boundary from the multiple second mesh units based on the inner direction; a traversal unit for traversing multiple first mesh units within the outline boundary based on a region growing algorithm, starting from the seed mesh unit, and determining multiple third mesh units within the target hole boundary; and a deletion unit for deleting multiple third mesh units to form holes in the circuit board model.

[0014] Thirdly, a computer-readable storage medium is provided, on which instructions are stored, which, when read by a processor, implement the method for processing the mesh holes of the circuit board model as provided in the first aspect. Attached Figure Description

[0015] The accompanying drawings used in the description of the embodiments of this disclosure are briefly introduced below:

[0016] Figure 1A flowchart illustrating a method for processing mesh holes in a circuit board model, provided in some embodiments of this disclosure, is shown.

[0017] Figure 2 This paper shows a schematic diagram of the geometric structure of a circuit board model before meshing, provided in some embodiments of this application.

[0018] Figure 3 This paper shows a schematic diagram of the first grid cell partitioning structure provided in some embodiments of this application;

[0019] Figure 4 This illustration shows a schematic diagram of a mesh structure for determining a second mesh cell, provided in some embodiments of this application.

[0020] Figure 5 A flowchart illustrating a method for determining a third grid cell provided in some embodiments of this application is shown.

[0021] Figure 6 A schematic diagram of a mesh structure for determining a third mesh cell is shown in some embodiments of this application;

[0022] Figure 7 A schematic diagram of a mesh structure optimized by introducing Steiner points is shown in some embodiments of this application;

[0023] Figure 8 The diagram shows a schematic representation of a device for processing mesh holes in a circuit board model, provided in some embodiments of this application. Detailed Implementation

[0024] To more clearly illustrate the technical solutions in the embodiments of this disclosure, examples of implementation methods of this disclosure will be described below with reference to the accompanying drawings. The accompanying drawings described below are merely some embodiments of this disclosure. For those skilled in the art, other drawings and other implementation methods can be obtained based on these drawings without creative effort. Adjustments and improvements made without departing from the concept of this disclosure are all within the protection scope of this disclosure.

[0025] To keep the drawings simple, each figure only schematically shows the parts relevant to the embodiment, and they do not represent the actual structure of the product. In addition, for the sake of clarity and ease of understanding, some figures only schematically show parts of components with the same structure or function, and there may actually be more or fewer components with the same structure or function.

[0026] In this disclosure, unless otherwise expressly specified and limited, ordinal numbers, such as “first”, “second”, etc., are used only to distinguish and describe related objects, and should not be construed as indicating or implying the relative importance or order between related objects; furthermore, they do not represent the quantity of related objects. “Multiple” includes two or more, and other quantifiers are similar. “ / ” is used to describe the relationship between related objects, indicating an “or” relationship between them. “And / or” is used to describe the relationship between related objects, including any combination relationship between them, such as “a and / or b” including: “a alone”, “b alone”, or “a and b”. “One or more” or “at least one” of multiple objects refers to any object or any combination of multiple objects, such as “one or more of a1, a2, a3” or “at least one of a1, a2, a3” including: “a1 alone”, “a2 alone”, “a3 alone”, “a1 and a2”, “a1 and a3”, “a2 and a3”, or “a1, a2 and a3”.

[0027] Electronic design automation (EDA) technology, as the cornerstone of modern integrated circuit and electronic system design, is widely used in chip design, packaging, and signal integrity and power integrity analysis of printed circuit boards. In electromagnetic field simulation, the quality and efficiency of mesh generation in the preprocessing stage directly determine the convergence and speed of subsequent simulation calculations. In actual PCB or IC layouts, there are often areas such as solder pads and anti-pads that do not require electromagnetic field calculations; these areas appear as hole structures in the mesh generation model. When using the finite element method or finite difference time-domain method for discretization modeling, it is essential to accurately and efficiently remove the mesh within these hole regions or assign them specific properties. Currently, the technical approaches for handling such hole structures are: 1) post-processing mesh deletion method, which first generates a complete mesh covering the entire area and then uses a global traversal of the geometric positions of all elements to determine and delete elements falling into the holes; 2) internal and external boundary marking method, which predefines the internal and external boundaries and directions of the holes (e.g., outward reverse, inward forward), skipping the hole regions during the meshing process; and 3) internal point marking method, which pre-calculates a marker point within each hole and uses this as the basis for mesh removal. However, the aforementioned existing technologies exhibit significant shortcomings when faced with the increasingly prevalent high-density, multi-layered, and nested hole structures in modern PCB design. Firstly, the post-processing deletion method requires geometric inclusion judgments on a massive number of mesh cells, resulting in extremely high time complexity and a tendency to generate low-quality degenerate cells at hole boundaries, leading to a double waste of computational resources and storage space. Secondly, the inner and outer boundary marking method requires cumbersome inclusion relationship judgments and direction conventions when handling complex nested boundaries formed by multiple anti-pads, resulting in extremely complex preprocessing logic and high memory consumption. Finally, the internal point marking method faces significant challenges in automatically generating reliable internal points in areas with extremely dense holes, making recognition failures highly likely. In summary, existing technologies struggle to achieve efficient hole processing while maintaining high reliability, severely limiting the efficiency of electromagnetic simulation for large-scale complex electronic systems. Therefore, this application proposes a method, apparatus, and storage medium for processing mesh holes in circuit board models. Through a feature-point-based region localization and region growth mechanism, it achieves efficient and accurate processing of high-density hole structures while avoiding global traversal and complex preprocessing.

[0028] The following description is in conjunction with the accompanying drawings:

[0029] Please refer to Figure 1 This illustration shows a flowchart of a method for processing mesh holes in a circuit board model, provided in some embodiments of this disclosure. The method includes at least the following steps:

[0030] S110: Obtain the geometric information of the circuit board model and determine the outline boundary and target hole boundary of the circuit board model;

[0031] S120: On the boundary of the target hole, determine at least three consecutive feature points based on the orientation of the vertices that characterize the inner direction of the target hole boundary.

[0032] S130: Based on geometric information and a preset mesh shape, multiple first mesh units are formed within the contour boundary;

[0033] S140: Among multiple first grid cells, search for second grid cells adjacent to the feature point;

[0034] S150: From multiple second grid cells, determine the seed grid cell located inside the boundary of the target hole according to the inner direction;

[0035] S160: Starting from the seed grid cell, multiple first grid cells are traversed within the contour boundary based on the region growing algorithm, and multiple third grid cells are determined within the target hole boundary.

[0036] S170: Delete multiple third mesh cells to form holes in the circuit board model.

[0037] In this embodiment, design data of the circuit board model to be processed can be read. Geometric information may include the set of all points and edges constituting the circuit board model. This data can be parsed from the circuit board model file. Based on this geometric information, the system automatically identifies closed geometric paths. The outermost closed path enclosing the entire circuit board or the current simulation area can be determined as the contour boundary; while closed paths located inside the contour boundary that require hollowing out, such as the anti-pad contour used to isolate signal vias, or the metal pad contour that does not require meshing, can be determined as the target hole boundary. To achieve rapid subsequent positioning, this application may not calculate the geometric center of the hole or determine complex nesting relationships, but only extract local feature information. Vertex direction refers to the order of the vertices arranged on the boundary (e.g., counterclockwise or clockwise direction). In computational geometry, the order of vertices implicitly contains information about the region's normal vector or inward direction. For example, the direction determined by following the left-hand rule is the inward direction. On the identified target hole boundary, the system can sequentially extract at least three consecutive vertices according to preset direction rules. For instance, if the local vector relationship formed by these three vertices uniquely indicates which side is the inner side enclosed by the boundary, then this set of vertices can be identified as feature points. The preset mesh shape can be a regular or irregular shape. Regular shapes include triangles, rectangles, pentagons, etc., or regular images with curves such as circles and ellipses. Irregular shapes can be combinations of straight lines and curves, or shapes with inconsistent side lengths; no specific limitations are made here. The system can use points in the circuit board model as vertices and, with the boundary as a constraint, discretize the region within the contour boundary to generate a large number of first mesh units with preset mesh shapes, thus forming the initial mesh. It should be noted that the partitioning process here needs to ensure that each edge of the target hole boundary completely becomes an edge of some first mesh unit, and cannot be crossed or broken by the first mesh unit, thereby achieving complete restoration of the physical boundary in the mesh topology. To avoid a global traversal of the massive number of first mesh cells, a local search strategy can be employed in this step. The system uses the feature point determined in step S120 as the center and searches for all mesh cells with that feature point as their vertex within the set of first mesh cells. These first mesh cells, directly connected to the feature point through topological relationships, can be identified as second mesh cells. Among the multiple second mesh cells, some are located outside the hole (i.e., the solid area of ​​the circuit board model), while others are located inside the hole (i.e., the area in the circuit board that needs to be hollowed out). Furthermore, the inner direction can be used as a benchmark for filtering. For example, by calculating the vector formed by the centroid of the second mesh cell and the feature point, and determining the angular relationship between this vector and the boundary tangent vector (e.g., using a cross product method), it is possible to accurately identify which second mesh cells are located inside the target hole boundary and determine the second mesh cells located inside as seed mesh cells.After obtaining the seed mesh element, the region growing algorithm is initiated. Starting from the seed mesh element, it checks its adjacent mesh elements, such as those sharing an edge. If the common edge between the adjacent element and the current element is not the edge of the target hole boundary and does not cross the physical boundary, then the adjacent element is determined to belong to the hole region, marked, and added to the queue. This process is executed recursively or iteratively, like ripples spreading, until the growth path touches the target hole boundary. Finally, the set of all mesh elements traversed and marked by the region growing algorithm is identified as the third mesh element located inside the target hole boundary. Finally, the system removes all meshes marked as third mesh elements from the data structure formed by the circuit board model. After removal, the meshes that originally filled the hole region disappear, leaving blank areas, while the meshes outside the hole boundary remain unchanged, thus forming a hole structure in the mesh model that conforms to the physical design. Furthermore, the remaining meshes can be smoothed or optimized to meet simulation quality requirements. The embodiments of this application can significantly improve the computational efficiency of mesh processing and reduce the computational complexity of hole mesh processing for large-scale complex circuit layouts. By adopting a strategy of local search combined with region growing, seed cells can be determined by only a small-scale search near feature points. Subsequent region growing is strictly limited to the inside of the holes, avoiding invalid traversal and calculation of a large number of external mesh cells, thus reducing computational complexity. Especially when processing complex PCBs containing tens of thousands of high-density holes, the speed of mesh generation and processing can be further improved.

[0038] In some embodiments of this application, the geometric information includes a discrete set of points and a set of boundary edges of the circuit board model; determining the contour boundary and target hole boundary of the circuit board model includes: identifying a closed outer contour as the contour boundary based on the set of boundary edges, and identifying a closed inner contour as the target hole boundary.

[0039] Figure 2This document illustrates a schematic diagram of the geometric structure of a circuit board model before meshing, as provided in some embodiments of this application. In the above embodiments, the system reads the circuit board design file and parses it into underlying geometric topology data. The discrete point set is the set of coordinates of all geometric vertices constituting the circuit board layout; each discrete point represents the position information of a geometric corner or endpoint. The boundary edge set is the set of line segments connecting the discrete points; each edge represents an edge segment of the circuit board's physical structure. These two sets of data together constitute the skeleton of the circuit board model. Furthermore, the system can perform topology traversal based on the boundary edge set. The algorithm identifies all connected geometric paths forming closed loops by tracing the connection relationships of edges, i.e., the endpoint of one edge is the starting point of the next edge. Each closed loop represents an independent geometric object boundary. After identifying all closed loops, the system classifies them according to geometric inclusion relationships, identifying closed outer contours as contour boundaries, and marking the outermost closed path that surrounds all other geometric objects and is not surrounded by any other geometric objects as contour boundaries, corresponding to the physical outline of the circuit board or the current simulation solution domain boundary, as referenced. Figure 2 The outline boundary is formed by points 0, 1, 2, and 3. For closed paths located within these outline boundaries, they can be identified as internal contours by combining the location information of pads or cutout areas on the circuit board. These internal contours correspond to pads, anti-pads, mounting holes, or cutout areas on the circuit board. These internal closed paths requiring mesh cutout processing are marked as target hole boundaries. For example, in the pad area, refer to... Figure 2 The inner region enclosed by the contour formed by points 4, 5, 6, 7, 8, 9, and 10 shown; if the inner contour region is an antipad region, the antipad hole is determined by the contour formed by points 12, 13, 14, and 15 and the region between the contour formed by points 4 to 10.

[0040] Figure 3 This diagram illustrates a first mesh unit partitioning structure provided in some embodiments of this application. The preset mesh shape is triangular. Based on geometric information and the preset mesh shape, multiple first mesh units are formed within the contour boundary, including: using discrete point sets as vertices and connecting them based on the triangular mesh shape to form multiple first mesh units within the contour boundary; wherein the boundary of the target hole overlaps with the edges of some first mesh units. Triangular mesh units have strong geometric adaptability and can well approximate arbitrarily complex two-dimensional plane boundaries. The system uses the discrete point set obtained in step S110 as the vertices for mesh generation and connects these discrete points pairwise, such as... Figure 3The diagram illustrates the construction of a series of non-overlapping triangles that cover the entire interior region of the outline boundary. During mesh generation, the target hole boundary is composed of several line segments, and these connecting segments must form complete edges of the generated mesh without being crossed or interrupted by any triangle. Each edge of the target hole boundary completely overlaps with the edges of some first mesh cells; that is, the physical outline of the hole is also part of the mesh topology.

[0041] In some embodiments of this application, the vertex representing the inner direction of the target hole boundary is oriented in a counterclockwise direction; determining at least three consecutive feature points includes: extracting at least three consecutive vertices as feature points in a counterclockwise direction on the target hole boundary.

[0042] In computational geometry algorithms, the order of vertices on a polygon boundary implicitly determines the region's topological properties. This embodiment uses the left-hand rule as a criterion for direction determination; when an observer walks along the boundary's direction of travel, the polygon's interior region is always on the left. Based on this rule, for a closed hole region, the counter-clockwise direction is defined as the vertex orientation representing the direction inside the target hole boundary. By traversing the points on the boundary in a counter-clockwise order, the normal vector pointing to the left will necessarily point inside the hole. The vertex sequence on the target hole boundary is traversed counter-clockwise, and during the traversal, an arbitrary position is selected as the starting point, and at least three consecutive vertices are extracted sequentially, for example... Figure 3 Points 5, 6, and 7 are selected as feature points. Since they are extracted strictly in a counter-clockwise order, the polygonal line formed by the vectors of points 5 and 6, and points 6 and 7, clearly indicates the inner orientation of the hole (i.e., the left side of the polygonal line). It should be noted that these three points can be any three consecutive points on the boundary; they do not need to be corner points or special geometric points. As long as they are topologically continuous and correctly oriented, they can meet the requirements for subsequent seed unit positioning. This application utilizes simple geometric conventions to achieve rapid and unique determination of the inner orientation of a hole. By presetting a counter-clockwise direction as the inner orientation, complex global geometric analysis is unnecessary to determine which side is the inside of the hole. Simply reading three points in a counter-clockwise order allows for the unique determination of the inner orientation of the hole using low-cost calculations such as vector cross products. This simplifies the data preprocessing logic and ensures rapid determination of the inner position of the hole when processing holes of various shapes (convex polygons, concave polygons, and even self-intersecting polygons).

[0043] In some embodiments of this application, searching for a second grid cell adjacent to a feature point includes: using the middle feature point among the feature points as the center point, searching among a plurality of first grid cells for a grid cell directly connected to the center point, and using it as the second grid cell.

[0044] The three consecutive feature points (e.g., points 5, 6, and 7) determined in step S120 constitute a segment of the broken line of the target hole boundary. Therefore, the middle feature point (i.e., point 6) located in the middle of the sequence can be selected as the center point of this search. The reason for selecting the middle point is that this point is the common vertex of the two boundary edges, which can most accurately reflect the local corner features and inner direction. Among the multiple first mesh cells that have been generated, all mesh cells directly connected to this center point are searched. Figure 4 This illustration shows a schematic diagram of a mesh structure for determining a second mesh cell according to some embodiments of this application. If point 6 is an intermediate feature point, the system will search for all triangular cells with point 6 as a vertex, thereby forming... Figure 4 Multiple second grid cells, such as cells S1, S2, S3, S4, S5, S6, and S7, enclosed by a dashed line, surround point 6, forming a set of second grid cells. These grid cells are a candidate set of potential seed grid cells. Subsequent steps only need to judge these few limited cells, without traversing the entire grid. By determining the second grid cells, the time complexity of the algorithm can be reduced, enabling fast localization. After determining multiple second grid cells, the seed grid cells located inside the boundary of the target hole are determined by combining the aforementioned inner direction. For example, cells S1, S2, and S7 can be determined as seed grid cells. Unlike this application, existing technologies typically require traversing tens of thousands of grid cells to determine their location, with the computational load increasing linearly or quadratically with the grid size. This application, however, selects an intermediate feature point as an anchor point and utilizes the topological connectivity of the grid, requiring only a search of a very small number of neighboring grid cells around the point to lock in the candidate range. This localized search strategy narrows the search scope from the global domain to the neighborhood of a single point, making the computation time for locating seed grid cells negligible and no longer affected by the total number of grids, thus significantly improving the running efficiency when processing large-scale complex circuit board models.

[0045] In some embodiments of this application, starting with a seed mesh cell, multiple first mesh cells are traversed within the contour boundary based on a region growing algorithm, and multiple third mesh cells are determined within the target hole boundary. Figure 5 A flowchart illustrating a method for determining a third grid cell according to some embodiments of this application is shown. The method includes:

[0046] S510: Mark multiple seed grid cells as third grid cells;

[0047] S520: Search for neighboring grid cells that are adjacent to the seed grid cell;

[0048] S530: Determine whether a neighboring mesh cell crosses the target hole boundary;

[0049] S540: When a neighboring mesh cell does not cross the target hole boundary, mark the neighboring mesh cell as the third mesh cell;

[0050] S550: Continue the search starting from the newly marked third grid cell until all grid cells in the target hole boundary are marked.

[0051] Figure 6 This illustration shows a schematic diagram of a mesh structure for determining a third mesh cell, provided in some embodiments of this application. In the above embodiments, the third mesh cell refers to the set of meshes located inside the boundary of the target hole and ultimately requiring an operation (such as deletion). Therefore, initialization marking can be performed first, for example, by setting... Figure 4 Units S1, S2, and S7 are labeled as units T2, T3, and T1, respectively. Since the seed grid units were identified as being located inside the target hole boundary through geometric judgment of feature points and inner directions in the preceding step S150, these seed grid units are themselves part of the hole region and can be directly identified as the first batch of third grid units. Taking a currently labeled third grid unit (initially a seed grid unit), and using the topological connectivity of the grid, all other directly adjacent first grid units are found; these units are called neighboring grid units. Determining whether a neighboring grid unit crosses the target hole boundary is the core criterion of the region growing algorithm. This can be done by checking the common edge between the current unit and its neighboring units. If the common edge is part of the target hole boundary, crossing this edge means crossing out of the hole region. If the common edge is not the target hole boundary, it means there is no physical isolation between the two units; they are in the same connected region (i.e., both inside the hole). If the result is no crossing (i.e., the common edge is not a boundary edge), then the neighboring grid unit is also determined to be inside the target hole boundary. At this point, it can be marked as a third grid cell for subsequent searches of its neighbors. If the result is a crossing (i.e., encountering a boundary edge), growth in that direction stops, and the neighbor is not marked. This process is recursive or iterative, continuously selecting newly marked third grid cells from the set of third grid cells and repeating steps S520 to S540. As the algorithm runs, the marked region spreads outward from the seed point like ripples. When all growth paths in all directions touch the boundary of the target hole and are blocked, the search terminates, thus forming... Figure 6 The elements T1, T2, T3, T4, T5, T6, and T7 are enclosed by double-dotted lines. At this point, the set of all marked mesh elements represents the entire set of mesh elements encompassed within the target hole boundary.

[0052] In some embodiments of this application, the target hole boundary includes: a first hole boundary and a second hole boundary, wherein the first hole boundary forms a first hole region, the second hole boundary forms a second hole region, and the first hole region is within the second hole region; determining a seed grid cell located inside the target hole boundary according to the inner direction further includes: determining a seed grid cell in the region inside the second hole region and outside the first hole region; determining a plurality of third grid cells within the target hole boundary further includes: searching for neighboring grid cells adjacent to the seed grid cells in the second hole region; determining whether the neighboring grid cells cross the first hole boundary and the second hole boundary; when the neighboring grid cells do not cross the first hole boundary and the second hole boundary, marking the neighboring grid cells as third grid cells.

[0053] In PCB design, anti-pads are typically represented as an internal metal pad preserved within a large insulating area. Current techniques using simple area filling can easily and mistakenly delete the necessary internal island as well. (Continue to refer to...) Figure 6 This application can process holes in circuit board models with nested structures, such as anti-pad structures. In this case, the target hole boundary consists of two closed paths. The second hole boundary is a closed contour formed by connecting external node sequences, such as points 4, 5, 6, 7, 8, 9, 10, and 11, which encloses a larger second hole region (corresponding to the overall contour of the anti-pad structure). The first hole boundary is located inside the second hole region and is a closed contour formed by connecting node sequences 12, 13, 14, and 15. It encloses a smaller first hole region (corresponding to the metal pad or island at the center of the anti-pad). The area to be processed is a ring-shaped interlayer region located within the second hole boundary and outside the first hole boundary. The mesh cells within this region (i.e....) Figure 6The targets marked T1 to T12 are those to be deleted in this operation. First, feature points, such as points 6, 7, and 8, are extracted on the boundary of the second hole, and the inner direction is determined according to a counter-clockwise direction. When searching for seed cells, the system performs a dual-judgment logic: first, it finds candidate cells located inside the boundary of the second hole (e.g., T1); second, it ensures that the cell is located outside the boundary of the first hole. Since region growing proceeds from the outer circle to the inner circle, generally, as long as the selected seed grid cell is adjacent to the outer boundary and inside, it satisfies the condition of being within the second region and outside the first region. Therefore, cells T1, T2, and T3 can be determined as seed grid cells, and the region growing algorithm is started starting with these seed grid cells. When traversing neighboring grid cells, a stricter boundary crossing judgment is performed, checking whether the common edge between the neighboring grid cell and the current grid cell belongs to the first hole boundary or the second hole boundary. Searching from cell T3 downwards and to the left, cell T4 is encountered. The common edge between cell T4 and cell T3 (the line segment formed by points 5 and 13) is an internal connection, not crossing any boundaries, thus marking it as the third mesh cell. Continuing the search, when the upper edge of T1 (the line segment formed by points 6 and 7) is found, this edge belongs to the second hole boundary and is considered a crossing, stopping outward growth. When the left side of T2 (the line segment formed by points 14 and 15) is found, this edge belongs to the first hole boundary and is considered a crossing, stopping inward growth. This means the algorithm will not enter the first hole region, i.e., it will not select the area enclosed by points 12 to 15. Through the above process, all mesh cells located in the mezzanine region (i.e., cells T1 to T12) are successfully marked and identified as the third mesh cells. Finally, a deletion operation is performed, removing cells T1 to T12, thus forming a ring-shaped void in the mesh model, i.e., the anti-pad region, while preserving the central pad island and the surrounding circuit board entity. This application can accurately perform hollowing-out operations on complex nested structures such as anti-pads. Existing technologies often require complex Boolean subtraction operations when processing such nested graphics, resulting in huge computational costs and a high risk of errors. This application can remove only the annular mesh between the two boundaries, while strictly protecting the first hole area inside from being affected, thereby accurately restoring the physical topology of the circuit board. It eliminates the need for complex Boolean operations and completes the identification and extraction of complex nested regions at a lower computational cost, making it particularly suitable for processing high-density BGA package areas containing thousands of anti-pads.

[0054] In some embodiments of this application, the method further includes: performing topology optimization on the remaining first mesh cells in the circuit board model, the topology optimization including at least one of edge swapping operation and vertex smoothing operation; determining whether the size of the first mesh cell not marked as the third mesh cell within the contour boundary conforms to the preset size standard based on the preset size standard; if it does not conform, inserting Steiner points in the first mesh cell, and performing mesh division on the first mesh cell based on the Steiner points and geometric information.

[0055] After deleting mesh cells inside holes, the mesh near the hole boundaries may exhibit shape distortions, such as elongated stripe cells or poor connectivity. To improve cell quality, topology optimization can be performed on the remaining first mesh cells, i.e., the circuit board entity mesh that was not deleted. Edge swapping checks the quadrilaterals formed by adjacent triangle pairs; if swapping their diagonals increases the minimum interior angle, then edge swapping is performed. This helps eliminate elongated triangles, making the mesh more equilateral. Vertex smoothing fine-tunes the positions of vertices within the mesh while maintaining topological connectivity; for example, Laplacian smoothing moves vertices to the geometric center of their neighboring nodes. These two operations can be performed individually or iteratively until the mesh's geometric quality metrics, such as aspect ratio and skewness, reach a preset threshold. Figure 7 This diagram illustrates a mesh structure optimized by introducing Steiner points, as provided in some embodiments of this application. When optimizing mesh size based on Steiner points, electromagnetic simulations typically have strict requirements on mesh size; for example, the mesh edge length must be less than a certain proportion of the electromagnetic wave wavelength. In this case, based on a preset size standard, the system traverses the first mesh cells within the contour boundary that are not marked as the third mesh cell to determine if their geometric dimensions are too large. If the standard is not met, and the mesh cell size is too large, affecting simulation accuracy, Steiner points can be inserted inside or on the edge of the mesh cell. Based on the newly inserted Steiner points and the original geometric vertices, the system re-divides the first mesh cells in that local area. Steiner points are neither original geometric vertices nor boundary intersections, but rather auxiliary points artificially added to improve mesh quality. This process increases the mesh density, ensuring that its size meets the simulation's spatial resolution requirements.

[0056] Figure 8The diagram illustrates a schematic of a processing apparatus for a circuit board model mesh hole in some embodiments of this application. The circuit board model mesh hole processing apparatus 800 includes: a boundary determination unit 810, used to acquire geometric information of the circuit board model and determine the outline boundary and target hole boundary of the circuit board model; a feature point determination unit 820, used to determine at least three consecutive feature points on the target hole boundary based on the vertex orientation representing the inner direction of the target hole boundary; a subdivision unit 830, used to divide the outline boundary into multiple first mesh units based on geometric information and a preset mesh shape; a search unit 840, used to search for second mesh units adjacent to the feature points among the multiple first mesh units; and to determine seed mesh units located inside the target hole boundary from the multiple second mesh units based on the inner direction; a traversal unit 850, used to traverse the multiple first mesh units within the outline boundary starting from the seed mesh unit, based on a region growing algorithm, and to determine multiple third mesh units within the target hole boundary; and a deletion unit 860, used to delete the multiple third mesh units to form holes in the circuit board model.

[0057] The above division of units is merely a logical functional division. In actual implementation, they can be fully or partially integrated into a single physical entity, or they can be physically separated. Furthermore, these units can be implemented by a processor calling software; for example, a signal processing device includes a processor coupled to memory, which stores instructions. The processor calls the instructions stored in memory to implement any of the above-mentioned circuit board model mesh hole processing methods or to implement the functions of each unit. The processor can be, for example, a general-purpose processor, such as a CPU, and the memory can be memory within a cross-platform acquisition device or memory outside of a cross-platform acquisition device. Alternatively, these units can be implemented as hardware circuits. The functions of some or all units can be implemented through the design of the hardware circuit, which can be understood as one or more processors. For example, the hardware circuit includes an application-specific integrated circuit (ASIC), which implements the functions of some or all units by designing the logical relationships between the components within the circuit. Another example is that the hardware circuit can be implemented using a programmable logic device (PLD), which can include a large number of logic gates. The logical relationships between the logic gates are configured through a configuration file, thereby implementing the functions of some or all units. All units of the above circuit board model mesh hole processing device can be implemented entirely through processor calling programs, or entirely through hardware circuits, or partially through processor calling programs and the remaining parts through hardware circuits.

[0058] Based on the same technical concept, this application also provides a computer-readable storage medium storing instructions thereon, which, when read by a processor, implement the method for processing grid holes in a circuit board model as provided in the above embodiments.

[0059] In the above embodiments, the descriptions of each embodiment have their own emphasis. Parts not described in detail or in a particular embodiment can be referred to in the relevant descriptions of other embodiments. Furthermore, the above embodiments can be freely combined as needed.

Claims

1. A method for processing mesh holes in a circuit board model, characterized in that, include: Obtain the geometric information of the circuit board model, and determine the outline boundary and target hole boundary of the circuit board model; On the boundary of the target hole, at least three consecutive feature points are determined based on the orientation of the vertices that characterize the inner direction of the target hole boundary; Based on the geometric information and the preset mesh shape, multiple first mesh units are formed within the contour boundary, including: the geometric information includes a discrete point set and a boundary edge set of the circuit board model; the preset mesh shape is a triangle; the discrete point set is used as vertices and connected based on the triangular mesh shape to form multiple first mesh units within the contour boundary; wherein, the boundary of the target hole overlaps with the edge of a portion of the first mesh unit; Among the plurality of first grid cells, search for a second grid cell adjacent to the feature point; From a plurality of second grid cells, a seed grid cell located inside the boundary of the target hole is determined according to the inner direction; Starting from the seed mesh unit, multiple first mesh units are traversed within the contour boundary based on the region growing algorithm, and multiple third mesh units are determined within the target hole boundary; Multiple third grid cells are deleted to form holes in the circuit board model.

2. The method for processing mesh holes in a circuit board model according to claim 1, characterized in that, Determining the outline boundary and target hole boundary of the circuit board model includes: Based on the boundary edge set, a closed outer contour is identified as the contour boundary, and a closed inner contour is identified as the target hole boundary.

3. The method for processing mesh holes in a circuit board model according to claim 2, characterized in that, The vertex representing the inner direction of the target hole boundary is oriented in a counterclockwise direction; The determination of at least three consecutive feature points includes: extracting at least three consecutive vertices as feature points in a counterclockwise direction on the boundary of the target hole.

4. The method for processing mesh holes in a circuit board model according to claim 3, characterized in that, The search for the second grid cell adjacent to the feature point includes: Using the middle feature point among the feature points as the center point, search for the grid cell directly connected to the center point among the multiple first grid cells, and use it as the second grid cell.

5. The method for processing mesh holes in a circuit board model according to claim 4, characterized in that, Starting from the seed mesh unit, the process involves traversing multiple first mesh units within the contour boundary using a region growing algorithm, and determining multiple third mesh units within the target hole boundary, including: The plurality of seed grid cells are labeled as the third grid cell; Search for neighboring grid cells that are adjacent to the seed grid cell; Determine whether the neighboring mesh cell crosses the boundary of the target hole; When the neighboring grid cell does not cross the boundary of the target hole, the neighboring grid cell is marked as the third grid cell; The search continues from the newly marked third grid cell until all grid cells in the target hole boundary have been marked.

6. The method for processing mesh holes in a circuit board model according to claim 5, characterized in that, Also includes: Topology optimization is performed on the remaining first mesh cells in the circuit board model, the topology optimization including at least one of edge swapping operation and vertex smoothing operation; Based on a preset size standard, determine whether the size of the first grid cell within the contour boundary that is not marked as the third grid cell conforms to the preset size standard; If the conditions are not met, a Steiner point is inserted into the first grid cell, and the first grid cell is meshed based on the Steiner point and the geometric information.

7. The method for processing mesh holes in a circuit board model according to claim 5, characterized in that, The target hole boundary includes: a first hole boundary and a second hole boundary, wherein the first hole boundary forms a first hole region, the second hole boundary forms a second hole region, and the first hole region is within the second hole region; The step of determining the seed mesh cell located inside the boundary of the target hole according to the inner direction further includes: The seed grid cell is defined within the second hole region and outside the first hole region; The step of determining multiple third grid cells within the boundary of the target hole also includes: In the second hole region, search for the neighboring grid cells adjacent to the seed grid cell; Determine whether the neighboring grid cell crosses the boundary of the first hole and the boundary of the second hole; When the neighboring grid cell does not cross the first hole boundary and the second hole boundary, the neighboring grid cell is marked as the third grid cell.

8. A device for processing mesh holes in a circuit board model, characterized in that, include: A boundary determination unit is used to acquire the geometric information of the circuit board model and determine the contour boundary and target hole boundary of the circuit board model; The feature point determination unit is used to determine at least three consecutive feature points on the boundary of the target hole based on the orientation of the vertices that characterize the inner direction of the boundary of the target hole. A partitioning unit is used to divide the contour boundary into multiple first mesh units based on the geometric information and a preset mesh shape, including: the geometric information includes a discrete point set and a boundary edge set of the circuit board model; the preset mesh shape is a triangle; the discrete point set is used as vertices and connected based on the triangular mesh shape to form multiple first mesh units within the contour boundary; wherein the boundary of the target hole overlaps with the edge of a portion of the first mesh unit; The search unit is configured to search for a second grid cell adjacent to the feature point among the plurality of first grid cells; and to determine a seed grid cell located inside the boundary of the target hole from among the plurality of second grid cells according to the inner direction. The traversal unit is used to traverse multiple first grid units within the contour boundary based on the region growing algorithm, starting from the seed grid unit, and to determine multiple third grid units within the target hole boundary. A deletion unit is used to delete multiple of the third grid units to form holes in the circuit board model.

9. A computer-readable storage medium, characterized in that, It stores instructions that, when read by a processor, implement the method for processing grid holes in a circuit board model as described in any one of claims 1 to 7.

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