2.5-dimensional core particle system static voltage drop prediction-oriented example generation method and prediction method
By generating circuit netlist files and data grids covering different parameter combinations, and combining a dual U-Net network architecture and attention mechanism, the problems of data scarcity and model architecture mismatch in voltage drop prediction in 2.5D core systems are solved, and high-precision voltage drop distribution prediction is achieved.
Patent Information
- Application Number
- CN202511646762.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-11
- Publication Date
- 2026-02-27
AI Technical Summary
Existing neural network-based voltage drop prediction methods suffer from several problems when dealing with 2.5-dimensional core-particle systems. These problems include the model's inability to effectively capture the voltage drop coupling effect between layers, mismatch between model architecture and data characteristics, and scarcity of training data, resulting in insufficient prediction accuracy and weakened generalization ability.
By identifying the key electrical parameters affecting static voltage drop and their value ranges, a circuit netlist file and initial data grid covering different parameter combinations are generated. The grid refinement and data filling are used to align the data of the adapter board and the core, a large-scale and diverse training dataset is constructed, and a dual U-Net network architecture is used for voltage drop prediction. An attention mechanism is used to improve the efficiency of feature utilization.
It achieves complete prediction of voltage drop distribution in 2.5D core-particle systems, significantly improving prediction accuracy and generalization ability. It can effectively capture the voltage drop coupling effect between the core-particle layer and the transition plate layer, overcoming the limitations of traditional single models.
Smart Images
Figure CN121580925A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application belongs to the technical field of integrated circuits, and particularly relates to an example generation method and a prediction method for static voltage drop prediction of a 2.5-dimensional chiplet system. BACKGROUND
[0002] In recent years, with the rise of chiplet technology, especially after the establishment of the UCIe industry alliance and the introduction of the standardized interconnection protocol, 2.5-dimensional chiplet integrated circuits have been widely used in high-performance computing fields such as artificial intelligence and vehicle chips. Compared with traditional 2-dimensional system integrated circuits, 2.5-dimensional chiplet systems realize high-density interconnection between chiplets through silicon interposers, which makes the power integrity, especially the static voltage drop (IR-Drop) problem particularly complex. The voltage drop not only exists in the horizontal direction, but also must consider the coupling effect of the vertical direction through the interposer, micro-bump and other multi-dimensional paths. The aggravation of system heat further worsens the problem.
[0003] In the process of technological evolution, artificial intelligence-based prediction methods, especially convolutional neural networks (CNN), have been tried for voltage drop prediction to accelerate the design process. Among them, image-to-image prediction architectures such as U-Net have attracted attention due to their effectiveness in pixel-level prediction tasks. However, existing neural network-based voltage drop prediction methods face significant technical bottlenecks when dealing with 2.5-dimensional chiplet systems, making them difficult to be effectively applied in actual engineering, which is specifically reflected in the following aspects: First, the existing model has a fundamental limitation in dimension when dealing with voltage drop prediction of 2.5-dimensional chiplet systems. The current mainstream model is based on a two-dimensional neural network architecture, and its inherent data processing dimension and feature extraction mechanism cannot effectively capture the cross-level voltage drop coupling effect between the chiplet layer and the interposer layer. This leads to the fact that the prediction result cannot fully and accurately reflect the global voltage drop distribution in the actual 2.5-dimensional chiplet system, and there is a ceiling in the prediction accuracy.
[0004] Second, there is a serious mismatch between the existing model architecture and the data characteristics of the voltage drop prediction task. The widely used U-Net-like architecture has a core design paradigm of single-input image to single-output image mapping. However, a single image input cannot fully represent these complex associated information, resulting in insufficient model prediction accuracy. Moreover, the voltage drop hotspot map usually exhibits high sparsity in spatial distribution, leading to low model prediction efficiency and severe detail loss, limiting the model's engineering practical value.
[0005] Third, the scarcity of training data seriously restricts the performance of the model. The effective training of neural networks depends on a large amount of high-precision data. However, for emerging 2.5-dimensional chip integrated circuits, it is extremely difficult and costly to obtain sufficient and high-precision measured voltage drop data. The scarcity of data severely limits the size and diversity of the training data set, making it difficult for the model to fully learn the deep features of the voltage drop under complex 2.5-dimensional structures, and easily leading to model overfitting, weakening of generalization ability and limitation of prediction accuracy. The above-mentioned dimensionality limitation and architecture mismatch problem is further magnified.
[0006] Therefore, there is an urgent need in the art for an example generation and prediction method that can effectively generate training data and overcome the above-mentioned architecture mismatch problem for 2.5-dimensional chip integrated circuits. SUMMARY
[0007] In order to solve the above-mentioned problems existing in the prior art, the present application provides an example generation method and a prediction method for static voltage drop prediction of a 2.5-dimensional chip system.
[0008] The technical problem to be solved by the present application is solved by the following technical scheme: In a first aspect, the present application provides an example generation method for static voltage drop prediction of a 2.5-dimensional chip system, comprising: Step S1: determining the key electrical parameters affecting the static voltage drop and their value ranges; Step S2: generating circuit netlist files and initial data grids covering different parameter combinations according to the value ranges of the key electrical parameters and the positions of the randomly generated chiplets; the initial data grids include adapter plate data grids and chiplet data grids of each chiplet; the grids of the chiplet data grids are used to store the parameters of the chiplet PDN units; the grids of the adapter plate data grids are used to store the parameters of the adapter plate PDN units; Step S3: for the initial data grid under each parameter combination, according to the size ratio of the adapter plate PDN unit corresponding to the adapter plate data grid and the chiplet PDN unit corresponding to the chiplet data grid, the adapter plate data grid is refined and filled with data to align the data granularity of the adapter plate data grid and the chiplet data grid, and the aligned adapter plate data grid is obtained; Step S4: generating an input data grid according to the aligned adapter plate data grid, the chiplet data grid of each chiplet and the positions of the chiplets; Step S5: obtaining the chiplet voltage drop and the adapter plate voltage drop through circuit simulation according to the circuit netlist file as the true value data during training; storing the input data grid, the circuit netlist file and the true value data in association to obtain an example for static voltage drop prediction; Step S6: Repeat steps S3-S5 to batch generate cases.
[0009] Optionally, the key electrical parameters include: core PDN unit DC resistance, adapter plate PDN unit DC resistance, core PDN unit size, adapter plate PDN unit size, core overall size, adapter plate overall size, micro solder ball resistance and layout density, C4 solder ball resistance and layout density, system power supply voltage and working current load.
[0010] Optionally, the parameters of the core PDN unit include working current load, core PDN unit DC resistance and core effective power distance; the parameters of the adapter plate PDN unit include adapter plate PDN unit DC resistance and adapter plate effective power distance.
[0011] Optionally, the core effective power distance is the sum of Manhattan distances from the grid storing the parameters of the core PDN unit to all micro solder balls; the adapter plate effective power distance is the sum of Manhattan distances from the grid storing the parameters of the adapter plate PDN unit to all C4 solder balls.
[0012] Optionally, for the initial data grid under each parameter combination, the adapter plate data grid is refined and filled with data according to the size ratio of the adapter plate PDN unit corresponding to the adapter plate data grid and the core PDN unit corresponding to the core data grid, including: For the initial data grid under each parameter combination, the size ratio of the adapter plate PDN unit corresponding to the adapter plate data grid and the size of the core PDN unit corresponding to the core data grid is calculated; Based on the ratio coefficient, each grid in the adapter plate data grid is refined into sub-grids, and the parameter value stored in the grid is copied and filled into the refined sub-grids; wherein, and determined by the ratio coefficient.
[0013] Optionally, the input data grid is generated according to the aligned adapter plate data grid, the core data grid of each core, and the position of each core, including: According to the actual physical position of each core, the parameters of the core PDN unit in the core data grid are mapped to the corresponding area of the adapter plate data grid, and the parameters of the core PDN unit are assigned a value of 0 in the area of the adapter plate data grid that is not mapped, to obtain the input data grid.
[0014] Optionally, the positions of the randomly generated cores do not overlap with each other.
[0015] The example generation method for static voltage drop prediction of the 2.5-dimensional chiplet system provided by the application can automatically realize parameter permutation and combination and random generation of chiplet positions by extracting key electrical parameters affecting static voltage drop and establishing the value range of the key electrical parameters, and can quickly construct a large-scale and diversified training data set under the premise of ensuring physical rationality, systematically solving the problem of scarcity of training data for static voltage drop prediction of the 2.5-dimensional chiplet system, and providing sufficient data support for subsequent model training. Moreover, in view of the inherent difference between the chiplet and the PDN unit in size, the application proposes a mesh subdivision scheme based on a size ratio coefficient, converts the adapter board data to the same size reference as the chiplet data, realizes accurate alignment of the adapter board data and the chiplet data, and enables the two-dimensional neural network to simultaneously process data from different physical levels and effectively capture the cross-level voltage drop coupling effect between the chiplet layer and the adapter board layer.
[0016] In a second aspect, the application provides a prediction method for static voltage drop prediction of a 2.5-dimensional chiplet system, comprising: obtaining an input data grid of a 2.5-dimensional chiplet system to be predicted; processing the input data grid into a multi-channel input feature map; simultaneously inputting the multi-channel input feature map into a pre-trained first U-Net network and a second U-Net network, so that the first U-Net network outputs a predicted chiplet static voltage drop distribution map, and the second U-Net network outputs a predicted adapter board voltage drop distribution map; the first U-Net network and the second U-Net network are trained in the following manner: generating an example for training by using the above example generation method; simultaneously inputting the input data grid in the example into the first U-Net network and the second U-Net network in training; using the chiplet voltage drop true value data in the example as the supervision signal of the first U-Net network in training, using the adapter board voltage drop true value data in the example as the supervision signal of the second U-Net network in training, and training the first U-Net network and the second U-Net network in training respectively.
[0017] Optionally, the input data grid comprises a plurality of grids, and each grid stores a plurality of parameters, and the parameter items stored in all grids are the same; processing the input data grid into a multi-channel input feature map comprises: forming a two-dimensional matrix according to each parameter stored in the input data grid, to obtain a plurality of two-dimensional matrices; A multi-channel feature map is formed according to the plurality of two-dimensional matrices; wherein the multi-channel and the plurality of two-dimensional matrices are one-to-one corresponding.
[0018] Optionally, the first U-Net network and the second U-Net network are both U-Net networks with an attention mechanism added to the skip connection between the encoder and the decoder of the U-Net network in the form of an attention gate.
[0019] The prediction method for 2.5-dimensional chip system static voltage drop prediction provided by the present application constructs a large-scale, high-confidence training set through the above-mentioned example generation method, so that the model can fully learn the complex voltage drop characteristics under the 2.5-dimensional chip system, thereby significantly improving the prediction accuracy and generalization ability; the present application adopts a double-model architecture of shared input and separate supervision, so that the two models learn the parameter information of the chip and the adapter board through shared input, and focus on the voltage drop characteristics of their respective levels through separate supervision. This design enables the model to accurately capture the voltage drop coupling effect between the chip and the adapter board, thereby realizing complete prediction of the voltage drop distribution of the 2.5-dimensional system and overcoming the limitation of traditional single models that can only predict local voltage drop.
[0020] The present application will be further described in detail below with reference to the accompanying drawings and the present application. BRIEF DESCRIPTION OF DRAWINGS
[0021] Figure 1 is a flowchart of the example generation method for 2.5-dimensional chip system static voltage drop prediction provided by the embodiment of the present application; Figure 2 is a schematic diagram of a chip PDN unit in the example generation method for 2.5-dimensional chip system static voltage drop prediction provided by the embodiment of the present application; Figure 3 is a schematic diagram of the adapter board PDN unit refined according to the size ratio in the embodiment of the present application; Figure 4 is a flowchart of the prediction method for 2.5-dimensional chip system static voltage drop prediction provided by the embodiment of the present application; Figure 5 is a structural schematic diagram of the U-Net network in the prediction method for 2.5-dimensional chip system static voltage drop prediction provided by the embodiment of the present application; Figure 6 is a schematic diagram of model training in the prediction method for 2.5-dimensional chip system static voltage drop prediction provided by the embodiment of the present application. DETAILED DESCRIPTION
[0022] The present application will be further described in detail below with reference to the accompanying drawings and the present application.
[0023] In order to overcome the problems that the existing neural network-based voltage drop prediction method cannot effectively capture the inter-level voltage drop coupling effect, the model architecture and data characteristics are mismatched, and the model training data is scarce when facing a 2.5-dimensional chip system, the embodiment of the present application provides an example generation and prediction method for static voltage drop prediction of a 2.5-dimensional chip system.
[0024] Firstly, the example generation method for static voltage drop prediction of a 2.5-dimensional chip system provided by the embodiment of the present application is described in detail. Referring to Figure 1 The method comprises the following steps: Step S1: Determine the key electrical parameters affecting the static voltage drop and their value range.
[0025] Specifically, the power distribution network (PDN) of the 2.5-dimensional chip integrated circuit is cooperatively designed, and by analyzing the process manual, technical report and related research literature, the key electrical parameters affecting the voltage drop and their reasonable value range are systematically determined, laying a foundation for subsequent automatic example generation.
[0026] Exemplarily, the key electrical parameters affecting the static voltage drop of the 2.5-dimensional chip system can include: chip PDN unit DC resistance, adapter plate PDN unit DC resistance, size of chip PDN unit, size of adapter plate PDN unit, overall size of chip, overall size of adapter plate, resistance and layout density of micro solder balls, resistance and layout density of C4 solder balls, system power supply voltage and working current load. Here, the value range of each key electrical parameter is determined by the following way: Firstly, the chip PDN unit DC resistance and the adapter plate PDN unit DC resistance are determined. Based on the research on multiple related research literatures, technical reports and semiconductor process manuals, the DC resistance characteristics of the PDN units on the adapter plate and the chip are analyzed. By summarizing the existing research and measured data, the typical values and common value ranges of the chip PDN unit DC resistance and the adapter plate PDN unit DC resistance are obtained, so as to ensure that the selected resistance parameters conform to the current process level and are consistent with the actual design practice.
[0027] Secondly, the size specifications of the chip and the adapter plate are standardized, which specifically includes: The size of the core grain PDN unit and the size of the adapter plate PDN unit are determined: according to the explicit constraints of the physical design rules in the relevant process manual, technical report and relevant research literature, the reasonable size range of the adapter plate PDN unit and the core grain PDN unit (i.e. the basic unit constituting the PDN grid) is determined, and the selected size value must meet the minimum line width, spacing and other design rules specified in the process document. For example: the size of the adapter plate PDN unit is 100µm or 200µm, and the size of the core grain PDN unit is 2.5µm or 5.0µm.
[0028] The overall size of the core grain and the overall size of the adapter plate are determined: the overall size of the adapter plate needs to meet the constraints of the relevant process manual and technical report; the overall size of the core grain is set by referring to the common size range of various typical functional modules (such as CPU cores, caches, AI accelerators and network on chips) in industry products, and is appropriately rounded off under the premise of meeting the design rules to approach the actual design scenario.
[0029] Then, the parameters of the micro-bumps (uBumps) connecting the core grain and the adapter plate and the C4 bumps (C4 Bumps) connecting the adapter plate and the package substrate are set. Specifically, the resistance values of the micro-bumps and the C4 bumps are set by referring to the typical values provided in the relevant process manual, technical report and relevant research literature; then, the layout of the micro-bumps and the C4 bumps is planned: the layout density of the C4 bumps is uniformly divided in proportion (determined by the length of the adapter plate PDN unit and the reasonable distance of the C4 bump) according to the size of the adapter plate PDN unit, ensuring that its distribution matches the grid structure of the adapter plate PDN, forming the access point of the external power supply; the layout density of the micro-bumps is calculated and determined in proportion (determined by the length of the core grain PDN unit and the reasonable distance of the micro-bump) according to the size of the core grain PDN unit, ensuring that its distribution matches the grid structure of the core grain PDN, to achieve efficient and uniform power connection between the core grain and the adapter plate.
[0030] It can be understood that the resistance values of micro-bumps and C4 bumps of different diameters are different, for example, the typical resistance value of a micro-bump with a diameter of 10µm is 0.01909Ω, and the typical resistance value of a C4 bump with a diameter of 100µm is 0.000744Ω.
[0031] Finally, the system supply voltage and working current load are set. Here, a uniform working voltage value is set for the system, which is connected to the adapter board PDN through the aforementioned planned C4 solder balls, and further supplied to the core particles through micro solder balls. The size of the working voltage strictly follows the set value of the core voltage in the relevant process manual and technical report (for example, 0.9V, 0.75V, etc.). Then, the working current load is set: the working current load is applied to the specific nodes of the core particle PDN, and its injection position simulates the actual working scene of the chip, focusing on the specific functional area of the core particle (such as the operation unit, memory interface, etc.), which can be set by referring to the common active area of various typical functional modules. The size of the working current load is set by referring to the working current level of the relevant typical functional modules in the 2.5-dimensional integrated circuit.
[0032] The parameters selected and set by the above method jointly constitute a set of key factors that affect the voltage drop of the 2.5-dimensional integrated circuit. Their combination determines the impedance characteristics and current path of the entire power distribution network, thereby accurately controlling the distribution of the static voltage drop.
[0033] Step S2: According to the value range of the key electrical parameters and the randomly generated positions of each core particle, generate circuit netlist files and initial data grids covering different parameter combinations; the initial data grid includes an adapter board data grid and a core particle data grid of each core particle; the grid of the core particle data grid is used to store the parameters of the core particle PDN unit; the grid of the adapter board data grid is used to store the parameters of the adapter board PDN unit.
[0034] Here, the positions of the randomly generated core particles do not overlap with each other.
[0035] Specifically, according to the key electrical parameters and their value ranges determined in step S1, the circuit netlist files and initial data grids covering different parameter combinations are generated in batches through an automated script, providing a data basis for subsequent simulation and neural network training. This step specifically includes: First, the circuit netlist file and initial data grid are generated synchronously. Using a Python script, the following operations are performed in each iteration: Within the parameter range determined in step S1, a set of values is randomly selected to form an electrical parameter combination for all key electrical parameters; simultaneously, the placement positions of each core are randomly generated on the adapter board plane, ensuring that all cores meet the physical design rule of non-overlapping pairs, forming a physical layout combination; based on this electrical parameter combination and layout combination, a new circuit with different parameters is obtained, generating the corresponding HSPICE circuit netlist file and initial data grid. The initial data grid includes the adapter board data grid and the core data grids for each core. These data grids can be created in memory as a two-dimensional matrix, with each grid cell storing the parameter value corresponding to the physical grid position. Specifically, the core data grid includes multiple grids corresponding one-to-one with multiple core PDN units, each grid storing the parameters of the corresponding core PDN unit; the adapter board data grid includes multiple grids corresponding one-to-one with multiple adapter board PDN units, each grid storing the parameters of the corresponding adapter board PDN unit.
[0036] Taking PDN as an example, see Figure 2 , Figure 2 The core PDN is shown. The PDN cells in column 2 (red box in the figure) are represented using a Cartesian coordinate system, starting from the bottom left corner. The physical mesh of the PDN cells is denoted as cell (1,1), cell (1,2), and cell (...). , 1), etc. Each PDN core includes 5 nodes, denoted as (1,2), (2,1), (2,2), (2,3), and (3,2), respectively. Each node corresponds to a connection point in the circuit, and the nodes are connected by resistive elements (as shown in the figure). , , and The circuits are connected to form a basic equivalent circuit unit that characterizes the local power network.
[0037] In this invention, node (2,2) out of the five nodes is used as the connection point and output point between layers. Specifically, when C4 solder balls are connected to the PDN unit of the adapter board, they are connected to node (2,2); when micro solder balls are connected to the core and the PDN unit of the adapter board, they are connected to node (2,2); when the core PDN unit needs to simulate the application of load current, it is connected to node (2,2); during circuit simulation, the voltage of node (2,2) of each core PDN unit is used as the output voltage of that core PDN unit.
[0038] It can be understood that each grid of the die data grid stores the parameters of the die PDN unit at the corresponding position, that is, each grid stores the parameters of the die PDN unit with the corresponding row and column index. For example, the first row and the first column of the die data grid store the parameters of the die PDN unit of the cell (1, 1). Similarly, the adapter plate PDN is divided into adapter plate PDN units in the same way, and each grid in the adapter plate data grid corresponds to the parameters of the adapter plate PDN unit with the corresponding row and column index.
[0039] By adopting the PDN unit division mode shown in Figure 2 The PDN unit division mode shown in the application can ensure the accuracy of the circuit netlist generation on the one hand, and the regular structure also provides a structural basis for converting the PDN parameters into data suitable for convolutional neural network processing on the other hand.
[0040] In an optional implementation, the initial data grid can be stored in a CSV table file. At this time, the row and column indexes of the CSV table correspond to the row and column indexes of the die PDN unit or the adapter plate PDN unit, that is, the parameters of the die PDN unit of the first row and the first column of the die are stored in the cell of the first row and the first column of the CSV table. It can be understood that when the initial data grid is stored in the CSV table, since the row and column counting of the traditional CSV table is from the top left corner, when generating the CSV data, it needs to be flipped up and down to realize the position correspondence.
[0041] In the application, the parameters of the die PDN unit include the working current load, the DC resistance of the die PDN unit and the effective power supply distance of the die, and the parameters of the adapter plate PDN unit include the DC resistance of the adapter plate PDN unit and the effective power supply distance of the adapter plate. The effective power supply distance of the die is the sum of the Manhattan distances from the grid storing the parameters of the die PDN unit to all micro solder balls; the effective power supply distance of the adapter plate is the sum of the Manhattan distances from the grid storing the parameters of the adapter plate PDN unit to all C4 solder balls. Here, the DC resistance of the die PDN unit is the PDN density of the die, and the DC resistance of the adapter plate PDN unit is the PDN density of the adapter plate.
[0042] Step S3: For the initial data grid under each parameter combination, according to the size ratio of the adapter plate PDN unit corresponding to the adapter plate data grid and the die PDN unit corresponding to the die data grid, the adapter plate data grid is refined and filled to realize the data granularity alignment of the adapter plate data grid and the die data grid, and the aligned adapter plate data grid is obtained.
[0043] Specifically, due to the inherent difference in the size of the PDN unit of the core particle and the PDN unit of the adapter plate (the size of the PDN unit of the adapter plate is usually several times the size of the PDN unit of the core particle), this inherent difference in unit size will cause the adapter plate data and the core particle data to be unable to be aligned through the row and column indexes in the unified data grid representation, so that the neural network cannot accurately establish the spatial correspondence of the two kinds of data, thereby greatly affecting the accuracy of the prediction. Therefore, the present application proposes a grid subdivision scheme based on a size ratio coefficient, which converts the adapter plate data to the same physical unit size reference as the core particle data, to achieve accurate alignment of the adapter plate data and the core particle data.
[0044] Specifically, for the initial data grid under each parameter combination generated in step S2, the adapter plate data grid is refined and filled with data according to the size ratio of the adapter plate PDN unit corresponding to the adapter plate data grid and the core particle PDN unit corresponding to the core particle data grid, including: for the initial data grid under each parameter combination, calculating the size ratio of the adapter plate PDN unit corresponding to the adapter plate data grid and the size of the core particle PDN unit corresponding to the core particle data grid to determine the granularity of grid subdivision; based on the ratio coefficient, each grid in the adapter plate data grid is refined into sub-grids, and the parameter values stored in the grid are copied and filled into the refined sub-grids; wherein, and determined by the ratio coefficient. It can be understood that by expanding and filling the parameter values stored in the grid, it can be ensured that the parameter values of the PDN units in the adapter plate PDN unit region are uniformly distributed in the subdivided sub-grids.
[0045] Referring to Figure 3 , Figure 3 is a schematic diagram of refining the adapter plate PDN unit according to the size ratio in the embodiments of the present application. Among them, the 4 gray areas represent 4 core particles, the black grid represents a core particle PDN unit (also known as a core particle basic unit, Chiplet Unit Cell), and the red square represents an adapter plate PDN unit (also known as an adapter plate basic unit, Interposer Unit Cell). From Figure 3It can be seen that one adapter PDN unit corresponds to 5x5 core grain PDN units in space (i.e. one adapter PDN unit can be subdivided into 5x5 sub-units with the same size as the core grain PDN unit), but in the data grid, since both the adapter PDN unit and the core grain PDN unit correspond to one grid in the data grid, when the adapter data grid is not grid-refined, the adapter data grid and the core grain data grid cannot be directly aligned. Therefore, based on the size ratio of the adapter PDN unit and the core grain PDN unit, at the physical space level, the adapter PDN unit (red box) can be subdivided into 5x5 sub-units with the same size as the core grain PDN unit; at the data level, each grid of the adapter data grid is refined into 5x5 sub-grids, and the parameter values stored in the grid are copied and filled into the corresponding 5x5 sub-grids, so that the adapter data grid and the core grain data grid correspond to the same unit size reference, and an aligned adapter data grid is obtained.
[0046] Step S4: generating an input data grid according to the aligned adapter data grid, the core grain data grid of each core grain, and the position of each core grain.
[0047] Specifically, generating an input data grid according to the aligned adapter data grid, the core grain data grid of each core grain, and the position of each core grain includes: According to the actual physical position of each core grain, the parameters of the core grain PDN unit in the core grain data grid are mapped to the corresponding area of the adapter data grid, and the parameters of the core grain PDN unit are assigned a value of 0 in the area of the adapter data grid that is not mapped, to obtain an input data grid. It can be understood that in each grid of the input data grid, the parameters of the core grain PDN unit and the parameters of the adapter PDN unit corresponding to the position are stored, i.e. the working current load, the DC resistance of the core grain PDN unit, the effective power supply distance of the core grain, the DC resistance of the adapter PDN unit, and the effective power supply distance of the adapter.
[0048] Step S5: obtaining the core grain voltage drop and the adapter voltage drop through circuit simulation according to the circuit netlist file as the true value data during training; and storing the input data grid, the circuit netlist file, and the true value data in association to obtain an example for static voltage drop prediction.
[0049] Specifically, for each parameter combination, the corresponding circuit netlist file is input into HSPICE or a circuit simulation tool of the same type for static voltage drop simulation analysis. After the simulation is completed, the voltage values of each node on the core grain layer and the adapter layer are extracted, and two two-dimensional voltage drop distribution maps are generated according to the same coordinate system and subdivision granularity as the input data grid, which are respectively used as the core grain voltage drop true value data and the adapter voltage drop true value data for subsequent model training. Here, for example, the core grain voltage drop true value data and the adapter voltage drop true value data are respectively as follows:Figure 2 The (2, 2) node voltage of each core particle PDN unit or adapter plate PDN unit is taken as an output voltage.
[0050] Referring to the method of storing the initial data grid as a CSV table file, the core particle voltage drop true value data, the adapter plate voltage drop true value data, and the input data grid are all stored as CSV table files. Finally, each complete training example includes: a circuit netlist file, a CSV table file of the input data grid, and a CSV table file of the core particle and adapter plate voltage drop true value data obtained through simulation. To ensure the clarity and traceability of data management, a unified naming rule (for example, sharing a unique example number) can be used, and these files can be stored in the same dedicated directory. Of course, the CSV table file of the input data grid can be stored in multiple CSV table files according to each parameter.
[0051] Step S6: Repeat steps S3 to S5 to batch generate examples.
[0052] Specifically, based on the circuit netlist files and initial data grids generated in step S2, which cover different parameter combinations, steps S3 to S5 are repeatedly executed for each parameter combination to batch generate an example library with high confidence, thereby providing sufficient data support for neural network training.
[0053] The example generation method for 2.5D core particle system static voltage drop prediction provided by the present application can automatically realize the permutation and combination of parameters and the random generation of core particle positions by extracting key electrical parameters that affect the static voltage drop and establishing the value range thereof. On the premise of ensuring physical rationality, the method can quickly construct a large-scale and diversified training data set, systematically solves the problem of scarcity of training data for 2.5D core particle system static voltage drop prediction, and provides sufficient data support for subsequent model training. Moreover, in view of the inherent difference between the sizes of the core particle and the adapter plate PDN unit, the present application proposes a grid subdivision scheme based on a size proportionality coefficient, which converts the adapter plate data to the same size reference as the core particle data, realizes accurate alignment of the adapter plate data and the core particle data, and enables the two-dimensional neural network to process data from different physical levels at the same time, thereby effectively capturing the cross-level voltage drop coupling effect between the core particle layer and the adapter plate layer.
[0054] Based on the above-mentioned example generation method for 2.5D core particle system static voltage drop prediction, an embodiment of the present application further provides a prediction method for 2.5D core particle system static voltage drop prediction; see Figure 4 The prediction method comprises: Step 1: Obtain the input data grid of the 2.5D core particle system to be predicted.
[0055] Specifically, first, key electrical parameters such as the core particle PDN unit DC resistance, the adapter plate PDN unit DC resistance, and the size of the core particle PDN unit are extracted from the design file, and the effective power supply distance of the core particle and the effective power supply distance of the adapter plate are calculated to construct an initial data grid. Subsequently, based on the size ratio of the core particle PDN unit and the adapter plate PDN unit, the adapter plate data grid is refined and filled with data, and the alignment of the adapter plate data grid and the core particle data grid is realized at the data level to obtain the aligned adapter plate data grid. Finally, according to the aligned adapter plate data grid, the core particle data grid in the initial data grid, and the designed core particle position, an input data grid is generated.
[0056] Step 2: Process the input data grid into a multi-channel input feature map.
[0057] Here, the input data grid includes multiple grids, and each grid stores multiple parameters. The input data grid is processed into a multi-channel input feature map that can be directly input into the prediction model, including: forming a two-dimensional matrix for each parameter in the input data grid to obtain multiple two-dimensional matrices; forming a multi-channel feature map based on the multiple two-dimensional matrices; wherein the multi-channel corresponds one-to-one to the multiple two-dimensional matrices.
[0058] Step 3: Simultaneously input the multi-channel input feature map into the first U-Net network and the second U-Net network that have been pre-trained to make the first U-Net network output a predicted core particle static voltage drop distribution map and the second U-Net network output a predicted adapter plate voltage drop distribution map; wherein the first U-Net network and the second U-Net network have the same network structure. Here, the first U-Net network and the second U-Net network are both U-Net networks with added attention mechanisms; wherein the attention mechanisms are added to the skip connections between the encoder and the decoder of the U-Net network in the form of attention gates.
[0059] Specifically, since the U-Net network can only make predictions in a two-dimensional plane, when predicting the static voltage drop of a 2.5-dimensional core particle integrated circuit, the 2.5-dimensional core particle integrated circuit needs to be disassembled into a two-dimensional plane. Specifically, the core particle layer and the adapter plate layer that are originally stacked in the vertical direction are considered as two independent two-dimensional planes. The plane where the core particle layer is located focuses on carrying the circuit parameter distribution of the core particle itself, while the adapter plate layer represents its circuit parameter distribution on its own two-dimensional plane. However, there is a correlation between the power supply networks of the core particle and the adapter plate in the 2.5-dimensional core particle integrated circuit, and there is a voltage drop coupling effect. Therefore, in order to realize effective voltage drop prediction, the parameter information of the two two-dimensional planes needs to be input into the prediction model, and different supervision signals are used during training.
[0060] Based on the above considerations, the present invention independently constructs a first U-Net network and a second U-Net network based on the same U-Net network structure, so that the first U-Net network outputs the predicted static voltage drop distribution map of the core, and the second U-Net network outputs the predicted voltage drop distribution map of the adapter board.
[0061] For details, see Figure 5 , Figure 5 The U-Net network in the prediction method for predicting static voltage drop in 2.5D chip systems provided by an embodiment of the present invention is illustrated. For example... Figure 5 As shown, the U-Net network introduces an additional pre-convolutional layer after the input layer. This pre-convolutional layer is used to preprocess the multi-channel feature maps of the input at the channel level before passing the preprocessed feature maps to the subsequent encoder. Specifically, for each image-based input, the pre-convolutional layer contains an independent convolutional module that uses a 2×2 convolutional kernel in conjunction with the ReLU activation function.
[0062] Then, the encoder performs hierarchical downsampling on the preprocessed feature map to extract multi-scale features from local details to global semantics. The U-Net network adds attention gates to the skip connections between the encoder and decoder. Attention gates, through a dynamic weight calculation mechanism, selectively enhance important features and suppress irrelevant information. In the voltage drop prediction task, due to the high sparsity of the input data (i.e., the current value in most regions is close to zero), these low-current regions contribute very little to the final voltage drop. Attention gates can effectively suppress the influence of these low-current regions, thereby guiding the model to focus on key regions that significantly contribute to voltage drop formation and improving feature utilization efficiency.
[0063] Finally, the decoder restores the feature map resolution through upsampling and skip connections with embedded attention gates. This mechanism dynamically focuses on key feature regions in the encoder that are highly correlated with the current voltage drop point, thereby significantly improving feature utilization efficiency and prediction accuracy. Finally, a high-precision voltage drop distribution prediction map that perfectly corresponds to the input data position is output via a 1×1 convolutional layer, achieving end-to-end prediction.
[0064] make The first character in the input feature map The feature vector at each position has a dimension of . ;make Represents the corresponding gating signal in the first The feature vector at each position has a dimension of . .
[0065] Here, the attention gating function is expressed as: ; in, denotes the attention coefficient of a position, the first denotes the attention coefficient of a position, the first denotes a RELU activation function, denotes a Sigmoid activation function, and denote linear transformation weight matrices applied to and respectively, and denote bias terms, denotes another linear transformation weight vector, denotes the transpose of a matrix.
[0066] The attention mechanism can be represented as: ; wherein, is the output result of element-wise multiplication, denotes the output feature vector. The size of each feature vector reflects the importance of each feature vector.
[0067] It can be understood that the first U-Net network and the second U-Net network of the present application both adopt the U-Net network based on the attention mechanism, and through the collaborative optimization of the attention mechanism and the multi-channel input, the prediction accuracy and efficiency are significantly improved. Specifically, the attention mechanism in the U-Net network enables the model to adaptively focus on the key area of voltage drop, effectively processing the spatial sparsity characteristics of the voltage drop distribution; at the same time, the multi-channel feature map input is adopted, which completely retains the spatial distribution information of each parameter. The combination of these two technologies enables the trained prediction model to achieve high-precision prediction.
[0068] Here, the first U-Net network and the second U-Net network are trained in the following manner: First, the above example generation method is applied to generate examples for training.
[0069] Secondly, the input data grid in the example is simultaneously input into the first U-Net network and the second U-Net network.
[0070] Specifically, the data of the input data grid is directly processed into a multi-channel input feature map, or the data is read from the stored CSV table file of the input data grid and processed into a multi-channel input feature map, and then the multi-channel input feature map is input as a shared input into the first U-Net network and the second U-Net network.
[0071] Finally, the core particle voltage drop true value data in the example is taken as the supervision signal of the first U-Net network, and the adapter plate voltage drop true value data in the example is taken as the supervision signal of the second U-Net network, and the first U-Net network and the second U-Net network are trained respectively.
[0072] Referring to Figure 6 As shown in the figure, the first U-Net network and the second U-Net network both take the current distribution (i.e. working current load), the PDN density of the core particle (i.e. core particle PDN unit DC resistance), the effective distance of the voltage source of the core particle (i.e. core particle effective power distance), the PDN density of the adapter plate (i.e. adapter plate PDN unit DC resistance) and the effective distance of the voltage source of the adapter plate (i.e. adapter plate effective power distance) as shared input data, the first U-Net network takes the voltage drop of the core particle as the supervision signal, and the second U-Net network takes the voltage drop of the adapter plate as the supervision signal. That is, the input variable of the first U-Net network includes the shared input data and the voltage drop of the core particle, and the output variable of the first U-Net network is the predicted voltage drop of the core particle. The input variable of the second U-Net network includes the shared input data and the voltage drop of the adapter plate, and the output variable of the second U-Net network is the predicted voltage drop of the adapter plate. The input variable of the second U-Net network includes the shared input data and the voltage drop of the adapter plate, and the output variable of the second U-Net network is the predicted voltage drop of the adapter plate. The input variable of the second U-Net network includes the shared input data and the voltage drop of the adapter plate, and the output variable of the second U-Net network is the predicted voltage drop of the adapter plate. The input variable of the second U-Net network includes the shared input data and the voltage drop of the adapter plate, and the output variable of the second U-Net network is the predicted voltage drop of the adapter plate.
[0073] Specifically, in the model training phase, a two-stage strategy of "pre-training-fine-tuning" is adopted, and all examples are randomly divided into three independent subsets in the ratio of 7:2:1: 70% of the examples are used for model pre-training, 20% of the examples are used for fine-tuning training, and the remaining 10% of the examples are used as a test set. Through this division method, the model can fully learn the data characteristics, and the performance in actual application can be objectively evaluated.
[0074] The prediction method for 2.5-dimensional core particle system static voltage drop prediction provided by the application constructs a large-scale, high-confidence training set through the above example generation method, so that the model can fully learn the complex voltage drop characteristics under the 2.5-dimensional core particle system, thereby significantly improving the prediction accuracy and generalization ability; the application adopts a double-model architecture of shared input and separate supervision, so that the two models learn the parameter information of the core particle and the adapter plate through shared input, and focus on the voltage drop characteristics of each layer through separate supervision. This design enables the model to accurately capture the voltage drop coupling effect between the core particle and the adapter plate, thereby realizing complete prediction of the voltage drop distribution of the 2.5-dimensional system and overcoming the limitation of traditional single models that can only predict local voltage drop.
[0075] It is to be understood that the terms "first", "second", and the like, used in the description and in the claims, are used as adjectives to distinguish between similar objects, and do not necessarily have a specific order or sequence. It is to be understood that the use of such terms can be interchanged, where appropriate, to refer to similar elements of the embodiments described herein. The embodiments described in the following examples do not represent all the implementations consistent with the present application. Instead, they are merely examples consistent with some aspects of the present application.
[0076] In the description of the specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" etc. means that the specific features or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described can be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples described in the specification.
[0077] Although the present application is described herein in conjunction with various embodiments, those skilled in the art, with the benefit of the description and drawings presented herein, can understand and appreciate other variations and modifications of the disclosed embodiments without departing from the scope of the claimed application. In the description of the present application, the word "comprising" does not exclude other components or steps, "a" or "one" does not exclude a plurality, and "multiple" means two or more, unless otherwise expressly specified. In addition, some measures are described in different embodiments, but this does not mean that these measures cannot be combined to produce good results.
[0078] The above is a further detailed description of the present application in conjunction with specific preferred embodiments, and the specific implementation of the present application cannot be limited to these descriptions. For those skilled in the art, without departing from the concept of the present application, a number of simple deductions or substitutions can be made, which should be considered as falling within the scope of protection of the present application.
Claims
1. A case generation method for 2.5-dimensional core particle system static voltage drop prediction, characterized by, The method comprises the following steps: Step S1: determining key electrical parameters affecting static voltage drop and their value ranges; Step S2: generating a circuit netlist file and an initial data grid covering different parameter combinations according to the value ranges of the key electrical parameters and the positions of the individual dies; Step S3: for the initial data grid under each parameter combination, performing grid refinement and data filling on the adapter data grid according to the size ratio of the adapter PDN unit corresponding to the adapter data grid and the die PDN unit corresponding to the die data grid of the individual die, so that the adapter data grid and the die data grid are aligned in data granularity, and an aligned adapter data grid is obtained; Step S4: generating an input data grid according to the aligned adapter data grid, the die data grid of each die and the positions of the individual dies; Step S5: obtaining die voltage drop and adapter voltage drop through circuit simulation according to the circuit netlist file as true value data during training; and storing the input data grid, the circuit netlist file and the true value data in association to obtain an example for static voltage drop prediction; Step S6: repeating steps S3 to S5 to generate examples in batches.
2. The case generation method for 2.5D core system oriented static voltage drop prediction according to claim 1, wherein, The key electrical parameters include die PDN unit DC resistance, adapter PDN unit DC resistance, die PDN unit size, adapter PDN unit size, die overall size, adapter overall size, resistance and layout density of micro solder balls, resistance and layout density of C4 solder balls, system power supply voltage and working current load.
3. The example generation method for 2.5-dimensional core system oriented static voltage drop prediction according to claim 2, wherein, The parameters of the die PDN unit include working current load, die PDN unit DC resistance and die effective power distance; and the parameters of the adapter PDN unit include adapter PDN unit DC resistance and adapter effective power distance.
4. The example generation method for 2.5-dimensional core system oriented static voltage drop prediction according to claim 3, wherein, The die effective power distance is the sum of the Manhattan distances from the grid storing the parameters of the die PDN unit to all micro solder balls; and the adapter effective power distance is the sum of the Manhattan distances from the grid storing the parameters of the adapter PDN unit to all C4 solder balls.
5. The method of claim 1, wherein the 2.5-dimensional corelet system static voltage drop prediction example generation method is characterized by, For the initial data grid under each parameter combination, the grid refinement and data filling on the adapter data grid are performed according to the size ratio of the adapter PDN unit corresponding to the adapter data grid and the die PDN unit corresponding to the die data grid of the individual die, which comprises the following steps: For the initial data grid under each parameter combination, a proportional coefficient of the size of the adapter PDN unit corresponding to the adapter data grid and the size of the die PDN unit corresponding to the die data grid is calculated; Based on the scale factor, each grid in the adapter plate data grid is refined into sub-grids, and the parameter values stored in the grid are copied and filled into the refined sub-grids; wherein, and are determined by the scale factor.
6. The method of claim 1, wherein the 2.5-dimensional corelet system static voltage drop prediction example generation method is characterized by, The input data grid is generated according to the aligned adapter data grid, the die data grid of each die and the positions of the individual dies, which comprises the following steps: According to the actual physical position of each core particle, the parameters of the core particle PDN unit in the core particle data grid are mapped to the corresponding area of the adapter plate data grid, and the parameters of the core particle PDN unit are assigned a value of 0 in the area not mapped in the adapter plate data grid, to obtain an input data grid.
7. The method of claim 1, wherein the 2.5-dimensional corelet system static voltage drop prediction example generation method is characterized by, The positions of the randomly generated core particles do not overlap with each other.
8. A prediction method for 2.5-dimensional core particle system static voltage drop prediction, characterized in that, The method comprises: obtaining an input data grid of a 2.5-dimensional core particle system to be predicted; processing the input data grid into a multi-channel input feature map; simultaneously inputting the multi-channel input feature map into a first U-Net network and a second U-Net network which have been pre-trained, so that the first U-Net network outputs a predicted core particle static voltage drop distribution map, and the second U-Net network outputs a predicted adapter plate voltage drop distribution map; the first U-Net network and the second U-Net network are trained in the following way: applying the example generation method of any one of claims 1-7 to generate an example for training; simultaneously inputting the input data grid in the example into the first U-Net network and the second U-Net network in training; using the core particle voltage drop true value data in the example as the supervision signal of the first U-Net network in training, and using the adapter plate voltage drop true value data in the example as the supervision signal of the second U-Net network in training, and training the first U-Net network and the second U-Net network in training respectively.
9. The prediction method of prediction of static voltage drop for 2.5D corelet system direction according to claim 8, characterized in that, The input data grid comprises a plurality of grids, and each grid stores a plurality of parameters, and the parameters stored in all grids are the same; processing the input data grid into a multi-channel input feature map comprises: forming a two-dimensional matrix according to each parameter stored in the input data grid, to obtain a plurality of two-dimensional matrices; forming a multi-channel feature map according to the plurality of two-dimensional matrices; wherein the multi-channel corresponds to the plurality of two-dimensional matrices one by one.
10. The prediction method of claim 8, wherein the 2.5-dimensional corelet system static voltage drop prediction is predicted by, The first U-Net network and the second U-Net network are both U-Net networks with an attention mechanism; the attention mechanism is added to the skip connection between the encoder and the decoder of the U-Net network in the form of an attention gate.