Clock tree synthesis method for frequency dividing circuit

Abstract

The invention provides a clock tree synthesis method related to a frequency dividing circuit. The clock tree synthesis method comprises the following steps: step 1, selectively adding / deleting buffers on a clock line; 2, dividing an independent clock region behind an output pin of a frequency dividing circuit trigger; 3, in the newly divided clock area, a clock is created again, and an independent clock network is created; step 4, adjusting clock delay by adopting an insertiondelay command, and guiding a tool to complete clock tree balance; and step 5, completing automatic wiring of the clock circuit. On the basis of the steps, the problems that time sequence violation of a frequency dividing circuit (DIV) cannot be repaired under an original clock tree synthesis method, and power consumption is increased are solved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of digital back-end design in chip design technology, and particularly relates to a clock tree synthesis method for frequency division circuit. BACKGROUND

[0002] In the chip digital back-end design process, clock tree synthesis is a necessary step of digital back-end design. The purpose of clock tree synthesis is to build a balanced clock network. The existing clock tree synthesis steps include:

[0003] 1, deleting the original buffer on the clock line, that is, removing the clock line buffer;

[0004] 2, creating a clock tree network, that is, creating a clock tree;

[0005] 3, clock balance, that is, clock balance;

[0006] 4, clock routing, that is, clock routing.

[0007] And clock balance is a key step of clock tree generation. The tool will balance the entire clock network by using delay cells (buffer cells / paired inverter cells) according to the clock start point and the end point. The clock skew between the clock start point and each clock end point is minimized, so as to achieve the final effect of timing convergence and power consumption reduction. However, when encountering a frequency division circuit, the tool will automatically regard the functional flip-flop (FF) in the frequency division circuit and other functional flip-flops (FF) in the design as default end points and complete clock balance. As a result, the clock length between the clock start point and the functional flip-flop (FF) in the frequency division circuit becomes longer, thereby causing the problems of timing violation and power consumption increase of the frequency division circuit. SUMMARY

[0008] To solve the problems in the prior art, the present application provides a clock tree synthesis method for frequency division circuit, which prevents the functional flip-flop (FF) in the frequency division circuit from being balanced with the remaining functional flip-flops (FF) in the design design by using a specific design, generates a clock tree in a region, and completes the balance of the clock according to a guide value, thereby solving the problems of timing violation and power consumption increase of the frequency division circuit (DIV).

[0009] The clock tree synthesis method for frequency division circuit provided by the present application includes the following steps:

[0010] Step 1, selectively adding / removing buffers on the clock line;

[0011] Step 2, after the output pin of the frequency divider circuit trigger, a separate clock region is divided;

[0012] Step 3, in the newly divided clock region, the clock starting point is recreated, and an independent clock network is created;

[0013] Step 4, using the insertion_delay command, adjust the clock delay, guide the tool to complete the clock tree balancing;

[0014] Step 5, complete the automatic wiring of the clock line.

[0015] First, under the usual clock tree generation method, the tool will automatically delete unnecessary buffers on the clock line.

[0016] Preferably, step 1 selectively adds buffers on the clock line, which is realized by using the ecoAddRepeater-cell***-loc{**}-name***-term*** command.

[0017] Preferably, step 1 selectively deletes buffers on the clock line, first the tool will automatically delete all redundant buffers, but for the buffers that need to be retained, after setting set_dont_touch***true, part of the buffers can be retained.

[0018] Preferably, the buffers that need to be retained include:

[0019] (1) Buffers that realize special functions. For example:

[0020] Clock definition point buffers, buffers that realize specific functions in the circuit.

[0021] (2) To ensure the signal integrity on the clock tree, the buffers preset in front of the Hard IP clock pin.

[0022] (3) To adjust the clock delay, buffers preset in advance.

[0023] Preferably, step 2 divides a separate clock region, which is realized by using the set_ccopt_property sink_type-pin***stop command.

[0024] Preferably, a separate clock region is divided, and the selected cutting point needs to be set at the clock pin of the frequency divider circuit frequency divider. And in the frequency divider circuit, all paths that can propagate the source clock also need to be set using the set_ccopt_property sink_type-pin***stop command.

[0025] Thus, the propagation of the source clock is prevented, and the division of the clock region is realized. This step can effectively prevent the function trigger (FF) of the frequency division circuit from balancing with the rest of the function trigger (FF) in the design design, that is, preventing the passive lengthening of the clock delay, fundamentally avoiding the problems of timing violation and power consumption.

[0026] Preferably, step 3 re-creates the clock starting point at the frequency division circuit clock generation, using the following command:

[0027] create_ccopt_clock_tree-name***-source***-no_skew_group set_ccopt_property clock_period-pin***1

[0028] In the command clock_period-pin***1, the unit of 1 is ns, and the specific setting time needs to be calculated according to the source clock period of the frequency division circuit, and is not a fixed value.

[0029] Thus, a new source clock is redefined at the output pin of the frequency division trigger FF of the frequency division circuit. This clock is an independent source clock, rather than a sub-clock of other source clocks.

[0030] Preferably, step 4 adjusts the clock delay to guide the tool to complete the clock tree balancing, and the command set_ccopt_property-pin***insertion_delay*** is used to realize it.

[0031] Preferably, in order to meet the timing convergence and reduce power consumption, the structure of the circuit needs to be investigated, the specific delay value of the clock propagation needs to be investigated, and the value of the insertion delay (its unit is ns) is selected. And it needs to be debugged several times to improve the setting.

[0032] Preferably, step 5 completes the automatic wiring of the clock line, and the automatic wiring of the clock tree is completed by using the layer number, metal width and metal spacing of the specified metal wiring layer.

[0033] Compared with the prior art, the present application has the following beneficial effects:

[0034] The application is a clock tree synthesis method for frequency division circuit, which can effectively and accurately realize clock tree balancing by selectively adding and retaining buffers. By cutting the clock, the unreasonable clock delay value between the functional flip-flop (FF) of the frequency division circuit and the remaining functional flip-flop (FF) in the design is prevented from being balanced. By dividing new clock regions, guiding the clock tree balancing stage, effectively balancing the intended value, and generating reasonable clock tree delay, the timing violation and power consumption increase problems of the frequency division circuit (DIV) are solved. Compared with the prior art, the timing violation and power consumption increase problems can be effectively solved. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1 It is a general clock tree synthesis design flow;

[0036] Figure 2 It is a module logic diagram containing a frequency division circuit;

[0037] Figure 3 It is the adverse result of clock synthesis of the frequency division circuit under the general flow;

[0038] Figure 4 It is a timing report excerpt after clock synthesis of the frequency division circuit under the general flow;

[0039] Figure 5 It is a setup violation description after clock synthesis of the frequency division circuit under the general flow;

[0040] Figure 6 It is a clock tree synthesis method for frequency division circuit according to an embodiment of the application;

[0041] Figure 7 It is an effect diagram of clock cutting and region division under the design flow of the embodiment of the application;

[0042] Figure 8 It is a report excerpt after clock cutting and region division under the design flow of the embodiment of the application;

[0043] Figure 9 It is a timing report excerpt of the timing met after clock balancing under the design flow of the embodiment of the application. DETAILED DESCRIPTION

[0044] The technical solutions in the embodiments of the application will be described clearly and completely below with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are only part of the embodiments of the application, not all the embodiments. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the application.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application.

[0046] Under the normal clock tree synthesis design flow (as shown in Figure 1 ), a design module containing a frequency division circuit (as shown in Figure 2 ), will use the following commands to achieve the definition of the source clock and the frequency division clock: create_cc opt_clock_tree -name CLKCM -source Sys_Clk -no_skew_group create_cc opt_generated_clock_tree -name Div_Clk -source Rsp / Rp / FF1 / Q -generated_by Rsp / Rp / FF1 / CK

[0047] In the normal digital back-end design flow, when encountering a frequency division circuit (DIV), the tool automatically regards the FF in the frequency division circuit and other functional FFs in the IP as the default end point and completes the balancing. This causes the clock delay between the clock start point and the FF in the frequency division circuit to be passively lengthened (as shown in Figure 3 ).

[0048] Due to the malicious lengthening of the clock delay, timing violations occur in the frequency division circuit (DIV) (as shown in Figure 4 ). This is a timing violation due to the setup violation at the E end of the ICG control cell in the frequency division circuit after a large number of unnecessary delay adjustment cells are inserted. The violation value is -1.269071 ns (as shown in Figure 5 ).

[0049] To solve the above problems, the embodiment proposes a clock tree synthesis method for a frequency division circuit (as shown in Figure 6 ).

[0050] First, to ensure the signal integrity on the clock tree, a repeater is pre-set in front of the clock pin of the sram:

[0051] ecoAddRepeater -cell BUFV4_96S7P5T16L -term Rsp / Rp / u_mem / CLK -name Rsp / Rp / ecoSiBuf -loc {1880.832 292.8}

[0052] And to reserve this cell from being deleted by the tool, the dont_touch setting is added: set_dont_touch Rsp / Rp / ecoSiBuf true

[0053] This command, when the tool automatically deletes the redundant buffers on the clock line, achieves: selectively add / delete buffers on the clock line.

[0054] Secondly, in order to prevent the propagation of the source clock CLKCM, the design experiment data, the following settings are used: set_ccopt_property sink_type-pin Rsp / Rp / clk_gate_u_7c15_reg_991_ / latch / CK stop

[0055] Stopping the source clock in front of the clock pin of the frequency divider trigger of the frequency divider circuit, the clock region is divided. This step can effectively prevent the functional trigger (FF) of the frequency divider circuit and the remaining functional triggers (FF) in the design design from balancing the unreasonable clock delay value in the clock tree balancing stage, that is, preventing the passive lengthening of the clock delay, fundamentally avoiding the timing violation.

[0056] In this design, in order to separately create the clock region of the subsequent circuit after the frequency divider circuit, realize the clock tree synthesis of the region, the usual setting is not used:

[0057] create_ccopt_clock_tree-name CLKCM-source Sys_Clk-no_skew_groupcreate_ccopt_generated_clock_tree-name Div_Clk-source Rsp / Rp / FF1 / Q-generated_by Rsp / Rp / FF1 / CK

[0058] And the following settings are used:

[0059] create_ccopt_clock_tree-name CLKCM-source Sys_Clk-no_skew_groupcreate_ccopt_clock_tree-name Div_Clk-source Rsp / Rp / FF1 / Q-no_skew_group

[0060] And the period of the above clock is set:

[0061] set_ccopt_property clock_period-pin Sys_Clk 0.5

[0062] set_ccopt_property clock_period-pin Rsp / Rp / FF / Q 1

[0063] Under this setting, a source clock Div_Clk is created separately at the output end of the frequency division trigger of the frequency division circuit.

[0064] Based on the above two steps, the propagation of the source clock is prevented, and a separate clock region is divided behind the output end of the frequency division trigger (as shown in Figure 7 ).

[0065] After the above processing, when the tool performs clock tree balancing, some inappropriate BUF and INV will still be inserted at the clock pin of the frequency division trigger of the frequency division circuit (as shown in Figure 8 ), although there is no timing violation, but it will increase the chip power consumption.

[0066] Therefore, it is also necessary to guide the tool to adjust the clock delay. That is, the following setting is added:

[0067] set_ccopt_property-pin Rsp / Bp / u_7c15_reg_7_ / CK insertion_delay 1

[0068] set_ccopt_property-pin Rsp / Rp / clk_gate_u_7c15_reg_991_ / latch / CKinsertion_delay 1

[0069] set_ccopt_property-pin Rsp / Rp / FF1 / CK insertion_delay 1.2

[0070] Using the command, a delay value is set for the clock input end of part of the frequency division circuit. In the clock tree balancing stage, the tool will adjust the delay from the source clock to the setting point according to the guided delay value, complete the balancing of the clock tree, and solve the problem of reducing power consumption (as shown in Figure 9 ).

Claims

1. A clock tree synthesis method for frequency divider circuits, characterized in that, Includes the following steps: Step 1: Selectively add / remove buffers on the clock line; Step 2: After the output pin of the frequency divider circuit flip-flop, an independent clock region is defined; Step 3: In the newly divided clock area, recreate the clocks and create an independent clock network; Step 4: Use the insertion_delay command to adjust the clock delay and guide the tool to complete the clock tree balancing; Step 5: Complete the automatic wiring of the clock circuit.

2. The method according to claim 1, characterized in that, Step 1 selectively adds buffers to the clock line using the ecoAddRepeater-cell***-loc{**}-name***-term*** command.

3. The method according to claim 1, characterized in that, Step 1 selectively removes buffers on the clock line. The tool will automatically remove all redundant buffers, but for buffers that need to be retained, adding the `set_dont_touch***true` setting can retain some buffers.

4. The method according to claim 3, characterized in that, The buffers that need to be retained include: (1) Buffers that perform special functions; (2) To ensure signal integrity on the clock tree, a buffer is pre-set before the Hard IP clock pin; (3) A buffer that is preset in advance to adjust clock delay.

5. The method according to claim 1, characterized in that, Step 2: Define an independent clock region. This is achieved by using the `set_ccopt_property sink_type-pin***stop` command.

6. The method according to claim 5, characterized in that, An independent clock region is defined, and the selected cut point is set at the Clock PIN of the frequency divider trigger in the frequency divider circuit. Furthermore, in the frequency divider circuit, all paths through which the source clock can propagate need to be cut using the `set_ccopt_property sink_type-pin***stop` command.

7. The method according to claim 1, characterized in that, Step 3: Recreate the clock start point. At the clock generation point of the frequency divider circuit, use the following command: create_ccopt_clock_tree-name***-source***-no_skew_group set_ccopt_property clock_period-pin***1 The unit of 1 is ns. The specific setting time needs to be calculated based on the source clock period of the frequency divider circuit and is not a fixed value.

8. The method according to claim 1, characterized in that, Step 4: Adjust clock delay and guide the tool to complete clock tree balancing. Use the command: set_ccopt_property-pin***insertion_delay***.

9. The method according to claim 8, characterized in that, To achieve timing convergence and reduce power consumption, a specific insertion delay value (in ns) needs to be selected based on the circuit structure and the specific clock propagation delay.

10. The method according to claim 1, characterized in that, Step 5 completes the automatic wiring of the clock line by using the specified metal wiring layer number, metal width, and metal spacing to complete the automatic wiring of the clock tree.

Images