Novel memory inductor equivalent circuit
By designing a novel equivalent circuit model for memory sensors, the theoretical stage problem of memory sensor device realization was solved, a clear and simple circuit structure was constructed, its feasibility was verified, and the application of memory sensors in intelligent electronic systems was promoted.
Patent Information
- Application Number
- CN202511680032.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-17
- Publication Date
- 2026-02-27
AI Technical Summary
In the current technology, the device implementation of memory containers and memory sensors is still in the theoretical stage, lacking effective memory element models, which affects the in-depth understanding of memory sensors and their application in intelligent electronic systems.
A novel equivalent circuit model for a memory sensor, consisting of various resistors, capacitors, and operational amplifiers, is designed. The magnetic flux and current relationship of the memory sensor are described through specific circuit connections and mathematical expressions, thus constructing a clear and simple equivalent circuit structure.
This paper presents an equivalent circuit model of a memory sensor that is clear in structure and easy to implement, verifies its feasibility and promotion value, and promotes the application research of memory sensors in intelligent electronic systems.
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Figure CN121580943A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to circuit design, and in particular to a novel meminductor equivalent circuit. BACKGROUND
[0002] Memristor, as the fourth basic circuit element after resistor, capacitor and inductor, was first proposed by Professor Chua in 1971 from the perspective of circuit completeness, to describe the functional relationship between charge q and magnetic flux , filling the gap in classical circuit theory. The proposal of this theory not only laid the foundation for the study of memory-type circuit elements, but also stimulated the exploration of more general "memory elements". In 2008, HP Laboratory first realized the physical structure of memristor based on titanium dioxide (TiO2) film, confirming its actual existence and reporting it in Nature. In the same year, at the symposium at the University of Berkeley, Professor Chua further pointed out that devices with memory characteristics should not be limited to memristors, but also include memcapacitors and meminductors, both of which are memory devices but are essentially energy storage elements. In 2009, Professor Chua proposed the concept of "memristor system", introducing a new variable and expanding the theoretical system of memory devices to a complete structure. At present, although the memristor has been physically prepared, the realization of the memcapacitor and the meminductor is still in the theoretical stage. Therefore, constructing an effective memory element model is not only crucial for a deep understanding of the dynamic characteristics of memory devices, but also has important significance for promoting its application in new intelligent electronic systems. SUMMARY
[0003] The purpose of the present application is to provide a novel meminductor equivalent circuit with clear and simple structure and easy implementation.
[0004] Technical scheme: A novel meminductor equivalent circuit is composed of a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R 10 , an eleventh resistor R 11 , a twelfth resistor R 12 , a thirteenth resistor R 13 , a fourteenth resistor R 14 , a fifteenth resistor R 15 , a sixteenth resistor R 16 , a first capacitor C1, a second capacitor C2, a first operational amplifier U1, a second operational amplifier U2, a third operational amplifier U3, a fourth operational amplifier U4, a fifth operational amplifier U5, a sixth operational amplifier U6, a first multiplier A1, a first DC power supply V1, and a second DC power supply V2.
[0005] Further, one end of the first resistor R1 is connected with the input power V in and the first operational amplifier is connected with the output of the sixth operational amplifier U6; the reverse input of the first operational amplifier U1 is connected with its output as the port V i .
[0006] Further, one end of the second resistor R2 is connected with the output of the first operational amplifier U1, and the other end is connected with the reverse input of the second operational amplifier U2; the same direction input of the second operational amplifier U2 is grounded; the first capacitor C1 is connected with the reverse input of the second operational amplifier U2, and the other end is connected with the output of the second operational amplifier U2; one end of the third resistor R3 is connected with the reverse input of the second operational amplifier U2, and the other end is connected with the output of the second operational amplifier U2 as the output port
[0007] Further, one end of the fourth resistor R4 is connected with the output of the first operational amplifier U1, and the other end is connected with the reverse input of the fourth operational amplifier U4; the same direction input of the fourth operational amplifier U4 is grounded; one end of the fifth resistor R5 is connected with the reverse input of the fourth operational amplifier U4, and the other end is connected with the output of the fourth operational amplifier U4; one end of the sixth resistor R6 is connected with the output of the second operational amplifier U2, and the other end is connected with the reverse input of the third operational amplifier U3; the same direction input of the third operational amplifier U3 is grounded; one end of the seventh resistor R7 is connected with the reverse input of the third operational amplifier U3, and the other end is connected with the output of the third operational amplifier U3 as the output port
[0008] Further, one end of the eighth resistor R8 is connected with the output of the second operational amplifier U2, and the other end is connected with the reverse input of the fifth operational amplifier U5; the same direction input of the fifth operational amplifier U5 is grounded; one end of the ninth resistor R9 is connected with the positive pole of the first direct current power V1, and the other end is connected with the reverse input of the fifth operational amplifier U5; the negative pole of the first direct current power V1 is grounded; the second capacitor C2 is connected with the reverse input of the fifth operational amplifier U5, and the other end is connected with the output of the fifth operational amplifier U5; one end of the tenth resistor R 10 is connected with the reverse input of the fifth operational amplifier U5, and the other end is connected with the output of the fifth operational amplifier U5 as the output port.
[0009] Further, one end of the eleventh resistor R 11One end is connected with the output end of the first multiplier A1, and the other end is connected with the reverse input end of the sixth operational amplifier U6; the x input end of the first multiplier A1 is connected with the output end of the third operational amplifier U3, and the y input end is connected with the output end of the fifth operational amplifier U5; the twelfth resistance R 12 One end is connected with the output end of the third operational amplifier U3, and the other end is connected with the reverse input end of the sixth operational amplifier U6; the thirteenth resistance R 13 One end is connected with the output end of the fifth operational amplifier U5, and the other end is connected with the reverse input end of the sixth operational amplifier U6; the fourteenth resistance R 14 One end is connected with the positive pole of the second direct current power supply V2, and the other end is connected with the reverse input end of the sixth operational amplifier U6; the negative pole of the second direct current power supply V2 is grounded; the fifteenth resistance R 15 One end is connected with the output end of the fourth operational amplifier U4, and the other end is connected with the reverse input end of the sixth operational amplifier U6; the same direction input end of the sixth operational amplifier U6 is grounded; the sixteenth resistance R 16 One end is connected with the reverse input end of the sixth operational amplifier U6, and the other end is connected with the output end of the sixth operational amplifier U6 and serves as an output port V out .
[0010] Beneficial effect: the application designs a novel meminductor equivalent circuit model with clear structure and simple realization. The model can provide an effective means for meminductor equivalent modeling, has good realizability and popularization value, and has important significance in the application research in the related field of the meminductor. BRIEF DESCRIPTION OF DRAWINGS
[0011] Figure 1 It is the structural schematic diagram of the application;
[0012] Figure 2 It is the equivalent model circuit structure diagram of the meminductor of the application;
[0013] Figure 3 It is the equivalent model of the meminductor of the application And the time sequence diagram of i(t);
[0014] Figure 4 It is the equivalent model of the meminductor of the application Variable phase diagram. DETAILED DESCRIPTION
[0015] In order to make the technical scheme of the application clearer, the application is further described in detail below in combination with the drawings and specific embodiments.
[0016] The mathematical expression based on the equivalent model circuit of the meminductor designed by the application is as follows:
[0017]
[0018] where, I L are the constitutive variables of the meminductor, which are respectively represented as the magnetic flux and the electric current of the meminductor, representing the input and output of the system. ρ is obtained by integration. In the above model, the parameter values are a=1 / 3, b=1 / 10, c=1 / 50, d=0.01 and e=-0.001, respectively. The magnetic flux is obtained by integration of the input voltage.
[0019] The equivalent model structure of the meminductor designed by the application is shown in Figure 1 . Wherein, V in port is the signal input port of the equivalent model of the meminductor, and the input voltage is input from the V in port, and the output feedback voltage V out is obtained through the voltage follower composed of the first operational amplifier U1 to obtain the variable V i , and the variable V i is obtained through the inverter composed of the fourth resistor R4, the fifth resistor R5 and the fourth operational amplifier U4 to obtain the variable-V i ; the variable V i is obtained through the reverse integration circuit composed of the second resistor R2, the third resistor R3, the first capacitor C1 and the second operational amplifier U2 to obtain the variable the variable is obtained through the inverter composed of the sixth resistor R6, the seventh resistor R7 and the third operational amplifier U3 to obtain the variable the variable is obtained through the reverse integration addition circuit composed of the eighth resistor R8, the ninth resistor R9, the tenth resistor R 10 , the second capacitor C2, the first DC power supply V1 and the fifth operational amplifier U5 to obtain the variable ρ; the variable and the variable ρ are obtained through the first multiplier A1 and the variable the variable ρ, the variable-V i and the second DC power supply V2 are obtained through the reverse addition circuit composed of the eleventh resistor R 11 , the twelfth resistor R 12 , the thirteenth resistor R 13 , the fourteenth resistor R 14 , the fifteenth resistor R 15 , the sixteenth resistor R 16 and the sixth operational amplifier U6 to obtain the output voltage V out , finally, the output voltage V out is converted into current through the first resistor R1, that is, the current I L flowing through the meminductor can be obtained.
[0020] As shown in Figure 2 the first resistor R1 one end and input power V in and the first operational amplifier same direction input end connected; the first resistor R1 the other end and output end V out connected; the first operational amplifier U1 reverse input end and its output end connected as port V i . The second resistor R2 one end and port V i connected, the other end and the second operational amplifier U2 reverse input end connected; the second operational amplifier U2 same direction input end ground; the first capacitor C1 and the second operational amplifier U2 reverse input end connected, the other end and the second operational amplifier U2 output end connected; the third resistor R3 one end and the second operational amplifier U2 reverse input end connected, the other end and the second operational amplifier U2 output end connected and as output port The fourth resistor R4 one end and port V i connected, the other end and the fourth operational amplifier U4 reverse input end connected; the fourth operational amplifier U4 same direction input end ground; the fifth resistor R5 one end and the fourth operational amplifier U4 reverse input end connected, the other end and the fourth operational amplifier U4 output end connected and as output port-V i ; the sixth resistor R6 one end and port connected, the other end and the third operational amplifier U3 reverse input end connected; the third operational amplifier U3 same direction input end ground; the seventh resistor R7 one end and the third operational amplifier U3 reverse input end connected, the other end and the third operational amplifier U3 output end connected and as output port The eighth resistor R8 one end and port connected, the other end and the fifth operational amplifier U5 reverse input end connected; the fifth operational amplifier U5 same direction input end ground; the ninth resistor R9 one end and the first DC power supply V1 positive pole connected, the other end and the fifth operational amplifier U5 reverse input end connected; the first DC power supply V1 negative pole ground; the second capacitor C2 and the fifth operational amplifier U5 reverse input end connected, the other end and the fifth operational amplifier U5 output end connected; the tenth resistor R 10 one end and the fifth operational amplifier U5 reverse input end connected, the other end and the fifth operational amplifier U5 output end connected and as output port p. The eleventh resistor R 11 one end and the output end of the first multiplier A1 connected, the other end and the sixth operational amplifier U6 reverse input end connected; the x input end of the first multiplier A1 and port connected, y input end and port p connected; the twelfth resistor R 12 one end and port One end is connected to the other end, which is connected to the inverting input of the sixth operational amplifier U6; the thirteenth resistor R 13 One end is connected to port ρ, and the other end is connected to the inverting input of the sixth operational amplifier U6; the fourteenth resistor R 14 One end is connected to the positive terminal of the second DC power supply V2, and the other end is connected to the inverting input terminal of the sixth operational amplifier U6; the negative terminal of the second DC power supply V2 is grounded; the fifteenth resistor R 15 One end and port -V i One end is connected to the other end, which is connected to the inverting input of the sixth operational amplifier U6; the non-inverting input of the sixth operational amplifier U6 is grounded; the sixteenth resistor R 16 One end is connected to the inverting input of the sixth operational amplifier U6, and the other end is connected to the output of the sixth operational amplifier U6 and serves as the output port V. out .
[0021] To verify the effectiveness of the proposed memory sensor circuit model, the circuit was built in Multisim simulation software, and a magnetic flux excitation signal v(t) = v0sin(2πft) (where v0 = 4V, f = 180Hz) was applied. Figure 3 The magnetic flux is given With current I L The time-domain response relationship, Figure 4 Showing The phase trajectory diagram on the plane exhibits typical hysteresis curve characteristics between constitutive variables of the memory sensor, which conforms to the definition of the equivalent model of the memory sensor. Simulation results verify the feasibility and effectiveness of the proposed memory sensor circuit model.
[0022] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.
Claims
1. A novel memory sensor equivalent circuit, characterized in that, The resistors are: R1 (first resistor), R2 (second resistor), R3 (third resistor), R4 (fourth resistor), R5 (fifth resistor), R6 (sixth resistor), R7 (seventh resistor), R8 (eighth resistor), R9 (ninth resistor), and R1 (tenth resistor). 10 Eleventh resistor R 11 12th resistor R 12 The thirteenth resistor R 13 Fourteenth resistor R 14 The fifteenth resistor R 15 The sixteenth resistor R 16 It consists of a first capacitor C1, a second capacitor C2, a first operational amplifier U1, a second operational amplifier U2, a third operational amplifier U3, a fourth operational amplifier U4, a fifth operational amplifier U5, a sixth operational amplifier U6, a first multiplier A1, a first DC power supply V1, and a second DC power supply V2.
2. The novel memory sensor equivalent circuit according to claim 1, characterized in that, One end of the first resistor R1 is connected to the input power supply V. in The first operational amplifier's non-inverting input is connected to the first operational amplifier; the other end of the first resistor R1 is connected to the output of the sixth operational amplifier U6; the inverting input of the first operational amplifier U1 is connected to its output as port V. i .
3. The novel memory sensor equivalent circuit according to claim 1, characterized in that, One end of the second resistor R2 is connected to the output terminal of the first operational amplifier U1, and the other end is connected to the inverting input terminal of the second operational amplifier U2; the non-inverting input terminal of the second operational amplifier U2 is grounded; the first capacitor C1 is connected to the inverting input terminal of the second operational amplifier U2, and the other end is connected to the output terminal of the second operational amplifier U2; one end of the third resistor R3 is connected to the inverting input terminal of the second operational amplifier U2, and the other end is connected to the output terminal of the second operational amplifier U2 and serves as the output port -φ.
4. The novel memory sensor equivalent circuit according to claim 1, characterized in that, The fourth resistor R4 is connected at one end to the output terminal of the first operational amplifier U1 and at the other end to the inverting input terminal of the fourth operational amplifier U4; the non-inverting input terminal of the fourth operational amplifier U4 is grounded; the fifth resistor R5 is connected at one end to the inverting input terminal of the fourth operational amplifier U4 and at the other end to the output terminal of the fourth operational amplifier U4; the sixth resistor R6 is connected at one end to the output terminal of the second operational amplifier U2 and at the other end to the inverting input terminal of the third operational amplifier U3; the non-inverting input terminal of the third operational amplifier U3 is grounded; the seventh resistor R7 is connected at one end to the inverting input terminal of the third operational amplifier U3 and at the other end to the output terminal of the third operational amplifier U3, serving as the output port φ.
5. The novel memory sensor equivalent circuit according to claim 1, characterized in that, The eighth resistor R8 has one end connected to the output of the second operational amplifier U2 and the other end connected to the inverting input of the fifth operational amplifier U5; the non-inverting input of the fifth operational amplifier U5 is grounded; the ninth resistor R9 has one end connected to the positive terminal of the first DC power supply V1 and the other end connected to the inverting input of the fifth operational amplifier U5; the negative terminal of the first DC power supply V1 is grounded; the second capacitor C2 is connected to the inverting input of the fifth operational amplifier U5 and the other end connected to the output of the fifth operational amplifier U5; the tenth resistor R... 10 One end is connected to the inverting input of the fifth operational amplifier U5, and the other end is connected to the output of the fifth operational amplifier U5 and serves as the output port ρ.
6. The novel memory sensor equivalent circuit according to claim 1, characterized in that, The eleventh resistor R 11 One end is connected to the output of the first multiplier A1, and the other end is connected to the inverting input of the sixth operational amplifier U6; the x input of the first multiplier A1 is connected to the output of the third operational amplifier U3, and the y input is connected to the output of the fifth operational amplifier U5; the twelfth resistor R 12 One end is connected to the output of the third operational amplifier U3, and the other end is connected to the inverting input of the sixth operational amplifier U6; the thirteenth resistor R 13 One end is connected to the output of the fifth operational amplifier U5, and the other end is connected to the inverting input of the sixth operational amplifier U6; the fourteenth resistor R 14 One end is connected to the positive terminal of the second DC power supply V2, and the other end is connected to the inverting input terminal of the sixth operational amplifier U6; the negative terminal of the second DC power supply V2 is grounded; the fifteenth resistor R 15 One end is connected to the output of the fourth operational amplifier U4, and the other end is connected to the inverting input of the sixth operational amplifier U6; the non-inverting input of the sixth operational amplifier U6 is grounded; the sixteenth resistor R 16 One end is connected to the inverting input of the sixth operational amplifier U6, and the other end is connected to the output of the sixth operational amplifier U6 and serves as the output port V. out .