Differential wiring verification method of PCB (Printed Circuit Board) and electronic equipment

Abstract

The invention relates to the technical field of hardware design, in particular to a differential wiring verification method for a PCB and electronic equipment, and the method comprises the steps: determining a differential wiring topology model in response to an obtained PCB design file; acquiring an electrical rule defined by a user, and performing geometric verification based on the differential routing topology model and the electrical rule to position geometric violation points; performing integrity analysis on a preset key structure in the differential routing topology model to determine a signal distortion risk point; and generating a visual view according to the geometric violation points and the signal distortion risk points. The method has the advantages that hard geometric violation and hidden electrical risks of differential wiring in PCB design are found, and verification accuracy and design reliability are remarkably improved.

Description

Technical Field

[0001] This application relates to the field of hardware design technology, and in particular to a differential trace verification method for PCB boards and an electronic device. Background Technology

[0002] Differential signal traces are widely used in high-speed digital circuits and high-frequency communication equipment due to their superior anti-interference capabilities and signal integrity. To ensure signal transmission quality, the physical and electrical parameters of differential traces must be rigorously verified during the PCB design phase to meet design requirements.

[0003] Design engineers typically rely on the Design Rule Check (DRC) tools built into Electronic Design Automation (EDA) software, or manually check differential pairs one by one against geometric constraints such as trace spacing and length tolerances according to design specifications. For signal integrity issues, engineers may use simulation tools to perform impedance analysis on specific traces. However, this traditional verification method is inefficient and prone to errors, especially when dealing with complex PCB designs with many layers and extremely high wiring density. Manual checks can hardly guarantee 100% accuracy, easily leading to missed or false positives. Furthermore, current simulation tools usually only analyze impedance at a single frequency point or under ideal conditions, making it difficult to locate the risk of broadband signal distortion caused by critical structures commonly encountered in actual manufacturing, such as vias for layer changes or sharp-angle turns in trace paths. This results in design defects in the PCB board, affecting the electrical performance and operational reliability of the final product, thus leaving room for improvement. Summary of the Invention

[0004] To improve the accuracy of verification and the reliability of design, this application provides a method and electronic device for verifying differential traces on a PCB board.

[0005] The above-mentioned objective of this application is achieved through the following technical solution:

[0006] A method for verifying differential traces on a PCB board, the method comprising:

[0007] In response to the acquired PCB design files, determine the differential routing topology model;

[0008] Obtain user-defined electrical rules, and perform geometric verification based on the differential routing topology model and the electrical rules to locate geometric violation points;

[0009] By performing integrity analysis on the preset key structures in the differential routing topology model, signal distortion risk points can be identified.

[0010] A visualization view is generated based on the geometric violation points and the signal distortion risk points.

[0011] By adopting the above technical solution, the differential routing topology model is determined in response to the acquired PCB design file, transforming the original PCB design file into a data model that can be efficiently analyzed by computers. Geometric verification based on the topology model and electrical rules enables automated and comprehensive inspection of the basic physical design rules of differential routing, thereby locating clear geometric violations. Integrity analysis of preset key structures allows for in-depth detection and identification of potential signal distortion risks that cannot be found through conventional inspections. By generating a visual view based on geometric violations and signal distortion risks, the analysis results are presented intuitively in the design interface, greatly improving the efficiency and accuracy of engineers in discovering, understanding, and locating problems, thus effectively improving the electrical performance and operational reliability of the product.

[0012] In a preferred embodiment, this application can be further configured such that the step of determining the differential routing topology model in response to the acquired PCB design file specifically includes:

[0013] The PCB design file is parsed, and the differential pair network in the PCB design file is identified according to the preset naming convention;

[0014] Based on the differential pair network, the connection relationship between the geometric elements of the differential pair network and the corresponding geometric elements is obtained, wherein the geometric elements include at least traces and vias;

[0015] The differential routing topology model is constructed based on the geometric elements of the differential pair network and the connection relationships between the geometric elements.

[0016] By adopting the above technical solution, in the process of determining the differential routing topology model, differential pair networks are automatically identified through a preset naming convention, and their geometric elements, including traces and vias, and their connection relationships are further obtained to construct the topology model. This approach ensures that the initial data model can be automatically and accurately constructed from various mainstream PCB design files, providing a solid foundation for the reliability of all subsequent analyses and enhancing the universality of the method.

[0017] In a preferred embodiment, this application can be further configured such that the step of obtaining user-defined electrical rules specifically includes:

[0018] A graphical user interface is provided for displaying a list of rules containing constraint thresholds, the constraint thresholds including at least a difference pair spacing constraint threshold and an equal length tolerance constraint threshold;

[0019] In response to user input in the graphical user interface, a user-defined rule list is obtained, and the electrical rules are derived based on the rule list.

[0020] By adopting the above technical solution, a graphical user interface is provided to display and receive user-defined modifications to rule constraint thresholds during the acquisition of electrical rules. This design makes the verification standards no longer fixed but flexibly configurable according to the specific technical specifications of different projects, thereby greatly expanding the engineering application scenarios and practical value.

[0021] In a preferred embodiment, this application can be further configured such that the step of performing geometric verification based on the differential routing topology model and the electrical rules to locate geometric violations specifically includes:

[0022] By traversing the differential routing topology model, the actual spacing and actual length difference between the two routing lines of the differential pair are calculated through geometric calculations.

[0023] The difference between the actual spacing and the actual length is compared with the corresponding constraint threshold in the electrical rules;

[0024] If the actual spacing does not meet the differential pair spacing constraint threshold, the corresponding position point is determined as a geometric violation point of insufficient spacing.

[0025] If the actual length difference does not meet the equal length tolerance constraint threshold, the corresponding position point is determined as a geometric violation point of equal length error type.

[0026] By employing the above technical solution, during geometric verification, the actual spacing and length difference between the differential pairs are precisely calculated and compared with a user-defined threshold, thereby clearly classifying violations into insufficient spacing or equal length error types. This quantification and classification approach not only ensures the high accuracy of the verification results but also provides clear guidance for subsequent targeted automated corrections.

[0027] In a preferred embodiment, this application can be further configured such that the step of determining signal distortion risk points by performing integrity analysis on preset key structures in the differential routing topology model specifically includes:

[0028] From the differential routing topology model, the acute angle turn between the layer-changing via and the routing path is identified, and the acute angle turn between the layer-changing via and the routing path is the preset key structure.

[0029] For the layer-changing via and the acute-angle turn, the electromagnetic field solver is called to perform simulation to obtain the corresponding frequency domain parameters within the preset frequency band;

[0030] Perform an inverse discrete Fourier transform on the frequency domain parameters to generate a time-domain reflection waveform, and identify the impedance abrupt peak in the time-domain reflection waveform;

[0031] Based on the impedance abrupt change peak, the corresponding physical coordinates are obtained by inverse calculation, and the physical coordinates are determined as the signal distortion risk points.

[0032] By employing the aforementioned technical solution, during integrity analysis, key structures such as layer-changing vias and acute-angle turns are first identified from the model. Then, an electromagnetic field solver is used to perform frequency domain simulation, and the results are converted to the time domain using inverse discrete Fourier transform. Finally, impedance abrupt peaks are identified in the time-domain reflection waveform, and their physical coordinates are calculated. This in-depth analysis method based on physics principles can accurately reveal and locate signal integrity problems caused by microstructural defects, fundamentally compensating for the blind spots of traditional rule-based checks and significantly improving the reliability of high-speed circuit design.

[0033] In a preferred embodiment, this application can be further configured such that the step of generating a visualization view based on the geometric violation point and the signal distortion risk point specifically includes:

[0034] Obtain the amplitude of the impedance abrupt change peak, and calculate the degree of deviation between the signal distortion risk point and the target characteristic impedance based on the amplitude;

[0035] In the EDA interface, the physical locations corresponding to the geometric violation points are highlighted, and according to the degree of deviation, an impedance anomaly heatmap is superimposed on the physical locations corresponding to the signal distortion risk points to construct the visualization view.

[0036] By adopting the above technical solution, when generating the visualization view, the deviation of impedance abrupt peaks is calculated, and geometric violations are highlighted, while signal risk points are overlaid with an impedance anomaly heatmap that reflects the degree of deviation. This differentiated and information-based visual presentation allows engineers to intuitively distinguish the nature of the problem, locate its position, and assess its severity level from a single interface, thereby significantly improving the efficiency of problem diagnosis and the accuracy of subsequent decisions.

[0037] In a preferred embodiment, this application can be further configured such that the differential trace verification method also includes:

[0038] In response to the user's selection of any of the geometric violation points or signal distortion risk points in the visualization view, a suggested remediation scheme is generated.

[0039] The proposed correction scheme is statistically validated using Monte Carlo simulation to determine its reliability. If reliable, the proposed correction scheme is then applied.

[0040] By employing the above technical solution, corrective action suggestions are generated in response to user selections, and these suggestions are statistically validated using Monte Carlo simulation. Only after reliable validation is the suggestion applied. This closed-loop design not only automatically generates high-quality repair strategies but also scientifically predicts their robustness under real manufacturing conditions before implementation, thereby significantly shortening the design and debugging cycle and reducing over-reliance on advanced engineer experience.

[0041] In a preferred embodiment, this application can be further configured such that the step of generating a suggested correction scheme in response to a user's selection of any of the geometric violation points or signal distortion risk points in the visualization view specifically includes:

[0042] If the selected point is the geometric violation point and its type is insufficient spacing, then the path planning algorithm is invoked, and the routing path is recalculated using the differential pair spacing constraint threshold in the electrical rules as the boundary condition, so as to generate a new set of path coordinates as the proposed correction scheme.

[0043] If the selected point is the geometric violation point and its type is the equal-length error type, then the geometry generation algorithm is invoked to generate a serpentine geometry structure in the available space of the differential routing topology model, so as to use the serpentine geometry structure as the proposed correction scheme.

[0044] If the selected point is the signal distortion risk point, the optimization algorithm is invoked to perform inverse calculation based on the target characteristic impedance and the stack-up parameters in the differential trace topology model to obtain the optimized antipad size as the suggested correction scheme.

[0045] By adopting the above technical solution, when generating correction suggestions, a path planning algorithm is used to address insufficient spacing issues, a geometry generation algorithm is used to address equal length errors, and an optimization algorithm is used to back-calculate the anti-pad dimensions for signal distortion risk points. This strategy of matching the appropriate optimal algorithm to different types of defects ensures that the generated correction suggestions are highly professional and effective.

[0046] In a preferred embodiment, this application can be further configured such that the step of statistically validating the proposed correction scheme through Monte Carlo simulation to determine whether the proposed correction scheme is reliable specifically includes:

[0047] For the geometric dimensional parameters in the proposed correction scheme, random perturbations are applied within a preset manufacturing tolerance range to generate a large number of simulation samples;

[0048] For the large number of simulation samples, fast electromagnetic simulation is performed one by one to obtain the corresponding electrical performance parameters after simulation.

[0049] The proportion of samples whose electrical performance parameters meet the preset design target after simulation is statistically analyzed, and when the proportion of samples exceeds the preset reliability threshold, the correction scheme is determined to be reliable.

[0050] By adopting the above technical solution, when performing Monte Carlo statistical verification, random perturbations are applied to the geometric dimensions of the modified scheme within the manufacturing tolerance range, and electromagnetic simulation is performed on a large number of generated samples. Finally, the reliability is judged by statistically analyzing the proportion of samples that meet the design goals. This allows for a scientific and quantitative prediction of the performance of the modified scheme in a real mass production environment, thereby effectively avoiding the problem of perfect design but difficult mass production, and greatly enhancing the manufacturability of the design and the market competitiveness of the final product.

[0051] The second objective of this invention is achieved through the following technical solution:

[0052] An electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the differential trace verification method for the PCB board described above.

[0053] In summary, this application includes at least one of the following beneficial technical effects:

[0054] 1. By responding to the acquired PCB design files, a differential routing topology model is determined, transforming the original PCB design files into a data model that can be efficiently analyzed by computers. Geometric verification based on the topology model and electrical rules enables automated and comprehensive checking of the fundamental physical design rules of differential routing, thereby locating clear geometric violations. Integrity analysis of preset key structures allows for in-depth detection and identification of potential signal distortion risks that conventional inspections cannot uncover. Visualization based on geometric violations and signal distortion risks presents the analysis results intuitively in the design interface, significantly improving the efficiency and accuracy of engineers in discovering, understanding, and locating problems, thus effectively improving the electrical performance and operational reliability of the product.

[0055] 2. When performing Monte Carlo statistical validation, random perturbations are applied to the geometric dimensions of the modified scheme within the manufacturing tolerance range, and electromagnetic simulations are performed on a large number of samples generated. Finally, the reliability is judged by the proportion of samples that meet the design goals. This allows for a scientific and quantitative prediction of the performance of the modified scheme in a real mass production environment, thereby effectively avoiding the problem of perfect design but difficult mass production, and greatly enhancing the manufacturability of the design and the market competitiveness of the final product. Attached Figure Description

[0056] Figure 1This is a flowchart illustrating the implementation of a differential trace verification method for a PCB board in one embodiment of this application.

[0057] Figure 2 This is a flowchart illustrating the implementation of step S10 in a differential trace verification method for a PCB board according to an embodiment of this application.

[0058] Figure 3 This is a flowchart illustrating the implementation of step S20 in a differential trace verification method for a PCB board according to an embodiment of this application.

[0059] Figure 4 This is another implementation flowchart of step S20 in the differential trace verification method of PCB board in one embodiment of this application;

[0060] Figure 5 This is a flowchart illustrating the implementation of step S30 in a differential trace verification method for a PCB board according to an embodiment of this application.

[0061] Figure 6 This is a flowchart illustrating the implementation of step S40 in a differential trace verification method for a PCB board according to an embodiment of this application.

[0062] Figure 7 This is another implementation flowchart of the differential trace verification method for PCB board in one embodiment of this application;

[0063] Figure 8 This is a flowchart illustrating the implementation of step S50 in a differential trace verification method for a PCB board according to an embodiment of this application.

[0064] Figure 9 This is a flowchart illustrating the implementation of step S60 in a differential trace verification method for a PCB board according to an embodiment of this application.

[0065] Figure 10 This is a schematic diagram of the internal structure of an electronic device according to an embodiment of this application. Detailed Implementation

[0066] The following embodiments will help those skilled in the art to further understand the function of this application, but do not limit this application in any way. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of this application. These all fall within the protection scope of this application.

[0067] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0068] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0069] The present application will be further described in detail below with reference to the accompanying drawings.

[0070] In one embodiment, such as Figure 1 As shown, this application discloses a method for verifying differential traces on a PCB board, which specifically includes the following steps:

[0071] S10: In response to the acquired PCB design file, determine the differential routing topology model.

[0072] Specifically, when a user triggers a verification command in the EDA software and specifies a PCB design file, the system receives and loads an industry-standard PCB design file, such as a Gerber file or an ODB++ file package, and performs in-depth structured analysis to identify all network connections and physical layout information on the circuit board. Finally, it builds a data model in memory that fully reflects the electrical and physical characteristics of the differential traces in the original design.

[0073] S20: Obtain user-defined electrical rules, perform geometric verification based on differential routing topology model and electrical rules to locate geometric violation points.

[0074] Specifically, before the analysis begins, an interactive rule setting interface is provided to the user, allowing the user to adjust various constraint parameters according to the design specifications of the specific project. After the verification is started, the program will traverse the entire topology model, extract the actual geometric dimensions of each differential trace, and compare them with the electrical rules confirmed by the user item by item, thereby automatically and without omission filtering out all geometric violation points that do not meet the design requirements.

[0075] S30: By performing integrity analysis on the preset key structures in the differential routing topology model, signal distortion risk points are identified.

[0076] Specifically, for specific physical structures in the differential routing topology model that have a significant impact on signal integrity, such as signal layer switching connection structures or locations where the routing direction changes drastically, a high-frequency electromagnetic simulation engine is invoked to analyze the reflection and loss that may occur when the signal passes through these structures. By interpreting the simulation results, potential risk areas that may lead to signal quality degradation or data transmission errors are accurately located.

[0077] S40: Generate a visualization view based on geometric violation points and signal distortion risk points.

[0078] Specifically, the data of all geometric violation points and signal distortion risk points located in the aforementioned steps are integrated and presented in an intuitive way in the design view of the EDA software by calling the graphics rendering interface. For example, the risk level can be represented by drawing a conspicuous mark on the physical location of the violation or by overlaying a layer of different shades of color on the risk area, thereby generating a comprehensive and easy-to-understand visualization report.

[0079] In one embodiment, such as Figure 2 As shown, in step S10, which is the step of determining the differential routing topology model in response to the acquired PCB design file, the specific steps include:

[0080] S11: Parse the PCB design file and identify the differential pair network in the PCB design file according to the preset naming convention.

[0081] Specifically, during the parsing process, the program employs a regular expression-based matching engine to scan the naming list of all networks in the file. The engine's rule base pre-sets various industry-common differential pair naming conventions. For example, it searches for all pairs of network names that end with "_P" and "_N" and have identical prefixes, such as "USB_D_P" and "USB_D_N", or pairs that end with "_DP" and "_DN", such as "MIPI_CLK_DP" and "MIPI_CLK_DN". Through this highly flexible and configurable automated name recognition mechanism, the system can efficiently and accurately filter out all sets of networks that the designer intended to define as differential pairs from complex designs containing hundreds or thousands of networks within milliseconds.

[0082] S12: Based on the differential pair network, obtain the geometric elements of the differential pair network and the connection relationships between the geometric elements. The geometric elements include at least traces and vias.

[0083] Specifically, for each differential pair network identified in the previous step, such as "USB_D_P", the program will further analyze the layout data to trace and extract each independent physical entity that constitutes the network. This process will record the precise geometric information of each copper foil trace in detail, including its start / end coordinates, line width, board layer number, and whether it is a straight line or an arc. At the same time, for each via used for interlayer connection, it will also record key geometric information such as its center coordinates, hole diameter, and pad diameter. Most importantly, the system will build a connection table to record how these elements are physically connected to each other, forming an ordered topology sequence, for example: pad A → trace segment 1 → via 1 → trace segment 2 → pad B.

[0084] S13: Based on the geometric elements of the differential pair network and the corresponding connection relationships between them, a differential routing topology model is constructed.

[0085] Specifically, using the large number of discrete geometric elements and their precise connections obtained in the previous step, the system creates a high-level, object-oriented graph data structure in computer memory to represent each differential pair. In this graph, each intersection of pads, vias, or traces can be considered a node, and each trace segment is a weighted edge. The weight of the edge can include attributes such as length, width, and impedance. This data structure completely breaks free from the graphical limitations of the original file, forming a differential trace topology model that contains all physical dimension information and reproduces the complete flow path of the signal from the source to the terminal, which can be efficiently processed by computer programs.

[0086] In one embodiment, such as Figure 3 As shown, step S20, namely the step of obtaining user-defined electrical rules, specifically includes:

[0087] S21: Provide a graphical user interface for displaying a list of rules containing constraint thresholds, which include at least a difference pair spacing constraint threshold and an equal length tolerance constraint threshold.

[0088] Specifically, the system will pop up a separate modal dialog box, or dynamically generate a configuration panel in the sidebar of the main interface. The panel lists all configurable electrical rule items in a clear, categorized table format with group headings. For example, under the spacing rule group, there is differential pair internal spacing, and under the timing rule group, there is differential pair equal length tolerance. Each rule is followed by an editable input box with units such as mil or mm. The input box not only has the industry-recommended default constraint thresholds pre-filled, but may also have a drop-down arrow that provides preset values ​​for several commonly used standards such as DDR4 and PCIe 5.0 for users to select with one click.

[0089] S22: In response to user input in the graphical user interface, obtain a list of user-defined rules, and obtain electrical rules based on the list of rules.

[0090] Specifically, the program binds corresponding event listeners to each input box and button control on the interface in the background. When it detects that the user has modified the value in the input box, changing the differential pair spacing from 8mil to 6mil, or clicked the Apply or OK button, the program will immediately trigger a callback function. This function will traverse all rule-related input controls on the interface, read their current final values, and use these new values ​​to update a global RuleSet configuration object in memory, thereby forming a set of personalized electrical rules that fully meet the user's current specific design requirements and take effect immediately.

[0091] In one embodiment, such as Figure 4 As shown, in step S20, which is the step of performing geometric verification based on the differential routing topology model and electrical rules to locate geometric violations, the specific steps include:

[0092] S23: Traverse the differential routing topology model and calculate the actual spacing and actual length difference between the two routing pairs through geometric calculations.

[0093] Specifically, for each differential pair in the topology model, the program synchronously samples along their centerline path with a very small step size, such as 0.1 mil. At each sampling point, the program calculates the normal vector of that point on the trace and probes along the normal direction to the other trace. By solving for the geometric intersection, the program obtains the most accurate spacing value at that location. After traversing the entire path, the program finds the minimum value among all measurements as the actual spacing of the differential pair. At the same time, the program accurately accumulates the lengths of all straight and circular segments that make up the P-line and N-line, and takes into account the vertical interlayer height caused by vias, finally obtaining the actual total length of the two traces and calculating the difference between them.

[0094] S24: Compare the difference between the actual spacing and the actual length with the corresponding constraint thresholds in the electrical rules.

[0095] Specifically, if the calculations in the aforementioned steps show that the actual spacing of a certain difference pair is 3.8 mil and the actual length difference is 12 mil, and the user set a spacing constraint threshold of 4 mil and an equal length tolerance constraint threshold of 10 mil in the aforementioned steps, then two logical judgments will be executed. The first is to compare whether 3.8 mil is less than 4 mil, and the second is to compare whether 12 mil is greater than 10 mil. These two comparison operations can be designed to be executed in parallel to maximize the utilization of CPU resources.

[0096] S25: If the actual spacing does not meet the differential pair spacing constraint threshold, the corresponding location point is determined as a geometric violation point of insufficient spacing.

[0097] Specifically, based on the first comparison result of the aforementioned steps, since 3.8mil is indeed less than 4mil, violating the spacing constraint, a violation record is created at this time. This record records the network name of the difference pair, the violation type marked as insufficient spacing, the precise X and Y coordinates of the violation, the current actual spacing value, and the threshold required by the rule. Finally, this object encapsulating all the information is pushed into a global violation result stack, awaiting subsequent processing.

[0098] S26: If the actual length difference does not meet the equal length tolerance constraint threshold, the corresponding position point is determined as a geometric violation point of equal length error type.

[0099] Specifically, based on the second comparison result of the aforementioned steps, since 12mil is indeed greater than 10mil and exceeds the equal length tolerance range, a violation record will be created at this time, recording the network name of the difference pair, the violation type marked as equal length error, the calculated current actual length, and the maximum tolerance value allowed by the rule; similarly, this object containing complete diagnostic information will also be pushed into the same global violation result stack so that it can be presented to the user in a unified manner later.

[0100] In one embodiment, such as Figure 5 As shown, in step S30, which involves performing an integrity analysis on preset key structures in the differential routing topology model to determine signal distortion risk points, the specific steps include:

[0101] S31: Identify the acute angle turns between layer-change vias and routing paths from the differential routing topology model. The acute angle turns between layer-change vias and routing paths are preset key structures.

[0102] Specifically, the program performs a structured scan of the topology model. When a topology node is marked as a via, the system automatically identifies it as a critical structure. In addition, when two consecutive trace elements are encountered, the system calculates the angle between the direction vectors of the two traces. If the absolute value of the angle is less than a threshold that can be configured in the background, such as the empirical value of 135 degrees, it means that the turning angle is less than 45 degrees. The system will mark this corner as another critical structure acute angle turn, because such a structure is very likely to cause impedance abrupt changes and signal reflections.

[0103] S32: For layer-changing vias and sharp-angle turns, call the electromagnetic field solver to perform simulation to obtain the corresponding frequency domain parameters within the preset frequency band.

[0104] Specifically, taking a differential via pair from the top to the bottom layer as an example, the system first extracts all the geometric and material parameters constituting the structure from the complete PCB data: via diameter such as D=0.2mm, pad diameter such as P=0.4mm, anti-pad diameter such as A=0.6mm, thickness of each dielectric layer such as H1=0.1mm, H2=1.4mm, H3=0.1mm, and dielectric constant such as εr=4.2; then, the system inputs these parameters into a built-in electromagnetic field solver based on the boundary element method; this solver will calculate the electromagnetic field of the via structure. Virtual wave ports are set at the input and output ends, and scanning excitation is performed in the frequency band from 0.1 GHz to 10 GHz with a preset step such as 0.05 GHz. At each frequency point f, the solver calculates the scattering parameter matrix, i.e. the frequency domain parameters, describing how the signal is reflected and transmitted in the structure by solving Maxwell's equations. In particular, S11(f) is the return loss of the input port and S21(f) is the insertion loss from the input to the output. These two complex parameters, including amplitude and phase, together constitute the complete frequency domain response characteristics of the structure in this frequency band.

[0105] S33: Perform an inverse discrete Fourier transform on the frequency domain parameters to generate a time-domain reflection waveform, and identify the impedance abrupt peak in the time-domain reflection waveform.

[0106] Specifically, the system takes the discrete S11(f) parameter sequence covering the entire frequency band, calculated in the previous step, as input. To transform it to the time domain, the system calls a Fast Inverse Fourier Transform (IFFT) algorithm library. Before the transformation, the frequency domain data needs to be processed to meet the requirements of IFFT, including ensuring that the frequency points are equally spaced through interpolation and increasing the time domain resolution by padding with zeros. The processed frequency domain response sequence S11[k] is then fed into the IFFT algorithm, whose core calculation formula is: Where n is the sampling point index in the time domain, and N is the total number of sampling points; the calculated result S11[n] is a time-domain impulse response sequence; in order to obtain a more intuitive time-domain reflection (TDR) waveform that reflects impedance changes, the system will further convolve the impulse response with an ideal step signal, or directly use the impedance transformation formula. Z0 is the reference impedance, and Γ(t) is s11(t), which is the continuous-time signal obtained by interpolation of s11[n]. The vertical axis of the final generated TDR waveform Z(t) represents impedance, and the horizontal axis represents time. The system will then perform a peak detection algorithm on the waveform, for example, by calculating the first and second derivatives of the waveform to find local maxima, and set a threshold, such as impedance change exceeding ±10%, to filter out those significant abrupt peaks that represent impedance discontinuities.

[0107] S34: Based on the impedance abrupt change peak, perform inverse calculation to obtain the corresponding physical coordinates, and determine the physical coordinates as the signal distortion risk point.

[0108] Specifically, the core of this calculation step is to convert the time point t_peak in the TDR waveform to its physical location on the PCB layout. First, the system needs to calculate the signal propagation speed v in the medium, which depends on the effective dielectric constant ε of the dielectric layer where the signal resides. eff Its calculation formula is Where c is the speed of light in a vacuum, approximately 3 x 10^8 m / s; for surface microstrip lines, Where h is the dielectric thickness and w is the linewidth, and for the inner stripline, ε eff Approximately equal to ε r Then, using the basic principle of TDR, the physical length d from the peak to the signal input can be calculated using the formula... The calculation shows that the division by 2 is because TDR measures the total round-trip time of the signal. Finally, the system will start from the input end of the via, such as the center of the top pad, and travel precisely along the signal propagation path in the topology model, such as vertically downward through the dielectric layer, for a length of d. This one-dimensional length value will then be accurately mapped back to the three-dimensional physical coordinates (x, y, z) of the PCB model, and this coordinate point will be ultimately identified as a signal distortion risk point that needs attention.

[0109] In one embodiment, such as Figure 6 As shown, step S40, which is the step of generating a visualization view based on geometric violation points and signal distortion risk points, specifically includes:

[0110] S41: Obtain the amplitude of the impedance abrupt change peak, and calculate the degree of deviation between the signal distortion risk point and the target characteristic impedance based on the amplitude.

[0111] Specifically, for each significant impedance abrupt change peak identified on the TDR curve in the previous step, the program precisely reads the ordinate value of its peak point. This value directly corresponds to the instantaneous impedance at that physical location, measured in ohms. Then, the system reads the target characteristic impedance set by the designer from the project's configuration file; for example, this value is 90 ohms for a USB differential line and 100 ohms for PCIe. By executing the formula: Deviation (%) = (Instantaneous Impedance - Target Impedance | / Target Impedance) * 100%, a standardized quantitative indicator that intuitively reflects the severity of signal distortion risk—the percentage deviation—is calculated. For example, if the target characteristic impedance of a differential pair is 100 ohms, and the impedance reading corresponding to a peak detected in the TDR waveform in the previous step is 115 ohms, then its deviation can be calculated as (115-100) / 100 = 15%. This percentage value will serve as a quantitative indicator used in subsequent visualization to represent the severity level of the risk.

[0112] S42: In the EDA interface, the physical locations corresponding to the geometric violation points are highlighted, and according to the degree of deviation, impedance anomaly heatmaps are overlaid on the physical locations corresponding to the signal distortion risk points to construct a visualization view.

[0113] Specifically, the program calls the graphics drawing application interface (API) provided by the EDA software to perform a dual rendering process. First, it iterates through the list of all recorded geometric violation points and, for each violation point, calls the DrawRectangle or a similar function to draw a prominent, semi-transparent red highlighted rectangle on the physical coordinates corresponding to the violation point, ensuring that the user does not miss any hard rule errors. Next, it iterates through the list of all signal distortion risk points and, based on the percentage deviation calculated in the previous step, linearly maps it to a preset color spectrum, from cool colors such as blue representing small deviations to warm colors such as red representing large deviations. Then, it calls the DrawHeatmapLayer or a similar function to overlay a semi-transparent layer of the corresponding color with a smooth transition effect on the physical location corresponding to the risk point and its adjacent area. Finally, it forms an impedance anomaly heatmap with extremely high information density, which can be used to instantly assess the signal integrity health of the entire circuit board without reading the report, simply by visual inspection.

[0114] In one embodiment, such as Figure 7 As shown, this differential trace verification method also includes:

[0115] S50: In response to the user's selection of any geometric violation point or signal distortion risk point in the visualization view, generate a suggested correction scheme.

[0116] Specifically, the system binds a mouse click event listener to each highlighted mark and heatmap area in the visualization view in the background. When the user moves the cursor to any problem area and clicks, the listener is immediately triggered and captures the unique ID of the clicked object. The system then retrieves all the detailed information of the corresponding problem based on the ID, including its type (insufficient spacing or impedance change), specific parameters, location coordinates, etc., and immediately uses this information as input to activate a built-in intelligent suggestion engine based on expert rules and algorithms. Based on the nature of the problem, the engine generates one or more specific operation suggestions aimed at completely fixing the problem in real time within a few hundred milliseconds and presents them on the user interface.

[0117] S60: Statistically validate the proposed modified scheme using Monte Carlo simulation to determine its reliability. If reliable, apply the proposed modified scheme.

[0118] Specifically, before formally presenting any correction scheme generated by the suggestion engine, such as a new routing path, to the user, the system first initiates an internal, rapid reliability assessment process. The core of this process is to simulate the inherent and unavoidable minute dimensional errors in the real-world PCB manufacturing process. For example, the line width may be 0.1 mil wider than the design value, or the dielectric thickness may be 0.2 mil thinner. By applying random perturbations that conform to a normal distribution to these key parameters, the system generates thousands of slightly different virtual samples and performs rapid simulations on each sample to predict the yield and performance stability of the correction scheme under real production conditions. Only when the simulation results show that the scheme has extremely high statistical robustness will the system mark it as verified and formally push it to the user, along with a one-click application button, ensuring that the user adopts a scientifically validated and highly reliable solution.

[0119] In one embodiment, such as Figure 8 As shown, in step S50, which is the step of generating a suggested correction scheme in response to the user's selection of any geometric violation point or signal distortion risk point in the visualization view, the specific steps include:

[0120] S51: If the selected point is a geometric violation and its type is insufficient spacing, the path planning algorithm is invoked, and the routing path is recalculated using the differential pair spacing constraint threshold in the electrical rules as the boundary condition, to generate a new set of path coordinates as a correction scheme suggestion.

[0121] Specifically, when the system detects that a user clicked on a point marked as having insufficient spacing, it immediately activates a dedicated, optimized A* path planning algorithm module. This algorithm sets the start and end points of the non-compliant trace segment as the pathfinding target, defines all other traces, vias, and component pads on the circuit board as insurmountable obstacle areas, and uses the user-defined minimum difference pair spacing constraint threshold as the core, mandatory boundary condition. The algorithm explores a virtual grid map, calculating one or more optimized new routing paths that avoid all obstacles, maintain sufficient spacing throughout, and have the shortest possible total length. It then returns the precise coordinate sequence of this path as a suggested correction scheme. For example, for a trace with a spacing of 3.8 mil but a requirement of 4 mil, by activating the A* path planning algorithm, which treats the surrounding routing space as a map, other traces and components as obstacles, and with the core constraint of maintaining a spacing greater than 4 mil at all times, it automatically calculates a new, collision-free routing path from start to finish that meets the spacing requirements.

[0122] S52: If the selected point is a geometric violation and its type is equal length error, then the geometry generation algorithm is called to generate a serpentine geometry in the available space of the differential routing topology model, and the serpentine geometry is used as a correction scheme suggestion.

[0123] Specifically, when the system detects that the user has selected an equal-length error problem, it first accurately calculates the specific length difference that needs to be compensated between the two differential lines. Then, it automatically analyzes the unrouted blank areas around the differential pair traces, evaluating the geometry and size of these areas. Finally, it calls a parameterized geometry generation algorithm that can generate various tuning modes, such as a standard serpentine or compact accordion-shaped pattern. Within the available space, it automatically and accurately generates a tuned trace geometry with the required compensation length, whose bending radius and spacing conform to manufacturing specifications, and uses the geometry data of this structure as a correction suggestion. For example, if the calculation shows that the P line is 12 mil shorter than the N line, and the equal-length tolerance is 10 mil, then the P line needs to be increased by at least 2 mil. In this case, the geometry generation algorithm will automatically generate a standard serpentine or accordion-shaped trace structure with a specific amplitude and period near a straight path of the P line, based on the available routing space. The precise total length of this structure is exactly the required compensation length, thus ensuring that the corrected P line and N line meet the equal-length requirement.

[0124] S53: If the selected point is a signal distortion risk point, the optimization algorithm is invoked to perform inverse calculation based on the target characteristic impedance and the stack-up parameters in the differential trace topology model to obtain the optimized anti-pad size as a correction scheme suggestion.

[0125] Specifically, this calculation process is a typical inverse optimization process; taking the optimization of the anti-pad diameter A of the via as an example, its goal is to make the equivalent characteristic impedance Z of the via... via As close as possible to the target impedance Z target For example, 100 ohms; the system will first use an approximate analytical formula based on a physical model as the starting point for optimization, for example... However, this is usually not accurate enough because it does not take into account the effect of anti-pads; therefore, the system will use a more accurate numerical optimization algorithm, such as gradient descent or particle swarm optimization; the objective function of the algorithm is defined as Z sim (A) is the actual via impedance calculated by fast electromagnetic field simulation when the anti-pad diameter is A; the algorithm execution flow is as follows: initialize a guessed value A0 for the anti-pad diameter; the iteration loop begins, and in the i-th iteration, calculate the current A. i The corresponding impedance Z sim (A i ) and the objective function value Cost(A) i ); Calculate the gradient by applying A i Apply a small perturbation ΔA and calculate Z. sim (A i +ΔA), thus obtaining the local gradient ∇Cost of the objective function with respect to A; update the parameters, and update the anti-pad diameter A according to the principle of gradient descent. (i+1) =A i -α*∇Cost, where α is the learning rate; loop back to step 2 until Cost(A) is less than a very small threshold, or the number of iterations reaches the upper limit; the final converged value of A is the optimized antipad size recommended by the system that makes the via impedance closest to the target. For example, for a risk point where the impedance drops from 100 ohms to 85 ohms due to a via change in layer, the optimization algorithm will take the via impedance reaching 100 ohms as the optimization target, and use the PCB stack-up parameters such as dielectric thickness and dielectric constant as known conditions. Through the inverse calculation formula of electromagnetic field theory, it will automatically iterate to calculate the optimal diameter of the window on the reference plane layer adjacent to the via, i.e., the antipad, and finally give a suggested value, such as increasing the antipad diameter from 20mil to 25mil.

[0126] In one embodiment, such as Figure 9 As shown, in step S60, which involves statistically validating the proposed corrective scheme using Monte Carlo simulation to determine its reliability, the specific steps include:

[0127] S61: Apply random perturbations to the geometric dimensional parameters in the proposed correction scheme within a preset manufacturing tolerance range to generate a large number of simulation samples.

[0128] Specifically, the system reads a pre-defined, industry-standard manufacturing tolerance table that defines the permissible error range for elements of different dimensions. For example, for a 5mil linewidth suggested in a correction scheme, the tolerance might be ±10%, or ±0.5mil. The system then starts a loop, for example, executing it 1000 times. In each loop, a Gaussian-distributed random number generator is used to generate a random linewidth value within the range of (5-0.5)mil to (5+0.5)mil. At the same time, similar random perturbations may be applied to other key parameters such as dielectric thickness and copper thickness. Each loop generates a simulation sample containing a unique set of random parameters that represents a possible production result, ultimately forming a large, statistically significant set of simulation samples.

[0129] S62: For a large number of simulation samples, perform fast electromagnetic simulation one by one to obtain the corresponding electrical performance parameters after simulation.

[0130] Specifically, the system initiates a parallel processing task, distributing the 1,000 simulation samples generated in the previous step to multiple CPU cores. Each core independently applies the random geometric dimensional parameters from the samples to the electromagnetic model of the modified scheme and performs an optimized, extremely fast electromagnetic simulation calculation, such as using a 2.5D solver, to obtain key electrical performance parameters under this specific combination of dimensions, such as the differential impedance value or S11 return loss value of this segment of the trace. The entire process can complete a comprehensive evaluation of thousands of samples within seconds.

[0131] S63: Statistically determine the proportion of samples whose electrical performance parameters meet the preset design objectives after simulation, and determine the corrective solution as reliable when the proportion of samples exceeds the preset reliability threshold.

[0132] Specifically, after all parallel simulation tasks are completed, the system collects all 1000 simulation results. Then, it counts how many of these 1000 results have differential impedance values ​​that successfully fall within the designer's preset acceptable design target window, such as 90 ohms to 110 ohms. Next, it divides this number of successful samples by the total number of samples, 1000, to calculate the statistical yield of the correction scheme considering manufacturing tolerances. Finally, it compares this calculated yield with a user-configurable reliability threshold representing the project's quality requirements, such as 99.7%, i.e., the 3σ standard. Only when the calculated yield is greater than or equal to this threshold will the system ultimately determine that the correction scheme recommendation is sufficiently robust and reliable, and allow it to be pushed to the user.

[0133] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0134] In one embodiment, an electronic device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 10 As shown, this electronic device includes a processor, memory, network interface, and database connected via a system bus. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and database. The internal memory provides the environment for the operation of the operating system and computer programs in the non-volatile storage media. The database stores data such as PCB design documents, electrical rules, differential trace topology models, and geometric violations. The network interface communicates with external terminals via a network connection. When executed by the processor, the computer program implements a differential trace verification method for a PCB board.

[0135] In one embodiment, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to perform the following steps:

[0136] In response to the acquired PCB design files, determine the differential routing topology model;

[0137] Obtain user-defined electrical rules, perform geometric verification based on differential routing topology model and electrical rules to locate geometric violation points;

[0138] By performing integrity analysis on the preset key structures in the differential wiring topology model, signal distortion risk points can be identified.

[0139] A visualization view is generated based on geometric violation points and signal distortion risk points.

[0140] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method for verifying differential traces on a PCB board, characterized in that, The differential trace verification method includes: In response to the acquired PCB design files, determine the differential routing topology model; Obtain user-defined electrical rules, and perform geometric verification based on the differential routing topology model and the electrical rules to locate geometric violation points; By performing integrity analysis on the preset key structures in the differential routing topology model, signal distortion risk points can be identified. A visualization view is generated based on the geometric violation points and the signal distortion risk points.

2. The differential trace verification method according to claim 1, characterized in that, The step of determining the differential routing topology model in response to the acquired PCB design file specifically includes: The PCB design file is parsed, and the differential pair network in the PCB design file is identified according to the preset naming convention; Based on the differential pair network, the connection relationship between the geometric elements of the differential pair network and the corresponding geometric elements is obtained, wherein the geometric elements include at least traces and vias; The differential routing topology model is constructed based on the geometric elements of the differential pair network and the connection relationships between the geometric elements.

3. The differential trace verification method according to claim 1, characterized in that, The step of obtaining user-defined electrical rules specifically includes: A graphical user interface is provided for displaying a list of rules containing constraint thresholds, the constraint thresholds including at least a difference pair spacing constraint threshold and an equal length tolerance constraint threshold; In response to user input in the graphical user interface, a user-defined rule list is obtained, and the electrical rules are derived based on the rule list.

4. The differential trace verification method according to claim 3, characterized in that, The step of performing geometric verification based on the differential routing topology model and the electrical rules to locate geometric violations specifically includes: By traversing the differential routing topology model, the actual spacing and actual length difference between the two routing lines of the differential pair are calculated through geometric calculations. The difference between the actual spacing and the actual length is compared with the corresponding constraint threshold in the electrical rules; If the actual spacing does not meet the differential pair spacing constraint threshold, the corresponding position point is determined as a geometric violation point of insufficient spacing. If the actual length difference does not meet the equal length tolerance constraint threshold, the corresponding position point is determined as a geometric violation point of equal length error type.

5. The differential trace verification method according to claim 4, characterized in that, The step of determining signal distortion risk points by performing integrity analysis on preset key structures in the differential routing topology model specifically includes: From the differential routing topology model, the acute angle turn between the layer-changing via and the routing path is identified, and the acute angle turn between the layer-changing via and the routing path is the preset key structure. For the layer-changing via and the acute-angle turn, the electromagnetic field solver is called to perform simulation to obtain the corresponding frequency domain parameters within the preset frequency band; Perform an inverse discrete Fourier transform on the frequency domain parameters to generate a time-domain reflection waveform, and identify the impedance abrupt peak in the time-domain reflection waveform; Based on the impedance abrupt change peak, the corresponding physical coordinates are obtained by inverse calculation, and the physical coordinates are determined as the signal distortion risk points.

6. The differential trace verification method according to claim 5, characterized in that, The step of generating a visualization view based on the geometric violation point and the signal distortion risk point specifically includes: Obtain the amplitude of the impedance abrupt change peak, and calculate the degree of deviation between the signal distortion risk point and the target characteristic impedance based on the amplitude; In the EDA interface, the physical locations corresponding to the geometric violation points are highlighted, and according to the degree of deviation, an impedance anomaly heatmap is superimposed on the physical locations corresponding to the signal distortion risk points to construct the visualization view.

7. The differential trace verification method according to claim 6, characterized in that, The differential trace verification method further includes: In response to the user's selection of any of the geometric violation points or signal distortion risk points in the visualization view, a suggested remediation scheme is generated. The proposed correction scheme is statistically validated using Monte Carlo simulation to determine its reliability. If reliable, the proposed correction scheme is then applied.

8. The differential trace verification method according to claim 7, characterized in that, The step of generating a suggested correction scheme in response to a user's selection of any geometric violation point or signal distortion risk point in the visualization view specifically includes: If the selected point is the geometric violation point and its type is insufficient spacing, then the path planning algorithm is invoked, and the routing path is recalculated using the differential pair spacing constraint threshold in the electrical rules as the boundary condition, so as to generate a new set of path coordinates as the proposed correction scheme. If the selected point is the geometric violation point and its type is the equal-length error type, then the geometry generation algorithm is invoked to generate a serpentine geometry structure in the available space of the differential routing topology model, so as to use the serpentine geometry structure as the proposed correction scheme. If the selected point is the signal distortion risk point, the optimization algorithm is invoked to perform inverse calculation based on the target characteristic impedance and the stack-up parameters in the differential trace topology model to obtain the optimized antipad size as the suggested correction scheme.

9. The differential trace verification method according to claim 7, characterized in that, The step of statistically validating the proposed correction scheme using Monte Carlo simulation to determine its reliability specifically includes: For the geometric dimensional parameters in the proposed correction scheme, random perturbations are applied within a preset manufacturing tolerance range to generate a large number of simulation samples; For the large number of simulation samples, fast electromagnetic simulation is performed one by one to obtain the corresponding electrical performance parameters after simulation. The proportion of samples whose electrical performance parameters meet the preset design target after simulation is statistically analyzed, and when the proportion of samples exceeds the preset reliability threshold, the correction scheme is determined to be reliable.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the differential trace verification method for the PCB board as described in any one of claims 1 to 9.

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