Eye pattern generation method and system

Abstract

The invention relates to an eye pattern generation method and system, and the method comprises the steps: triggering a tested device to output a tested signal in a circulating manner for each target delay time and each target threshold voltage, and if the voltage instantaneous value of the tested signal reaches the target threshold voltage at a sampling moment matched with the target delay time, outputting the tested signal; if yes, sampling and counting are carried out, circulation is stopped until a first stopping condition is met, and sampling numerical values of the measured signals at the coordinates are obtained; wherein the target threshold voltage and the target delay time jointly define coordinates in a two-dimensional space for generating the eye pattern; and performing eye pattern generation in the two-dimensional space based on the sampling numerical values of the measured signal at the coordinates to obtain an eye pattern corresponding to the measured device. By adopting the method, the eye pattern generation cost can be reduced.

Description

Technical Field

[0001] This application relates to the field of digital signal technology, and in particular to an eye diagram generation method and system. Background Technology

[0002] An eye diagram is one of the most important graphical tools for evaluating the quality of digital signals. It is a series of digital signal waveforms superimposed together to form a pattern resembling an "eye." The size and clarity of the "eye" in the eye diagram can reflect the quality of the digital signal.

[0003] Traditional techniques utilize high-speed analog-to-digital converters (ADCs) to achieve continuous, high-density signal sampling of the signal waveform, and then superimpose the sampled results to synthesize an eye diagram. However, this method relies heavily on high-speed ADCs, which are expensive, leading to high costs for eye diagram generation. Summary of the Invention

[0004] Therefore, it is necessary to provide an eye diagram generation method and system that can reduce the cost of eye diagram generation in order to address the above-mentioned technical problems.

[0005] Firstly, this application provides an eye diagram generation method, including: For each target delay time and each target threshold voltage, the device under test is triggered to output the signal under test in a loop. If the instantaneous voltage value of the signal under test reaches the target threshold voltage at a sampling time that matches the target delay time, the sampling counting step is performed until the first stopping condition is met and the loop stops, thereby obtaining the sampled value of the signal under test at the coordinates. The target threshold voltage and the target delay time together define the coordinates in the two-dimensional space used to generate the eye diagram. Based on the sampled values ​​of the signal under test at each of the coordinates, an eye diagram is generated in the two-dimensional space to obtain the eye diagram corresponding to the device under test.

[0006] Secondly, this application also provides an eye diagram generation system, characterized in that the system includes a device under test and an electronic device; wherein the electronic device is connected to the device under test and is used to implement the steps of the method according to any one of claims 1 to 8.

[0007] Thirdly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above-described method.

[0008] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps in the above-described method.

[0009] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps in the above-described method.

[0010] The aforementioned eye diagram generation method, system, computer device, storage medium, and computer program product, for each target delay time and each target threshold voltage, cyclically execute the step of triggering the device under test to output the measured signal. If the instantaneous voltage value of the measured signal reaches the target threshold voltage at a sampling time matching the target delay time, a sampling counting step is performed until the first stopping condition is met, at which point the loop stops, and the sampled value of the measured signal at the coordinates is obtained. Here, the target threshold voltage and the target delay time together define the coordinates in the two-dimensional space used to generate the eye diagram. The two basic dimensions of an eye diagram are voltage and time. An eye diagram can be considered as the probability distribution of a signal in a two-dimensional "time-voltage" space. By using the coordinates (target delay time, target threshold voltage), the position within this two-dimensional space can be located. In subsequent iterations, sampling counts are continuously performed to count the number of times the instantaneous voltage value of the measured signal reaches the target threshold voltage at each sampling moment. The larger the sampling count, the greater the probability that the measured signal passes above the (target delay time, target threshold voltage) coordinate. Therefore, the sampled values ​​of the measured signal at the coordinate obtained when the first stopping condition is met can reflect the probability distribution of the measured signal at that coordinate. Thus, based on the sampled values ​​of the measured signal at each coordinate, an eye diagram is generated in two-dimensional space to obtain the eye diagram corresponding to the device under test. Eye diagram generation can be achieved without relying on a high-speed analog-to-digital converter, significantly reducing the cost of eye diagram generation. Attached Figure Description

[0011] Figure 1 This is a flowchart illustrating an eye diagram generation method provided in an embodiment of this application.

[0012] Figure 2 This is a schematic diagram of coordinates in a two-dimensional space provided in an embodiment of this application.

[0013] Figure 3 An eye diagram corresponding to a device under test provided in an embodiment of this application.

[0014] Figure 4 This is a schematic diagram illustrating the connection relationship between an electronic device and a device under test, as provided in an embodiment of this application.

[0015] Figure 5 This is a schematic diagram of various signal and data triggers provided in an embodiment of this application.

[0016] Figure 6A This is a schematic diagram of sampled values ​​at various coordinates provided in an embodiment of this application.

[0017] Figure 6B This is a schematic diagram of frequency values ​​at various coordinates provided in an embodiment of this application.

[0018] Figure 6C This is a schematic diagram showing the location through which a measured signal passes, as provided in an embodiment of this application.

[0019] Figure 7 This is a simplified flowchart illustrating an eye diagram generation method provided in an embodiment of this application.

[0020] Figure 8 This is a structural block diagram of an eye diagram generation system provided in an embodiment of this application.

[0021] Figure 9 This is a structural block diagram of an electronic device provided in an embodiment of this application.

[0022] Figure 10 This is an internal structural diagram of an electronic device provided in an embodiment of this application.

[0023] Figure 11 This is an internal structure diagram of another electronic device provided in an embodiment of this application. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0025] In one exemplary embodiment, such as Figure 1 As shown, a flowchart of an eye diagram generation method is provided. Taking the application of this method to an electronic device as an example, the method includes the following steps 102 to 104.

[0026] Step 102: For each target delay time and each target threshold voltage, the device under test is triggered to output the signal under test in a loop. If the instantaneous voltage value of the signal under test reaches the target threshold voltage at the sampling time that matches the target delay time, the sampling counting step is performed until the first stopping condition is met and the loop stops, and the sampled value of the signal under test at the coordinate is obtained. The target threshold voltage and the target delay time together define the coordinates in the two-dimensional space used to generate the eye diagram.

[0027] For example, the electronic device may, for each of at least one signal waveform, for each of the target delay times and for each of the target threshold voltages, repeatedly execute the trigger signal corresponding to the output signal waveform of the device under test. If the instantaneous voltage value of the measured signal reaches the target threshold voltage at a sampling time that matches the target delay time, a sampling counting step is performed until the first stopping condition is met and the loop stops. The value obtained by the sampling count is recorded as the sampling value of the measured signal corresponding to the signal waveform at the coordinate.

[0028] In some embodiments, an electronic device can obtain the sampled value of the measured signal at the coordinates by storing the value obtained from the sampling count in association with the target delay time and the target threshold voltage.

[0029] In some embodiments, the electronic device may include at least one of a computer device, an oscilloscope, or a programmable logic chip. The computer device may include at least one of a terminal or a server.

[0030] In some embodiments, the electronic device can acquire pattern data of at least one signal waveform. The pattern data may be, but is not limited to, a binary digital sequence describing the signal waveform. For each of the at least one signal waveform, the pattern data of that signal waveform is configured into the storage space of the device under test (DUT). Subsequently, the electronic device can trigger the DUT to output the test signal corresponding to that signal waveform based on the pattern data in the storage space.

[0031] In some embodiments, the target delay time is used to indicate the time difference between the sampling time and the trigger time. The trigger time refers to the moment when the device under test (DUT) is triggered to output the signal under test. Correspondingly, the sampling time refers to the moment when the DUT is delayed by the target delay time compared to the trigger time. The electronic device can repeatedly trigger the DUT to output the signal under test, determine the sampling time that differs from the trigger time by the target delay time, and if the instantaneous voltage value of the signal under test reaches the target threshold voltage at the sampling time, the sampling counting step is performed until the first stop condition is met, at which point the loop stops, and the sampled value of the signal under test at the coordinate is obtained.

[0032] In some embodiments, the electronic device can send a trigger signal to the device under test (DUT) and determine a sampling time that differs from the triggering time of the sent trigger signal by a target delay time. The trigger signal is used to trigger the DUT to output a measured signal. The electronic device can then acquire the measured signal output by the DUT.

[0033] In some embodiments, reaching the target threshold voltage can be, but is not limited to, either the absolute value of the instantaneous voltage value being not less than or exceeding the absolute value of the target threshold voltage.

[0034] In some embodiments, the electronic device may increment the sampling count if the instantaneous voltage value of the measured signal reaches the target threshold voltage at the sampling time.

[0035] In some embodiments, the target threshold voltage and the measured signal may not include negative voltage values. The electronic device may increment the sample count if, at the sampling time, the instantaneous voltage value of the measured signal is not less than the target threshold voltage. Alternatively, the electronic device may increment the sample count if, at the sampling time, the instantaneous voltage value of the measured signal exceeds the target threshold voltage.

[0036] In some embodiments, the first stopping condition may be, but is not limited to, at least one of the following: the current loop duration reaches a preset loop duration, the number of signal triggers reaches a preset number of repeated triggers, or the number of signal captures reaches a preset number of repeated captures. The current loop duration refers to the duration from the start of each loop to the present. It can be understood that at the start of the loop, the current loop duration is zero; during the loop, the current loop duration is continuously accumulated until it reaches the preset loop duration, at which point the loop stops. The number of signal triggers refers to the number of times the device under test (DUT) outputs a measured signal during the loop. It can be understood that at the start of the loop, the number of signal triggers is zero; during the loop, the number of signal triggers is incremented by one each time the DUT outputs a measured signal, until the number of signal triggers reaches the preset number of repeated triggers, at which point the loop stops. The number of signal captures refers to the number of times the instantaneous voltage value is captured at the sampling time in each loop. It can be understood that at the start of the loop, the number of signal captures is zero; during the loop, the number of signal captures is incremented by one each time a sampling time is reached, until the number of signal captures reaches the preset number of repeated captures, at which point the loop stops.

[0037] In some embodiments, the electronic device may repeatedly trigger the device under test to output the signal under test, increment the signal capture count by one, and if the instantaneous voltage value of the signal under test reaches the target threshold voltage at the sampling time that matches the target delay time, the sampling counting step is performed until the signal capture count reaches the preset number of repeated captures, at which point the loop stops and the signal capture count is set to zero.

[0038] It is understandable that, due to various factors such as jitter in the propagation of the measured signal in the circuit, capturing it only once at each coordinate (target delay time, target threshold voltage) would result in a large error. Therefore, it is necessary to capture it multiple times at each coordinate until the preset number of captures is reached in order to obtain a more accurate sampled value at each coordinate.

[0039] In some embodiments, the number of signal captures reaching the preset number of repeated captures may be, but is not limited to, the number of signal captures not being less than the preset number of repeated captures.

[0040] In some embodiments, the electronic device can change the target delay time and the target threshold voltage through nested loops. It is understood that there are at least two loops in each round. One loop refers to the entire process from the start of loop execution to the satisfaction of the first stopping condition. The electronic device can change the target delay time in each round and the target threshold voltage in each loop to achieve sampling counts at each coordinate and obtain the sampled values ​​of the measured signal at each coordinate.

[0041] In some embodiments, the electronic device can also change the target threshold voltage in each cycle and change the target delay time in each cycle to achieve sampling count at each coordinate and obtain the sampled values ​​of the measured signal at each coordinate. Specifically, in each cycle, the electronic device can determine the target threshold voltage in the current cycle, and in each cycle of the current cycle, determine the target delay time in the current cycle. It can repeatedly execute the triggering of the device under test to output the measured signal. If the instantaneous voltage value of the measured signal reaches the target threshold voltage in the current cycle at the sampling time that matches the target delay time in the current cycle, the sampling count step is performed until the first stop condition is met, and the current cycle is stopped. The sampled values ​​of the measured signal at the coordinate are obtained, the next cycle is taken as the current cycle, and the step of determining the target delay time in the current cycle is returned until the second stop condition is met, and the current cycle is stopped. The next cycle is taken as the current cycle, and the step of determining the target threshold voltage in the current cycle is returned until the third stop condition is met, and the sampled values ​​of the measured signal at each coordinate are obtained.

[0042] Step 104: Based on the sampled values ​​of the signal under test at each coordinate, generate an eye diagram in a two-dimensional space to obtain the eye diagram corresponding to the device under test.

[0043] For example, the electronic device can determine a reference coordinate adjacent to that coordinate, with the same target delay time and a higher target threshold voltage, for each coordinate. The sampled values ​​of the signal under test (SUT) at that coordinate and the reference coordinate are subtracted to obtain the frequency value of the SUT at that coordinate. The frequency value of the SUT at each coordinate represents the frequency of the SUT passing through that coordinate or between that coordinate and the corresponding reference coordinate. Based on the frequency values ​​of the SUT at each coordinate, an eye diagram corresponding to the device under test (DUT) is generated in two-dimensional space.

[0044] It is understandable that when the instantaneous voltage value of the measured signal reaches the target threshold voltage, the sampling count increases, and a higher instantaneous voltage value will inevitably reach a lower target threshold voltage. Therefore, the sampled value of the measured signal at each coordinate will necessarily contain the frequency value at that coordinate, which is higher than the target threshold voltage at that coordinate. Thus, only by subtracting the sampled values ​​of the measured signal at that coordinate from the sampled values ​​at the corresponding reference coordinate can the frequency value of the measured signal at that coordinate be obtained.

[0045] For example, for coordinates (t) m V n The sampled values ​​reflect the measured signal at time t. m The instantaneous voltage value at time t is greater than or equal to V. n The probability of . For coordinates (t) m V n The corresponding reference coordinates (t) m V n+1 The sampled values ​​reflect the measured signal at time t. m The instantaneous voltage value at time t is greater than or equal to V. n+1 The probability is greater than or equal to V. n+1 The instantaneous voltage value must be greater than V. n Therefore, the coordinates (t) m V n The sampled value at point (t) minus the coordinate (t) m V n+1 The frequency value obtained from the sampled value at t reflects the measured signal at t. m The instantaneous voltage value at time t is greater than or equal to V. n And less than V n+1 The probability that the measured signal passes through (t) m V n ) or after (t) m V n ) and (t m V n+1 The probability between () and (). The frequency value can more accurately reflect the probability distribution of the measured signal than the sampled value.

[0046] It should be noted that due to various factors, the output signal of the device under test will be different each time it is triggered. For example, the jitter may be different. These differences may cause the sampled value of the measured signal at the coordinates to be smaller than the sampled value at the corresponding reference coordinates, which may result in the frequency value of the measured signal at the coordinates being negative.

[0047] In some embodiments, such as Figure 2The diagram illustrates a coordinate system in a two-dimensional space. The target delay times include t0, t1, t2, t3, t4, t5, t6, and t7… The target threshold voltages include V0, V1, V2, V3, V4, V5, V6, and V7… It can be understood that a target threshold voltage and a target delay time can uniquely identify a coordinate system.

[0048] In some embodiments, the electronic device may include a programmable logic chip and a host computer. The programmable logic chip can feed back the sampled values ​​of the measured signal at various coordinates to the host computer. The host computer can generate an eye diagram in two-dimensional space based on the sampled values ​​of the measured signal at the coordinates to obtain the eye diagram corresponding to the device under test.

[0049] In some embodiments, the host computer may include at least one of a terminal, a server, or a display.

[0050] In some embodiments, the programmable logic chip can generate an eye diagram in a two-dimensional space based on the sampled values ​​of the signal under test at the coordinates, obtain relevant data of the eye diagram corresponding to the device under test, and send the relevant data of the eye diagram to the host computer for display of the eye diagram.

[0051] In some embodiments, such as Figure 3 As shown, an eye diagram corresponding to a device under test (DUT) is provided. Electronic devices can generate an eye diagram by color-filling the coordinates of the measured signal in a two-dimensional space based on the frequency value of the measured signal at the coordinates.

[0052] In the above eye diagram generation method, for each target delay time and each target threshold voltage, the method repeatedly triggers the output of the measured signal from the device under test (DUT). If the instantaneous voltage value of the measured signal reaches the target threshold voltage at a sampling time matching the target delay time, a sampling counting step is performed until the first stopping condition is met, at which point the loop stops and the sampled value of the measured signal at the coordinates is obtained. The target threshold voltage and target delay time together define the coordinates in the two-dimensional space used to generate the eye diagram. The two basic dimensions of the eye diagram are voltage and time. The eye diagram can be considered as the probability distribution of the signal in the "time-voltage" two-dimensional space. By using the coordinates of (target delay time, target threshold voltage), the position in the two-dimensional space can be located. In subsequent loops, the number of times the instantaneous voltage value of the measured signal reaches the target threshold voltage at the sampling time is continuously counted through sampling counting. The larger the sampling count, the greater the probability that the measured signal passes above the coordinate of (target delay time, target threshold voltage). Therefore, the sampled value of the measured signal at the coordinates obtained when the first stopping condition is met can reflect the probability distribution of the measured signal at that coordinate. Therefore, based on the sampled values ​​of the signal under test at each coordinate, an eye diagram is generated in a two-dimensional space to obtain the eye diagram corresponding to the device under test. Eye diagram generation can be achieved without relying on a high-speed analog-to-digital converter, which greatly reduces the cost of eye diagram generation.

[0053] In some embodiments, for each target delay time and each target threshold voltage, the process of triggering the device under test (DUT) to output the measured signal is executed cyclically. If the instantaneous voltage value of the measured signal reaches the target threshold voltage at a sampling time matching the target delay time, a sampling count is performed until a first stop condition is met, at which point the loop stops, and the sampled values ​​of the measured signal at the coordinates are obtained. This includes: using the initial threshold voltage as the target threshold voltage; using the initial delay time as the target delay time; cyclically executing the step of triggering the DUT to output the measured signal, and if the instantaneous voltage value of the measured signal reaches the target threshold voltage at a sampling time matching the target delay time, a sampling count is performed until a first stop condition is met, at which point the loop stops, and the sampled values ​​of the measured signal at the coordinates are recorded; the target delay time is adjusted step by step; the process of returning to the step of triggering the DUT to output the measured signal is executed cyclically until a second stop condition is met, at which point the target threshold voltage is adjusted step by step, and the process of returning to the step of using the initial delay time as the target delay time is executed cyclically until a third stop condition is met, at which point the sampled values ​​of the measured signal at each coordinate are obtained.

[0054] In this context, "stepping" refers to moving forward or backward step by step according to a fixed step size. "Stepping adjustment of the target delay time" means adjusting the target delay time step by step according to the delay step size. "Stepping adjustment of the target threshold voltage" means adjusting the target threshold voltage step by step according to the voltage step size.

[0055] In some embodiments, the second stopping condition may be, but is not limited to, at least one of the following: the target delay time reaches a preset delay threshold, the number of delay steps reaches a preset total number of delay steps, etc. The number of delay steps is used to characterize the number of steps required to step from the initial delay time to the target delay time.

[0056] In some embodiments, the third stopping condition may be, but is not limited to, at least one of the following: the target threshold voltage reaches a preset voltage threshold, the number of voltage steps reaches a preset total number of voltage steps, etc. The number of voltage steps is used to characterize the number of steps required to step from the initial threshold voltage to the target threshold voltage.

[0057] In some embodiments, the electronic device may use an initial threshold voltage as the target threshold voltage in the first cycle and an initial delay time as the target delay time in the first cycle of each cycle. The first cycle is considered the current cycle, and the first iteration is considered the current iteration. In the current iteration of this cycle, the device under test (DUT) is repeatedly triggered to output the measured signal, the signal acquisition count is incremented by one, and if the instantaneous voltage value of the measured signal reaches the target threshold voltage in this cycle at a sampling time matching the target delay time, the sampling counting step continues until the signal acquisition count reaches a preset number of repetitions. Then, the current cycle stops, the signal acquisition count is reset to zero, the sampled value of the measured signal at the coordinates is recorded, and the sampling count is cleared.

[0058] The electronic device can take the next cycle in the current loop as the current loop, add the delay step size to the target delay time to obtain the target delay time in the current loop, increment the delay step count by one, and return to the loop to execute the step of triggering the device under test to output the test signal until the delay step count reaches the preset total number of delay steps, at which point the current loop stops and the delay step count is set to zero.

[0059] The electronic device can treat the next cycle as the current cycle, add the voltage step size to the target threshold voltage to obtain the target threshold voltage in the current cycle, increment the voltage step count by one, and return to the step of using the initial delay time as the target delay time in the first cycle of each cycle until the voltage step count reaches the preset total number of voltage steps, then set the voltage step count to zero to obtain the sampled values ​​of the measured signal at each coordinate.

[0060] In some embodiments, reaching a preset total number of delay steps may mean that the number of delay steps is not less than the preset total number of delay steps.

[0061] In some embodiments, reaching a preset total number of voltage steps may mean that the number of voltage steps is not less than the preset total number of voltage steps.

[0062] In this embodiment, the initial threshold voltage is used as the target threshold voltage; the initial delay time is used as the target delay time; the process of triggering the device under test (DUT) to output the measured signal is executed cyclically. If the instantaneous voltage value of the measured signal reaches the target threshold voltage at a sampling time that matches the target delay time, the sampling counting step is performed until the first stopping condition is met, at which point the loop stops, the sampling values ​​of the measured signal at the coordinates are recorded, and the target delay time is adjusted step by step; the process of triggering the DUT to output the measured signal is executed cyclically again until the second stopping condition is met, at which point the target threshold voltage is adjusted step by step, and the process of using the initial delay time as the target delay time is executed again until the third stopping condition is met, thus obtaining the sampling values ​​of the measured signal at each coordinate. By progressively adjusting the target delay time and target threshold voltage, sufficient sampling is performed in both time and voltage dimensions to obtain the sampled values ​​of the signal under test at each coordinate. These sampled values ​​at each coordinate can fully reflect the probability distribution of the signal under test at each coordinate in the two-dimensional space. Subsequently, based on the sampled values ​​of the signal under test at each coordinate, an eye diagram is generated in the two-dimensional space to obtain the eye diagram corresponding to the device under test, ensuring the accuracy of the eye diagram generation.

[0063] In some embodiments, the method further includes: traversing at least one signal waveform; triggering the device under test (DUT) to output a measured signal, including: triggering the DUT to output the measured signal corresponding to the currently traversed signal waveform; returning to the step of using the initial delay time as the target delay time until a third stop condition is met, and obtaining the sampled values ​​of the measured signal at each coordinate, including: returning to the step of using the initial delay time as the target delay time until the third stop condition is met, obtaining the sampled values ​​of the measured signal corresponding to the currently traversed signal waveform at each coordinate, continuing to traverse at least one signal waveform, and returning to the step of using the initial threshold voltage as the target threshold voltage until the traversal ends, and obtaining the sampled values ​​of the measured signal corresponding to at least one signal waveform at each coordinate; generating an eye diagram in a two-dimensional space based on the sampled values ​​of the measured signal at each coordinate, and obtaining the eye diagram corresponding to the DUT, including: generating an eye diagram in a two-dimensional space based on the sampled values ​​of the measured signal corresponding to at least one signal waveform at each coordinate, and obtaining the eye diagram corresponding to the DUT.

[0064] For example, an electronic device can acquire pattern data of at least one signal waveform. It iterates through at least one signal waveform, configuring the pattern data of the currently iterated signal waveform into the storage space of the device under test (DUT). An initial threshold voltage is used as a target threshold voltage, and an initial delay time is used as a target delay time. A trigger signal is sent to the DUT to trigger it to output the test signal corresponding to the currently iterated signal waveform based on the pattern data in the storage space.

[0065] Each iteration of the signal waveform involves multiple loops to obtain the sampled values ​​of the measured signal at each coordinate. The electronic device can use the initial threshold voltage as the target threshold voltage in the first loop corresponding to the signal waveform, and the initial delay time as the target delay time in the first loop of each loop. The electronic device can use the next loop corresponding to the signal waveform as the current loop, add the voltage step size to the target threshold voltage to obtain the target threshold voltage in the current loop, increment the voltage step count by one, and return to the step of using the initial delay time as the target delay time in the first loop of each loop until the voltage step count reaches the preset total number of voltage steps. This indicates that the multiple loops corresponding to the currently traversed signal waveform have ended, and the sampled values ​​of the measured signal at each coordinate have been obtained. The voltage step count is then set to zero, and the iteration continues with at least one signal waveform. The step of configuring the mode data of the currently traversed signal waveform to the storage space of the device under test continues until the iteration ends. This indicates that the multiple loops corresponding to at least one signal waveform have all ended, and the sampled values ​​of the measured signal at each coordinate have been obtained for at least one signal waveform.

[0066] For each coordinate, the electronic device can determine a reference coordinate that is adjacent to that coordinate, has the same target delay time, and has a higher target threshold voltage. The sampled values ​​of the measured signal corresponding to the signal waveform at that coordinate are subtracted from the sampled values ​​at the reference coordinate to obtain the frequency value of the measured signal corresponding to the signal waveform at that coordinate. Based on the frequency values ​​of the measured signal corresponding to at least one signal waveform at that coordinate, an eye diagram corresponding to the device under test is generated in two-dimensional space.

[0067] In some embodiments, the initial threshold voltage is related to the voltage range corresponding to the signal waveform. The initial delay time is related to the duration of a single bit of the signal waveform. Specifically, the initial threshold voltage can be less than or equal to the minimum voltage value within the voltage range. For example, if the voltage range corresponding to the signal waveform includes 0-3.3V, the initial threshold voltage can be less than or equal to 0. It is understood that different signal waveforms correspond to different voltage ranges, and the corresponding initial threshold voltages can also be different.

[0068] In some embodiments, the initial threshold voltage is related to each voltage range corresponding to at least one signal waveform. Specifically, the initial threshold voltage may be less than or equal to the minimum voltage value within each voltage range. It can be understood that for any signal waveform, the initial threshold voltage may be a fixed value. In some embodiments, to ensure sufficient sampling of the signal under test (DUT) in the time dimension, the sampling time indicated by the initial delay time may be, but is not limited to, one bit earlier than the time when the DUT is detected. In this case, the initial delay time may be, but is not limited to, obtained by subtracting the one bit duration from the signal path delay. The signal path delay is used to characterize the delay time from triggering the output of the DUT signal to detecting the DUT signal. For example, if the one bit duration of the waveform is 2.5 ns, then the initial delay time can be the signal path delay - 2.5 ns.

[0069] In some embodiments, the electronic device has a storage area for storing sampled values ​​at each coordinate. The electronic device can store the values ​​obtained from sampling counts in this storage area to record the sampling counts as the sampled values ​​of the measured signal at the coordinates. It is understood that since the target delay time and target threshold voltage are adjusted in steps, and at least one signal waveform has a specific traversal order, there is a strict sequential correspondence between the target delay time, target threshold voltage, and signal waveform. Therefore, by simply recording the values ​​obtained from sampling counts sequentially at each loop stop, i.e., each time the first stop condition is met, in the aforementioned storage area, each sampled value can be associated with the corresponding signal waveform, target delay time, and target threshold voltage based on the storage order of the sampled values ​​in the storage area. This accurately records the sampled values ​​of the measured signal corresponding to each signal waveform at the coordinates jointly defined by (target delay time, target threshold voltage).

[0070] In this embodiment, at least one signal waveform is traversed; the device under test (DUT) is triggered to output the DUT signal corresponding to the currently traversed signal waveform; the step of using the initial delay time as the target delay time is returned until the third stopping condition is met, obtaining the sampled values ​​of the DUT signal corresponding to the currently traversed signal waveform at each coordinate, and continuing to traverse at least one signal waveform, returning to the step of using the initial threshold voltage as the target threshold voltage until the traversal ends, obtaining the sampled values ​​of the DUT signal corresponding to at least one signal waveform at each coordinate, thus achieving sufficient sampling of at least one signal waveform. Therefore, based on the sampled values ​​of the DUT signal corresponding to at least one signal waveform at each coordinate, an eye diagram is generated in two-dimensional space to obtain the eye diagram corresponding to the DUT. Eye diagram generation can be achieved without relying on a high-speed analog-to-digital converter, greatly reducing the cost of eye diagram generation.

[0071] In some embodiments, if the instantaneous voltage value of the measured signal reaches the target threshold voltage at a sampling time that matches the target delay time, the method includes: generating a comparison signal based on the measured signal and the target threshold voltage; wherein, when the instantaneous voltage value of the measured signal reaches the target threshold voltage, the comparison signal is at a first level; delay counting begins at the triggering time of the measured signal, and a sampling pulse is output when the delay count value matches the target delay time; the sampling pulse is used to indicate the sampling time; if the comparison signal is at the first level when the sampling pulse occurs, sampling counting is performed.

[0072] The trigger time refers to the moment when the device under test (DUT) is triggered to output the signal under test.

[0073] For example, the electronic device can acquire a comparison signal generated based on the measured signal and a target threshold voltage. The first level may include a high level. The electronic device can start delay counting simultaneously with issuing a trigger signal to the device under test (DUT), i.e., at the trigger moment of the measured signal. When the delay count value matches the target delay time, it outputs a sampling pulse. Here, the trigger signal is the signal that triggers the measured signal corresponding to the output waveform of the DUT. The rising edge of the sampling pulse is the sampling moment. If the comparison signal is high at the rising edge of the sampling pulse, sampling counting is performed.

[0074] In some embodiments, the electronic device may include a comparator and a digital-to-analog converter (DAC). Both the device under test (DUT) and the DAC are connected to the comparator. The DUT inputs the measured signal to the comparator. The electronic device can set a target threshold voltage to the DAC to instruct it to output a voltage signal matching the target threshold voltage. The electronic device can input the voltage signal to the comparator via the DAC. The electronic device can generate a comparison signal based on the measured signal and the target threshold voltage using the comparator, and transmit the comparison signal to the electronic device.

[0075] In some embodiments, the delay counting method may include at least one of coarse delay counting and fine delay counting. Specifically, the electronic device may first perform coarse delay counting, then fine delay counting, until the delay count value matches the target delay time. The delay count value can be the sum of the coarse and fine delay counts. Alternatively, the delay count value can be the fine delay count value when the coarse delay count time is fixed. It is understood that since the coarse delay count time is fixed, and different target delay times are achieved by adjusting the fine delay count, it is only necessary to match the fine delay count value with the target delay time to determine whether the sampling time has been reached.

[0076] In some embodiments, the electronic device includes a delay chain. The electronic device can perform coarse delay counting, generate a raw pulse after the coarse delay counting is completed, input the raw pulse to the delay chain, and after fine delay counting by the delay chain, if the delay count value matches the target delay time, a sampled pulse output by the delay chain is obtained.

[0077] In this embodiment, a comparison signal is generated based on the measured signal and the target threshold voltage. The comparison signal can characterize the magnitude relationship between the instantaneous voltage values ​​of the measured signal and the target threshold voltage. Delay counting begins at the trigger moment of the measured signal. When the delay count value matches the target delay time, a sampling pulse is output. The sampling moment can be accurately located through delay counting and sampling pulse. Furthermore, if the comparison signal is at the first level when the sampling pulse appears, sampling counting is performed, which can ensure the accuracy of sampling.

[0078] In some embodiments, generating a comparison signal based on the measured signal and the target threshold voltage includes: controlling the digital-to-analog converter to output a voltage signal that matches the target threshold voltage; inputting the measured signal to the first input terminal of the comparator and inputting the voltage signal to the second input terminal of the comparator to obtain the comparison signal output by the comparator.

[0079] For example, an electronic device can set a target threshold voltage to a digital-to-analog converter (DAC) to instruct the DAC to output a voltage signal that matches the target threshold voltage. The device under test (DUT) can input the measured signal to the first input of a comparator. The DAC can input a voltage signal to the second input of the comparator. The comparator can generate a comparison signal by comparing the measured signal with the voltage signal.

[0080] In some embodiments, the first input terminal can be a non-inverting input terminal, and the second input terminal can be an inverting input terminal. For example... Figure 4 The diagram illustrates the connection between an electronic device and a device under test (DUT). The electronic device, shown in the dashed box, includes a programmable logic chip (FPGA), a digital-to-analog converter (DAC), a host computer, and a comparator. The FPGA is connected to the DUT, the DAC, and the host computer. The DUT is connected to the non-inverting input of the comparator, and the DAC is connected to the inverting input of the comparator. The comparator's output is connected to the FPGA.

[0081] A programmable logic chip (PLC) can set the mode data corresponding to the waveform to the device under test (DUT), and then send a trigger signal to trigger the DUT to output the corresponding measured signal. The measured signal output by the DUT is transmitted to the non-inverting input of a comparator. The PLC can also set a target threshold voltage to the digital-to-analog converter (DAC) to instruct the DAC to output a voltage signal matching the target threshold voltage. The voltage signal output by the DAC is transmitted to the inverting input of the comparator. The comparator compares the two signals at the non-inverting and inverting inputs and outputs a comparison signal. This comparison signal is transmitted to the PLC. If the comparison signal is high at the sampling time, the PLC can perform sample counting. The PLC can also feed back the sampled values ​​of the measured signal at each coordinate point to the host computer.

[0082] In this embodiment, the digital-to-analog converter (DAC) is controlled to output a voltage signal that matches the target threshold voltage. The DAC can provide a stable and accurate voltage signal. The measured signal is input to the first input terminal of the comparator, and the voltage signal is input to the second input terminal of the comparator. The comparator can accurately determine the magnitude relationship between the measured signal and the voltage signal, and output a comparison signal that accurately reflects the magnitude relationship.

[0083] In some embodiments, if the comparison signal is at a first level when the sampling pulse occurs, sampling counting is performed, including: inputting the sampling pulse to the clock terminal of the data flip-flop; inputting the comparison signal to the data terminal of the data flip-flop; and if the output terminal level of the data flip-flop is at a first level at the rising edge of the sampling pulse, sampling counting is performed.

[0084] For example, a programmable logic chip may include a data flip-flop. The data terminal of the data flip-flop is connected to the output terminal of a comparator. The comparator can transmit a comparison signal to the data terminal of the data flip-flop. The programmable logic chip can input a sampling pulse to the clock terminal of the data flip-flop and acquire the output level of the data flip-flop at the rising edge of the sampling pulse. If the output level is the first level, sampling and counting are performed.

[0085] In some embodiments, such as Figure 5The diagram illustrates various signals and data triggers. The signal waveform represents the ideal waveform expected to be output by the device under test (DUT). Deviations between the signal waveform and the corresponding DUT signal are significant reasons for the reduced opening and blurred outline of the "eye" in the eye diagram. The comparison signal is a binary digital level signal. The rising edge of the sampling pulse is delayed by a target delay time tdelay compared to the trigger moment. The sampling pulse is input to the clock terminal CLK of the data trigger, and the comparison signal is input to the data terminal D of the data trigger. At the rising edge of the sampling pulse, the output level of the data trigger's output terminal Q changes to the current level of the data terminal D, i.e., the level of the comparison signal at the rising edge of the sampling pulse.

[0086] In this embodiment, the sampling pulse is input to the clock terminal of the data trigger; the comparison signal is input to the data terminal of the data trigger; if the output level of the data trigger is at the first level at the rising edge of the sampling pulse, sampling counting is performed. By accurately sampling the level of the comparison signal at the rising edge of the sampling pulse through the data trigger, the accuracy of the sampling counting can be guaranteed.

[0087] In some embodiments, an eye diagram is generated in a two-dimensional space based on the sampled values ​​of the signal under test at each coordinate to obtain the eye diagram corresponding to the device under test. This includes: for each coordinate in the two-dimensional space, determining a reference coordinate that is adjacent to the coordinate, has the same target delay time, and has a higher target threshold voltage; subtracting the sampled values ​​of the signal under test at the coordinate and the reference coordinate respectively to obtain the frequency value of the signal under test at the coordinate; and generating an eye diagram in a two-dimensional space based on the frequency value of the signal under test at each coordinate to obtain the eye diagram corresponding to the device under test.

[0088] For example, an electronic device can determine a reference coordinate for each coordinate in a two-dimensional space that has the same target delay time as that coordinate and is one voltage step higher than the target threshold voltage of that coordinate. For each signal waveform corresponding to the signal under test, the sampled value of the signal under test at that coordinate is subtracted from the sampled value of the signal under test at the reference coordinate to obtain the frequency value of the signal under test at that coordinate.

[0089] The electronic device can sum the frequency values ​​of the measured signal corresponding to at least one signal waveform at each coordinate to obtain the total frequency at that coordinate. The total frequency at each coordinate represents the sum of the frequencies of the measured signal corresponding to at least one signal waveform passing through that coordinate or between that coordinate and the corresponding reference coordinate. Based on the total frequency at each coordinate, an eye diagram is generated in two-dimensional space to obtain the eye diagram corresponding to the device under test.

[0090] In some embodiments, such as Figure 6AThe diagram illustrates the sampled values ​​at various coordinates. The capture was repeated 100 times, and the sampled value at each coordinate was no greater than 100. Figure 6B As shown, a schematic diagram of the frequency values ​​at various coordinates is provided. Figure 6A In this context, by subtracting the sampled values ​​at two adjacent coordinates along the voltage dimension, the frequency value at the coordinate of the low threshold voltage is obtained. For example... Figure 6C As shown, this diagram illustrates the location traversed by the measured signal. A frequency value greater than 0 at a coordinate indicates that the measured signal will pass through that coordinate or between that coordinate and the corresponding reference coordinate. After filling the corresponding grid with grayscale, the positions of these grayscale fills collectively reflect the location traversed by the measured signal.

[0091] In some embodiments, an electronic device can generate an eye diagram in two-dimensional space by connecting the coordinates of frequencies or total frequencies that are greater than the eye diagram determination threshold, thereby obtaining the eye diagram corresponding to the device under test. The eye diagram determination threshold may, but is not limited to, 0.

[0092] In this embodiment, for each coordinate in the two-dimensional space, a reference coordinate is determined that is adjacent to the coordinate, has the same target delay time, and has a higher target threshold voltage. The sampled values ​​of the signal under test at the coordinate and the reference coordinate are subtracted to obtain the frequency value of the signal under test at the coordinate. The frequency value can more accurately reflect the probability distribution of the signal under test than the sampled value. Furthermore, based on the frequency value of the signal under test at each coordinate, an eye diagram is generated in the two-dimensional space to obtain the eye diagram corresponding to the device under test, ensuring the accuracy of the eye diagram generation.

[0093] In some embodiments, an eye diagram is generated in a two-dimensional space based on the frequency value of the signal under test at each coordinate to obtain the eye diagram corresponding to the device under test, including: determining the target color data corresponding to the coordinate from each preset color data based on the frequency value of the signal under test at each coordinate; and filling the color at each coordinate in the two-dimensional space according to the corresponding target color data to obtain the eye diagram corresponding to the device under test.

[0094] For example, different preset color data correspond to different color filling conditions. The electronic device can, for each coordinate, sum the frequency values ​​of the measured signal corresponding to at least one signal waveform at that coordinate to obtain the total frequency at that coordinate. From the various color filling conditions, a target filling condition satisfied by the total frequency at that coordinate is determined, and the preset color data corresponding to the target filling condition is used as the target color data. The coordinate in two-dimensional space is filled with a color that matches the target color data to obtain the eye diagram corresponding to the device under test.

[0095] In some embodiments, the color fill condition may be, but is not limited to, at least one of a color fill threshold or a color fill range. Specifically, the electronic device can determine the target fill range in which the total frequency at the coordinate lies from each color fill range, and use the preset color data corresponding to the target fill range as the target color data. The electronic device can also determine the target fill threshold reached by the total frequency at the coordinate from each color fill threshold, and use the preset color data corresponding to the target fill threshold as the target color data. For example, if the total frequency is greater than or equal to the first color fill threshold but less than the second color fill threshold, the target fill threshold reached by the total frequency can be considered to be the first color fill threshold.

[0096] In this embodiment, the frequency value can more accurately reflect the probability distribution of the measured signal than the sampled value. Based on the frequency value of the measured signal at each coordinate, the target color data corresponding to each coordinate is determined from each preset color data. Then, according to the corresponding target color data, color is filled at each coordinate in the two-dimensional space to obtain the eye diagram corresponding to the device under test. Different preset color data can be used to more intuitively identify the probability distribution of the eye diagram in the two-dimensional space, ensuring the effect of eye diagram generation.

[0097] In some embodiments, such as Figure 7 The diagram shows a simplified flowchart of an eye diagram generation method. The example used is a programmable logic chip applied in electronic devices.

[0098] The programmable logic chip first undergoes hardware initialization.

[0099] Programmable logic chips (PLCs) can acquire waveform mode data from traversed waveforms, using the initial threshold voltage as the target threshold voltage and the initial delay time as the target delay. Specifically, the PLC can set the waveform mode data to the device under test (DUT).

[0100] Programmable logic chips can set target threshold voltages. Specifically, the target threshold voltage can be set to the digital-to-analog converter (DAC) to instruct the DAC to output a voltage signal that matches the target threshold voltage.

[0101] Programmable logic chips can send trigger signals to trigger the device under test (DUT) to output a waveform corresponding to the measured signal. In other words, the DUT can output the corresponding measured signal based on the waveform pattern data upon receiving the trigger signal.

[0102] The device under test (DUT) is connected to the non-inverting input of the comparator, and the digital-to-analog converter (DAC) is connected to the inverting input. The DUT's output signal is input to the non-inverting input of the comparator, and the DAC's output voltage signal is input to the inverting input. The comparator then compares the DUT signal with the voltage signal and outputs a comparison signal. The data input of the data flip-flop in the programmable logic chip is connected to the comparator, and the comparator's output comparison signal is input to the data input of the data flip-flop.

[0103] Programmable logic chips can perform coarse delay counting at the moment a trigger signal is issued. After the coarse delay counting ends, fine delay counting is triggered until the delay count value matches the target delay time.

[0104] The programmable logic chip can increment the signal capture count by 1, obtain the output level of the data flip-flop, and update the sampling count. Specifically, when the delay count value matches the target delay time, the programmable logic chip can input a sampling pulse to the clock terminal of the data flip-flop, causing the output level of the data flip-flop to change to the level of the comparison signal at the rising edge of the sampling pulse. Furthermore, if the output level of the data flip-flop is high, the programmable logic chip can increment the sampling count by 1.

[0105] The programmable logic chip can return to the step of triggering the output waveform of the device under test (DUT) corresponding to the measured signal when the number of signal captures is less than a preset number of repetitions. When the number of signal captures is greater than or equal to the preset number of repetitions, the number of signal captures is cleared to 0, the sampling count is recorded, the sampling count is cleared to 0, and the target delay time is adjusted in steps, with the delay step count incremented by 1. Specifically, the programmable logic chip can record the sampling count as the sample value at the coordinate (target delay time, target threshold voltage), and then clear the sampling count to 0. The target delay time is adjusted in steps by adding the delay step size to obtain the new target delay time.

[0106] The programmable logic chip can return to the step of setting the target delay time when the number of delay steps is less than the preset total number of delay steps. When the number of delay steps is greater than or equal to the preset total number of delay steps, the number of delay steps is reset to 0, the initial delay time is used as the target delay time, and the target threshold voltage is adjusted in steps, with the voltage step count incremented by 1. Specifically, the programmable logic chip can add a voltage step size to the target threshold voltage to achieve step adjustment of the target threshold voltage and obtain a new target threshold voltage.

[0107] The programmable logic chip can return to the step of setting the target threshold voltage when the number of voltage steps is less than a preset number of voltage steps. When the number of voltage steps is greater than or equal to the preset total number of voltage steps, the number of voltage steps is cleared to 0, and at least one signal waveform is traversed again to obtain the pattern data of the traversed waveform. The initial threshold voltage is used as the target threshold voltage, and the initial delay time is used as the target delay time. It can be understood that different signal waveforms may correspond to different voltage ranges, and therefore, the initial threshold voltages corresponding to different signal waveforms may also be different. At least one signal waveform may correspond to the same single-bit duration, and therefore, the initial delay times corresponding to different signal waveforms may be the same. The programmable logic chip can obtain the pattern data of the traversed waveforms and the corresponding initial threshold voltage.

[0108] The programmable logic chip (PLC) can return to the step of setting the waveform mode data if the traversal is not yet complete. If the traversal is complete, data processing is performed to generate the eye diagram. Specifically, data processing and eye diagram generation can be implemented by a host computer. The PLC can feed back the sampled values ​​of the measured signal at each coordinate point corresponding to each signal waveform to the host computer. The host computer can generate an eye diagram in two-dimensional space based on the sampled values ​​of the measured signal at each coordinate point corresponding to each signal waveform, obtain the eye diagram corresponding to the device under test, and display the eye diagram corresponding to the device under test on the display.

[0109] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0110] Based on the same inventive concept, this application provides an eye diagram generation system for implementing the eye diagram generation method described above. The solution provided by this system is similar to the implementation described in the above method; therefore, the specific limitations in one or more eye diagram generation system embodiments provided below can be found in the limitations of the eye diagram generation method described above, and will not be repeated here.

[0111] In one exemplary embodiment, such as Figure 8As shown, an eye diagram generation system 800 is provided, including: a device under test 802 and an electronic device 804; wherein, the electronic device 804 is connected to the device under test 802 and is used to implement the steps in the above method embodiments.

[0112] In some embodiments, the device under test 802 is used to trigger the output signal waveform corresponding to the test signal by the programmable logic chip.

[0113] In some embodiments, such as Figure 9 As shown, an electronic device 804 is provided, including a programmable logic chip 902, a host computer 904, a comparator 906, and a digital-to-analog converter 908.

[0114] In some embodiments, the programmable logic chip 902 is used to cyclically execute the step of triggering the device under test (DUT) to output the DUT signal for each target delay time and each target threshold voltage. If the instantaneous voltage value of the DUT signal reaches the target threshold voltage at a sampling time matching the target delay time, a sampling counting step is performed until the first stopping condition is met and the loop stops, thereby obtaining the sampled value of the DUT signal at the coordinates. The target threshold voltage and the target delay time together define the coordinates in the two-dimensional space used to generate the eye diagram. The sampled value of the DUT signal at the coordinates is fed back to the host computer 904. The host computer 904 is used to generate an eye diagram in the two-dimensional space based on the sampled value of the DUT signal at each coordinate, thereby obtaining the eye diagram corresponding to the DUT.

[0115] In some embodiments, the programmable logic chip 902 is further configured to: use an initial threshold voltage as a target threshold voltage; use an initial delay time as a target delay time; repeatedly execute the step of triggering the device under test to output the signal under test; if the instantaneous voltage value of the signal under test reaches the target threshold voltage at a sampling time matching the target delay time, then perform sampling counting until the first stop condition is met, then stop the loop; record the sampling values ​​of the signal under test at the coordinates; and adjust the target delay time step by step; return to repeatedly execute the step of triggering the device under test to output the signal under test until the second stop condition is met, then adjust the target threshold voltage step by step, and return to the step of using the initial delay time as the target delay time until the third stop condition is met, thus obtaining the sampling values ​​of the signal under test at each coordinate; and feed back the sampling values ​​of the signal under test at each coordinate to the host computer 904.

[0116] In some embodiments, the programmable logic chip 902 is further configured to traverse at least one signal waveform; trigger the device under test (DUT) to output the DUT signal corresponding to the currently traversed signal waveform; return to the step of using the initial delay time as the target delay time until the third stop condition is met, obtain the sampled values ​​of the DUT signal corresponding to the currently traversed signal waveform at each coordinate, continue traversing at least one signal waveform, and return to the step of using the initial threshold voltage as the target threshold voltage until the traversal ends, obtain the sampled values ​​of the DUT signal corresponding to at least one signal waveform at each coordinate; feed back the sampled values ​​of the DUT signal corresponding to at least one signal waveform at each coordinate to the host computer 904; the host computer 904 is further configured to generate an eye diagram in a two-dimensional space based on the sampled values ​​of the DUT signal corresponding to at least one signal waveform at each coordinate, and obtain the eye diagram corresponding to the DUT.

[0117] In some embodiments, comparator 906 is used to generate a comparison signal based on the measured signal and a target threshold voltage; wherein, when the instantaneous voltage value of the measured signal reaches the target threshold voltage, the comparison signal is at a first level; the programmable logic chip is also used to start delay counting at the trigger time of the measured signal, and output a sampling pulse when the delay count value matches the target delay time; the sampling pulse is used to indicate the sampling time; if the comparison signal is at the first level when the sampling pulse appears, sampling counting is performed.

[0118] In some embodiments, the digital-to-analog converter 908 is connected to the programmable logic chip 902 and the second input terminal of the comparator 906; the programmable logic chip 902 is further configured to set a target threshold voltage to the digital-to-analog converter; the digital-to-analog converter 908 is configured to output a voltage signal that matches the target threshold voltage; the device under test 802 is further configured to input the measured signal to the first input terminal of the comparator; the digital-to-analog converter 908 is further configured to input a voltage signal to the second input terminal of the comparator; the comparator 906 is configured to compare the measured signal and the voltage signal to output a comparison signal.

[0119] In some embodiments, the programmable logic chip 902 includes a data trigger; the data terminal of the data trigger is connected to a comparator; the programmable logic chip 902 is further configured to input a sampling pulse to the clock terminal of the data trigger; the comparator 906 is further configured to input a comparison signal to the data terminal of the data trigger; the programmable logic chip 902 is further configured to perform sampling counting if the output level of the data trigger is a first level at the rising edge of the sampling pulse.

[0120] In some embodiments, the host computer 904 is further configured to, for each coordinate in the two-dimensional space, determine a reference coordinate that is adjacent to the coordinate, has the same target delay time, and has a higher target threshold voltage; subtract the sampled values ​​of the measured signal at the coordinate and the reference coordinate respectively to obtain the frequency value of the measured signal at each coordinate; and generate an eye diagram in the two-dimensional space based on the frequency value of the measured signal at the coordinate to obtain the eye diagram corresponding to the device under test 802.

[0121] In some embodiments, the host computer 904 is further configured to determine the target color data corresponding to each coordinate from each preset color data based on the frequency value of the signal under test at each coordinate; and to fill the color at each coordinate in the two-dimensional space according to the corresponding target color data to obtain the eye diagram corresponding to the device under test.

[0122] In some embodiments, the programmable logic chip 902 is connected to the device under test 802, the output of the comparator 906, and the input of the digital-to-analog converter 908, respectively; the first input of the comparator 906 is connected to the device under test 802, and the second input of the comparator 906 is connected to the output of the digital-to-analog converter 908.

[0123] The various devices or equipment in the aforementioned eye diagram generation system can be implemented entirely or partially through software, hardware, or a combination thereof. These devices or equipment can be embedded in or independent of the processor in a computer device in hardware form, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each of the above devices or equipment.

[0124] In one exemplary embodiment, an electronic device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 10 As shown, this electronic device includes a processor, memory, input / output (I / O) interfaces, and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores the operating system, computer programs, and a database. The internal memory provides the environment for the operation of the operating system and computer programs in the non-volatile storage medium. The database stores the sampled values ​​or total frequency of at least one signal waveform corresponding to the measured signal at each coordinate. The I / O interfaces are used for information exchange between the processor and external devices. The communication interface is used for communication with external terminals via a network connection. When executed by the processor, the computer program implements an eye diagram generation method.

[0125] In one exemplary embodiment, an electronic device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 11 As shown, the electronic device includes a processor, memory, input / output interface, communication interface, display unit, and input device. The processor, memory, and input / output interface are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interface. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The input / output interface is used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, NFC (Near Field Communication), or other technologies. When the computer program is executed by the processor, it implements an eye diagram generation method. The display unit is used to form a visually visible image and can be a display screen, projection device, or virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the electronic device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the electronic device, or external keyboards, touchpads, or mice, etc.

[0126] Those skilled in the art will understand that Figure 10 or Figure 11 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the electronic device to which the present application is applied. The specific electronic device may include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements.

[0127] In one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0128] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0129] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0130] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0131] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0132] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. An eye diagram generation method, characterized in that, The method includes: For each target delay time and each target threshold voltage, the device under test is triggered to output the signal under test in a loop. If the instantaneous voltage value of the signal under test reaches the target threshold voltage at a sampling time that matches the target delay time, the sampling counting step is performed until the first stopping condition is met and the loop stops, thereby obtaining the sampled value of the signal under test at the coordinates. The target threshold voltage and the target delay time together define the coordinates in the two-dimensional space used to generate the eye diagram. Based on the sampled values ​​of the signal under test at each of the coordinates, an eye diagram is generated in the two-dimensional space to obtain the eye diagram corresponding to the device under test.

2. The method according to claim 1, characterized in that, For each target delay time and each target threshold voltage, the process of cyclically triggering the device under test to output the measured signal is executed. If, at a sampling time matching the target delay time, the instantaneous voltage value of the measured signal reaches the target threshold voltage, a sampling counting step is performed until the first stopping condition is met, at which point the loop stops, and the sampled value of the measured signal at the coordinates is obtained. This includes: Use the initial threshold voltage as the target threshold voltage; Use the initial delay time as the target delay time; The process involves repeatedly triggering the device under test (DUT) to output the signal under test. If the instantaneous voltage value of the signal under test reaches the target threshold voltage at a sampling time that matches the target delay time, the sampling counting step is performed until the first stopping condition is met, at which point the loop stops. The sampling value of the signal under test at the coordinates is recorded, and the target delay time is adjusted step by step. The process returns to the step of triggering the output of the test signal by the device under test in a loop until the second stop condition is met. The target threshold voltage is then adjusted step by step, and the process returns to the step of using the initial delay time as the target delay time until the third stop condition is met, thus obtaining the sampled values ​​of the test signal at each of the coordinates.

3. The method according to claim 2, characterized in that, The method further includes: Traverse at least one signal waveform; The triggering of the device under test to output the test signal includes: Trigger the device under test to output the measured signal corresponding to the currently traversed signal waveform; The step of returning to the initial delay time as the target delay time, until the third stopping condition is met, to obtain the sampled values ​​of the measured signal at each of the coordinates, includes: Return to the step of using the initial delay time as the target delay time until the third stopping condition is met, obtain the sampled values ​​of the measured signal at each of the coordinates corresponding to the currently traversed signal waveform, continue traversing the at least one signal waveform, and return to the step of using the initial threshold voltage as the target threshold voltage until the traversal ends, obtain the sampled values ​​of the measured signal at each of the coordinates corresponding to the at least one signal waveform; The step of generating an eye diagram in the two-dimensional space based on the sampled values ​​of the signal under test at each of the coordinates to obtain the eye diagram corresponding to the device under test includes: Based on the sampled values ​​of the signal under test at each of the coordinates corresponding to the at least one signal waveform, an eye diagram is generated in the two-dimensional space to obtain the eye diagram corresponding to the device under test.

4. The method according to claim 1, characterized in that, If, at a sampling time matching the target delay time, the instantaneous voltage value of the measured signal reaches the target threshold voltage, then sampling counting is performed, including: A comparison signal is generated based on the measured signal and the target threshold voltage; wherein, when the instantaneous voltage value of the measured signal reaches the target threshold voltage, the comparison signal is at a first level; Delay counting begins at the trigger time of the signal under test, and a sampling pulse is output when the delay count value matches the target delay time; the sampling pulse is used to indicate the sampling time. If the comparison signal is at the first level when the sampling pulse occurs, then sampling counting is performed.

5. The method according to claim 4, characterized in that, The generation of a comparison signal based on the measured signal and the target threshold voltage includes: Control the digital-to-analog converter to output a voltage signal that matches the target threshold voltage; The measured signal is input to the first input terminal of the comparator, and the voltage signal is input to the second input terminal of the comparator to obtain the comparison signal output by the comparator.

6. The method according to claim 4, characterized in that, If the comparison signal is at the first level when the sampling pulse occurs, then sampling counting is performed, including: The sampling pulse is input to the clock terminal of the data trigger; The comparison signal is input to the data terminal of the data trigger. If the output level of the data trigger is the first level at the rising edge of the sampling pulse, then sampling counting is performed.

7. The method according to any one of claims 1 to 6, characterized in that, The step of generating an eye diagram in the two-dimensional space based on the sampled values ​​of the signal under test at each of the coordinates to obtain the eye diagram corresponding to the device under test includes: For each coordinate in the two-dimensional space, a reference coordinate is determined that is adjacent to the coordinate, has the same target delay time, and has a higher target threshold voltage; Subtract the sampled values ​​of the measured signal at the coordinate and the reference coordinate respectively to obtain the frequency value of the measured signal at the coordinate. Based on the frequency values ​​of the signal under test at each of the coordinates, an eye diagram is generated in the two-dimensional space to obtain the eye diagram corresponding to the device under test.

8. The method according to claim 7, characterized in that, The step of generating an eye diagram in the two-dimensional space based on the frequency values ​​of the signal under test at each of the coordinates to obtain the eye diagram corresponding to the device under test includes: Based on the frequency value of the measured signal at each coordinate, the target color data corresponding to each coordinate is determined from each preset color data; Based on the corresponding target color data, color is filled at each of the coordinates in the two-dimensional space to obtain the eye diagram corresponding to the device under test.

9. An eye diagram generation system, characterized in that, The system includes the device under test and electronic equipment; The electronic device is connected to the device under test and is used to implement the steps of the method according to any one of claims 1 to 8.

10. The system according to claim 9, characterized in that, The electronic device includes a programmable logic chip, a comparator, and a digital-to-analog converter; wherein the programmable logic chip is connected to the device under test, the output of the comparator, and the input of the digital-to-analog converter; the first input of the comparator is connected to the device under test, and the second input of the comparator is connected to the output of the digital-to-analog converter.

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