Control method and device for improving current-carrying capability of hybrid device power module

Abstract

The invention relates to the technical field of electric drive system power control, and discloses a control method and device for improving the current-carrying capacity of a hybrid device power module, and the method comprises the steps: obtaining the magnitude and direction of each phase of current of the hybrid device power module under a locked-rotor condition, and positioning a current bottleneck phase; adjusting the duty ratio of the upper and lower bridge arms of each phase of the hybrid device power module, and transferring the conduction loss of the current bottleneck phase between the upper and lower bridge arms; selecting at least two PWM wave sending modes, adjusting the switching frequency proportion of different PWM wave sending modes, and continuously distributing the switching loss of each device in the hybrid device power module; the method is based on the duty ratio of upper and lower bridge arms of each phase of the hybrid device power module and the wave sending mode of each device. The current-carrying capacity is optimized through a two-degree-of-freedom loss adjustment strategy, and the hardware cost is remarkably reduced while the current-carrying capacity of the hybrid device power module under the locked-rotor working condition is effectively improved.

Description

Technical Field

[0001] This invention relates to the field of power control technology for electric drive systems, and more specifically to a control method and apparatus for improving the current carrying capacity of power modules in hybrid devices. Background Technology

[0002] Stall capability is one of the important performance parameters of electric drive products, reflecting the vehicle's hill-start ability and directly determining key performance aspects such as maximum starting gradient. Stall capability is primarily limited by the current output capacity of the electronic control power module; therefore, electronic control power module products often need to meet high stall capability requirements. Traditional methods to improve stall capability mainly involve increasing the amount of chips used, but this approach has the following significant drawbacks: 1. High cost and waste of resources: Increasing the amount of chips directly leads to an increase in hardware costs. Furthermore, due to the fixed current direction under stall conditions (alternating current under non-rotating conditions), the loss distribution of each bridge arm in the power module is uneven. Some bottleneck bridge arms (bridge arms that bear switching losses and high current conduction losses) have excessively high temperatures, while the remaining bridge arms have low losses and idle performance, making it impossible to fully utilize the chip's capabilities.

[0003] 2. Insufficient flexibility in loss adjustment: Under rotating conditions, different devices on the same bridge arm can use alternating current to achieve different switching sequences at different instantaneous currents, thus allowing switching losses to vary with the alternating AC current. Furthermore, the current threshold for these changes can be continuously adjusted to balance losses. However, under stall conditions, the current is DC. Traditional control methods have a fixed duty cycle of 50% when the output voltage is close to zero phase, limiting the application to a single PWM waveform mode. This prevents continuous adjustment of switching losses and further exacerbates the overload problem of the bottleneck bridge arm.

[0004] In summary, existing technologies rely on increasing the number of chips to improve stall capability, which has inherent drawbacks such as high hardware costs and poor flexibility in loss adjustment. Therefore, there is an urgent need for a technical solution that can improve the current carrying capacity of hybrid device power modules through control strategy optimization. Summary of the Invention

[0005] In view of this, the present invention provides a control method and apparatus for improving the current carrying capacity of a power module of a hybrid device, so as to solve the problems of high hardware cost and poor flexibility of loss adjustment that exist in the prior art in which the improvement of stall capability depends on increasing the number of chips.

[0006] In a first aspect, the present invention provides a control method for improving the current-carrying capacity of a hybrid device power module, wherein the hybrid device power module includes two controllable devices integrated in parallel and each having a corresponding freewheeling diode, and the method includes: The magnitude and direction of the current in each phase of the hybrid device power module under stall conditions are obtained, and the current bottleneck phase is located. Adjust the duty cycle of the upper and lower bridge arms of each phase of the hybrid device power module to transfer the conduction loss of the current bottleneck phase between its upper and lower bridge arms. Select at least two PWM waveform modes, adjust the switching frequency ratio of different PWM waveform modes, and continuously distribute the switching losses of each device in the hybrid device power module. Based on the duty cycle of each phase upper and lower bridge arm of the hybrid device power module and the waveform of each device, the loss distribution of different devices in the hybrid device power module is adjusted while ensuring the same output current.

[0007] This invention provides a control method for improving the current-carrying capacity of a hybrid device power module. It optimizes current-carrying capacity through a two-degree-of-freedom loss adjustment strategy: the first degree of freedom adjusts the duty cycle of the upper and lower bridge arms of each phase to directionally transfer the conduction loss of the bottleneck bridge arm to the non-bottleneck bridge arm, balancing the conduction loss distribution of the bridge arms; the second degree of freedom uses dynamic alternation of various PWM waveform modes and proportional control of switching frequency to achieve continuous and precise allocation of switching losses between the two parallel integrated controllable devices, avoiding overload of a single device. This method requires no additional chip usage, effectively improving the current-carrying capacity of the hybrid device power module under stall conditions while significantly reducing hardware costs, solving the economic and performance waste problems of traditional chip stacking-for-performance solutions.

[0008] In one optional implementation, adjusting the duty cycle of the upper and lower bridge arms of each phase of the hybrid device power module includes: Based on SPWM modulation, the duty cycle is adjusted by zero-sequence component injection or carrier bias. Alternatively, based on SVPWM modulation, the duty cycle can be adjusted by changing the ratio of the 0 vector to the 7 vector; Alternatively, based on FOC modulation, the duty cycle can be adjusted by uniformly biasing the three-phase modulated signals.

[0009] In one optional implementation, the duty cycle offset is calculated as follows: The current operating conditions and motor electrical angles are obtained, and the corresponding duty cycle bias is matched from the pre-stored calibration database and output to the hybrid device power module. Alternatively, the calibration data of the duty cycle offset can be pre-set in the control system, and open-loop control can be performed during operation based on the motor electrical angle and the current operating conditions; Alternatively, closed-loop control can be performed based on the real-time junction temperature estimation results of the hybrid device power module, dynamically adjusting the duty cycle bias.

[0010] In one optional implementation, closed-loop control is performed based on the real-time junction temperature estimation of the hybrid device power module, dynamically adjusting the duty cycle bias, including: Collect the operating current of the current bottleneck phase, the junction temperature of the upper and lower bridge arms, and the switching frequency within the power module of the hybrid device, and calculate the total loss of the upper and lower bridge arms. The total loss of the upper bridge arm and the total loss of the lower bridge arm are calculated by subtracting the loss from the total loss of the lower bridge arm to obtain the loss deviation. The duty cycle bias is obtained by performing PID calculations based on the loss deviation.

[0011] In one optional implementation, the total loss of the upper and lower bridge arms is calculated, including: Based on the junction temperature of the upper and lower bridge arms, the on-state voltage drop and single-cycle switching loss of the upper and lower bridge arms of the current bottleneck phase are corrected. Calculate the conduction loss of the upper arm of the current bottleneck phase based on the operating current of the upper arm, the corrected on-state voltage drop, and the current duty cycle. Calculate the switching loss of the upper arm of the current bottleneck phase based on the operating current, switching frequency, and corrected single switching loss of the upper arm. The total loss of the upper bridge arm is obtained by summing the conduction loss and the switching loss of the upper bridge arm. Calculate the total loss of the lower arm of the current bottleneck phase based on the operating current of the lower arm, the corrected on-state voltage drop, and the current duty cycle.

[0012] In one alternative implementation, the duty cycle adjustment target is to minimize the highest junction temperature of each arm in the current bottleneck phase under the same stall condition; or, to maximize the stall current output by the hybrid power module, provided that the junction temperature of each arm does not exceed a preset limit.

[0013] In one optional implementation, at least two PWM emission modes are selected, and the switching frequency ratio of different PWM emission modes is adjusted, including: Select at least two PWM waveform modes, and use the sum of the number of switching on and off in the first PWM waveform mode and the number of switching on and off in the second PWM waveform mode as a control cycle; Adjust the ratio of the number of switching cycles in the first PWM waveform mode to the number of switching cycles in the second PWM waveform mode.

[0014] In a second aspect, the present invention provides a control device for improving the current carrying capacity of a power module in a hybrid device, the device comprising: The positioning module is used to obtain the magnitude and direction of the current in each phase of the hybrid device power module under stall conditions, and to locate the current bottleneck phase. The duty cycle adjustment module is used to adjust the duty cycle of each phase of the hybrid device power module, transferring the conduction loss of the current bottleneck phase between its upper and lower bridge arms. The mode adjustment module is used to select at least two PWM waveform modes, adjust the switching ratio of different PWM waveform modes, and continuously distribute the switching losses of each device in the hybrid device power module. The control module is used to regulate the loss distribution of different devices in the hybrid device power module based on the duty cycle of the upper and lower bridge arms of each phase and the waveform of each device, while ensuring that the output current is the same.

[0015] This invention provides a control device for improving the current-carrying capacity of hybrid device power modules. It optimizes current-carrying capacity through a two-degree-of-freedom loss adjustment strategy: the first degree of freedom adjusts the duty cycle of the upper and lower bridge arms of each phase to directionally transfer the conduction loss of the bottleneck bridge arm to the non-bottleneck bridge arm, balancing the conduction loss distribution of the bridge arms; the second degree of freedom achieves continuous and precise allocation of switching losses between SiC MOSFETs and IGBTs through dynamic alternation of various PWM waveform modes and proportional control of switching frequency, avoiding overload of a single device. This method requires no additional chip usage, effectively improving the current-carrying capacity of hybrid device power modules under stall conditions while significantly reducing hardware costs, solving the economic and performance waste problems of traditional chip stacking-for-performance solutions.

[0016] Thirdly, the present invention provides a computer device, comprising: a memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the control method for improving the current carrying capacity of the power module of the hybrid device as described in the first aspect or any corresponding embodiment.

[0017] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to execute the control method for improving the current-carrying capacity of a hybrid device power module as described in the first aspect or any corresponding embodiment. Attached Figure Description

[0018] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0019] Figure 1 It is a voltage and current waveform diagram of the power module of the hybrid device during the turn-on and turn-off process; Figure 2 This is a waveform diagram of the operation of a hybrid device power module using SiC MOSFET devices; Figure 3 This is a waveform diagram of the operation of a hybrid device power module using IGBT devices; Figure 4 This is a schematic diagram of the topology of a hybrid device power module; Figure 5 This is a schematic diagram comparing the switching losses of MOSFET and IGBT devices; Figure 6 This is a flowchart illustrating a control method for improving the current-carrying capacity of a power module in a hybrid device according to an embodiment of the present invention. Figure 7 This is a schematic diagram of the duty cycle adjustment of each phase upper and lower bridge arm of the power module of the hybrid device in an embodiment of the present invention; Figure 8 This is a schematic diagram of the waveform of normal SVPWM modulation in stall steady state according to an embodiment of the present invention; Figure 9 This is a schematic diagram of the SVPWM modulation waveform during normal operation according to an embodiment of the present invention; Figure 10 This is a schematic diagram of the control waveform after adjusting the duty cycle according to an embodiment of the present invention; Figure 11 This is a schematic diagram of another control waveform after the duty cycle adjustment method according to an embodiment of the present invention; Figure 12 This is a block diagram of the junction temperature closed-loop control according to an embodiment of the present invention; Figure 13 This is a schematic diagram of the control logic for the PWM modulation wave to the bridge arm drive signal according to an embodiment of the present invention; Figure 14 This is a schematic diagram of the PWM waveform generation mode according to an embodiment of the present invention; Figure 15 This is a schematic diagram illustrating the coordinated operation of duty cycle adjustment and PWM waveform adjustment under a hybrid module topology according to an embodiment of the present invention. Figure 16 This is a structural block diagram of a control device for improving the current carrying capacity of a hybrid device power module according to an embodiment of the present invention; Figure 17 This is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] Stall capability is a core performance parameter of electric drive products, directly determining the vehicle's hill-start capability and having a decisive impact on key indicators such as maximum starting gradient. Since the upper limit of stall capability is entirely limited by the current output capability of the electronic control power module, these modules typically need to meet extremely high stall performance requirements. However, traditional methods for improving stall capability have significant drawbacks. A detailed analysis, considering the characteristics of stall conditions and the actual performance of the devices, is as follows: 1. The traditional method to improve stall capability is to increase the amount of chips used, but this method will directly lead to a significant increase in hardware costs.

[0022] 2. The motor impedance is mainly composed of resistance and inductance, and the formula is Z = R + 2πfL (where Z is the impedance, R is the resistance, f is the frequency, and L is the inductance). In the locked-rotor condition, f = 0, and the motor exhibits only resistive behavior. Because the motor winding resistance is very small (typically in the mΩ range), regardless of the control method, the average phase voltage Vrms = I*R output by the inverter is very small in the locked-rotor condition. The closed-loop control system only needs to make minor adjustments to the phase voltage to regulate and stabilize the locked-rotor current. For the bus voltage of several hundred volts in a high-voltage system, the output voltage is almost negligible.

[0023] 3. Switching losses occur only during hard switching (i.e., when voltage and current overlap to be non-zero). When the reverse freewheeling arm transitions from blocking to conducting, the diode conducts first, resulting in an extremely low voltage drop, close to zero-voltage switching (ZVS). Therefore, during power module operation, only the forward arm experiences switching losses, while the reverse arm has no switching losses. Under rotating conditions, the output current is a sine wave, and its alternation between positive and negative signals causes each phase's upper and lower bridges to alternate between hard switching and freewheeling. However, under stall conditions, due to the fixed angle and DC output of each phase, the hard switching and freewheeling do not alternate, causing losses to concentrate in specific bridge arms. See waveform diagram. Figure 1 .

[0024] 4. In existing technologies, whether it is sinusoidal pulse width modulation (SPWM) or space vector pulse width modulation (SVPWM), the output duty cycle is fixed at 50% when the output phase voltage is close to 0. Under the traditional control method, both the upper and lower bridges bear the locked rotor current with a duty cycle close to 50%, but the switching bridge arm also needs to bear the switching losses, while the freewheeling bridge arm does not need to bear the switching losses, which further aggravates the imbalance of losses between the bridge arms.

[0025] 5. For SiC MOSFET devices, because they can conduct bidirectionally and their conduction capabilities are similar in both directions, under traditional control methods, the conduction losses of the upper and lower bridges are similar when the rotor is stalled, but one bridge arm bears the switching losses. Figure 2 Taking the typical adverse angle shown as an example, the current flowing into phase A is I, and the current flowing out of phases B and C is 0.5I. At this time, the losses of the three-phase (A / B / C) six-bridge (upper and lower bridge U / L) arms are as follows:

[0026]

[0027]

[0028]

[0029] in, This refers to the on-resistance of the SiC MOSFET. For switching frequency, Let I be the single-cycle switching loss at current I, and this function is monotonically increasing.

[0030] Therefore, it can be seen that:

[0031]

[0032] The temperature difference between the upper and lower bridges of phase A is large, and the losses are much greater than those of phases B and C. The stall capability is limited by the active switching bridge arm of the phase with the largest current (the AL bridge arm in the example).

[0033] 6. For IGBT devices, because they cannot conduct bidirectionally, under traditional control methods, both the IGBT and the fast recovery diode (FRD) of the bridge arm bear nearly 50% of the conduction current during stall. See waveform diagram. Figure 3 Taking the same adverse angle as an example, with a current I flowing into phase A and a current of 0.5I flowing out of phases B and C, the losses of the three-phase (A / B / C) six-bridge (upper and lower bridge U / L) arms are as follows:

[0034]

[0035]

[0036]

[0037] in, Forward voltage drop of the diode, The slope of the UI curve after the diode is turned on. Forward voltage drop of IGBT This represents the slope of the UI curve after the IGBT is turned on.

[0038] Under rotating conditions, the output current is a sinusoidal wave. Its alternating positive and negative values ​​cause each phase's upper and lower bridges to take turns handling hard switching and freewheeling. The FRD capability requirement is not high, and to achieve stall capability, the amount of FRD used often needs to be increased. The increased FRD usage under rotating conditions is excessive, increasing costs. Furthermore, due to the reverse recovery characteristic of FRDs, this increased usage leads to a significant increase in the turn-on losses of the bridge arm IGBTs, affecting the module's current capability and drive efficiency.

[0039] 7. Therefore, for IGBTs, more reverse diodes are needed to achieve the target capability. For SiC MOSFETs, a larger area is needed to achieve the target capability (reducing Rdson while increasing heat dissipation area); due to the bottleneck bridge arm limitation, the capabilities of other chips cannot be fully utilized, resulting in additional costs / performance sacrifices.

[0040] The topology of the hybrid device power module is as follows: Figure 4 As shown, the hybrid device power module consists of two controllable devices (typically SiC MOSFETs and IGBTs) connected in parallel with corresponding freewheeling diodes. Each device can be controlled independently. By controlling whether the devices are switched on or off, the conduction loss distribution between the two devices on the same bridge arm can be changed; by adjusting the order in which the devices are turned on and off, the turn-on and turn-off losses on the same bridge arm can be controlled by which device bears the losses.

[0041] The above combinations of switching methods can generate six PWM waveforms, and their turn-on timing and switching / conduction loss distribution are shown in the table below: Table 1. Turn-on timing and switching / conduction losses of various devices under different waveform transmission methods.

[0042] In rotating operation, mode switching is often performed based on the phase current to balance losses and achieve maximum current output within a certain junction temperature limit. Under this control method, the heat dissipation power of each chip varies significantly depending on the wave generation mode. However, rotating operation possesses a key characteristic that offsets this difference: during high current output, the motor frequency is typically higher than 50Hz, which is much larger than the time constant of the power module's thermal network. This means that the chip temperature changes much slower than the current alternation cycle, and ultimately, the junction temperature of each chip stabilizes within the temperature rise range corresponding to its own average loss. Furthermore, by adjusting the current threshold for mode switching, continuous control of the loss distribution between SiC MOSFETs and IGBTs can be achieved.

[0043] Unlike the rotating condition, the motor current does not exhibit alternating characteristics in the stalled state. Therefore, the strategy of switching the PWM emission mode based on the phase current magnitude is completely ineffective. Current mainstream hybrid device power module stall control schemes typically employ a fixed PWM emission mode, resulting in an inflexible adjustment of the switching loss allocation ratio.

[0044] Even when four of the six methods described above are used for stall control, the switching loss distribution of SiC MOSFETs and IGBTs still exhibits a discrete characteristic. The loss values ​​can only switch between fixed ranges, making continuous adjustment impossible and failing to meet the requirements for fine-grained loss allocation under stall conditions. See the schematic diagrams for the switching losses of MOSFETs and IGBTs. Figure 5 .

[0045] According to an embodiment of the present invention, a control method embodiment for improving the current carrying capacity of a power module of a hybrid device is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0046] This embodiment provides a control method for improving the current-carrying capacity of a hybrid device power module. Figure 6 This is a flowchart of a control method for improving the current-carrying capacity of a power module in a hybrid device according to an embodiment of the present invention, such as... Figure 6 As shown, the process includes the following steps: Step S1: Obtain the magnitude and direction of the current in each phase of the hybrid device power module under stall conditions, and locate the current bottleneck phase.

[0047] Specifically, under stall conditions, the motor speed is 0, the output current exhibits DC characteristics, and the magnitude and direction of the current in each phase differ significantly. By acquiring the amplitude and direction of the three-phase current in real time through a current acquisition unit (such as a Hall sensor), the bottleneck phase can be located. The bottleneck phase is the phase with the largest current amplitude.

[0048] Step S2: Adjust the duty cycle of the upper and lower bridge arms of each phase of the hybrid device power module to transfer the conduction loss of the current bottleneck phase between its upper and lower bridge arms.

[0049] Specifically, under stall conditions, in traditional control methods, the duty cycle of the upper and lower bridge arms is fixed at 50%, causing the active switching bridge arm of the current bottleneck phase to bear both switching losses and high conduction losses. By adjusting the duty cycle, the conduction losses of the bottleneck phase are redistributed between its upper and lower bridge arms, appropriately transferring the conduction losses of the bottleneck bridge arm to the non-bottleneck bridge arms, thereby improving stall capability and achieving the goal of increasing overall capability or reducing chip usage. For example, as... Figure 7 As shown, the duty cycle of the upper arm in the bottleneck phase is increased from 50% to 50% + ΔD, while the duty cycle of the lower arm is decreased to 50%. ΔD (ΔD is the duty cycle offset, ranging from 0 to 1) transfers some of the conduction losses that were originally concentrated in the lower axle arm to the upper axle arm, thereby balancing the losses of the upper and lower axle arms and improving stall capability.

[0050] The control strategy for the distribution of conduction losses between the upper and lower bridges is as follows: Under a certain temperature and current, the on-state voltage drop U of the device is constant. Under PWM modulation, its conduction loss is:

[0051] When the phase duty cycle is D, the conduction losses of the upper and lower bridges are:

[0052]

[0053] Adjusting the value of D can transfer the conduction loss between the upper and lower bridges. This method is not only effective for stalled rotors, but can also be extended to low-speed operating conditions to reduce junction temperature fluctuations and improve stalled rotor capability.

[0054] Step S3: Select at least two PWM waveform modes, adjust the switching frequency ratio of different PWM waveform modes, and continuously distribute the switching losses of each device in the hybrid device power module.

[0055] Specifically, the current is usually at a high level under stall conditions, so the first four PWM waveform modes in Table 1 should be selected first. These modes can enable all available devices (SiC MOSFET, IGBT) in the hybrid device power module to be turned on in parallel, minimizing conduction losses and adapting to the loss control requirements of high current conditions.

[0056] Because the motor current exhibits DC characteristics and lacks an alternating process under stall conditions, it cannot achieve natural switching of the PWM waveform mode through the alternation of positive and negative current as it does under rotating conditions. Therefore, it is difficult to continuously adjust switching losses in this way. To achieve continuous distribution of switching losses, it is necessary to actively switch between PWM waveform modes. Based on the actual loss distribution target, at least two PWM waveform modes suitable for stall conditions should be selected. Using several switching cycles as the control unit, the ratio of the number of switching cycles in different modes should be adjusted (e.g., mode 1 runs X times, mode 2 runs Y times, and the ratio of X to Y is dynamically changed) to ultimately achieve continuous distribution of switching losses and avoid device overload problems caused by discrete losses in a single mode.

[0057] Step S4: Based on the duty cycle of the upper and lower bridge arms of each phase of the hybrid device power module and the waveform of each device, the loss distribution of different devices in the hybrid device power module is adjusted while ensuring that the output current is the same.

[0058] Specifically, the duty cycle of each phase upper and lower bridge arm determined in step S2, the PWM waveform mode and the switching frequency ratio determined in step S3 are input to the control unit of each bridge arm of the hybrid device power module, and the module outputs current accordingly.

[0059] The entire control process is based on the maximum allowable junction temperature (Tjmax) of each bridge arm as the core constraint. If the current junction temperature of each bridge arm is lower than Tjmax, the module output current can be appropriately increased to maximize the module's current carrying capacity. If the junction temperature of some bridge arms is close to Tjmax, the duty cycle determined in step S2 and the switching ratio of the PWM wave generation mode determined in step S3 are finely adjusted to balance the losses of each bridge arm without reducing the module output current, ensuring that the junction temperature of each bridge arm is stable within a safe range.

[0060] This invention provides a control method to improve the current-carrying capacity of hybrid device power modules. It optimizes current-carrying capacity through a two-degree-of-freedom loss adjustment strategy: the first degree of freedom adjusts the duty cycle of the upper and lower bridge arms of each phase to directionally transfer the conduction loss of the bottleneck bridge arm to the non-bottleneck bridge arm, balancing the conduction loss distribution of the bridge arms; the second degree of freedom achieves continuous and precise allocation of switching losses between SiC MOSFETs and IGBTs through dynamic alternation of various PWM waveform modes and proportional control of switching frequency, avoiding overload of a single device. This method requires no additional chip usage, effectively improving the current-carrying capacity of hybrid device power modules under stall conditions while significantly reducing hardware costs, solving the economic and performance waste problems of traditional chip stacking-for-performance solutions.

[0061] In one alternative implementation, any one of the steps S21 to S23 can be selected to adjust the duty cycle of the upper and lower bridge arms of each phase of the hybrid device power module.

[0062] Step S21: Based on SPWM modulation, the duty cycle is adjusted by zero-sequence component injection or carrier bias.

[0063] Specifically, under stalled operation, the target phase voltage is close to 0, and the three-phase modulation wave of traditional SPWM is also close to 0. Its intersection with the triangular carrier wave is symmetrical, resulting in a fixed duty cycle of 50% for both upper and lower bridge arms. This limitation can be overcome using the following two methods: 1. In the three-phase sinusoidal modulation wave of SPWM, an identical DC component (i.e., zero-sequence component) is synchronously superimposed to form a new modulation wave. Since the line voltage is the difference between the three-phase phase voltages, the superimposed zero-sequence component will completely cancel out in the difference and will not affect the actual line voltage received by the motor; however, the amplitude and position of the single-phase modulation wave change, and the intersection point with the triangular carrier wave shifts, causing the conduction time of the upper and lower bridge arms of that phase to change.

[0064] 2. Without changing the sinusoidal modulation wave, the triangular carrier wave is shifted upwards or downwards as a whole to adjust the relative position of the carrier wave and the modulation wave. The triangular carrier wave is the reference for PWM generation. When the carrier wave is shifted upwards, the intersection point with the fixed modulation wave shifts upwards, shortening the conduction time of the upper bridge arm; when the carrier wave is shifted downwards, the intersection point shifts downwards, lengthening the conduction time of the upper bridge arm.

[0065] Step S22: Based on SVPWM modulation, the duty cycle is adjusted by adjusting the ratio of the 0 vector to the 7 vector.

[0066] Specifically, under stall conditions, the target voltage vector is close to zero. Traditional SVPWM mainly relies on the synthesis of 0-vector and 7-vector, and the ratio of their action time is fixed, resulting in the duty cycle of each phase's upper and lower bridge arms approaching 50%. Adjusting the ratio of the two can directly change the duty cycle. Within one control cycle of SVPWM, the total time consists of the effective vector time and the zero-vector time. During stall, the effective vector time is extremely short and can be ignored; the total time is approximately the zero-vector time T0 + T7 (T0 is the 0-vector time, and T7 is the 7-vector time). By adjusting the ratio of T0 and T7, the conduction time of each phase bridge arm is changed. When the 0-vector (both upper and lower bridges are completely off) is applied, there is no current in any phase bridge arm; when the 7-vector (both upper and lower bridges are completely on) is applied, both upper and lower bridge arms of each phase are conducting, and the current is shunt through the upper and lower bridge arms.

[0067] Step S23: Based on the FOC modulation method, the duty cycle is adjusted by uniformly biasing the three-phase modulated signals.

[0068] Specifically, under stall conditions, the d / q axis commands of the FOC are stable (fixed flux linkage, low torque demand). In traditional control, the amplitude of the three-phase modulated signals is close to 0, and the duty cycle is fixed at 50%, which can be flexibly adjusted through a unified bias. For the three-phase modulated signals output by the FOC, an identical bias amount ΔT is synchronously superimposed, and then compared with a triangular carrier wave to generate PWM. The unified bias of the three-phase modulated signals does not change the actual effect of the d / q axis voltage, nor does it affect the field orientation accuracy or stall current stability; however, the amplitude of a single-phase modulated signal changes with the bias amount ΔT, and the intersection point with the carrier wave shifts, directly changing the duty cycle of the upper and lower arms of that phase.

[0069] In one alternative implementation, taking the worst-case scenario of a stalled rotor condition where phase A has a negative current and phases B and C have the same positive current as an example: at this time, the current amplitude of phase A is twice that of phases B and C, resulting in the temperature of phase A being much higher than that of phases B and C; and the lower arm of phase A needs to bear additional switching losses, which makes the temperature rise of the lower arm of phase A even higher than that of the upper arm.

[0070] In normal SVPWM modulation, during stall steady state, the timing is dominated by the zero vector, and the specific waveform is as follows: Figure 8 As shown. At this time, the inverter output phase voltage is close to 0, and only the 0 vector is needed to maintain the stability of the switching cycle. Because the locked rotor process requires closed-loop control to stabilize the current, an effective vector needs to be output at certain times (taking vectors 110 and 100 as examples). Its operating state is as follows. Figure 9As shown in the diagram, in this state, the effective value (RMS, root mean square) of the current flowing through the upper and lower arms of each phase is almost the same. However, only one arm of each phase bears the switching loss, while the other arm only has freewheeling and no switching loss. Based on this characteristic, the conduction loss can be transferred by adjusting the duty cycle: increasing the duty cycle of the upper arms of the three phases (and correspondingly decreasing the duty cycle of the lower arms) can transfer more conduction loss to the upper arms; conversely, decreasing the duty cycle of the upper arms can transfer conduction loss to the lower arms, ultimately achieving temperature balance between the upper and lower arms of the bottleneck phase.

[0071] The control waveform after using the above duty cycle adjustment method is as follows: Figure 10 , Figure 11 As shown (taking vectors 110 and 100 as examples), the loss transfer effect is directly reflected through changes in the vector proportion. For example... Figure 10 As shown, when the proportion of zero vector increases, the conduction time of the lower bridge arm increases, and the conduction loss increases accordingly, while the conduction loss of the upper bridge arm decreases accordingly, which can alleviate the overheating problem of the upper bridge arm. Figure 11 As shown, when the proportion of vector 1 increases, the conduction time of the upper bridge arm is prolonged, and the conduction loss increases accordingly, while the conduction loss of the lower bridge arm is reduced accordingly, which can specifically reduce the temperature of the lower bridge arm.

[0072] It should be noted that this adjustment method may bring two changes: First, the uneven temperature distribution between phases B and C may be slightly aggravated, but since the temperatures of phases B and C are much lower than the bottleneck phase (phase A), even if the uneven temperature distribution is aggravated, it will not affect the overall temperature bottleneck of the system. Second, the voltage utilization rate may be slightly reduced, but the motor does not need to overcome back electromotive force during stalled operation, so there is no requirement for voltage utilization rate. The system's requirement for voltage utilization rate is also low under low-speed conditions. Therefore, this method will not affect the system performance under stalled and low-speed conditions. The scope of application of this method is not limited to SPWM, FOC, SVPWM, and other control methods. As long as the duty cycle corresponding to the output voltage approaching 0 is adjusted to optimize losses under stalled conditions, it falls within the protection scope of this invention. The duty cycle bias ΔD ranges from 0 to 1. Its adjustment is constrained by the highest junction temperature (Tjmax) of all bridge arms. The control objective of the duty cycle is: for each bridge arm of the current bottleneck phase, under the same stall condition, to reduce the highest junction temperature of each bridge arm in that phase to the minimum; or, under the premise that the junction temperature of each bridge arm does not exceed the preset limit, to maximize the stall current that the hybrid power module can output.

[0073] In one optional implementation, the following duty cycle offset calculation process is not executed sequentially, but rather consists of three independent calculation methods. The duty cycle offset calculation process is as follows: Step S24: Obtain the current operating condition and motor electrical angle, match the corresponding duty cycle bias from the pre-stored calibration database and output it to the hybrid device power module.

[0074] Specifically, key parameters of the stall condition, such as stall current level and bus voltage, are identified through system sensors. The fixed electrical angle during stall is read using motor position sensors. Based on the pre-stored correspondence between the current operating condition, motor electrical angle, and duty cycle offset, the duty cycle offset is directly matched and output. This duty cycle offset is then output to the hybrid device power module to adjust the duty cycle of the upper and lower arms of the bottleneck phase.

[0075] Step S25, or the calibration data of the duty cycle offset is preset in the control system, and open-loop control is performed during operation based on the motor electrical angle and the current operating conditions.

[0076] Specifically, for typical stall conditions commonly encountered by the system, the tested bias values ​​are directly written into the controller program to form calibration data for the duty cycle bias. During operation, the system identifies typical stall conditions and corresponding angles, and matches the corresponding duty cycle bias from the calibration data. The duty cycle bias is then output to the hybrid device power module to adjust the duty cycle of the upper and lower arms of the bottleneck phase.

[0077] Step S26, or based on the real-time junction temperature estimation result of the hybrid device power module, perform closed-loop control and dynamically adjust the duty cycle bias.

[0078] Specifically, step S26 above includes: Step S261: Collect the operating current of the current bottleneck phase, the junction temperature of the upper and lower bridge arms, and the switching frequency within the power module of the hybrid device.

[0079] Step S262: Based on the junction temperature of the upper and lower bridge arms, correct the on-state voltage drop and single-cycle switching loss of the upper and lower bridge arms of the current bottleneck phase.

[0080] Step S263: Calculate the conduction loss of the upper arm of the current bottleneck phase based on the operating current of the upper arm, the corrected on-state voltage drop, and the current duty cycle.

[0081] Step S264: Calculate the switching loss of the upper arm of the current bottleneck phase based on the operating current, switching frequency, and corrected single switching loss of the upper arm.

[0082] Step S265: Sum the conduction loss of the upper bridge arm with the switching loss of the upper bridge arm to obtain the total loss of the upper bridge arm.

[0083] Step S266: Calculate the total loss of the lower arm of the current bottleneck phase based on the operating current of the lower arm, the corrected on-state voltage drop, and the current duty cycle.

[0084] Step S267: The total loss of the upper bridge arm and the total loss of the lower bridge arm are calculated by subtracting the difference to obtain the loss deviation.

[0085] Step S268: Perform PID calculation based on the loss deviation to obtain the duty cycle bias.

[0086] Specifically, the real-time DC current of the bottleneck phase is acquired using a Hall sensor, and the real-time junction temperature of the upper arm (AU) and lower arm (AL) of the bottleneck phase is obtained using a temperature sensor or junction temperature estimation model. The current PWM switching frequency of the hybrid device power module is then read. Since the loss characteristics of power devices (SiC MOSFET / IGBT) change significantly with junction temperature, it is necessary to correct the on-state voltage drop and single-cycle switching loss of the upper and lower arms of the current bottleneck phase using real-time junction temperature.

[0087] Combining the real-time operating current I, the temperature-corrected on-state voltage drop U, and the current duty cycle D, according to the formula... or Calculate the real-time conduction loss of the bottleneck phase bridge arm. Combine this with the real-time operating current I and the switching frequency. Temperature-corrected single-cycle switching loss According to the formula The real-time switching loss of the bottleneck phase bridge arm is calculated. The conduction loss and switching loss of the upper bridge arm are summed to obtain the total loss of the upper bridge arm. During stall, the upper bridge arm bears the switching loss, while the lower bridge arm only bears the freewheeling conduction loss and has no switching loss; therefore, the total loss of the lower bridge arm is only the conduction loss. The total loss of the upper bridge arm is subtracted from the total loss of the lower bridge arm to obtain the loss deviation. If the loss deviation is greater than 0, the duty cycle of the lower bridge arm needs to be increased (the duty cycle of the upper bridge arm needs to be decreased) to transfer the conduction loss of the upper bridge arm to the lower bridge arm; if the loss deviation is less than 0, the duty cycle of the upper bridge arm needs to be increased to transfer the loss of the lower bridge arm. The PID controller converts the loss deviation ΔP into a duty cycle bias ΔD that meets the constraints, achieving closed-loop control for loss balancing. The output duty cycle bias ΔD is directly used to adjust the duty cycles of the upper and lower bridge arms in the bottleneck phase to achieve loss transfer and ultimately balance the junction temperature of the upper and lower bridge arms. See the detailed flowchart. Figure 12 See the schematic diagram of the control logic for the PWM modulation wave to the bridge arm drive signal. Figure 13 .

[0088] For the PWM modulation control requirements of hybrid device power modules, the specific implementation method using a conventional MCU (microcontroller) is as follows: Configure the MCU's timer to center-aligned mode, and write the modulated values ​​Tm of phases A, B, and C to the timer's compare register. a、Tm b、Tm c. Generate PWM signals for each bridge arm of the power module driving the hybrid device; in this microcontroller application scenario, to achieve the duty cycle adjustment target of not interfering with line voltage and transferring conduction losses, verify Tm. a、Tm b、Tm c. These three modulated values ​​are increased or decreased synchronously.

[0089] In one optional implementation, step S3 includes: Step S31: Select at least two PWM waveform modes, and use the sum of the number of switching on and off in the first PWM waveform mode and the number of switching on and off in the second PWM waveform mode as a control cycle.

[0090] Step S32: Adjust the ratio of the number of switching cycles of the first PWM wave generation mode to the number of switching cycles of the second PWM wave generation mode.

[0091] Specifically, since the current does not alternate in the stalled state, continuous regulation cannot be achieved by switching based on the current magnitude. To achieve continuous regulation, active mode switching is required. Based on the required loss distribution, two modes, A and B, are selected. The switching losses of devices 1 and 2 when fixed in modes A and B are A1, A2, B1, and B2, respectively. With X+Y switching cycles as one control cycle, where mode A switches X times and mode B switches Y times, the switching losses of devices 1 and 2 are as follows:

[0092]

[0093] In this context, A represents the first mode, B represents the second mode, X represents the number of times the device is switched on and off in the first mode, and Y represents the number of times the device is switched on and off in the second mode.

[0094] For example, as shown in Table 1, SiC performs more switching actions in Mode 1, resulting in lower switching losses, while IGBT performs more switching actions in Mode 4, resulting in higher switching losses. Therefore, to achieve continuous distribution of switching losses, a control cycle can be set to every 5 PWM switching cycles. The first 3 cycles execute the waveform generation sequence of Mode 4, and the last 2 cycles switch to the waveform generation sequence of Mode 1, and this cycle is repeated. See the waveform diagram below. Figure 14 .

[0095] Figure 15 illustrates the coordinated operation of duty cycle adjustment and PWM waveform adjustment in a hybrid module topology. Figure 15 focuses on the loss and junction temperature control of the worst-case phase under stall conditions. When the worst-case phase current is positive, the SiC MOSFET and IGBT on the upper bridge of this phase must simultaneously bear switching and conduction losses, while the freewheeling diode on the lower bridge bears reverse conduction losses. At this time, uneven losses can easily lead to localized overheating in the devices. Figure 15 provides a coordinated adjustment scheme for this scenario. Its core objective is to achieve dynamic balance of the junction temperature margin of the worst-case phase switching devices (SiC / IGBT) and the freewheeling diode through the linkage of the two adjustment methods, ultimately maximizing current capability or achieving the most balanced overall junction temperature under the same stall current.

[0096] The structure shown in Figure 15 can be divided into three parts: a junction temperature monitoring layer, a controller layer, and an output regulation layer. The junction temperature monitoring layer is used to acquire the junction temperature and its margin in real time. This layer collects the junction temperature data of key components in the upper and lower bridge of the hybrid device power module in real time through a junction temperature monitoring system or a junction temperature estimation model, specifically including the junction temperature of the SiC MOSFET, IGBT, and freewheeling diode. Simultaneously, based on the junction temperature limits of each device, the junction temperature margin of each device is calculated.

[0097] The controller layer comprises two core controllers, each corresponding to one of the two dimensions of the two-degree-of-freedom loss regulation strategy. They work together to balance the junction temperature margins of different devices. The switching ratio controller outputs the switching ratio (X / Y) of the PWM waveform mode. Its control objective is to dynamically equalize the junction temperature margins of SiC and IGBT. By adjusting the switching ratio of the two PWM waveform modes (X being the number of switches in the first mode and Y being the number of switches in the second mode), the switching losses of SiC and IGBT are continuously distributed, preventing excessively high junction temperatures in a single device due to concentrated losses. The duty cycle bias controller outputs the duty cycle bias (ΔD). The goal of this regulation is to dynamically equalize the junction temperature margin of SiC and IGBT with that of the diode. By finely adjusting the duty cycle of the upper and lower bridge arms of the current bottleneck phase (e.g., adjusting the duty cycle of the upper bridge arm from 50% to 50%+ΔD and the lower bridge arm to 50%-ΔD), the conduction loss is transferred between the upper and lower bridge arms, thus balancing the loss distribution of the diode and the switching device (SiC / IGBT).

[0098] The adjustment output layer is used to apply decision parameters to the switching ratio (X / Y) and duty cycle bias (ΔD) of the hybrid device power module controller output. These parameters are directly input to the control units of each bridge arm of the hybrid device power module, thereby adjusting the PWM waveform timing and bridge arm conduction time. Ultimately, this allows for the control of the loss distribution of different devices while ensuring the same output current, thus ensuring that the junction temperature of each device remains stable within a safe range.

[0099] This embodiment also provides a control device for improving the current-carrying capacity of a hybrid device power module. This device is used to implement the above embodiments and preferred embodiments, and details already described will not be repeated. As used below, the term "module" can be a combination of software and / or hardware that performs a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0100] This embodiment provides a control device for improving the current-carrying capacity of a hybrid device power module, such as... Figure 16 As shown, it includes: The positioning module 161 is used to obtain the magnitude and direction of the current in each phase of the hybrid device power module under stall conditions, and to locate the current bottleneck phase.

[0101] The duty cycle adjustment module 162 is used to adjust the duty cycle of each phase of the hybrid device power module, thereby transferring the conduction loss of the current bottleneck phase between its upper and lower bridge arms.

[0102] The mode adjustment module 163 is used to select at least two PWM waveform modes, adjust the switching frequency ratio of different PWM waveform modes, and continuously distribute the switching losses of each device in the hybrid device power module.

[0103] The control module 164 is used to regulate the loss distribution of different devices in the hybrid device power module based on the duty cycle of the upper and lower bridge arms of each phase and the waveform of each device, while ensuring that the output current is the same.

[0104] Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0105] In this embodiment, the control device for enhancing the current-carrying capacity of the power module of the hybrid device is presented in the form of a functional unit. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0106] This invention provides a control device for improving the current-carrying capacity of hybrid device power modules. It optimizes current-carrying capacity through a two-degree-of-freedom loss adjustment strategy: the first degree of freedom adjusts the duty cycle of the upper and lower bridge arms of each phase to directionally transfer the conduction loss of the bottleneck bridge arm to the non-bottleneck bridge arm, balancing the conduction loss distribution of the bridge arms; the second degree of freedom achieves continuous and precise allocation of switching losses between SiC MOSFETs and IGBTs through dynamic alternation of various PWM waveform modes and proportional control of switching frequency, avoiding overload of a single device. This method requires no additional chip usage, effectively improving the current-carrying capacity of hybrid device power modules under stall conditions while significantly reducing hardware costs, solving the economic and performance waste problems of traditional chip stacking-for-performance solutions.

[0107] This invention also provides a computer device having the above-described features. Figure 16 The control device shown is designed to enhance the current-carrying capacity of the power module of a hybrid device.

[0108] Please see Figure 17 , Figure 17 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of the present invention, such as... Figure 17 As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 17 Take a processor 10 as an example.

[0109] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0110] The memory 20 stores instructions executable by at least one processor 10 to cause the at least one processor 10 to perform the method shown in the above embodiments.

[0111] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0112] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0113] The computer device also includes a communication interface 30 for communicating with other devices or communication networks.

[0114] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.

[0115] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A control method for improving the current-carrying capacity of a hybrid device power module, wherein the hybrid device power module comprises two controllable devices integrated in parallel and each having a corresponding freewheeling diode, characterized in that, The method includes: The magnitude and direction of the current in each phase of the hybrid device power module under stall conditions are obtained, and the current bottleneck phase is located. Adjust the duty cycle of the upper and lower bridge arms of each phase of the hybrid device power module to transfer the conduction loss of the current bottleneck phase between its upper and lower bridge arms. Select at least two PWM waveform modes, adjust the switching frequency ratio of different PWM waveform modes, and continuously distribute the switching losses of each device in the hybrid device power module. Based on the duty cycle of each phase upper and lower bridge arm of the hybrid device power module and the waveform of each device, the loss distribution of different devices in the hybrid device power module is adjusted while ensuring the same output current.

2. The control method for improving the current-carrying capacity of a hybrid device power module according to claim 1, characterized in that, Adjusting the duty cycle of each phase upper and lower bridge arm of the hybrid device power module, including: Based on SPWM modulation, the duty cycle is adjusted by zero-sequence component injection or carrier bias. Alternatively, based on SVPWM modulation, the duty cycle can be adjusted by changing the ratio of the 0 vector to the 7 vector; Alternatively, based on FOC modulation, the duty cycle can be adjusted by uniformly biasing the three-phase modulated signals.

3. The control method for improving the current-carrying capacity of a hybrid device power module according to claim 2, characterized in that, The calculation process for duty cycle offset is as follows: The current operating conditions and motor electrical angles are obtained, and the corresponding duty cycle bias is matched from the pre-stored calibration database and output to the hybrid device power module. Alternatively, the calibration data of the duty cycle offset can be pre-set in the control system, and open-loop control can be performed during operation based on the motor electrical angle and the current operating conditions; Alternatively, closed-loop control can be performed based on the real-time junction temperature estimation results of the hybrid device power module, dynamically adjusting the duty cycle bias.

4. The control method for improving the current-carrying capacity of a hybrid device power module according to claim 3, characterized in that, Closed-loop control is executed based on the real-time junction temperature estimation results of the hybrid device power module, dynamically adjusting the duty cycle bias, including: Collect the operating current of the current bottleneck phase, the junction temperature of the upper and lower bridge arms, and the switching frequency within the power module of the hybrid device, and calculate the total loss of the upper and lower bridge arms. The total loss of the upper bridge arm and the total loss of the lower bridge arm are subtracted to obtain the loss deviation. The duty cycle bias is obtained by performing PID calculations based on the loss deviation.

5. The control method for improving the current-carrying capacity of a hybrid device power module according to claim 4, characterized in that, Calculate the total loss of the upper and lower bridge arms, including: Based on the junction temperature of the upper and lower bridge arms, the on-state voltage drop and single-cycle switching loss of the upper and lower bridge arms of the current bottleneck phase are corrected. Calculate the conduction loss of the upper arm of the current bottleneck phase based on the operating current of the upper arm, the corrected on-state voltage drop, and the current duty cycle. Calculate the switching loss of the upper arm of the current bottleneck phase based on the operating current, switching frequency, and corrected single switching loss of the upper arm. The total loss of the upper bridge arm is obtained by summing the conduction loss and the switching loss of the upper bridge arm. Calculate the total loss of the lower arm of the current bottleneck phase based on the operating current of the lower arm, the corrected on-state voltage drop, and the current duty cycle.

6. The control method for improving the current-carrying capacity of a hybrid device power module according to claim 2, characterized in that, The duty cycle control target is to minimize the highest junction temperature of each arm in the current bottleneck phase under the same stall condition; or, to maximize the stall current output by the hybrid power module, provided that the junction temperature of each arm does not exceed the preset limit.

7. The control method for improving the current-carrying capacity of a hybrid device power module according to claim 1, characterized in that, Select at least two PWM waveform modes and adjust the switching frequency ratio for different PWM waveform modes, including: Select at least two PWM waveform modes, and use the sum of the number of switching on and off in the first PWM waveform mode and the number of switching on and off in the second PWM waveform mode as a control cycle; Adjust the ratio of the number of switching cycles in the first PWM waveform mode to the number of switching cycles in the second PWM waveform mode.

8. A control device for improving the current-carrying capacity of a hybrid device power module, characterized in that, The device includes: The positioning module is used to obtain the magnitude and direction of the current in each phase of the hybrid device power module under stall conditions, and to locate the current bottleneck phase. The duty cycle adjustment module is used to adjust the duty cycle of each phase of the hybrid device power module, transferring the conduction loss of the current bottleneck phase between its upper and lower bridge arms. The mode adjustment module is used to select at least two PWM waveform modes, adjust the switching ratio of different PWM waveform modes, and continuously distribute the switching losses of each device in the hybrid device power module. The control module is used to regulate the loss distribution of different devices in the hybrid device power module based on the duty cycle of the upper and lower bridge arms of each phase and the waveform of each device, while ensuring that the output current is the same.

9. A computer device, characterized in that, include: A memory and a processor are communicatively connected, the memory stores computer instructions, and the processor executes the computer instructions to perform the control method for improving the current carrying capacity of the power module of the hybrid device as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing a computer to execute the control method for improving the current-carrying capacity of the power module of a hybrid device as described in any one of claims 1 to 7.

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