Novel low-delay demodulation circuit and system

Abstract

The invention relates to the technical field of analog integrated circuits, in particular to a novel low-delay demodulation circuit and system.The constant current generated by a voltage source module is copied to a differential demodulation module through a first current mirror module, so that when an original modulation signal is converted into a non-input signal from an input signal, the constant current is converted into the differential demodulation module; the voltage of the differential demodulation module can be quickly discharged through the first current mirror module, so that the output original signal can be quickly reversed according to the conversion of the differential modulation signal, and the time delay of converting the high-level output into the low-level output after the demodulation circuit is converted is remarkably reduced. Meanwhile, the first current mirror module assists the differential demodulation module to perform voltage discharge, so that the differential demodulation module can improve the amplification capability of the input original modulation signal and obtain the differential modulation signal with higher amplitude and better quality without generating negative influence on the demodulation rate; and the time delay of converting the demodulation circuit from low-level output to high-level output is obviously reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of analog integrated circuit technology, in particular to a novel low-delay demodulation circuit and system. BACKGROUND

[0002] The low-delay demodulation circuit is widely used in isolation driving chips. After the modulated differential signal is amplified by a high-bandwidth peak gain amplifier, it is input into the demodulation circuit to restore the original signal. The existing low-delay demodulation circuit is similar to a two-stage comparator, wherein the positive and negative terminals of the front stage of the two-stage comparator receive the differential modulated signal. The positive input of the original modulated signal is connected to the gate of the second MOS tube after being amplified and filtered by the first capacitor and the first resistor, and the negative input of the original modulated signal is connected to the gate of the third MOS tube after being amplified and filtered by the second capacitor and the second resistor. When the circuit does not receive the carrier signal, only the common-mode voltage is superimposed on the gates of the second MOS tube and the third MOS tube, so that the demodulation circuit outputs a low level; when the receiver receives the carrier signal, the differential modulated signal is superimposed on the common-mode voltage of the gates of the second MOS tube and the third MOS tube, so that the demodulation circuit outputs a high level after a certain delay t dlh When the receiver stops receiving the carrier signal, the differential modulated signal input disappears, and only the common-mode signal is left on the gates of the second MOS tube and the third MOS tube, so that the demodulation circuit outputs a low level after a certain delay t dhl .

[0003] As the main part of the high-pass filter of the differential modulated signal in the front-stage comparator, the values of the first resistor and the second resistor not only affect the input quality of the original modulated signal, but also affect the transmission delays t dlh and t dhl of the demodulation circuit for outputting the original signal. Generally, in order to better amplify the original modulated signal and improve the quality of the differential modulated signal, the resistance values of the first resistor and the second resistor should be as high as possible; however, if the resistance values of the first resistor and the second resistor are too large, the voltage discharge of the first capacitor and the second capacitor will be slow when the original modulated signal changes from input to no input, thereby increasing the transmission delay t dhl of the demodulation circuit when the differential modulated signal changes. If the resistance values of the first resistor and the second resistor are reduced, the original modulated signal cannot be effectively amplified, the differential signal is greatly attenuated, the front-stage comparator and the rear-stage comparator cannot perform the original current-voltage comparison function, the comparator cannot be flipped, and the demodulation function of the demodulation circuit is lost.

[0004] Therefore, how to reduce the signal demodulation delays t dlh and t dhl of the demodulation circuit while effectively ensuring the signal demodulation function of the demodulation circuit has become a technical problem to be solved in the field. SUMMARY

[0005] The present application aims to provide a new low-latency demodulation circuit and system to reduce the signal demodulation latency of the demodulation circuit and improve the demodulation rate on the basis of effectively ensuring the signal demodulation function of the demodulation circuit.

[0006] To achieve the above-mentioned purpose, the present application provides a new low-latency demodulation circuit in the first aspect, comprising a differential demodulation module, a first current mirror module, a second current mirror module, a third current mirror module, a voltage biasing module, a voltage source module and an original signal output port; wherein: The voltage source module is used to output a constant working current to the first current mirror module, the second current mirror module, the third current mirror module and the voltage biasing module; The first current mirror module is used to copy the constant working current to the differential demodulation module; The voltage biasing module is used to generate a first bias voltage and a second bias voltage; The differential demodulation module is used to convert an external original modulated signal input into a first comparison current and a second comparison current according to the first bias voltage and the second bias voltage; The second current mirror module is used to transmit the first comparison current to the original signal output port; The third current mirror module is used to transmit the second comparison current to the original signal output port; The original signal output port is used to compare the first comparison current and the second comparison current, and then generate an original signal.

[0007] In the above-mentioned new low-latency demodulation circuit, the constant current generated by the voltage source module is copied to the differential demodulation module through the first current mirror module, so that when the original modulated signal changes from input to non-input, the voltage of the differential demodulation module can be quickly discharged through the first current mirror module, so that the output original signal can be quickly reversed according to the change of the differential modulated signal, and the latency t dhl .

[0008] At the same time, the first current mirror module assists the differential demodulation module to discharge voltage, so that the differential demodulation module can improve the amplification capability of the input original modulated signal, get a differential modulated signal with higher amplitude and better quality, and will not have a negative impact on the demodulation rate, so that the output original signal can be quickly reversed according to the change of the differential modulated signal, and the latency t dlh .

[0009] In summary, the new low-latency demodulation circuit significantly reduces the signal demodulation delay t dhl and t dlh , effectively improving the original signal output quality and signal demodulation rate.

[0010] It should be noted that when the original modulated signal is not input, the first comparison current generated by the second current mirror module is greater than the second comparison current generated by the third current mirror module, so that the original signal generated by the original signal output port is converted to low level; when the original modulated signal is input, the first comparison current generated by the second current mirror module is less than the second comparison current generated by the third current mirror module, so that the original signal generated by the original signal output port is converted to high level, thereby realizing demodulation of the original modulated signal.

[0011] Further, the differential demodulation module comprises a first NMOS tube, a second NMOS tube, a third NMOS tube, a first capacitor, a second capacitor, a first resistor and a second resistor; wherein: The first end of the first capacitor is used to receive an external original modulated signal positive input, and the second end of the first capacitor is electrically connected with the first end of the first resistor; the second end of the first resistor is used to receive the first bias voltage generated by the voltage biasing module; The first end of the second capacitor is used to receive an external original modulated signal negative input, and the second end of the second capacitor is electrically connected with the first end of the second resistor; the second end of the second resistor is used to receive the first bias voltage generated by the voltage biasing module; The source of the first NMOS tube is electrically connected with the source of the second NMOS tube, the drain of the first NMOS tube is electrically connected with the first end of the second current mirror module, and the gate of the first NMOS tube is used to receive the second bias voltage generated by the voltage biasing module; The drain of the second NMOS tube is electrically connected with the first end of the third current mirror module, and the gate of the second NMOS tube is electrically connected with the second end of the first capacitor; The drain of the third NMOS tube is electrically connected with the first end of the third current mirror module, and the gate of the third NMOS tube is electrically connected with the second end of the second capacitor; The voltage source module is used to output a constant working current to the first current mirror module, the second current mirror module, the third current mirror module and the voltage biasing module; The first current mirror module is used to copy the constant current generated by the voltage source module to the first end of the first resistor and the first end of the second resistor; The second current mirror module is used to output a first comparison current to the original signal output port; The third current mirror module is configured to output a second comparison current to the original signal output port. The original signal output port generates an original signal based on the first comparison current and the second comparison current.

[0012] In the new low-delay demodulation circuit, the first capacitor and the first resistor form a high-pass filter, and the second capacitor and the second resistor form another high-pass filter, which are used to convert the input original modulation signal into a differential modulation signal at the gates of the second NMOS transistor and the third NMOS transistor. The first current mirror module copies the constant current generated by the voltage source module to the first end of the first resistor and the first end of the second resistor, so that when the original modulation signal changes from input to no input, the voltage of the first capacitor and the second capacitor can be quickly discharged through the first current mirror module, and the output original signal can be quickly reversed according to the change of the differential modulation signal, thereby significantly reducing the delay t dhl .

[0013] Meanwhile, the first current mirror module makes the voltage discharge speed no longer dominated by the first resistor and the second resistor, allowing the values of the first resistor and the second resistor to be increased, thereby improving the amplification capability of the differential demodulation module to the input original modulation signal, obtaining a differential modulation signal with higher amplitude and better quality, and making the output original signal quickly reversed according to the change of the differential modulation signal, thereby significantly reducing the delay t dlh .

[0014] In summary, the new low-delay demodulation circuit significantly reduces the signal demodulation delay t dhl and t dlh of the demodulation circuit while effectively ensuring the signal demodulation function, thereby effectively improving the output quality of the original signal and the signal demodulation rate.

[0015] It should be noted that the second current mirror module copies the current flowing through the first NMOS transistor as the first comparison current, and the third current mirror module copies the current flowing through the second NMOS transistor and the current of the third NMOS transistor as the second comparison current. The voltage biasing module is configured to provide a first bias voltage and a second bias voltage, so that when the original modulation signal is not input, the first comparison current generated by the second current mirror module is greater than the second comparison current generated by the third current mirror module, and the original signal output port generates an original signal that changes to a low level.

[0016] When the original modulation signal is input, the differential modulation signal is superimposed on the first end of the first resistor and the first end of the second resistor, so that the voltage amplitude of the end point is much greater than the voltage difference between the first bias voltage and the second bias voltage, resulting in a first comparison current I thThe second comparison current I CM The original signal output port generates an original signal transition to a high level.

[0017] Further, the first current mirror module includes a first PMOS tube, a fourth NMOS tube, a fifth NMOS tube, and a sixth NMOS tube, wherein: the source of the first PMOS tube is electrically connected to the first end of the voltage source module, and the gate of the first PMOS tube is electrically connected to the second end of the voltage source module; The source of the fourth NMOS tube is electrically connected to the third end of the voltage bias module, and the drain and gate of the fourth NMOS tube are electrically connected to the drain of the first PMOS tube; The source of the fifth NMOS tube is electrically connected to the third end of the voltage bias module, the drain of the fifth NMOS tube is electrically connected to the first end of the first resistor, and the gate of the fifth NMOS tube is electrically connected to the gate of the fourth NMOS tube; The source of the sixth NMOS tube is electrically connected to the third end of the voltage bias module, the drain of the sixth NMOS tube is electrically connected to the first end of the second resistor, and the gate of the sixth NMOS tube is electrically connected to the gate of the fourth NMOS tube.

[0018] In this implementation, the first PMOS tube, the fourth NMOS tube, the fifth NMOS tube, and the sixth NMOS tube constitute a current mirror, which copies the constant operating current received by the first PMOS tube from the voltage source module to the fifth NMOS tube and the sixth NMOS tube. Since the drains of the fifth NMOS tube and the sixth NMOS tube are respectively connected to the first ends of the first resistor and the second resistor, the first ends of the first resistor and the second resistor are equivalent to being connected to a constant current source. This circuit structure design makes the voltage V inp at the second end of the second capacitor inn can be quickly discharged through the fifth NMOS tube and the sixth NMOS tube, so that the second comparison current I CM transmitted to the third current mirror module is smaller than the first comparison current I th transmitted to the second current mirror module, so that the original signal V DMOD output by the original signal output module flips to a low level faster. The delay t dhl of the output transition from a high level to a low level of the demodulation circuit is significantly reduced.

[0019] Since the voltage discharge speed of the first capacitor and the second capacitor is accelerated by the first current mirror module when the original modulation signal input turns to zero, and is no longer shackled by the first resistor and the second resistor, the application can increase the resistance value of the first resistor and the second resistor, so that when the original modulation signal input turns from zero input to positive input, the signal amplification degree of amplifying the original modulation signal to the differential modulation signal can be improved, so that the second comparison current I CM is transmitted to the second current mirror module is greater than the first comparison current I th transmitted to the second current mirror module, so that the original signal V DMOD output by the original signal output module turns to high level faster, significantly reducing the delay t dlh from low level output to high level output of the demodulation circuit.

[0020] In this implementation, the first capacitor and the first resistor constitute a high-pass filter, and the second capacitor and the second resistor constitute another high-pass filter, which filters out the direct current voltage in the original modulation signal. After increasing the resistance value of the first resistor and the second resistor, the voltage difference between the first end of the resistor and the first bias voltage of the second end of the resistor after superimposing the differential modulation signal voltage on the first end of the resistor can be increased, thereby generating a larger overdrive voltage, and further improving the current value change rate of the first comparison current and the second comparison current, so that the original signal V DMOD turns to high level faster.

[0021] Further, the voltage biasing module comprises a second PMOS tube, a third resistor, a fourth resistor, a seventh NMOS tube and an eighth NMOS tube; wherein: the source of the second PMOS tube is electrically connected with the first end of the voltage source module, the drain of the second PMOS tube is electrically connected with the first end of the third resistor, and the gate of the second PMOS tube is electrically connected with the second end of the voltage source module; the first end of the third resistor is electrically connected with the gate of the first NMOS tube, and the second end of the third resistor is electrically connected with the first end of the fourth resistor; the second end of the third resistor serves as the third end of the voltage biasing module; the second end of the first resistor and the second end of the second resistor are respectively electrically connected with the first end of the fourth resistor; the source of the seventh NMOS tube and the drain of the eighth NMOS tube are electrically connected, and the drain and the gate of the seventh NMOS tube are both electrically connected with the second end of the fourth resistor; the source of the eighth NMOS tube is grounded, and the gate of the eighth NMOS tube is electrically connected with the second end of the fourth resistor.

[0022] In this implementation, the first end of the third resistor in the voltage biasing module provides a second bias voltage Vth , the second end of the third resistor provides a second bias voltage V CM to the second NMOS transistor and the third NMOS transistor. Since the second PMOS transistor receives a constant working current transmitted by the voltage source, the eighth PMOS transistor is grounded, so that the first end of the third resistor becomes a high voltage end of the resistor, and the second end of the third resistor becomes a low voltage end of the resistor, so that the second bias voltage V th is constant and greater than the first bias voltage V CM .

[0023] The second bias voltage V th is constant and greater than the first bias voltage V CM . The smaller the voltage difference between the second bias voltage V DMOD and the first bias voltage V dlh , the smaller the delay t DMOD caused by the change of the original signal V dhl from a low level to a high level; the greater the voltage difference between the second bias voltage V th and the first bias voltage V CM , the greater the delay t DMOD caused by the change of the original signal V dlh from a high level to a low level. By changing the resistance value of the third resistor, the voltage difference between the second bias voltage V DMOD and the first bias voltage V dhl can be adjusted, so that the difference between t th and t CM is adjusted, so that the difference between t dlh and t dhl is minimized, thereby reducing the distortion of signal demodulation, so that the pulse width distortion of the entire circuit is less than 5 ns.

[0024] Preferably, in an implementation, the size of the first NMOS transistor is equal to the sum of the sizes of the second NMOS transistor and the third NMOS transistor, so that the width / length ratio of the first NMOS transistor, the second NMOS transistor and the third NMOS transistor is 2:1:1. When the receiver does not receive a carrier signal, only the first bias voltage V inp is present on V inn , V CM , and V th , and the second bias voltage V CM is constant and greater than the first bias voltage V th , and the width / length ratio of the first NMOS transistor, the second NMOS transistor and the third NMOS transistor is 2:1:1, the current I CM flowing through the first NMOS transistor is a first comparison current I DMOM greater than a second comparison current I inp flowing through the second NMOS transistor and the third NMOS transistor, so that the original signal V inn is changed from a low level to a high level.The flip-flop is low. When the receiver receives the carrier signal, V inp , V inn The first bias voltage V CM is superimposed with a differential modulation signal, whose amplitude is much larger than the second bias voltage V th . The first bias voltage V CM is different from the second bias voltage V th , so the first comparison current I CM flowing through the first NMOS transistor is smaller than the second comparison current I DMOM flowing through the second and third NMOS transistors. Therefore, after several carrier cycles, V inp becomes high. When the transmitter stops generating the carrier signal, the differential modulation signal disappears, and only the first bias voltage V inn remains. The first bias voltage V CM is different from the second bias voltage V th , so the first comparison current I CM flowing through the first NMOS transistor is larger than the second comparison current I DMOM flowing through the second and third NMOS transistors. Therefore, after several carrier cycles, V th becomes low.

[0025] Further, the second current mirror module includes a third PMOS transistor, a fourth PMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, and a first voltage source. The source of the third PMOS transistor is electrically connected to the first end of the voltage source module, and the drain and gate of the third PMOS transistor are both electrically connected to the drain of the first NMOS transistor. The source of the fourth PMOS transistor is electrically connected to the first end of the voltage source module, and the gate of the fourth PMOS transistor is electrically connected to the gate of the third PMOS transistor. The source of the ninth NMOS transistor is grounded, the drain and gate of the ninth NMOS transistor are both electrically connected to the drain of the fourth PMOS transistor, and the gate of the ninth NMOS transistor is electrically connected to the gate of the tenth NMOS transistor. The source of the tenth NMOS transistor is grounded, and the drain and gate of the tenth NMOS transistor are both electrically connected to the original signal output port. The source of the second NMOS transistor and the source of the third NMOS transistor are grounded through the first voltage source.

[0026] In this implementation, the third PMOS transistor, the fourth PMOS transistor, the ninth NMOS transistor, and the tenth NMOS transistor constitute a current mirror, which copies the first comparison current I th from the drain of the first NMOS transistor to the drain of the tenth NMOS transistor, thereby inputting the first comparison current I th to the original signal output port.

[0027] Preferably, in an implementation, the first voltage source is configured to provide a constant static bias voltage as a static working point for the first NMOS transistor, the second NMOS transistor and the third NMOS transistor. By changing the voltage of the first voltage source and increasing the current at the first voltage source, the static working point of the first NMOS transistor, the second NMOS transistor and the third NMOS transistor can be changed, so as to increase the charging and discharging speed of the first capacitor and the second capacitor, and further reduce the signal demodulation delay.

[0028] When the current value at the first voltage source is increased and reaches the saturation region of the first NMOS transistor, the second NMOS transistor and the third NMOS transistor, continuously increasing the current value of the first voltage source has little effect on reducing the signal demodulation delay. At this time, by providing a voltage discharge channel for the differential demodulation module through the first current mirror module, the saturation region of the first NMOS transistor, the second NMOS transistor and the third NMOS transistor can be overcome, and the signal demodulation delay can be further reduced.

[0029] Further, the third current mirror module includes a fifth PMOS transistor and a sixth PMOS transistor; wherein: the source of the fifth PMOS transistor is electrically connected to the first end of the voltage source module, and the drain and the gate of the fifth PMOS transistor serve as the first end of the third current mirror module; the source of the sixth PMOS transistor is electrically connected to the first end of the voltage source module, the drain of the sixth PMOS transistor is electrically connected to the original signal output port, and the gate of the sixth PMOS transistor is electrically connected to the gate of the fifth PMOS transistor.

[0030] In this implementation, the fifth PMOS transistor and the sixth PMOS transistor constitute a current mirror, which copies the second comparison current I CM from the drains of the second NMOS transistor and the third NMOS transistor to the drain of the sixth PMOS transistor, so as to input the second comparison current I CM to the original signal output port.

[0031] Further, the voltage source module includes a fifth PMOS transistor, a second voltage source, an eleventh NMOS transistor and a twelfth NMOS transistor; wherein: the source of the fifth PMOS transistor serves as the first end of the voltage source module, and the drain and the gate of the fifth PMOS transistor serve as the second end of the voltage source module; the negative end of the second voltage source is electrically connected to the source of the fifth PMOS transistor; the source of the eleventh NMOS transistor is grounded, and the drain and the gate of the eleventh NMOS transistor are both electrically connected to the positive end of the second voltage source; The source of the twelfth NMOS is grounded, the drain of the twelfth NMOS is electrically connected with the drain of the fifth PMOS, and the gate of the twelfth NMOS is electrically connected with the gate of the eleventh NMOS.

[0032] In the implementation, the fifth PMOS, the eleventh NMOS and the twelfth NMOS constitute a current mirror, the constant working current output by the second voltage source is copied to the gate of the fifth PMOS, and then the constant working current is output to the first current mirror module, the second current mirror module, the third current mirror module and the voltage bias module.

[0033] The second aspect of the application provides a novel low-delay demodulation system, comprising a novel low-delay demodulation circuit and a high-bandwidth peak gain amplifier; the novel low-delay demodulation circuit comprises a differential demodulation module, a first current mirror module, a second current mirror module, a third current mirror module, a voltage bias module, a voltage source module and an original signal output port; wherein: The high-bandwidth peak gain amplifier is used for amplifying an external carrier signal input into an original modulation signal output; The voltage source module is used for outputting a constant working current to the first current mirror module, the second current mirror module, the third current mirror module and the voltage bias module; The first current mirror module is used for copying the constant working current to the differential demodulation module; The voltage bias module is used for generating a first bias voltage and a second bias voltage; The differential demodulation module is used for converting an external original modulation signal input into a first comparison current and a second comparison current according to the first bias voltage and the second bias voltage; The second current mirror module is used for transmitting the first comparison current to the original signal output port; The third current mirror module is used for transmitting the second comparison current to the original signal output port; The original signal output port is used for comparing the first comparison current and the second comparison current, and then generating an original signal.

[0034] A carrier signal refers to a basic signal used for transmitting information in communication. In the novel low-delay demodulation system, the high-bandwidth peak gain amplifier amplifies an external carrier signal to obtain an original modulation signal which can be processed by a subsequent demodulation circuit, and then inputs the original modulation signal to the differential demodulation module of the novel low-delay demodulation circuit.

[0035] The new low-delay demodulation circuit can quickly discharge the voltage of the differential demodulation module through the first current mirror module when the original modulation signal is converted from input to no input, so that the output original signal can be quickly reversed according to the conversion of the differential modulation signal, and the delay t of the demodulation circuit from high-level output to low-level output is significantly reduced dhl .

[0036] Meanwhile, the first current mirror module assists the differential demodulation module in voltage discharge, so that the differential demodulation module can improve the amplification capability of the input original modulation signal, obtain a differential modulation signal with higher amplitude and better quality, and will not have a negative impact on the demodulation rate, so that the output original signal can be quickly reversed according to the conversion of the differential modulation signal, and the delay t of the demodulation circuit from low-level output to high-level output is significantly reduced dlh .

[0037] In summary, the new low-delay demodulation circuit significantly reduces the signal demodulation delay t of the demodulation circuit on the basis of effectively ensuring the signal demodulation function dhl and t dlh , effectively improves the output quality of the original signal and the signal demodulation rate.

[0038] Further, the differential demodulation module includes a first NMOS tube, a second NMOS tube, a third NMOS tube, a first capacitor, a second capacitor, a first resistor, and a second resistor; wherein: The first end of the first capacitor is used to receive an external original modulation signal positive input, and the second end of the first capacitor is electrically connected with the first end of the first resistor; the second end of the first resistor is used to receive the first bias voltage; The first end of the second capacitor is used to receive an external original modulation signal negative input, and the second end of the second capacitor is electrically connected with the first end of the second resistor; the second end of the second resistor is used to receive the first bias voltage; The source of the first NMOS tube is electrically connected with the source of the second NMOS tube, the drain of the first NMOS tube is electrically connected with the first end of the second current mirror module, and the gate of the first NMOS tube is used to receive the second bias voltage; The drain of the second NMOS tube is electrically connected with the first end of the third current mirror module, and the gate of the second NMOS tube is electrically connected with the second end of the first capacitor; The drain of the third NMOS tube is electrically connected with the first end of the third current mirror module, and the gate of the third NMOS tube is electrically connected with the second end of the second capacitor.

[0039] Further, the first current mirror module comprises a first PMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube, wherein: the source of the first PMOS tube is electrically connected with the first end of the voltage source module, and the gate of the first PMOS tube is electrically connected with the second end of the voltage source module; the source of the fourth NMOS tube is electrically connected with the third end of the voltage bias module, and the drain and the gate of the fourth NMOS tube are electrically connected with the drain of the first PMOS tube; the source of the fifth NMOS tube is electrically connected with the third end of the voltage bias module, the drain of the fifth NMOS tube is electrically connected with the first end of the first resistor, and the gate of the fifth NMOS tube is electrically connected with the gate of the fourth NMOS tube; the source of the sixth NMOS tube is electrically connected with the third end of the voltage bias module, the drain of the sixth NMOS tube is electrically connected with the first end of the second resistor, and the gate of the sixth NMOS tube is electrically connected with the gate of the fourth NMOS tube. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1 is a structural schematic diagram of a novel low-delay demodulation circuit provided by an embodiment of the present application; Figure 2 is a structural schematic diagram of another novel low-delay demodulation circuit provided by an embodiment of the present application; Figure 3 is a working principle schematic diagram of a low-delay demodulation circuit provided by an embodiment of the present application; Figure 4 is a structural schematic diagram of a novel low-delay demodulation system provided by an embodiment of the present application. DETAILED DESCRIPTION

[0041] The present application will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments. It should be noted that the following detailed description is exemplary and is intended to provide further detailed description of the present application. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as understood by those skilled in the art to which the present application belongs; the terms used in the specification of the present application are only for the purpose of describing the specific embodiments and are not intended to limit the present application; the specification and claims of the present application and the above description of the drawings, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. The terms "first", "second" and the like in the specification and claims of the present application or the above description of the drawings are used to distinguish different objects and are not intended to describe a specific order.

[0042] The present invention aims to provide a novel low-latency demodulation circuit and system, which reduces the signal demodulation delay of the demodulation circuit and improves the demodulation rate while effectively ensuring the signal demodulation function of the demodulation circuit.

[0043] Please refer to Figure 1 To achieve the above objectives, the first embodiment of the present invention provides a novel low-delay demodulation circuit, comprising a differential demodulation module 100, a first current mirror module 210, a second current mirror module 220, a third current mirror module 230, a voltage bias module 300, a voltage source module 400, and a raw signal output port 500; wherein: The voltage source module 400 is used to output a constant operating current to the first current mirror module 210, the second current mirror module 220, the third current mirror module 230 and the voltage bias module 300; The first current mirror module 210 is used to copy the constant operating current to the differential demodulation module 100; The voltage bias module 300 is used to generate a first bias voltage and a second bias voltage; The differential demodulation module 100 is used to convert the external original modulation signal input into a first comparison current and a second comparison current according to the first bias voltage and the second bias voltage. The second current mirror module 220 is used to transmit the first comparison current to the original signal output port 500; The third current mirror module 230 is used to transmit the second comparison current to the original signal output port 500; The original signal output port 500 is used to compare the first comparison current and the second comparison current to generate the original signal.

[0044] In the aforementioned novel low-delay demodulation circuit, the constant current generated by the voltage source module 400 is copied to the differential demodulation module 100 through the first current mirror module 210. This allows the voltage of the differential demodulation module 100 to be quickly discharged through the first current mirror module 210 when the original modulation signal changes from input to no input. This enables the original output signal to quickly reverse according to the change of the differential modulation signal, significantly reducing the delay t between high-level output and low-level output after demodulation. dhl .

[0045] Meanwhile, the first current mirror module 210 assists the differential demodulation module 100 to discharge voltage, so that the differential demodulation module 100 can improve the amplification capability of the input original modulation signal, obtain a differential modulation signal with higher amplitude and better quality, and will not have a negative impact on the demodulation rate, so that the output original signal can be quickly reversed according to the transition of the differential modulation signal, significantly reducing the delay t of the demodulation circuit from low level output to high level output dlh .

[0046] In summary, the above-mentioned new low-delay demodulation circuit significantly reduces the signal demodulation delay t of the demodulation circuit on the basis of effectively ensuring the signal demodulation function dhl and t dlh , effectively improving the output quality of the original signal and the signal demodulation rate.

[0047] It should be noted that when the original modulation signal is not input, the first comparison current generated by the second current mirror module 220 is greater than the second comparison current generated by the third current mirror module 230, so that the original signal output port 500 generates a low-level transition of the original signal; when the original modulation signal is input, the first comparison current generated by the second current mirror module 220 is less than the second comparison current generated by the third current mirror module 230, so that the original signal output port 500 generates a high-level transition of the original signal, thereby realizing the demodulation of the original modulation signal.

[0048] Please refer to Figure 2 Further, the differential demodulation module 100 comprises a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3, a first capacitor C1, a second capacitor C2, a first resistor R1 and a second resistor R2; wherein: The first end of the first capacitor C1 is used for receiving an external original modulation signal positive input, and the second end of the first capacitor C1 is electrically connected with the first end of the first resistor R1; the second end of the first resistor R1 is used for receiving a first bias voltage generated by the voltage bias module 300; The first end of the second capacitor C2 is used for receiving an external original modulation signal negative input, and the second end of the second capacitor C2 is electrically connected with the first end of the second resistor R2; the second end of the second resistor R2 is used for receiving a first bias voltage generated by the voltage bias module 300; The source of the first NMOS tube MN1 is electrically connected with the source of the second NMOS tube MN2, the drain of the first NMOS tube MN1 is electrically connected with the first end of the second current mirror module 220, and the gate of the first NMOS tube MN1 is used for receiving a second bias voltage generated by the voltage bias module 300; The drain of the second NMOS tube MN2 is electrically connected with the first end of the third current mirror module 230, and the gate of the second NMOS tube MN2 is electrically connected with the second end of the first capacitor C1. The drain of the third NMOS tube MN3 is electrically connected with the first end of the third current mirror module 230, and the gate of the third NMOS tube MN3 is electrically connected with the second end of the second capacitor C2. The voltage source module 400 is used to output a constant working current to the first current mirror module 210, the second current mirror module 220, the third current mirror module 230 and the voltage bias module 300. The first current mirror module 210 is used to copy the constant current generated by the voltage source module 400 to the first end of the first resistor R1 and the first end of the second resistor R2. The second current mirror module 220 is used to output a first comparison current to the original signal output port 500. The third current mirror module 230 is used to output a second comparison current to the original signal output port 500. The original signal output port 500 generates an original signal based on the first comparison current and the second comparison current.

[0049] In the new low-delay demodulation circuit, the first capacitor C1 and the first resistor R1 constitute a high-pass filter, and the second capacitor C2 and the second resistor R2 constitute another high-pass filter, which are used to convert the input original modulation signal into a differential modulation signal at the gates of the second NMOS tube MN2 and the third NMOS tube MN3. The first current mirror module 210 copies the constant current generated by the voltage source module 400 to the first end of the first resistor R1 and the first end of the second resistor R2, so that when the original modulation signal changes from input to non-input, the voltage of the first capacitor C1 and the second capacitor C2 can be quickly discharged through the first current mirror module 210, so that the output original signal can quickly reverse according to the change of the differential modulation signal, significantly reducing the delay t dhl .

[0050] At the same time, the first current mirror module 210 makes the voltage discharge speed no longer dominated by the first resistor R1 and the second resistor R2, allowing the values of the first resistor R1 and the second resistor R2 to be increased, thereby improving the amplification capability of the differential demodulation module 100 to the input original modulation signal, obtaining a differential modulation signal with higher amplitude and better quality, so that the output original signal can quickly reverse according to the change of the differential modulation signal, significantly reducing the delay t dlh .

[0051] In summary, the new low-latency demodulation circuit significantly reduces the signal demodulation delay t dhl and t dlh , effectively improving the original signal output quality and signal demodulation rate.

[0052] It should be noted that the second current mirror module 220 copies the current flowing through the first NMOS tube MN1 as the first comparison current; the third current mirror module 230 copies the current flowing through the second NMOS tube MN2 and the current flowing through the third NMOS tube MN3 as the second comparison current. The voltage biasing module 300 is used to provide the first bias voltage and the second bias voltage, so that when the original modulation signal is not input, the first comparison current generated by the second current mirror module 220 is greater than the second comparison current generated by the third current mirror module 230, so that the original signal output port 500 generates the original signal to turn to low level.

[0053] When the original modulation signal is input, the differential modulation signal is superimposed on the first end of the first resistor R1 and the first end of the second resistor R2, so that the voltage amplitude of the end point is much larger than the voltage difference between the first bias voltage and the second bias voltage, resulting in that the first comparison current I th flowing through the first NMOS tube MN1 is less than the second comparison current I CM flowing through the second NMOS tube MN2 and the third NMOS tube MN3, so that the original signal output port 500 generates the original signal to turn to high level.

[0054] Please refer to Figure 2 Further, the first current mirror module 210 includes a first PMOS tube MP1, a fourth NMOS tube MN4, a fifth NMOS tube MN5, and a sixth NMOS tube MN6, wherein: the source of the first PMOS tube MP1 is electrically connected to the first end of the voltage source module 400, and the gate of the first PMOS tube MP1 is electrically connected to the second end of the voltage source module 400; The source of the fourth NMOS tube MN4 is electrically connected to the third end of the voltage biasing module 300, and the drain and gate of the fourth NMOS tube MN4 are electrically connected to the drain of the first PMOS tube MP1; The source of the fifth NMOS tube MN5 is electrically connected to the third end of the voltage biasing module 300, the drain of the fifth NMOS tube MN5 is electrically connected to the first end of the first resistor R1, and the gate of the fifth NMOS tube MN5 is electrically connected to the gate of the fourth NMOS tube MN4; The source of the sixth NMOS transistor MN6 is electrically connected to the third terminal of the voltage bias module 300, the drain of the sixth NMOS transistor MN6 is electrically connected to the first terminal of the second resistor R2, and the gate of the sixth NMOS transistor MN6 is electrically connected to the gate of the fourth NMOS transistor MN4.

[0055] In this embodiment, the first PMOS transistor MP1, the fourth NMOS transistor MN4, the fifth NMOS transistor MN5, and the sixth NMOS transistor MN6 form a current mirror, replicating the constant operating current received by the first PMOS transistor MP1 from the voltage source module 400 into the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6. Since the drains of the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are connected to the first terminals of the first resistor R1 and the second resistor R2, respectively, the first terminals of the first resistors R1 and R2 are equivalent to being connected to a constant current source. This circuit design ensures that when the original modulation signal input becomes zero during PWM signal modulation and demodulation, the voltage V at the second terminal of the first capacitor C1... inp The voltage V at the second terminal of the second capacitor C2 inn The second comparison current I transmitted to the third current mirror module 230 can be quickly discharged through the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6. CM Faster than the first comparison current I transmitted to the second current mirror module 220 th The original signal V output by the original signal output module DMOD Faster transition to low level. Significantly reduces the delay t_t from high-level output to low-level output after demodulation. dhl .

[0056] When the original modulation signal input becomes zero, the voltage discharge speed of the first capacitor C1 and the second capacitor C2 is accelerated by the first current mirror module 210 and is no longer constrained by the first resistor R1 and the second resistor R2. This invention can increase the resistance values ​​of the first resistor R1 and the second resistor R2, so that when the original modulation signal input changes from zero input to positive input, it can improve the signal amplification degree of amplifying the original modulation signal into a differential modulation signal, thereby increasing the second comparison current I transmitted to the third current mirror module 230. CM Faster than the first comparison current I transmitted to the second current mirror module 220 th The original signal V output by the original signal output module DMOD Faster switching to high level significantly reduces the delay t_t required for the demodulation circuit to transition from low to high output. dlh .

[0057] Wherein, the first capacitor C1 and the first resistor R1 constitute a high-pass filter, the second capacitor C2 and the second resistor R2 constitute another high-pass filter, filtering out the direct current voltage in the original modulation signal. After increasing the resistance value of the first resistor R1 and the second resistor R2, the voltage difference between the first end of the resistor superimposed with the differential modulation signal voltage and the first bias voltage between the first end of the resistor and the second end of the resistor can be increased, thereby generating a larger overdrive voltage, and further improving the current value change rate of the first comparison current and the second comparison current, so that the original signal V DMOD faster flips to high level.

[0058] Please refer to Figure 2 Further, the voltage biasing module 300 includes a second PMOS tube MP2, a third resistor R3, a fourth resistor R4, a seventh NMOS tube MN7 and an eighth NMOS tube MN8; wherein: the source of the second PMOS tube MP2 is electrically connected to the first end of the voltage source module 400, the drain of the second PMOS tube MP2 is electrically connected to the first end of the third resistor R3, and the gate of the second PMOS tube MP2 is electrically connected to the second end of the voltage source module 400; The first end of the third resistor R3 is electrically connected to the gate of the first NMOS tube MN1, and the second end of the third resistor R3 is electrically connected to the first end of the fourth resistor R4; the second end of the third resistor R3 serves as the third end of the voltage biasing module 300; The second end of the first resistor R1 and the second end of the second resistor R2 are respectively electrically connected to the first end of the fourth resistor R4; The source of the seventh NMOS tube MN7 and the drain of the eighth NMOS tube MN8 are electrically connected, and the drain and the gate of the seventh NMOS tube MN7 are both electrically connected to the second end of the fourth resistor R4; The source of the eighth NMOS tube MN8 is grounded, and the gate of the eighth NMOS tube MN8 is electrically connected to the second end of the fourth resistor R4.

[0059] In this embodiment, in the voltage biasing module 300, the first end of the third resistor R3 provides a second bias voltage V th for the first NMOS tube MN1, and the second end of the third resistor R3 provides a first bias voltage V CM for the second NMOS tube MN2 and the third NMOS tube MN3. Since the second PMOS tube MP2 receives a constant working current transmitted by the voltage source and the eighth PMOS tube is grounded, the first end of the third resistor R3 becomes a resistor high-voltage end, the second end of the third resistor R3 becomes a resistor low-voltage end, and the second bias voltage V th is constant and greater than the first bias voltage V CM .

[0060] second bias voltage V th with the first bias voltage V CM The smaller the differential voltage, the smaller the delay t DMOD The smaller the delay t dlh The smaller the differential voltage, the smaller the delay t DMOD The smaller the delay t dhl The larger the differential voltage, the larger the delay t th with the first bias voltage V CM The larger the differential voltage, the larger the delay t DMOD The larger the delay t dlh The larger the differential voltage, the larger the delay t DMOD The larger the delay t dhl The smaller the differential voltage, the smaller the delay t th with the first bias voltage V CM The differential voltage, thereby adjusting t dlh The differential voltage, thereby adjusting t dhl The differential voltage, thereby adjusting t dlh The differential voltage, thereby adjusting t dhl The differential voltage, thereby adjusting t

[0061] Please refer to Figure 3 , preferably, in an embodiment, the size of the first NMOS transistor MN1 is equal to the sum of the second NMOS transistor MN2 and the third NMOS transistor MN3, so that the width / length ratio of the first NMOS transistor MN1, the second NMOS transistor MN2 and the third NMOS transistor MN3 is 2:1:1. When the receiver does not receive the carrier signal, V inp , V inn only has the first bias voltage V CM , since the second bias voltage V th is always greater than the first bias voltage V CM , and the width / length ratio of the first NMOS transistor MN1, the second NMOS transistor MN2 and the third NMOS transistor MN3 is 2:1:1, the current flowing through the first NMOS transistor MN1 is the first comparison current I th is greater than the second comparison current I CM flowing through the second NMOS transistor MN2 and the third NMOS transistor MN3, so that the original signal V DMOD is inverted to low level. When the receiver receives the carrier signal, V inp , V inn is superimposed with the first bias voltage V CM , and the amplitude is much greater than the second bias voltage V th with the first bias voltage V CMThe first comparison current I flowing through the first NMOS transistor MN1 is greater than the second comparison current I flowing through the second NMOS transistor MN2 and the third NMOS transistor MN3 th The first comparison current I flowing through the first NMOS transistor MN1 is greater than the second comparison current I flowing through the second NMOS transistor MN2 and the third NMOS transistor MN3 CM Therefore, after a few carrier cycle delays t dlh The original signal output V DMOD becomes high. When the transmitter stops generating the carrier signal, V inp , V inn The upper differential modulation signal disappears, and only the first bias voltage V CM The first comparison current I flowing through the first NMOS transistor MN1 is greater than the second comparison current I flowing through the second NMOS transistor MN2 and the third NMOS transistor MN3 th The first comparison current I flowing through the first NMOS transistor MN1 is greater than the second comparison current I flowing through the second NMOS transistor MN2 and the third NMOS transistor MN3 CM Therefore, after a few carrier cycle delays t dhl The original signal output V DMOD becomes low.

[0062] Further, the second current mirror module 220 includes a third PMOS transistor MP3, a fourth PMOS transistor MP4, a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, and a first voltage source U1; wherein: The source of the third PMOS transistor MP3 is electrically connected to the first end of the voltage source module 400, and the drain and gate of the third PMOS transistor MP3 are both electrically connected to the drain of the first NMOS transistor MN1; The source of the fourth PMOS transistor MP4 is electrically connected to the first end of the voltage source module 400, and the gate of the fourth PMOS transistor MP4 is electrically connected to the gate of the third PMOS transistor MP3; The source of the ninth NMOS transistor MN9 is grounded, the drain and gate of the ninth NMOS transistor MN9 are both electrically connected to the drain of the fourth PMOS transistor MP4, and the gate of the ninth NMOS transistor MN9 is electrically connected to the gate of the tenth NMOS transistor MN10; The source of the tenth NMOS transistor MN10 is grounded, and the drain and gate of the tenth NMOS transistor MN10 are both electrically connected to the original signal output port 500; The source of the second NMOS transistor MN2 and the source of the third NMOS transistor MN3 are grounded through the first voltage source U1.

[0063] In this embodiment, the third PMOS transistor MP3, the fourth PMOS transistor MP4, the ninth NMOS transistor MN9, and the tenth NMOS transistor MN10 constitute a current mirror, which copies the first comparison current I th from the drain of the first NMOS transistor MN1 to the drain of the tenth NMOS transistor MN10, thereby copying the first comparison current Ith The input is connected to the original signal output port 500.

[0064] Preferably, in an embodiment, the first voltage source U1 is used to provide a constant static bias voltage as a static working point for the first NMOS transistor MN1, the second NMOS transistor MN2 and the third NMOS transistor MN3. By changing the voltage of the first voltage source U1, the current at the first voltage source U1 is increased, the static working point of the first NMOS transistor MN1, the second NMOS transistor MN2 and the third NMOS transistor MN3 can be changed, thereby increasing the charging and discharging speed of the first capacitor C1 and the second capacitor C2, and further reducing the signal demodulation delay.

[0065] When the voltage of the first voltage source U1 is changed, the current value provided by the first voltage source U1 is increased, and after reaching the saturation region of the first NMOS transistor MN1, the second NMOS transistor MN2 and the third NMOS transistor MN3, continuing to increase the current value of the first voltage source U1 has little effect on reducing the signal demodulation delay. At this time, by providing a voltage discharge channel for the differential demodulation module 100 through the first current mirror module 210, the saturation region of the first NMOS transistor MN1, the second NMOS transistor MN2 and the third NMOS transistor MN3 can be overcome, and the signal demodulation delay can be further reduced.

[0066] Further, the third current mirror module 230 includes a fifth PMOS transistor MP5 and a sixth PMOS transistor MP6; wherein: the source of the fifth PMOS transistor MP5 is electrically connected to the first end of the voltage source module 400, and the drain and gate of the fifth PMOS transistor MP5 serve as the first end of the third current mirror module 230; The source of the sixth PMOS transistor MP6 is electrically connected to the first end of the voltage source module 400, the drain of the sixth PMOS transistor MP6 is electrically connected to the original signal output port 500, and the gate of the sixth PMOS transistor MP6 is electrically connected to the gate of the fifth PMOS transistor MP5.

[0067] In this embodiment, the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 constitute a current mirror, which copies the second comparison current I CM from the drains of the second NMOS transistor MN2 and the third NMOS transistor MN3 to the drain of the sixth PMOS transistor MP6, thereby copying the second comparison current I CM The input is connected to the original signal output port 500.

[0068] Further, the voltage source module 400 includes a fifth PMOS transistor MP5, a second voltage source U2, an eleventh NMOS transistor MN11 and a twelfth NMOS transistor MN12; wherein: The source of the fifth PMOS tube MP5 is the first end of the voltage source module 400, and the drain and gate of the fifth PMOS tube MP5 are the second end of the voltage source module 400. The negative end of the second voltage source U2 is electrically connected with the source of the fifth PMOS tube MP5. The source of the eleventh NMOS tube MN11 is grounded, and the drain and gate of the eleventh NMOS tube MN11 are electrically connected with the positive end of the second voltage source U2. The source of the twelfth NMOS tube MN12 is grounded, the drain of the twelfth NMOS tube MN12 is electrically connected with the drain of the fifth PMOS tube MP5, and the gate of the twelfth NMOS tube MN12 is electrically connected with the gate of the eleventh NMOS tube MN11.

[0069] In this embodiment, the fifth PMOS tube MP5, the eleventh NMOS tube MN11 and the twelfth NMOS tube MN12 constitute a current mirror, which copies the constant working current output by the second voltage source U2 to the gate of the fifth PMOS tube MP5, and then outputs the constant working current to the first current mirror module 210, the second current mirror module 220, the third current mirror module 230 and the voltage bias module 300.

[0070] Please refer to Figure 4 The second embodiment of the present application provides a novel low-delay demodulation system, which comprises a novel low-delay demodulation circuit and a high-bandwidth peak gain amplifier; the novel low-delay demodulation circuit comprises a differential demodulation module 100, a first current mirror module 210, a second current mirror module 220, a third current mirror module 230, a voltage bias module 300, a voltage source module 400 and an original signal output port 500; wherein: The high-bandwidth peak gain amplifier is used for amplifying an external carrier signal input into an original modulation signal output; The voltage source module 400 is used for outputting a constant working current to the first current mirror module 210, the second current mirror module 220, the third current mirror module 230 and the voltage bias module 300; The first current mirror module 210 is used for copying the constant working current to the differential demodulation module 100; The voltage bias module 300 is used for generating a first bias voltage and a second bias voltage; The differential demodulation module 100 is used for converting an external original modulation signal input into a first comparison current and a second comparison current according to the first bias voltage and the second bias voltage; The second current mirror module 220 is used for transmitting the first comparison current to the original signal output port 500; The third current mirror module 230 is used to transmit the second comparison current to the original signal output port 500. The original signal output port 500 is used to compare the first comparison current and the second comparison current, thereby generating an original signal.

[0071] The carrier signal refers to a basic signal used for transmitting information in communication. In the above-mentioned new low-delay demodulation system, the high-bandwidth peak gain amplifier amplifies the external carrier signal to obtain an original modulation signal that can be processed by the subsequent demodulation circuit, and then inputs the original modulation signal to the differential demodulation module 100 of the new low-delay demodulation circuit.

[0072] In the above-mentioned new low-delay demodulation circuit, the constant current generated by the voltage source module 400 is copied to the differential demodulation module 100 through the first current mirror module 210, so that when the original modulation signal changes from input to non-input, the voltage of the differential demodulation module 100 can be quickly discharged through the first current mirror module 210, so that the output original signal can quickly reverse according to the change of the differential modulation signal, significantly reducing the delay t dhl .

[0073] At the same time, the first current mirror module 210 assists the differential demodulation module 100 to discharge voltage, so that the differential demodulation module 100 can improve the amplification capability of the input original modulation signal to obtain a differential modulation signal with higher amplitude and better quality, without negatively affecting the demodulation rate, so that the output original signal can quickly reverse according to the change of the differential modulation signal, significantly reducing the delay tdlh of the demodulation circuit from low-level output to high-level output.

[0074] In summary, the above-mentioned new low-delay demodulation circuit significantly reduces the signal demodulation delay tdlh and tdlh of the demodulation circuit on the basis of effectively ensuring the signal demodulation function, effectively improving the original signal output quality and signal demodulation rate.

[0075] Further, the differential demodulation module 100 includes a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3, a first capacitor C1, a second capacitor C2, a first resistor R1, and a second resistor R2; wherein: The first end of the first capacitor C1 is used to receive an external original modulation signal positive input, and the second end of the first capacitor C1 is electrically connected with the first end of the first resistor R1; the second end of the first resistor R1 is used to receive the first bias voltage; The first end of the second capacitor C2 is configured to receive an external original modulated signal negative input, and the second end of the second capacitor C2 is electrically connected with the first end of the second resistor R2; and the second end of the second resistor R2 is configured to receive the first bias voltage. The source of the first NMOS transistor MN1 is electrically connected with the source of the second NMOS transistor MN2, the drain of the first NMOS transistor MN1 is electrically connected with the first end of the second current mirror module 220, and the gate of the first NMOS transistor MN1 is configured to receive the second bias voltage. The drain of the second NMOS transistor MN2 is electrically connected with the first end of the third current mirror module 230, and the gate of the second NMOS transistor MN2 is electrically connected with the second end of the first capacitor C1. The drain of the third NMOS transistor MN3 is electrically connected with the first end of the third current mirror module 230, and the gate of the third NMOS transistor MN3 is electrically connected with the second end of the second capacitor C2.

[0076] Further, the first current mirror module 210 comprises a first PMOS transistor MP1, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5 and a sixth NMOS transistor MN6, wherein: the source of the first PMOS transistor MP1 is electrically connected with the first end of the voltage source module 400, and the gate of the first PMOS transistor MP1 is electrically connected with the second end of the voltage source module 400; The source of the fourth NMOS transistor MN4 is electrically connected with the third end of the voltage bias module 300, and the drain and the gate of the fourth NMOS transistor MN4 are both electrically connected with the drain of the first PMOS transistor MP1; The source of the fifth NMOS transistor MN5 is electrically connected with the third end of the voltage bias module 300, the drain of the fifth NMOS transistor MN5 is electrically connected with the first end of the first resistor R1, and the gate of the fifth NMOS transistor MN5 is electrically connected with the gate of the fourth NMOS transistor MN4; The source of the sixth NMOS transistor MN6 is electrically connected with the third end of the voltage bias module 300, the drain of the sixth NMOS transistor MN6 is electrically connected with the first end of the second resistor R2, and the gate of the sixth NMOS transistor MN6 is electrically connected with the gate of the fourth NMOS transistor MN4.

[0077] The term "embodiment" mentioned in this document means that the specific features, structures, or characteristics described in connection with the embodiment can be included in at least one embodiment of the present application. The phrase appears at various places in the specification does not necessarily all refer to the same embodiment, nor is it necessarily independent or alternative embodiments to other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments. In order to make the description simple, all possible combinations of the above-mentioned technical features in the embodiments are not described, however, as long as the combinations of the technical features do not contradict, it should be considered that they are within the scope described in the specification.

[0078] The above-described embodiments only express several implementation manners of the present application, which are described in a more specific and detailed manner, but should not be understood as a limitation on the patent scope of the present application. It should be noted that for those skilled in the art, several improvements and replacements can be made without departing from the concept of the present application, and these improvements and replacements should also be regarded as the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A novel low latency demodulation circuit characterized by, The differential demodulation module, the first current mirror module, the second current mirror module, the third current mirror module, the voltage biasing module, the voltage source module and the original signal output port are included. The voltage source module is configured to output a constant working current to the first current mirror module, the second current mirror module, the third current mirror module and the voltage biasing module. The first current mirror module is configured to copy the constant working current to the differential demodulation module. The voltage biasing module is configured to generate a first bias voltage and a second bias voltage. The differential demodulation module is configured to convert an external original modulated signal input into a first comparison current and a second comparison current according to the first bias voltage and the second bias voltage. The second current mirror module is configured to transmit the first comparison current to the original signal output port. The third current mirror module is configured to transmit the second comparison current to the original signal output port. The original signal output port is configured to compare the first comparison current and the second comparison current to generate an original signal.

2. A novel low latency demodulation circuit as claimed in claim 1, wherein, The differential demodulation module includes a first NMOS tube, a second NMOS tube, a third NMOS tube, a first capacitor, a second capacitor, a first resistor and a second resistor. A first end of the first capacitor is configured to receive an external original modulated signal positive input, and a second end of the first capacitor is electrically connected with a first end of the first resistor. A first end of the second capacitor is configured to receive an external original modulated signal negative input, and a second end of the second capacitor is electrically connected with a first end of the second resistor. A source of the first NMOS tube is electrically connected with a source of the second NMOS tube, a drain of the first NMOS tube is electrically connected with a first end of the second current mirror module, and a gate of the first NMOS tube is configured to receive the second bias voltage. A drain of the second NMOS tube is electrically connected with a first end of the third current mirror module, and a gate of the second NMOS tube is electrically connected with a second end of the first capacitor. A drain of the third NMOS tube is electrically connected with a first end of the third current mirror module, and a gate of the third NMOS tube is electrically connected with a second end of the second capacitor.

3. A novel low latency demodulation circuit as claimed in claim 2, wherein, The first current mirror module includes a first PMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube. A source of the fourth NMOS tube is electrically connected with a third end of the voltage biasing module, and a drain and a gate of the fourth NMOS tube are electrically connected with a drain of the first PMOS tube. A source of the fifth NMOS tube is electrically connected with the third end of the voltage biasing module, a drain of the fifth NMOS tube is electrically connected with the first end of the first resistor, and a gate of the fifth NMOS tube is electrically connected with a gate of the fourth NMOS tube. The source of the sixth NMOS tube is electrically connected with the third end of the voltage bias module, the drain of the sixth NMOS tube is electrically connected with the first end of the second resistor, and the gate of the sixth NMOS tube is electrically connected with the gate of the fourth NMOS tube.

4. A novel low latency demodulation circuit as claimed in claim 2, wherein, The voltage bias module comprises a second PMOS tube, a third resistor, a fourth resistor, a seventh NMOS tube and an eighth NMOS tube; wherein: the source of the second PMOS tube is electrically connected with the first end of the voltage source module, the drain of the second PMOS tube is electrically connected with the first end of the third resistor, and the gate of the second PMOS tube is electrically connected with the second end of the voltage source module; The first end of the third resistor is electrically connected with the gate of the first NMOS tube, the second end of the third resistor is electrically connected with the first end of the fourth resistor; and the second end of the third resistor serves as the third end of the voltage bias module; The second end of the first resistor and the second end of the second resistor are respectively electrically connected with the first end of the fourth resistor; The source of the seventh NMOS tube and the drain of the eighth NMOS tube are electrically connected, the drain and the gate of the seventh NMOS tube are both electrically connected with the second end of the fourth resistor; The source of the eighth NMOS tube is grounded, and the gate of the eighth NMOS tube is electrically connected with the second end of the fourth resistor.

5. A novel low latency demodulation circuit as claimed in claim 2, wherein, The second current mirror module comprises a third PMOS tube, a fourth PMOS tube, a ninth NMOS tube, a tenth NMOS tube and a first voltage source; wherein: The source of the third PMOS tube is electrically connected with the first end of the voltage source module, and the drain and the gate of the third PMOS tube are both electrically connected with the drain of the first NMOS tube; The source of the fourth PMOS tube is electrically connected with the first end of the voltage source module, and the gate of the fourth PMOS tube is electrically connected with the gate of the third PMOS tube; The source of the ninth NMOS tube is grounded, the drain and the gate of the ninth NMOS tube are both electrically connected with the drain of the fourth PMOS tube, and the gate of the ninth NMOS tube is electrically connected with the gate of the tenth NMOS tube; The source of the tenth NMOS tube is grounded, and the drain and the gate of the tenth NMOS tube are both electrically connected with the original signal output port; The source of the second NMOS tube and the source of the third NMOS tube are grounded through the first voltage source.

6. A novel low latency demodulation circuit as claimed in claim 2, wherein, The third current mirror module comprises a fifth PMOS tube and a sixth PMOS tube; wherein: the source of the fifth PMOS tube is electrically connected with the first end of the voltage source module, and the drain and the gate of the fifth PMOS tube serve as the first end of the third current mirror module; The source of the sixth PMOS tube is electrically connected with the first end of the voltage source module, the drain of the sixth PMOS tube is electrically connected with the original signal output port, and the gate of the sixth PMOS tube is electrically connected with the gate of the fifth PMOS tube.

7. A novel low latency demodulation circuit as claimed in claim 2, wherein, The voltage source module comprises a fifth PMOS tube, a second voltage source, an eleventh NMOS tube and a twelfth NMOS tube; wherein: The source of the fifth PMOS tube is the first end of the voltage source module, and the drain and gate of the fifth PMOS tube are the second end of the voltage source module; The negative end of the second voltage source is electrically connected with the source of the fifth PMOS tube; The source of the eleventh NMOS tube is grounded, and the drain and gate of the eleventh NMOS tube are electrically connected with the positive end of the second voltage source; The source of the twelfth NMOS tube is grounded, the drain of the twelfth NMOS tube is electrically connected with the drain of the fifth PMOS tube, and the gate of the twelfth NMOS tube is electrically connected with the gate of the eleventh NMOS tube.

8. A novel low latency demodulation system characterized by, The application relates to a new low-delay demodulation circuit and a high-bandwidth peak gain amplifier; the new low-delay demodulation circuit comprises a differential demodulation module, a first current mirror module, a second current mirror module, a third current mirror module, a voltage biasing module, a voltage source module and an original signal output port; wherein: The high-bandwidth peak gain amplifier is used for amplifying an external carrier signal input into an original modulation signal output; The voltage source module is used for outputting a constant working current to the first current mirror module, the second current mirror module, the third current mirror module and the voltage biasing module; The first current mirror module is used for copying the constant working current to the differential demodulation module; The voltage biasing module is used for generating a first bias voltage and a second bias voltage; The differential demodulation module is used for converting an external original modulation signal input into a first comparison current and a second comparison current according to the first bias voltage and the second bias voltage; The second current mirror module is used for transmitting the first comparison current to the original signal output port; The third current mirror module is used for transmitting the second comparison current to the original signal output port; The original signal output port is used for comparing the first comparison current and the second comparison current to generate an original signal.

9. A novel low latency demodulation system as claimed in claim 8, wherein, The differential demodulation module comprises a first NMOS tube, a second NMOS tube, a third NMOS tube, a first capacitor, a second capacitor, a first resistor and a second resistor; wherein: The first end of the first capacitor is used for receiving an external original modulation signal positive input, and the second end of the first capacitor is electrically connected with the first end of the first resistor; the second end of the first resistor is used for receiving the first bias voltage; The first end of the first capacitor is used for receiving an external original modulation signal positive input, and the second end of the first capacitor is electrically connected with the first end of the first resistor; the second end of the first resistor is used for receiving the first bias voltage; The source of the first NMOS tube is electrically connected with the source of the second NMOS tube, the drain of the first NMOS tube is electrically connected with the first end of the second current mirror module, and the gate of the first NMOS tube is used for receiving the second bias voltage; The drain of the second NMOS tube is electrically connected with the first end of the third current mirror module, and the gate of the second NMOS tube is electrically connected with the second end of the first capacitor; The drain of the third NMOS tube is electrically connected with the first end of the third current mirror module, and the gate of the third NMOS tube is electrically connected with the second end of the second capacitor.

10. A novel low latency demodulation system as claimed in claim 9, wherein, The first current mirror module comprises a first PMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube, wherein: the source of the first PMOS tube is electrically connected with the first end of the voltage source module, and the gate of the first PMOS tube is electrically connected with the second end of the voltage source module; The source of the fourth NMOS tube is electrically connected with the third end of the voltage bias module, and the drain and the gate of the fourth NMOS tube are electrically connected with the drain of the first PMOS tube; The source of the fifth NMOS tube is electrically connected with the third end of the voltage bias module, the drain of the fifth NMOS tube is electrically connected with the first end of the first resistor, and the gate of the fifth NMOS tube is electrically connected with the gate of the fourth NMOS tube; The source of the sixth NMOS tube is electrically connected with the third end of the voltage bias module, the drain of the sixth NMOS tube is electrically connected with the first end of the second resistor, and the gate of the sixth NMOS tube is electrically connected with the gate of the fourth NMOS tube.

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