Signal detection system based on differential amplifier

Abstract

The invention discloses a signal detection system based on a differential amplifier, and belongs to the field of signal detection, the system is composed of two groups of parallel processing units, and each unit comprises a signal input module, a double-RC low-pass filter, a fully differential operational amplifier, an ADC chip, an FPGA processing module and an upper computer. After a signal is accessed through the input module, common-mode interference is suppressed through the common-mode inductor and the terminal resistor, high-frequency noise is filtered through the double-RC low-pass filter, gain-adjustable differential amplification is carried out through the fully-differential operational amplifier, after analog-to-digital conversion is carried out through the ADC chip, real-time decoding and filtering are carried out through the FPGA module, and waveform visualization is achieved through transmission of the FPGA module to the upper computer through the Ethernet. The double processing units adopt common-ground connection to avoid ground potential difference interference, support switching between a differential signal input mode and a single-ended signal input mode, and improve signal consistency through symmetrical hardware design and impedance matching.

Description

Technical Field

[0001] This application belongs to the field of signal detection, and specifically relates to a signal detection system based on a differential amplifier. Background Technology

[0002] In industrial automation, precision measurement, and high-end manufacturing, the analog signals output by devices such as grating rulers (e.g., optical grating rulers, magnetic grating rulers) and displacement sensors often require high-precision acquisition and analysis. The signal quality directly determines the positioning accuracy of the equipment and the stability of the system control. These signals typically have weak amplitudes (mV level), are susceptible to electromagnetic interference, and are used in scenarios where differential signals (e.g., sine / cosine differential signals) and single-ended signals (e.g., reference pulse signals) coexist. This places stringent requirements on the compatibility, anti-interference capabilities, and signal reconstruction accuracy of the detection system.

[0003] Traditional signal detection systems face the following technical bottlenecks in practical applications: 1. Insufficient anti-interference capability: Common-mode signals such as motor noise and cable coupling interference in industrial environments can easily intrude into the acquisition link. Traditional single-ended amplifier circuits have low common-mode rejection ratio (CMRR), which leads to a deterioration of the signal-to-noise ratio and weak signals are submerged in noise. High-frequency electromagnetic interference (such as harmonics generated by frequency converters and switching power supplies) is not effectively filtered out and directly enters the subsequent amplifier circuit, causing signal distortion.

[0004] 2. Limited signal compatibility: Most systems only support one of the differential or single-ended signal input modes, requiring external adapter circuits to switch signal types, which increases system complexity and signal loss, and the adapter process is prone to introducing additional interference.

[0005] 3. Poor gain adjustment flexibility: Traditional fixed gain amplifier circuits cannot adapt to the amplitude differences of different sensor output signals (such as 5mV~5V dynamic range). It is necessary to replace the hardware resistor to achieve gain switching, which is cumbersome and difficult to meet the needs of rapid on-site debugging. Summary of the Invention

[0006] This application provides a signal detection system based on a differential amplifier. By using a dual RC filter network in conjunction with the differential amplifier, it effectively suppresses high-frequency electromagnetic interference and improves common-mode rejection capability. At the same time, a variable gain amplifier circuit is introduced to solve problems such as insufficient anti-interference capability, limited signal compatibility, and poor gain adjustment flexibility.

[0007] To achieve the above objectives, this application provides a signal detection system based on a differential amplifier, which consists of two sets of parallel-connected processing units. Each processing unit includes a signal input module, a first RC low-pass filter, a second RC low-pass filter, a fully differential operational amplifier, an ADC chip, an FPGA processing module, and a host computer. The signal input module is connected in parallel to the input terminals of the first RC low-pass filter and the second RC low-pass filter, respectively. The output terminal of the first RC low-pass filter is connected to the positive input terminal of the fully differential operational amplifier, and the output terminal of the second RC low-pass filter is connected to the negative input terminal of the fully differential operational amplifier. The fully differential operational amplifier amplifies the two input signals differentially and outputs them to the ADC chip for analog-to-digital conversion. The converted digital signal is received and analyzed in real time by the FPGA processing module, and the analyzed data is transmitted to the host computer via the Ethernet interface.

[0008] In one embodiment, the processing unit is connected to a common ground via the ground terminals of the adjacent first RC low-pass filter and the second RC low-pass filter.

[0009] In one embodiment, the non-inverting input of the fully differential operational amplifier is connected to the output of the first RC low-pass filter via an input resistor RD24, and the inverting input of the fully differential operational amplifier is connected to the output of the second RC low-pass filter via an input resistor RD31. The input resistor RD24 and the feedback resistor RD25 are connected in series, and the feedback resistor RD25 is connected to the fully differential operational amplifier to form a gain adjustment network at the non-inverting input terminal; the input resistor RD31 and the feedback resistor RD32 are connected in series, and the feedback resistor RD32 is connected to the inverting input terminal to form a gain control loop for the inverting channel.

[0010] In one embodiment, the signal input module is connected to terminals 4 and 1 of the common-mode inductor CMLD1 at the SCSIN+ and SCSIN- terminals, respectively. Terminals 3 and 2 of the common-mode inductor CMLD1 are connected to the input terminals of the first RC low-pass filter and the second RC low-pass filter, respectively. A terminating resistor RD26 is connected in parallel between the input terminals of the first RC low-pass filter and the second low-pass filter and terminals 3 and 2 of the common-mode inductor CMLD1.

[0011] In one embodiment, the first RC low-pass filter includes a resistor RD23 connected to terminal 3 of the common-mode inductor CMLD1, the resistor RD23 being connected to the capacitor CD75, and the resistor RD23 also being connected to the input resistor RD24.

[0012] In one embodiment, the second RC low-pass filter includes a resistor RD33 connected to two terminals of the common-mode inductor CMLD1, the resistor RD33 being connected to the capacitor CD74, and the resistor RD33 also being connected to the input resistor RD31.

[0013] In one embodiment, the resistors RD23 and RD33 have the same resistance value, the capacitors CD75 and CD74 have the same capacitance value, the feedback resistors RD25 and RD32 have the same resistance value, and the input resistors RD24 and RD31 have the same resistance value.

[0014] In one embodiment, the ADC chip is connected to the FPGA via a serial communication interface, which includes a serial data output (SDO), a serial data input (SDI), and a serial clock (SCLK).

[0015] In one embodiment, the FPGA processing module performs real-time decoding and filtering on the digital signals acquired by the ADC chip, and packages the decoded and filtered signals into data frames and transmits them to the host computer via an Ethernet interface.

[0016] In one embodiment, the host computer parses the received data frames, extracts the data sent by the FPGA processing module, and displays the scan points to realize the oscilloscope function.

[0017] Compared with the prior art, the beneficial effects of this application are: By employing a combined architecture of a fully differential operational amplifier and a dual RC low-pass filter, along with a front-end processing design using common-mode inductors and terminating resistors, common-mode interference and high-frequency noise can be effectively suppressed, significantly improving the system signal-to-noise ratio and enhancing the detection capability of weak signals.

[0018] The system utilizes a gain adjustment network comprised of feedback and input resistors to flexibly configure the amplification factor, adapting to input signal requirements of varying amplitudes and improving detection adaptability. The dual processing units employ a common ground connection to avoid interference introduced by ground potential differences, further ensuring signal consistency and system stability.

[0019] Supporting both differential and single-ended sinusoidal signal input modes, the system achieves flexible signal type switching through symmetrical hardware circuit design and impedance matching, broadening its application scenarios. The FPGA processing module, combined with high-speed Ethernet transmission, enables real-time decoding, filtering, and data encapsulation of digital signals. Coupled with the waveform visualization function of the host computer, it can accurately reconstruct signal characteristics, meeting the requirements for high-precision, real-time signal detection. The overall system, through coordinated optimization of hardware-level noise suppression and digital processing, demonstrates excellent anti-interference capabilities and signal reconstruction accuracy in fields such as industrial automation and precision measurement. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 A schematic flowchart of a signal detection system based on a differential amplifier is provided for this application; Figure 2 This application provides a schematic diagram of the overall circuit connection of a signal detection system based on a differential amplifier. Figure 3 This application provides a schematic diagram of the processing unit connection for a signal detection system based on a differential amplifier.

[0022] Reference numerals: 1. Fully differential operational amplifier; 2. First RC low-pass filter; 3. Second RC low-pass filter; 4. Signal input module. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions in the embodiments of this application are described clearly and completely below. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are also within the scope of protection of this application.

[0024] See Figures 1 to 2 As shown, the signal detection system based on a differential amplifier provided in this application consists of two sets of parallel-connected processing units. The processing unit includes a signal input module 4, a first RC low-pass filter, a second RC low-pass filter 3, a fully differential operational amplifier 1, an ADC chip, an FPGA processing module, and a host computer.

[0025] The signal input module 4 is connected in parallel to the input terminals of the first RC low-pass filter and the second RC low-pass filter 3. The output terminal of the first RC low-pass filter is connected to the positive input terminal of the fully differential operational amplifier 1, and the output terminal of the second RC low-pass filter 3 is connected to the negative input terminal of the fully differential operational amplifier 1. The fully differential operational amplifier 1 amplifies the two input signals differentially and outputs them to the ADC chip for analog-to-digital conversion. The converted digital signal is received and analyzed in real time by the FPGA processing module, and the analyzed data is transmitted to the host computer via the Ethernet interface.

[0026] After external signals are input through signal input module 4, they undergo noise suppression and bandwidth limitation via a first RC low-pass filter and a second RC low-pass filter 3, respectively, eliminating the impact of high-frequency interference on subsequent processing. A differential amplifier performs differential operations on the two filtered signals, effectively enhancing the amplitude of the useful signal and suppressing common-mode interference, thus improving the system's signal-to-noise ratio. The ADC chip completes the analog-to-digital signal conversion at a high sampling rate, and the FPGA module performs real-time decoding, digital filtering, and data encapsulation of the received digital signal, ensuring the real-time performance and accuracy of signal processing. Finally, the data frame is stably transmitted to the host computer via Ethernet, enabling waveform reconstruction and visualization, meeting the requirements for high-precision signal detection. The entire system, through hardware-level differential processing and front-end filtering optimization, not only reduces the impact of external electromagnetic interference but also enhances the detectability of weak signals.

[0027] Optionally, the processing unit is connected to a common ground via the ground terminals of the adjacent first RC low-pass filter and the second RC low-pass filter 3. This common ground connection effectively avoids common-mode interference introduced by ground potential difference, further improving system stability and signal consistency.

[0028] Optionally, the non-inverting input of the fully differential operational amplifier 1 is connected to the output of the first RC low-pass filter through the input resistor RD24, and the inverting input of the fully differential operational amplifier 1 is connected to the output of the second RC low-pass filter 3 through the input resistor RD31. The input resistor RD24 and the feedback resistor RD25 are connected in series, and the feedback resistor RD25 is connected to the fully differential operational amplifier 1 to form a gain adjustment network at the non-inverting input terminal; the input resistor RD31 and the feedback resistor RD32 are connected in series, and the feedback resistor RD32 is connected to the inverting input terminal to form a gain control loop for the inverting channel.

[0029] In this embodiment, the positive and negative input terminals (+ / -) of the fully differential operational amplifier 1 are connected to the signals output by the first RC low-pass filter and the second RC low-pass filter 3 through the input resistors RD24 and RD31. After differential amplification, the feedback resistors RD25 and RD32 form a closed-loop gain network to achieve further signal conditioning.

[0030] It should be noted that the feedback resistors RD25 and RD32, and the input resistors RD24 and RD31 together determine the gain of the fully differential operational amplifier 1.

[0031] Optionally, the signal input module 4 is connected to terminals 4 and 1 of the common-mode inductor CMLD1 at the SCSIN+ and SCSIN- terminals, respectively. Terminals 3 and 2 of the common-mode inductor CMLD1 are connected to the input terminals of the first RC low-pass filter and the second RC low-pass filter 3, respectively. A terminating resistor RD26 is connected in parallel between the input terminals of the first RC low-pass filter and the second low-pass filter and terminals 3 and 2 of the common-mode inductor CMLD1.

[0032] In this embodiment, terminal 3 of the common-mode inductor CMLD1 is connected to the input terminal of the first RC low-pass filter, and terminal 2 is connected to the input terminal of the second RC low-pass filter 3, thereby effectively suppressing high-frequency common-mode noise in the differential signal.

[0033] Optionally, the first RC low-pass filter includes a resistor RD23 connected to terminal 3 of the common-mode inductor CMLD1, the resistor RD23 being connected to the capacitor CD75, and the resistor RD23 also being connected to the input resistor RD24.

[0034] Optionally, the second RC low-pass filter 3 includes a resistor RD33 connected to two terminals of the common-mode inductor CMLD1. The resistor RD33 is connected to the capacitor CD74 and is also connected to the input resistor RD31.

[0035] Optionally, the resistors RD23 and RD33 have the same resistance value, the capacitors CD75 and CD74 have the same capacitance value, the feedback resistors RD25 and RD32 have equal resistance values, and the input resistors RD24 and RD31 have equal resistance values.

[0036] Optionally, the ADC chip is connected to the FPGA via a serial communication interface, which includes a serial data output SDO, a serial data input SDI, and a serial clock SCLK.

[0037] Optionally, the FPGA processing module performs real-time decoding and filtering on the digital signals acquired by the ADC chip, and packages the decoded and filtered signals into data frames and transmits them to the host computer via an Ethernet interface.

[0038] Optionally, the host computer parses the received data frames, extracts the data sent by the FPGA processing module, and displays the scan points to realize the oscilloscope function.

[0039] Example 1: Differential Sine and Cosine Signal Input Connection When a differential sine / cosine signal is input, SIN+ is connected to SCSIN+, and SIN- is connected to SCSIN-. After the common-mode noise in the signal harness is filtered out by the common-mode inductor CMLD1, the transmission line impedance is matched by the terminating resistor RD26 to ensure signal integrity. Subsequently, high-frequency noise is filtered out by the resistor RD23 and capacitor CD75 of the first RC low-pass filter and the resistor RD33 and capacitor CD74 of the second RC low-pass filter 3, resulting in a clean differential sine signal that is input to the positive and negative input terminals of the fully differential amplifier UD5A. The amplifier gain is set by the ratio of the feedback resistor RD25 to the input resistor RD24 and the feedback resistor RD32 to the input resistor RD31, which is configured as 10 times in this embodiment. The common-mode level of the amplified differential signal is set to 2.5V by an internal reference. The output signal is sampled by the ADC chip and then sent to the FPGA processing module for decoding to achieve high-precision signal restoration. The FPGA processing module transmits the decoded data to the host computer in real time via the Ethernet interface. The host computer parses the received data frames and plots waveform curves, displaying the amplitude and frequency characteristics of the input signal in real time.

[0040] Example 2: Single-ended sine and cosine signal input connection method When a single-ended sine / cosine signal is input, SIN+ is connected to SCSIN+, and SIN- is grounded. After common-mode interference is filtered out by common-mode inductor CMLD1, the transmission line impedance is matched through terminating resistor RD26. Subsequently, high-frequency noise is filtered out by resistor RD23 and capacitor CD75 of the first RC low-pass filter, and resistor RD33 and capacitor CD74 of the second RC low-pass filter 3. The single-ended signal is converted into a differential signal and input to the positive input terminal of the fully differential amplifier UD5A, while the negative input terminal is grounded through a matching resistor. The amplifier gain is set to 10 times by the ratio of feedback resistor RD25 to input resistor RD24, and feedback resistor RD32 to input resistor RD31. The output common-mode voltage is set to 2.5V by an internal reference. The amplified differential signal is sampled by the ADC chip, decoded and filtered by the FPGA module, and the data frame is transmitted to the host computer via Ethernet for real-time waveform display and analysis. The host computer supports cursor measurement, waveform zoom, data storage, and screenshot functions, facilitating precise analysis and recording of signal characteristics.

[0041] Example 3: Gain Setting To facilitate gain adjustment, the input resistors at both input terminals of an operational amplifier are typically kept at the same value, and the feedback resistors are also set symmetrically. The gain can be precisely set by adjusting the ratio of the feedback resistor to the input resistor. To achieve a 2x amplification, appropriate feedback and input resistors can be selected. Assuming the input resistor is Rg and the feedback resistor is Rf, the gain Av can be calculated using the formula Av = Rf / Rg.

[0042] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A signal detection system based on a differential amplifier, comprising two sets of parallel-connected processing units, characterized in that: The processing unit includes a signal input module (4), a first RC low-pass filter (2), a second RC low-pass filter (3), a fully differential operational amplifier (1), an ADC chip, an FPGA processing module, and a host computer; The signal input module (4) is connected in parallel to the input terminals of the first RC low-pass filter (2) and the second RC low-pass filter (3). The output terminal of the first RC low-pass filter (2) is connected to the positive input terminal of the fully differential operational amplifier (1), and the output terminal of the second RC low-pass filter (3) is connected to the negative input terminal of the fully differential operational amplifier (1). The fully differential operational amplifier (1) amplifies the two input signals differentially and outputs them to the ADC chip for analog-to-digital conversion. The converted digital signal is received and analyzed in real time by the FPGA processing module. The analyzed data is transmitted to the host computer via the Ethernet interface.

2. The signal detection system based on a differential amplifier according to claim 1, characterized in that: The processing unit is connected to a common ground via the ground terminals of the adjacent first RC low-pass filter (2) and the second RC low-pass filter (3).

3. The signal detection system based on a differential amplifier according to claim 1, characterized in that: The non-inverting input terminal of the fully differential operational amplifier (1) is connected to the output terminal of the first RC low-pass filter (2) through the input resistor RD24, and the inverting input terminal of the fully differential operational amplifier (1) is connected to the output terminal of the second RC low-pass filter (3) through the input resistor RD31. The input resistor RD24 is connected in series with the feedback resistor RD25, and the feedback resistor RD25 is connected to the fully differential operational amplifier (1) to form a gain adjustment network at the non-inverting input terminal; the input resistor RD31 is connected in series with the feedback resistor RD32, and the feedback resistor RD32 is connected to the inverting input terminal to form a gain control loop for the inverting channel.

4. The signal detection system based on a differential amplifier according to claim 3, characterized in that: The signal input module (4) is connected to terminals 4 and 1 of the common mode inductor CMLD1 at the SCSIN+ and SCSIN- terminals respectively. Terminals 3 and 2 of the common mode inductor CMLD1 are connected to the input terminals of the first RC low-pass filter (2) and the second RC low-pass filter (3) respectively. A terminating resistor RD26 is connected in parallel between the input terminals of the first RC low-pass filter (2) and the second low-pass filter and terminals 3 and 2 of the common mode inductor CMLD1.

5. A signal detection system based on a differential amplifier according to claim 4, characterized in that: The first RC low-pass filter (2) includes a resistor RD23 connected to the 3rd terminal of the common-mode inductor CMLD1. The resistor RD23 is connected to the capacitor CD75 and is also connected to the input resistor RD24.

6. The signal detection system based on a differential amplifier according to claim 4, characterized in that: The second RC low-pass filter (3) includes a resistor RD33 connected to two terminals of the common-mode inductor CMLD1. The resistor RD33 is connected to the capacitor CD74 and is also connected to the input resistor RD31.

7. A signal detection system based on a differential amplifier according to claims 5 and 6, characterized in that: The resistors RD23 and RD33 have the same resistance value, the capacitors CD75 and CD74 have the same capacitance value, the feedback resistors RD25 and RD32 have the same resistance value, and the input resistors RD24 and RD31 have the same resistance value.

8. The signal detection system based on a differential amplifier according to claim 1, characterized in that: The ADC chip is connected to the FPGA via a serial communication interface, which includes a serial data output SDO, a serial data input SDI, and a serial clock SCLK.

9. A signal detection system based on a differential amplifier according to claim 1, characterized in that: The FPGA processing module performs real-time decoding and filtering on the digital signals acquired by the ADC chip, and packages the decoded and filtered signals into data frames and transmits them to the host computer via the Ethernet interface.

10. A signal detection system based on a differential amplifier according to claim 1, characterized in that: The host computer parses the received data frames, extracts the data sent by the FPGA processing module, and displays the scan points to realize the oscilloscope function.

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