Reset circuit and power-on reset system

Abstract

The invention discloses a reset circuit and a power-on reset system, and relates to the technical field of radio frequency transceiver chips, and the circuit comprises a first detection module which is connected with a power supply and is used for obtaining a power supply voltage and generating a first current signal according to the change of the power supply voltage, and the first current signal is in linear correlation with the size of the power supply voltage; the second detection module is connected with the power supply and is used for acquiring the power supply voltage and generating a second current signal according to the change of the power supply voltage, and the second current signal is in quadratic correlation with the size of the power supply voltage; the signal generation module is connected with the first detection module, the second detection module and the to-be-reset module, and is used for outputting a power supply reset signal to the to-be-reset module when the amplitude of the second current signal is greater than the amplitude of the first current signal. Compared with the prior art. According to the invention, the power supply reset signal is automatically generated through internal comparison of two current signals with different change rules, and the to-be-reset module can be reset without an external reference source.

Description

Technical Field

[0001] This application relates to the field of radio frequency transceiver chip technology, and in particular to a reset circuit and a power-on reset system. Background Technology

[0002] In low-power integrated circuits such as RF transceiver chips, power-on reset (POR) circuits are used to monitor the establishment and drop of power supply voltage, ensuring reliable system reset during power-on and power-off processes and avoiding logic state errors. With the evolution of process technology and the widespread adoption of multi-power domain designs, POR circuits often need to reliably monitor low operating voltages such as 1.8V, 1.2V, and 0.9V directly without an external reference source, and maintain extremely low power consumption throughout the entire operating and sleep modes.

[0003] Currently, common POR circuits typically rely on external reference voltage or current sources to set the reset threshold. However, when monitoring high power supply domains such as 1.8V, the system often lacks a stable internal reference source, causing the circuit to malfunction. Furthermore, due to process variations and temperature changes, the threshold voltage of traditional structures is prone to drift, with an overall error of approximately ±20%. If an internal system reference source (such as a band-gap reference (BGR)) is used for calibration, the POR circuit will malfunction due to reference failure when the power supply voltage drops below the minimum operating voltage of the reference source, reducing reliability.

[0004] Therefore, how to realize a POR circuit that is compatible with a variety of low operating voltages and has high precision and ultra-low power consumption without relying on an external reference source is an urgent problem to be solved. Summary of the Invention

[0005] The main objective of this application is to provide a reset circuit and a power-on reset system, aiming to solve the technical problem of how to realize a POR circuit that is compatible with a variety of low operating voltages and has high precision and ultra-low power consumption without relying on an external reference source.

[0006] To achieve the above objectives, this application proposes a reset circuit, which includes: a first detection module, a second detection module, and a signal generation module; The first detection module is connected to a power supply and is used to acquire the power supply voltage and generate a first current signal based on the change of the power supply voltage. The first current signal is linearly related to the magnitude of the power supply voltage. The second detection module is connected to the power supply and is used to acquire the power supply voltage and generate a second current signal based on the change of the power supply voltage. The second current signal is related to the magnitude of the power supply voltage. The signal generation module is connected to the first detection module, the second detection module, and the module to be reset, respectively, and is used to output a power reset signal to the module to be reset when the amplitude of the second current signal is greater than the amplitude of the first current signal.

[0007] In one embodiment, the signal generation module is further configured to output a reset invalid signal to the module to be reset when the amplitude of the second current signal is less than the amplitude of the first current signal.

[0008] In one embodiment, the signal generation module includes: a comparison unit and a latch output unit; The comparison unit is connected to the first detection module and the second detection module respectively, and is used to transmit the generated reset signal to the latch output unit when the amplitude of the second current signal is greater than the amplitude of the first current signal. The latch output unit is connected to the comparison unit and the module to be reset, respectively, and is used to transmit the generated power reset signal to the module to be reset according to the signal to be reset, and to latch the power reset signal.

[0009] In one embodiment, the comparison unit includes: a first transistor and a second transistor; The source of the first transistor is connected to the power supply, the source of the second transistor is connected to the reference ground, the gate of the first transistor is connected to the second detection module, the drains of the first transistor and the drains of the second transistor are both connected to the latch output unit, and the gate of the second transistor is connected to the first detection module.

[0010] In one embodiment, the latch output unit includes: a third transistor to a sixth transistor; The source of the third transistor is connected to the power supply, the drain of the third transistor is connected to the source of the fourth transistor, the gates of the third transistor and the fourth transistor are both connected to the drains of the fifth transistor, the drain of the sixth transistor, and the module to be reset, the drain of the fourth transistor is connected to the gates of the fifth transistor and the sixth transistor, the source of the fifth transistor is connected to the power supply, and the source of the sixth transistor is connected to reference ground.

[0011] In one embodiment, the first detection module includes: a resistor and a seventh transistor; The first end of the resistor is connected to the power supply, and the second end of the resistor is connected to the drain of the seventh transistor, the gate of the seventh transistor, and the signal generation module, respectively. The source of the seventh transistor is connected to the reference ground.

[0012] In one embodiment, the second detection module includes: an eighth transistor to a fourteenth transistor; The source of the eighth transistor is connected to the power supply. The gate of the eighth transistor is connected to the signal generation module, the drain of the eighth transistor, and the drain of the ninth transistor. The gate of the ninth transistor is connected to the gates of the tenth, eleventh, twelfth, thirteenth, and fourteenth transistors. The source of the ninth transistor is connected to the drain of the tenth transistor. The source of the tenth transistor is connected to the drain of the eleventh transistor. The source of the eleventh transistor is connected to the drain of the twelfth transistor. The source of the twelfth transistor is connected to the drain of the thirteenth transistor. The source of the thirteenth transistor is connected to the drain of the fourteenth transistor. The source of the fourteenth transistor is connected to a reference ground.

[0013] In one embodiment, the circuit further includes: an output buffer module; The output buffer module is disposed between the signal generation module and the module to be reset. The output buffer module is used to transmit the power reset signal or reset invalid signal to the module to be reset after power driving.

[0014] In one embodiment, the output buffer module includes a fifteenth transistor and a sixteenth transistor; The gate of the fifteenth transistor is connected to the gate of the signal generation module and the gate of the sixteenth transistor, the source of the fifteenth transistor is connected to the power supply, the drain of the fifteenth transistor is connected to the module to be reset and the drain of the sixteenth transistor, and the source of the sixteenth transistor is connected to the reference ground.

[0015] In addition, to achieve the above objectives, this application also proposes a power-on reset system, which includes the reset circuit described above.

[0016] This application proposes a reset circuit, comprising: a first detection module, a second detection module, and a signal generation module; the first detection module is connected to a power supply and is used to acquire the power supply voltage and generate a first current signal based on the change of the power supply voltage, wherein the first current signal is linearly related to the magnitude of the power supply voltage; the second detection module is connected to the power supply and is used to acquire the power supply voltage and generate a second current signal based on the change of the power supply voltage, wherein the second current signal is related to the magnitude of the power supply voltage; the signal generation module is connected to the first detection module, the second detection module, and the module to be reset, respectively, and is used to output a power reset signal to the module to be reset when the amplitude of the second current signal is greater than the amplitude of the first current signal.

[0017] Because this application includes a reset circuit in its power-on reset system, the first detection module in the reset circuit is connected to the power supply. It first acquires the power supply voltage and generates a first current signal based on the change in the power supply voltage, wherein the first current signal is linearly correlated with the magnitude of the power supply voltage. Similarly, the second detection module is also connected to the power supply, first acquires the power supply voltage, and generates a second current signal based on the change in the power supply voltage, wherein the second current signal is quadratically correlated with the magnitude of the power supply voltage. Then, a signal generation module is connected to the first detection module, the second detection module, and the module to be reset, respectively, and outputs a power reset signal to the module to be reset when the amplitude of the second current signal is greater than the amplitude of the first current signal. Compared to existing methods, this application generates a power reset signal internally by comparing two current signals with different changing patterns, thus resetting the module to be reset without an external reference source. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the structure of the first embodiment of the reset circuit proposed in this application; Figure 2 This is a schematic diagram of the structure of the second embodiment of the reset circuit proposed in this application; Figure 3 This is a circuit diagram of a third embodiment of the reset circuit proposed in this application.

[0021] Explanation of icon numbers:

[0022] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0023] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0025] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.

[0026] Furthermore, the use of terms such as "first" and "second" in this application is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed in this application.

[0027] It should be noted that in low-power integrated circuits such as RF transceiver chips, the power-on reset (POR) circuit is used to monitor the establishment and drop of the power supply voltage, ensuring reliable system reset during power-on and power-off processes and avoiding logic state errors. With the evolution of process technology and the widespread adoption of multi-power domain designs, POR circuits often need to reliably monitor low operating voltages such as 1.8V, 1.2V, and 0.9V directly without an external reference source, and maintain extremely low power consumption throughout the entire operating and sleep modes.

[0028] Currently, common POR circuits typically rely on external reference voltage or current sources to set the reset threshold. However, when monitoring high power supply domains such as 1.8V, the system often lacks a stable internal reference source, causing the circuit to malfunction. Furthermore, due to process variations and temperature changes, the threshold voltage of traditional structures is prone to drift, with an overall error of approximately ±20%. If an internal system reference source (such as a band-gap reference (BGR)) is used for calibration, the POR circuit will malfunction due to reference failure when the power supply voltage drops below the minimum operating voltage of the reference source, reducing reliability.

[0029] To address the aforementioned technical problems, this embodiment provides a reset circuit. This embodiment includes a reset circuit in the power-on reset system. The first detection module 1 in the reset circuit is connected to the power supply VDD, first acquiring the power supply voltage, and generating a first current signal based on the change in the power supply voltage. The first current signal is linearly correlated with the magnitude of the power supply voltage. Similarly, the second detection module 2 is also connected to the power supply VDD, first acquiring the power supply voltage, and generating a second current signal based on the change in the power supply voltage. The second current signal is quadratically correlated with the magnitude of the power supply voltage. Then, a signal generation module 3 is connected to the first detection module 1, the second detection module 2, and the module to be reset 4, respectively. When the amplitude of the second current signal is greater than the amplitude of the first current signal, it outputs a power supply VDD reset signal to the module to be reset 4. Compared to existing methods, this application generates a power supply VDD reset signal by internally comparing two current signals with different changing patterns, thus resetting the module to be reset 4 without an external reference source.

[0030] For ease of understanding, the following is combined with Figures 1 to 3 The reset circuit provided in the embodiments of this application will be described in detail.

[0031] Reference Figure 1 , Figure 1 This is a schematic diagram of the structure of the first embodiment of the reset circuit proposed in this application.

[0032] like Figure 1 As shown, in this embodiment, the circuit includes: a first detection module 1, a second detection module 2, and a signal generation module 3; The first detection module 1 is connected to the power supply VDD and is used to acquire the power supply voltage and generate a first current signal according to the change of the power supply voltage. The first current signal is linearly related to the magnitude of the power supply voltage. The second detection module 2 is connected to the power supply VDD and is used to acquire the power supply voltage and generate a second current signal based on the change of the power supply voltage. The second current signal is related to the magnitude of the power supply voltage. The signal generation module 3 is connected to the first detection module 1, the second detection module 2, and the module to be reset 4, respectively, and is used to output a power supply VDD reset signal to the module to be reset 4 when the amplitude of the second current signal is greater than the amplitude of the first current signal.

[0033] It should be noted that the power supply voltage can be the potential of the power supply network that provides energy to the entire circuit, and its value can be, for example, 0.9V, 1.2V or 1.8V.

[0034] The first detection module 1 can be any module capable of responding to changes in power supply voltage and outputting a current signal that is linearly proportional to the voltage value.

[0035] The second detection module 2 can be any module capable of responding to changes in power supply voltage and outputting a current signal that changes in a quadratic relationship with the voltage value. For example, it can be a branch consisting of multiple N-type transistors with interconnected gates and drains connected in series.

[0036] The signal generation module 3 can be any module capable of receiving and comparing the amplitudes of the first current signal and the second current signal, and generating an output signal based on the comparison result.

[0037] The module to be reset 4 can be an external functional circuit that serves the reset circuit, or any digital or analog module that requires power-on reset control, such as a digital baseband processor or phase-locked loop circuit in an RF transceiver chip.

[0038] Understandably, the first current signal can be the current signal output by the first detection module 1, and its amplitude increases approximately linearly with the increase of the power supply voltage.

[0039] The second current signal can be the current signal output by the second detection module 2. Its amplitude increases sharply (square relationship) as the voltage rises after the power supply voltage exceeds a certain threshold.

[0040] The power supply VDD reset signal is a logic signal output by the signal generation module 3, used to control the reset state of the module 4 to be reset. Its effective level (such as high level) usually indicates that the reset is released.

[0041] In the specific implementation, two detection modules operate by sensing the same power supply voltage differently. The first detection module 1 generates a current that increases linearly with the power supply voltage, simulating a smooth response. The second detection module 2 generates a current that increases quadratically with the power supply voltage, simulating a response that sharply increases after a threshold point. When the power supply voltage rises from zero, the first current signal is initially present while the second current signal is almost zero. As the power supply voltage continues to rise, the faster-growing second current signal will eventually surpass the first current signal at a certain power supply voltage point. The signal generation module 3 continuously compares the amplitudes of these two current signals. Once it detects that the amplitude of the second current signal exceeds that of the first current signal, it determines that the power supply voltage has reached the reliable operating threshold and immediately outputs a valid power supply VDD reset signal to the module to be reset, notifying it that it can safely start. Throughout this process, the circuit does not rely on any externally provided reference voltage or reference current source to determine this switching threshold.

[0042] Furthermore, in order to output a valid power supply VDD reset signal under specific conditions, and also to output a clear reset invalid signal under the opposite conditions, the following continues... Figure 1 As shown, in this embodiment, the signal generation module 3 is further configured to output a reset invalid signal to the module to be reset 4 when the amplitude of the second current signal is less than the amplitude of the first current signal.

[0043] Understandably, the amplitude of the second current signal can be the magnitude of the current signal generated by the second detection module 2, which is quadratically correlated with the power supply voltage.

[0044] The amplitude of the first current signal can be the amplitude of a current signal generated by the first detection module 1 that is linearly related to the power supply voltage.

[0045] The reset invalid signal can be a logic level signal output by the signal generation module 3, used to indicate that the power supply voltage has not reached or has fallen below the reliable operating threshold, commanding the module 4 to be reset to enter or remain in the reset state. The reset invalid signal is the opposite of the logic state of the power supply VDD reset signal.

[0046] In its implementation, signal generation module 3 achieves complete status output by continuously comparing the amplitudes of the first current signal and the second current signal. When the power supply voltage is low, such as during system power-on or voltage dips, the amplitude of the slowly increasing first current signal will be greater than the amplitude of the rapidly increasing second current signal. At this time, signal generation module 3 determines that the power supply voltage does not meet the operating requirements and outputs a reset invalid signal (such as a low level) to the module to be reset 4. This signal serves as an explicit shutdown or wait instruction, ensuring that the logic within the module to be reset 4 will not malfunction under unstable voltage conditions. Only when the power supply voltage rises to the point that the amplitude of the second current signal surpasses it will the output of signal generation module 3 flip to a valid power supply VDD reset signal.

[0047] Furthermore, to ensure the generated reset signal has the reliability and stability to drive subsequent loads, the process continues as follows: Figure 1 As shown, in this embodiment, the circuit further includes: an output buffer module 5; The output buffer module 5 is disposed between the signal generation module 3 and the module to be reset 4; The output buffer module 5 is used to transmit the power supply VDD reset signal or reset invalid signal to the module to be reset 4 after power driving.

[0048] It should be noted that the output buffer module 5 can be any circuit unit that can receive logic input signals, amplify and shape their power, and drive subsequent loads with low impedance output.

[0049] In the specific implementation, the output buffer module 5 is connected on the signal path between the signal generation module 3 and the module to be reset 4. To achieve low power consumption and fast response, the signal generation module 3 may have limited direct output signal driving capability. The output buffer module 5 receives the original power supply VDD reset signal and performs power driving processing on it. This process is like equipping a clear instruction with a powerful loudspeaker: the instruction content (logic state) remains unchanged, but after driving the loudspeaker, the volume of the instruction (current driving capability) is greatly enhanced, propagating further and becoming more resistant to interference. The power-driven signal is finally transmitted to the module to be reset 4, thus ensuring that even if the input capacitance of the module to be reset 4 is large or the distance is far, the reset signal can quickly and stably establish the correct logic level, guaranteeing reliable reset and startup of the entire system.

[0050] This embodiment includes a reset circuit in the power-on reset system. The first detection module 1 in the reset circuit is connected to the power supply VDD. It first acquires the power supply voltage and generates a first current signal based on the change in the power supply voltage, where the first current signal is linearly correlated with the magnitude of the power supply voltage. Similarly, the second detection module 2 is also connected to the power supply VDD. It first acquires the power supply voltage and generates a second current signal based on the change in the power supply voltage, where the second current signal is quadratically correlated with the magnitude of the power supply voltage. Then, a signal generation module 3 is connected to the first detection module 1, the second detection module 2, and the module to be reset 4, respectively. When the amplitude of the second current signal is greater than the amplitude of the first current signal, it outputs a power supply VDD reset signal to the module to be reset 4. Compared to existing methods, this application generates a power supply VDD reset signal by internally comparing two current signals with different changing patterns, thus resetting the module to be reset 4 without an external reference source.

[0051] Reference Figure 2 , Figure 2 This is a schematic diagram of the second embodiment of the reset circuit proposed in this application.

[0052] Based on the above embodiments, a second embodiment of this application is proposed. In order to complete the entire process from current comparison to stable reset signal output through the division of labor and cooperation between the comparison unit 31 and the latch output unit 32, as follows... Figure 2 As shown, in this embodiment, the signal generation module 3 includes: a comparison unit 31 and a latch output unit 32; The comparison unit 31 is connected to the first detection module 1 and the second detection module 2 respectively, and is used to transmit the generated reset signal to the latch output unit 32 when the amplitude of the second current signal is greater than the amplitude of the first current signal. The latch output unit 32 is connected to the comparison unit 31 and the reset module 4 respectively, and is used to transmit the generated power supply VDD reset signal to the reset module 4 according to the reset signal, and latch the power supply VDD reset signal.

[0053] It should be noted that the comparison unit 31 can be any circuit module capable of receiving two current signals, comparing their amplitudes, and outputting corresponding logic signals.

[0054] The latch output unit 32 can be any storage circuit capable of receiving logic input signals, shaping them, and maintaining a stable output. For example, an SR latch composed of cross-coupled inverters, or a gate circuit with feedback function.

[0055] Understandably, the reset signal can be an intermediate logic signal output by the comparison unit 31 after performing current comparison, reflecting the comparison result. The level of this signal indicates whether the amplitude of the second current signal is greater than the amplitude of the first current signal.

[0056] In its implementation, the signal generation module 3 functions through a cascaded comparison unit 31 and latch output unit 32. The comparison unit 31 continuously monitors the first current signal from the first detection module 1 and the second current signal from the second detection module 2. When the power supply voltage rises to the point that the amplitude of the second current signal exceeds the amplitude of the first current signal, the internal state of the comparison unit 31 flips, generating a level-changing reset signal and transmitting it to the latch output unit 32. The latch output unit 32 functions similarly to a state memory switch. Upon receiving the transition edge of the reset signal, it immediately switches its output state to a valid power supply VDD reset signal (e.g., high level) and locks this output state firmly. Even if the subsequent two current signals experience slight fluctuations near the threshold point, causing some jitter in the output of the comparison unit 31, the latch output unit 32 ensures that the final output power supply VDD reset signal is stable and jitter-free, thus reliably controlling the state of the module 4 to be reset.

[0057] Reference Figure 3 , Figure 3 This is a circuit diagram of a third embodiment of the reset circuit proposed in this application.

[0058] Based on the above embodiments, a third embodiment of this application is proposed. In order to convert the current signal comparison between the first detection module 1 and the second detection module 2 into a voltage logic signal (a reset signal) through a specific connection of two transistors, such as... Figure 3 As shown, in this embodiment, the comparison unit 31 includes: a first transistor M1 and a second transistor M2; The source of the first transistor M1 is connected to the power supply VDD, the source of the second transistor M2 is connected to the reference ground VSS, the gate of the first transistor M1 is connected to the second detection module 2, the drains of the first transistor M1 and the drains of the second transistor M2 are both connected to the latch output unit 32, and the gate of the second transistor M2 is connected to the first detection module 1.

[0059] It should be noted that the first transistor M1 can be any P-type field-effect transistor whose conduction state is controlled by the gate voltage. A P-type transistor conducts when the gate voltage is lower than the source voltage by a certain value. For example, a transistor of type PMOS.

[0060] The second transistor M2 can be any N-type field-effect transistor whose conduction state is controlled by the gate voltage. An N-type transistor conducts when the gate voltage is higher than the source voltage by a certain value. For example, an NMOS transistor.

[0061] The reference ground VSS can be the zero-potential node in the circuit that serves as a reference for voltage measurement.

[0062] In its implementation, the comparison unit 31 achieves current comparison through a series and controlled connection of the first transistor M1 and the second transistor M2. The source of the first transistor M1 is connected to the power supply VDD, and the source of the second transistor M2 is connected to the reference ground VSS. Their drains are interconnected to form a common output node, which is connected to the latch output unit 32. This common drain node is the point where the reset signal is generated. The gate voltage of the first transistor M1 is determined by the second current signal output by the second detection module 2. This voltage controls the amount of current (denoted as I_P) that the first transistor M1 is allowed to flow from the power supply VDD to the output node. The gate voltage of the second transistor M2 is determined by the first current signal output by the first detection module 1. This voltage controls the amount of current (denoted as I_N) that the second transistor M2 is allowed to flow from the output node to the reference ground VSS. The voltage of the output node (i.e., the reset signal) is determined by the competition between these two currents: if I_N > I_P, the output node is pulled low; if I_P > I_N, the output node is pulled high. Therefore, when the second current signal, which reflects the square increase of the power supply voltage, is enhanced, making I_P greater than I_N, the output node becomes high, generating the aforementioned reset signal.

[0063] Furthermore, in order to construct a latching logic gate through a specific interconnection of four transistors to stably generate and hold the power supply VDD reset signal, the process continues as follows... Figure 3 As shown, in this embodiment, the latch output unit 32 includes: a third transistor M3 to a sixth transistor M6; The source of the third transistor M3 is connected to the power supply VDD, and the drain of the third transistor M3 is connected to the source of the fourth transistor M4. The gates of the third transistor M3 and the fourth transistor M4 are both connected to the drains of the fifth transistor M5, the sixth transistor M6, and the module 4 to be reset. The drain of the fourth transistor M4 is connected to the gates of the fifth transistor M5 and the sixth transistor M6, respectively. The source of the fifth transistor M5 is connected to the power supply VDD, and the source of the sixth transistor M6 is connected to the reference ground VSS.

[0064] It should be noted that the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 can all be P-type or N-type field-effect transistors selected according to design requirements. In this embodiment, the third transistor M3 and the fifth transistor M5 can be P-type transistors (e.g., PMOS), and the fourth transistor M4 and the sixth transistor M6 can be N-type transistors (e.g., NMOS).

[0065] In its implementation, the latch output unit 32 forms a static latch through the cross-coupling connection of the third transistor M3 to the sixth transistor M6. The third transistor M3 and the fourth transistor M4 are connected in series between the power supply VDD and the reference ground VSS, forming the first inverter (inverter A). Similarly, the fifth transistor M5 and the sixth transistor M6 are connected in series between the power supply VDD and the reference ground VSS, forming the second inverter (inverter B). The key is their cross-coupling connection: the input of inverter A (i.e., the gates of the third transistor M3 and the fourth transistor M4) is connected to the output of inverter B (i.e., the connection point between the drain of the fifth transistor M5 and the drain of the sixth transistor M6), which is also the node that ultimately outputs the aforementioned power supply VDD reset signal to the aforementioned module 4 to be reset. The input of inverter B (i.e., the gates of the fifth transistor M5 and the sixth transistor M6) is connected to the output of inverter A (i.e., the drain of the fourth transistor M4). When the reset signal from the comparison unit 31 is applied to the input of inverter A, it drives a change in the output state of inverter A. This change is immediately fed back to the input of inverter B via cross-coupling, causing a corresponding and amplified flip in the output state of inverter B (i.e., the power supply VDD reset signal). Once the flip is complete, the two inverters lock each other's input states through the aforementioned cross-coupling connection, forming a stable bistable circuit. Even if there are minor disturbances in the reset signal at the input terminal thereafter, this latched state remains unchanged, thus ensuring that the output power supply VDD reset signal is stable and jitter-free.

[0066] Furthermore, to construct a circuit branch capable of generating a current signal linearly related to the power supply voltage through a simple connection of a resistor R and a transistor, we can continue as follows... Figure 3 As shown, in this embodiment, the first detection module 1 includes: a resistor R and a seventh transistor M7; The first end of the resistor R is connected to the power supply VDD, and the second end of the resistor R is connected to the drain of the seventh transistor M7, the gate of the seventh transistor M7, and the signal generation module 3, respectively. The source of the seventh transistor M7 is connected to the reference ground VSS.

[0067] It should be noted that the resistor R can be any passive circuit element with a certain impedance value, used to generate a voltage drop and limit the current in the circuit, such as a polysilicon resistor R or a diffusion resistor R.

[0068] The seventh transistor M7 can be any N-type field-effect transistor whose conduction state is controlled by the gate voltage. For example, an NMOS transistor.

[0069] In its implementation, the first detection module 1 functions by connecting a resistor R in series with the seventh transistor M7. The first end of resistor R is directly connected to the power supply VDD. The second end of resistor R is connected to the drain of the seventh transistor M7, while the gate of the seventh transistor M7 is also shorted to the drain. The source of the seventh transistor M7 is connected to the reference ground VSS. This short-circuiting of the gate and drain ensures that the seventh transistor M7 always operates in its saturation conduction region, similar to a diode. The current flowing through this branch (i.e., the first current signal) is determined by subtracting the gate-source on-state voltage of the seventh transistor M7 from the power supply voltage, and then dividing by the resistance value of resistor R. Since the gate-source on-state voltage of the seventh transistor M7 is relatively stable within a certain range, the amplitude of the first current signal increases approximately linearly with the increase of the power supply voltage. This linearly changing current signal is drawn from the connection point of resistor R and the seventh transistor M7 and transmitted to the signal generation module 3 for comparison and processing.

[0070] Furthermore, in order to construct a circuit branch capable of generating a current signal related to the square of the power supply voltage by combining a current mirror composed of a transistor with a series of transistors, the following continues... Figure 3 As shown, in this embodiment, the second detection module 2 includes: the eighth transistor M8 to the fourteenth transistor M14; The source of the eighth transistor M8 is connected to the power supply VDD. The gate of the eighth transistor M8 is connected to the signal generation module 3, the drain of the eighth transistor M8, and the drain of the ninth transistor M9. The gate of the ninth transistor M9 is connected to the gates of the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, and the fourteenth transistor M14. The source of the ninth transistor M9 is connected to the drain of the tenth transistor M10. The source of the tenth transistor M10 is connected to the drain of the eleventh transistor M11. The source of the eleventh transistor M11 is connected to the drain of the twelfth transistor M12. The source of the twelfth transistor M12 is connected to the drain of the thirteenth transistor M13. The source of the thirteenth transistor M13 is connected to the drain of the fourteenth transistor M14. The source of the fourteenth transistor M14 is connected to the reference ground VSS.

[0071] It should be noted that the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, and the fourteenth transistor M14 can all be P-type or N-type field-effect transistors selected according to the circuit design requirements. In this embodiment, the eighth transistor M8 can be a P-type transistor (e.g., PMOS), and the ninth transistor M9 to the fourteenth transistor M14 can be N-type transistors (e.g., NMOS).

[0072] In its implementation, the second detection module 2 functions through two main parts: the eighth transistor M8 forms the input stage of a current mirror; the ninth transistor M9 to the fourteenth transistor M14 are connected in series to form a voltage control path. The source of the eighth transistor M8 is connected to the power supply VDD, and its gate and drain are shorted and connected to the drain of the ninth transistor M9. This connection allows the current flowing through the eighth transistor M8 to be mirrored to other branches. All the gates of the ninth transistor M9 to the fourteenth transistor M14 are interconnected and connected to the connection point between the drain of the ninth transistor M9 and the eighth transistor M8. This makes the six series-connected N-type transistors function as a whole, and their conduction state is controlled by the voltage at the connection point. As the power supply voltage increases, the potential at the connection point between the eighth transistor M8 and the series transistor group is raised, causing the gate voltage of the series transistor group to increase. When this voltage exceeds the conduction threshold of the series transistor group, a current path is established. Since each transistor in the series transistor group operates in the linear or saturation region, and their gates are controlled by the same voltage, the current flowing through the entire branch (i.e., the second current signal) is proportional to the square of the difference between the power supply voltage and the threshold voltage of the series transistors. Therefore, the amplitude of the second current signal increases sharply (square relationship) as the power supply voltage increases. This current is sensed by the eighth transistor M8 and transmitted to the signal generation module 3.

[0073] Furthermore, in order to construct a basic unit capable of power-driving the reset signal through a simple connection of two complementary transistors, we continue as follows... Figure 3 As shown, in this embodiment, the output buffer module 5 includes: a fifteenth transistor M15 and a sixteenth transistor M16; The gate of the fifteenth transistor M15 is connected to the gate of the signal generation module 3 and the gate of the sixteenth transistor M16, respectively. The source of the fifteenth transistor M15 is connected to the power supply VDD. The drain of the fifteenth transistor M15 is connected to the drain of the module to be reset 4 and the drain of the sixteenth transistor M16, respectively. The source of the sixteenth transistor M16 is connected to the reference ground VSS.

[0074] It should be noted that the fifteenth transistor M15 can be any P-type field-effect transistor whose conduction state is controlled by the gate voltage. For example, a PMOS transistor.

[0075] The sixteenth transistor, M16, can be any N-type field-effect transistor whose conduction state is controlled by the gate voltage. For example, an NMOS transistor.

[0076] In its implementation, the output buffer module 5 forms a complementary inverter using the fifteenth transistor M15 and the sixteenth transistor M16. The source of the fifteenth transistor M15 is connected to the power supply VDD, and the source of the sixteenth transistor M16 is connected to the reference ground VSS. The gates of the two transistors are interconnected, serving as the input terminal to receive the original reset signal from the signal generation module 3. The drains of the two transistors are interconnected, serving as the output terminal to the module 4 to be reset. When the input is low, the fifteenth transistor M15 is turned on while the sixteenth transistor M16 is turned off, and the output is pulled up to the power supply voltage (high level). When the input is high, the fifteenth transistor M15 is turned off while the sixteenth transistor M16 is turned on, and the output is pulled down to the reference ground VSS voltage (low level). This structure makes the unit an inverting driver with rail-to-rail output swing and low output impedance, enabling rapid charging and discharging of any input capacitance present in the module 4 to be reset, thereby achieving power driving and waveform shaping of the original reset signal and ensuring the reliable quality of the power supply VDD reset signal finally transmitted to the module 4 to be reset.

[0077] To achieve the above objectives, this application also proposes a power-on reset system, which includes the reset circuit described above.

[0078] It should be noted that the specific implementation of the power-on reset system provided in this embodiment can refer to the above embodiments, and this embodiment will not elaborate on it further. Therefore, the effects achieved by the power-on reset system in this embodiment can also refer to the above embodiments, and this embodiment will not elaborate on them further.

[0079] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A reset circuit, characterized in that, The circuit includes: a first detection module, a second detection module, and a signal generation module; The first detection module is connected to a power supply and is used to acquire the power supply voltage and generate a first current signal based on the change of the power supply voltage. The first current signal is linearly related to the magnitude of the power supply voltage. The second detection module is connected to the power supply and is used to acquire the power supply voltage and generate a second current signal based on the change of the power supply voltage. The second current signal is related to the magnitude of the power supply voltage. The signal generation module is connected to the first detection module, the second detection module, and the module to be reset, respectively, and is used to output a power reset signal to the module to be reset when the amplitude of the second current signal is greater than the amplitude of the first current signal.

2. The reset circuit as described in claim 1, characterized in that, The signal generation module is further configured to output a reset invalid signal to the module to be reset when the amplitude of the second current signal is less than the amplitude of the first current signal.

3. The reset circuit as described in claim 1, characterized in that, The signal generation module includes: a comparison unit and a latch output unit; The comparison unit is connected to the first detection module and the second detection module respectively, and is used to transmit the generated reset signal to the latch output unit when the amplitude of the second current signal is greater than the amplitude of the first current signal. The latch output unit is connected to the comparison unit and the module to be reset, respectively, and is used to transmit the generated power reset signal to the module to be reset according to the signal to be reset, and to latch the power reset signal.

4. The reset circuit as described in claim 3, characterized in that, The comparison unit includes: a first transistor and a second transistor; The source of the first transistor is connected to the power supply, the source of the second transistor is connected to the reference ground, the gate of the first transistor is connected to the second detection module, the drains of the first transistor and the drains of the second transistor are both connected to the latch output unit, and the gate of the second transistor is connected to the first detection module.

5. The reset circuit as described in claim 3, characterized in that, The latch output unit includes: a third transistor to a sixth transistor; The source of the third transistor is connected to the power supply, the drain of the third transistor is connected to the source of the fourth transistor, the gates of the third transistor and the fourth transistor are both connected to the drains of the fifth transistor, the drain of the sixth transistor, and the module to be reset, the drain of the fourth transistor is connected to the gates of the fifth transistor and the sixth transistor, the source of the fifth transistor is connected to the power supply, and the source of the sixth transistor is connected to the reference ground.

6. The reset circuit as described in claim 1, characterized in that, The first detection module includes: a resistor and a seventh transistor; The first end of the resistor is connected to the power supply, and the second end of the resistor is connected to the drain of the seventh transistor, the gate of the seventh transistor, and the signal generation module, respectively. The source of the seventh transistor is connected to the reference ground.

7. The reset circuit as described in claim 1, characterized in that, The second detection module includes: the eighth transistor to the fourteenth transistor; The source of the eighth transistor is connected to the power supply. The gate of the eighth transistor is connected to the signal generation module, the drain of the eighth transistor, and the drain of the ninth transistor. The gate of the ninth transistor is connected to the gates of the tenth, eleventh, twelfth, thirteenth, and fourteenth transistors. The source of the ninth transistor is connected to the drain of the tenth transistor. The source of the tenth transistor is connected to the drain of the eleventh transistor. The source of the eleventh transistor is connected to the drain of the twelfth transistor. The source of the twelfth transistor is connected to the drain of the thirteenth transistor. The source of the thirteenth transistor is connected to the drain of the fourteenth transistor. The source of the fourteenth transistor is connected to a reference ground.

8. The reset circuit as described in claim 1, characterized in that, The circuit also includes: an output buffer module; The output buffer module is disposed between the signal generation module and the module to be reset. The output buffer module is used to transmit the power reset signal or reset invalid signal to the module to be reset after power driving.

9. The reset circuit as described in claim 8, characterized in that, The output buffer module includes: a fifteenth transistor and a sixteenth transistor; The gate of the fifteenth transistor is connected to the gate of the signal generation module and the gate of the sixteenth transistor, the source of the fifteenth transistor is connected to the power supply, the drain of the fifteenth transistor is connected to the module to be reset and the drain of the sixteenth transistor, and the source of the sixteenth transistor is connected to the reference ground.

10. A power-on reset system, characterized in that, The power-on reset system includes the reset circuit according to any one of claims 1 to 9.

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