Five-phase five-frequency-division circuit
By designing a five-phase divider circuit that includes flip-flops and inverters, the problems of counting errors, high power consumption, and narrow frequency range in existing frequency divider circuits for high-frequency applications are solved, achieving a simple, low-power, and fast five-phase frequency division effect.
Patent Information
- Application Number
- CN202511682491.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-17
- Publication Date
- 2026-02-27
AI Technical Summary
Existing frequency divider circuits suffer from problems such as counting errors, high power consumption, complex design, and narrow frequency range in high-frequency applications, making it difficult to realize a five-phase five-frequency divider circuit that is simple in structure, low in power consumption, small in area, and fast in speed.
A five-phase frequency divider circuit is adopted, including flip-flops DFF1, DFF2, DFF3, NAND gates, inverters INV1 and INV2, which are constructed through complementary CMOS logic gates to realize frequency division and generate five clock signals with different phases. The signal delay and combination are performed by using three flip-flops and two inverters.
A five-phase frequency divider circuit with simple structure, low power consumption, small area, and high speed was implemented. It can work stably at high frequencies and is suitable for demultiplexers and distributors.
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Figure CN121585162A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application belongs to the technical field of analog integrated circuits, and relates to a five-phase five-frequency division circuit. BACKGROUND
[0002] Demultiplexers and distributors are widely used in various chips. When data recovery is performed, the serial signal needs to be deserialized, that is, a high-speed clock needs to be divided to generate low-frequency clocks of different phases to sample high-frequency signals of different phases, and therefore a distribution circuit is needed to divide the high-speed clock and generate different phases.
[0003] Existing frequency division circuits include counter frequency division, phase-locked loop (PLL) frequency division, delay-locked loop (DLL) frequency division, etc.
[0004] The counter frequency division structure is simple and easy to integrate, but the highest working frequency is limited by the flip speed of the counter, and counting errors may occur in high-frequency applications, and the duty cycle of the output signal is usually not 50%.
[0005] The PLL frequency division can achieve a very high frequency division ratio, and the frequency stability of the output signal is high and the phase noise is low; the frequency and phase of the input signal can be quickly locked, but the design is relatively complex, the loop parameters need to be accurately adjusted to ensure stability and fast locking, and the power consumption is high, especially when working at high frequency.
[0006] The DLL frequency division can achieve relatively low phase noise and is relatively insensitive to power noise and process variation; the structure is relatively simple and easy to integrate, but the working frequency range is relatively narrow, and it is usually suitable for fixed frequency or small frequency variation range applications, and is sensitive to temperature variation and needs temperature compensation.
[0007] In summary, there is an urgent need for a five-phase five-frequency division circuit with simple structure, low power consumption, small area and high speed. SUMMARY
[0008] To solve the above-mentioned problems in the prior art, the present application adopts a five-phase five-frequency division circuit, which comprises:
[0009] The D terminal of the flip-flop DFF1 is connected to the output terminal of the inverter INV2, the Q terminal of the flip-flop DFF1 is connected to one input terminal of the NAND gate, the other input terminal of the NAND gate is connected to the output terminal of the inverter INV2, the output terminal of the NAND gate is connected to the D terminal of the flip-flop DFF2, the Q terminal of the flip-flop DFF2 is connected to the input terminal of the inverter INV1, the output terminal of the inverter INV1 is connected to the Q terminal of the flip-flop DFF3, and the Q terminal of the flip-flop DFF3 is connected to the input terminal of the inverter INV2; wherein the Q terminal is the output terminal of the flip-flop, and the D terminal is the input terminal of the flip-flop.
[0010] The D terminal of the flip-flop DFF1 is the first output terminal P1 of the five-phase five-frequency circuit, the Q terminal of the flip-flop DFF1 is the second output terminal P2 of the five-phase five-frequency circuit, the output terminal of the inverter INV1 is the third output terminal P3 of the five-phase five-frequency circuit, the output terminal of the AND gate is the fourth output terminal P4 of the five-phase five-frequency circuit, and the Q terminal of the flip-flop DFF2 is the fifth output terminal P5 of the five-phase five-frequency circuit.
[0011] The phases of the signals output by the output terminals P1 to P5 are sequentially different by 72°.
[0012] The duty cycle of the signal output by the third output terminal P3 is 40%, and the duty cycles of the signals output by the other output terminals are all 60%.
[0013] The CLK terminals of the flip-flop DFF1, the flip-flop DFF2 and the flip-flop DFF3 are connected to the clock signal CLK.
[0014] The frequency of the clock signal CLK is 6.25 GHz.
[0015] The flip-flop DFF1, the flip-flop DFF2 and the flip-flop DFF3 are triggered by the rising edge of the clock signal CLK.
[0016] The NAND gate and the inverters INV1 and INV2 are complementary CMOS logic gates.
[0017] The CMOS logic gates used by the NAND gate and the inverters INV1 and INV2 have a size of 65 nm.
[0018] Advantages:
[0019] The five-phase five-frequency dividing circuit of the present application can divide the input high-speed clock signal by five and generate five different phase five-frequency clocks only by three flip-flops, one AND gate and two inverters, and the NAND gate and the two inverters are composed of complementary CMOS logic gates with minimum size, so the circuit has simple structure, low power consumption, small area and high speed, and can be widely used in demultiplexer and distributor. BRIEF DESCRIPTION OF DRAWINGS
[0020] Figure 1 A structural diagram of a five-phase five-frequency dividing circuit provided for the embodiment of the present application is provided.
[0021] Figure 2 A simulation result diagram of a five-phase five-frequency dividing circuit provided for the embodiment of the present application is provided. DETAILED DESCRIPTION
[0022] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.
[0023] As shown in Figure 1 the embodiment of the present application adopts a five-phase five-frequency dividing circuit, which comprises:
[0024] a flip-flop DFF1, a flip-flop DFF2, a flip-flop DFF3, a NAND gate, an inverter INV1 and an inverter INV2; the CLK port of the flip-flops DFF1, DFF2 and DFF3 is connected to a clock signal CLK and triggered by the rising edge of the clock signal CLK, the D port of the flip-flop DFF1 is the first output port P1 of the five-phase five-frequency dividing circuit and connected to the output port of the inverter INV2, the Q port of the flip-flop DFF1 is the second output port P2 of the five-phase five-frequency dividing circuit and connected to one input port of the NAND gate, the other input port of the NAND gate is connected to the output port of the inverter INV2, the output port of the NAND gate is the fourth output port P4 of the five-phase five-frequency dividing circuit and connected to the D port of the flip-flop DFF2, the Q port of the flip-flop DFF2 is the fifth output port P5 of the five-phase five-frequency dividing circuit and connected to the input port of the inverter INV1, the output port of the inverter INV1 is the third output port P3 of the five-phase five-frequency dividing circuit and connected to the Q port of the flip-flop DFF3, and the Q port of the flip-flop DFF3 is connected to the input port of the inverter INV2; wherein the Q port is the data output port of the flip-flop, and the D port is the data input port of the flip-flop.
[0025] The NAND gates and inverters INV1, INV2 are complementary CMOS logic gates; preferably, the NAND gates and inverters INV1, INV2 are 65 nm complementary CMOS logic gates.
[0026] The clock phases of the signals output by the output terminals P1 to P5 are sequentially different by 72°, the phase of the signal output by the output terminal P1 is 0°, the phase of the signal output by the output terminal P2 is 72°, the phase of the signal output by the output terminal P3 is 144°, the phase of the signal output by the output terminal P4 is 216°, and the phase of the signal output by the output terminal P5 is 288°; wherein, the duty cycle of the signal output by the output terminal P3 is 40%, and the duty cycles of the signals output by the other output terminals are all 60%.
[0027] The signal output by the output terminal P4 is obtained by performing NAND operation on the signals output by the output terminals P1 and P2, so the duty cycle of the signal output by the output terminal P4 is 60%, the signal output by the output terminal P5 is generated by the D flip-flop from the signal output by the output terminal P4, so the phase of the signal output by the output terminal P5 is only different from that of the signal output by the output terminal P4 by 72°, and the duty cycle is also 60%, the signal output by the output terminal P3 is the inverse of the signal output by the output terminal P5, so the duty cycle is complementary to that of the signal output by the output terminal P5, and the duty cycle is 40%, and the signals output by the output terminals P1 and P2 are both inverted from the signal output by the output terminal P3 by inverters, so the duty cycles are both 60%.
[0028] The principle of the circuit structure for realizing five-frequency is that:
[0029] The period of the output signal is five times that of the input signal, i.e. five-frequency, the present application realizes five-frequency by delaying the input signal through three DFFs (D flip-flops) to make the period of the output signal five times that of the input signal; specifically, the present application uses the outputs of 3 DFFs (D flip-flops) to represent 5 states, and when each clock edge comes, the states are sequentially increased according to the above 5 states, thereby completing a 5-period cycle, and finally a specific state is taken as the frequency division output, thereby realizing five-frequency.
[0030] The principle of the circuit structure for realizing five-phase is that:
[0031] The period of the output clock is If the phase difference is 360°, then each input clock corresponds to a phase shift of 360° / 5, i.e. 72°; the phase of the signal at the output end P1 is 0°, the signal at the output end P1 is delayed by one input clock through the flip-flop DFF1, thus the phase of the signal at the output end P2 is 72°, which is different from the phase of the signal at the output end P1 by 72°; the phase of the signal at the output end P4 is 216°, which is obtained by performing an AND-NOT operation between the signal at the output end P1 and the signal at the output end P2; the phase of the signal at the output end P4 is different from the phase of the signal at the output end P1 by 72°, thus the phase of the signal at the output end P5 is 288°; the signal at the output end P3 is obtained by inverting the signal at the output end P5 through the inverter INV1; since the duty cycle of the signal at the output end P5 is 60%, the duty cycle of the signal at the output end P3 is 40%, thus the inverter inverts the signal and generates a phase shift of 20% at the same time, thus the phase of the signal at the output end P3 is 144°; the phase of the signal at the output end P1 is 0°, which is obtained by delaying the signal at the output end P3 by one input clock through the flip-flop DFF3.
[0032] In one embodiment, the signal outputted by the output end P1 of each five-frequency circuit is taken as the CLK clock signal of the next five-frequency circuit, thus 5N frequency division is realized.
[0033] The frequency of the input clock CLK is up to 10GHz; preferably, the frequency of the clock signal CLK is 6.25GHz.
[0034] In order to further verify the effect of the embodiment of the present application, a five-phase five-frequency circuit is realized by using 1.2V as the power voltage under the 65nm CMOS process, the input clock is 6.25GHz, and the signal can realize better frequency division and phase difference; the input clock signal CLK and the output five clock signals are shown in Figure 2 It can be seen that the frequency division circuit of the present application is stable and fast.
[0035] The above embodiments further illustrate the purpose, technical scheme and advantages of the present application, and it should be understood that the above embodiments are only the preferred embodiments of the present application, and are not intended to limit the present application, and any modification, equivalent replacement, improvement, etc. made to the present application within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims
1. A five-phase five-division circuit, characterized by, Comprise: The trigger DFF1, the trigger DFF2, the trigger DFF3, the NAND gate, the inverter INV1 and the inverter INV2;The D end of trigger DFF1 is connected to the output end of inverter INV2, the Q end of trigger DFF1 is connected to one input end of NAND gate, the other input end of NAND gate is connected to the output end of inverter INV2, the output end of NAND gate is connected to the D end of trigger DFF2, the Q end of trigger DFF2 is connected to the input end of inverter INV1, the output end of inverter INV1 is connected to the Q end of trigger DFF3, the Q end of trigger DFF3 is connected to the input end of inverter INV2;Wherein, the Q end is the output port of trigger, and the D end is the input port of trigger.
2. A five-phase five-division circuit according to claim 1, characterized in that, The D end of trigger DFF1 is the first output end P1 of five-phase five-frequency circuit, the Q end of trigger DFF1 is the second output end P2 of five-phase five-frequency circuit, the output end of inverter INV1 is the third output end P3 of five-phase five-frequency circuit, the output end of AND gate is the fourth output end P4 of five-phase five-frequency circuit, and the Q end of trigger DFF2 is the fifth output end P5 of five-phase five-frequency circuit.
3. A five-phase five-division circuit according to claim 2, characterized in that, The phase of the signal output by output end P1 to P5 is sequentially different by 72°.
4. A five-phase five-division circuit according to claim 2, characterized in that, The duty cycle of the signal output by third output end P3 is 40%, and the duty cycle of the signal output by the remaining output ends is 60%.
5. A five-phase five-division circuit according to claim 1, characterized in that, The CLK port of trigger DFF1, trigger DFF2 and trigger DFF3 is connected to clock signal CLK.
6. A five-phase five-division circuit according to claim 5, characterized in that, The frequency of clock signal CLK is 6.25GHz.
7. A five-phase five-division circuit according to claim 5, characterized in that, Trigger DFF1, trigger DFF2 and trigger DFF3 are triggered by the rising edge of clock signal CLK.
8. A five-phase five-division circuit according to claim 1, characterized in that, The NAND gate and the inverters INV1, INV2 use complementary CMOS logic gates.
9. A five-phase five-division circuit according to claim 8, characterized in that, The size of the CMOS logic gate used by the NAND gate and the inverters INV1, INV2 is 65nm.