SDH (Synchronous Digital Hierarchy) data monitoring equipment and method

Abstract

The invention relates to SDH data monitoring equipment and method, the equipment comprises a field programmable gate array (FPGA), a central processing unit (CPU) and an interconnection interface, the FPGA is used for receiving an SDH data stream from an SDH optical transmission channel, performing hardware-level preprocessing on the SDH data stream to obtain preprocessed data, packaging the preprocessed data into a structured data message, and sending the structured data message to the interconnection interface; the processor is used for receiving the structured data message through the interconnection interface and sending the structured data message to the CPU through the interconnection interface, and the CPU is used for receiving the structured data message through the interconnection interface, deeply analyzing the structured data message to obtain analyzed information and visually displaying and / or uploading the analyzed information to a monitoring system. According to the invention, millisecond-level real-time perception of network events is realized, integration from data access and processing to analysis and display can be realized, and a solid foundation is provided for low-cost flexible deployment and centralized monitoring of the SDH network.

Description

Technical Field

[0001] This application belongs to the field of communication network operation and maintenance technology, and in particular relates to an SDH data monitoring device and method. Background Technology

[0002] Synchronous Digital Hierarchy (SDH) is the backbone transmission technology of modern communication networks, carrying a large number of critical services. To ensure reliable network operation, it is essential to conduct real-time and continuous monitoring and performance analysis of SDH links.

[0003] Currently, mainstream SDH network monitoring methods have significant limitations. On the one hand, software processing solutions based on general-purpose processors are limited by their serial computing architecture, facing performance bottlenecks when processing high-speed SDH data streams. This makes it difficult to achieve line-speed processing, resulting in lagging monitoring data and failing to meet the need for real-time perception and response to network anomalies. On the other hand, although dedicated hardware can achieve high-performance processing, existing solutions are usually characterized by low integration, high cost, or poor deployment flexibility, making it difficult to adapt to application scenarios that require low-cost, flexible deployment of network nodes and 24 / 7 uninterrupted online monitoring. Summary of the Invention

[0004] The purpose of this application is to provide an SDH data monitoring device and method. The SDH data monitoring device and method provided by this application can not only solve the performance bottleneck of general-purpose processors and realize millisecond-level real-time perception of network events, but also realize the integration of data access, processing to parsing and display, providing a solid foundation for low-cost and flexible deployment and centralized monitoring of SDH networks.

[0005] This application provides an SDH data monitoring device, including: a field-programmable gate array (FPGA), a central processing unit (CPU), and an interconnection interface connecting the FPGA and the CPU; The FPGA is used to receive SDH data streams from the SDH optical transmission channel, perform hardware-level preprocessing on the SDH data streams to obtain preprocessed data, encapsulate the preprocessed data into structured data packets, and send them to the CPU through the interconnect interface. The CPU is used to receive the structured data message through the interconnection interface, perform deep parsing on the structured data message to obtain the parsed information, and visualize and / or upload the parsed information to the monitoring system.

[0006] Optionally, the preprocessing includes at least frame positioning, byte alignment, descrambling, and overhead byte extraction.

[0007] Optionally, the parsed information includes at least SDH alarm information, channel line information at all levels, and bearer service protocol information.

[0008] Optionally, it also includes: multiple SFP+ optical interfaces; Multiple SFP+ optical interfaces are used to access SDH data streams of different rates; The FPGA is connected to multiple SFP+ optical interfaces for receiving SDH data streams at at least one of the STM-1, STM-4, STM-16, and STM-64 standard rates.

[0009] Optionally, The FPGA is also used to detect alarm and / or bit error information in the SDH data stream in real time during the hardware-level preprocessing process, and report the alarm and / or bit error information to the CPU via the interconnect interface in an interrupt manner.

[0010] Optionally, the device connects to the SDH main transmission link via an optical splitter to obtain the SDH data stream in a bypass mirroring manner.

[0011] Optionally, the interconnect interface is a communication interface conforming to the PCIe bus standard, used to provide the CPU with a channel to access the internal registers of the FPGA, and to transmit the structured data messages and alarm and / or error information reported by the FPGA.

[0012] Optionally, the device further includes a storage unit; The storage unit is connected to the CPU and is used to store the information parsed by the CPU. The stored data supports subsequent playback and analysis.

[0013] Optionally, the CPU is also used to run or connect to a web service to visualize the parsed information.

[0014] This application also provides an SDH data monitoring method applied to an SDH data monitoring device, the device comprising: a field-programmable gate array (FPGA), a central processing unit (CPU), and an interconnection interface connecting the FPGA and the CPU, the method comprising: The FPGA receives SDH data streams from the SDH optical transmission channel, performs hardware-level preprocessing on the SDH data streams to obtain preprocessed data, encapsulates the preprocessed data into structured data packets, and sends them to the CPU through the interconnect interface. The CPU receives the structured data message through the interconnection interface, performs deep parsing on the structured data message to obtain the parsed information, and then visualizes and / or uploads the parsed information to the monitoring system.

[0015] Compared with existing technologies, this application provides an SDH data monitoring device and method. The device includes: a field-programmable gate array (FPGA), a central processing unit (CPU), and an interconnection interface connecting the FPGA and the CPU. The FPGA is used to receive SDH data streams from the SDH optical transmission channel, perform hardware-level preprocessing on the SDH data streams to obtain preprocessed data, encapsulate the preprocessed data into structured data packets, and send them to the CPU through the interconnection interface. The CPU is used to receive the structured data packets through the interconnection interface, perform deep parsing on the structured data packets to obtain parsed information, and visualize and / or upload the parsed information to the monitoring system. Through a heterogeneous fusion architecture of FPGA and CPU, the SDH data monitoring task is decoupled into two highly efficient and collaborative stages: First, the FPGA performs hardware-level line-speed preprocessing of the SDH data stream, thereby overcoming the performance bottleneck of general-purpose processors and achieving millisecond-level real-time perception of network events; second, the CPU performs in-depth analysis and display of the preprocessed structured messages. This division of labor fully leverages the advantages of each hardware component, significantly improving overall processing efficiency and resource utilization. Finally, the above functions are integrated into a complete dedicated device, enabling the integration of data access, processing, analysis, and display, providing a solid foundation for low-cost, flexible deployment and centralized monitoring of SDH networks. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a structural block diagram of an SDH data monitoring device disclosed in an embodiment of this application; Figure 2 This is a structural block diagram of another SDH data monitoring device disclosed in an embodiment of this application; Figure 3 This is a flowchart of an SDH data monitoring method disclosed in an embodiment of this application. Detailed Implementation

[0018] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0019] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly set on the other component; when a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to the other component.

[0020] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0021] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "a plurality of" or "several" means two or more, unless otherwise explicitly specified.

[0022] It should be noted that the structures, proportions, sizes, etc., shown in the accompanying drawings of this specification are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the conditions under which this application can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size should still fall within the scope of the technical content disclosed in this application, provided that they do not affect the effects and purposes that this application can produce.

[0023] like Figure 1As shown, this application provides an SDH data monitoring device, including: a field-programmable gate array (FPGA), a central processing unit (CPU), and an interconnection interface connecting the FPGA and the CPU; the FPGA is used to receive SDH data streams from the SDH optical transmission channel, perform hardware-level preprocessing on the SDH data streams to obtain preprocessed data, encapsulate the preprocessed data into structured data packets, and send them to the CPU through the interconnection interface; the CPU is used to receive the structured data packets through the interconnection interface, perform deep parsing on the structured data packets to obtain parsed information, and visualize and / or upload the parsed information to the monitoring system.

[0024] In this embodiment, the device operates based on a heterogeneous architecture that combines an FPGA and a CPU. The data stream of the SDH optical transmission channel is first received by the FPGA. Leveraging its hardware programmability, the FPGA performs a series of low-level, fixed hardware-level preprocessing operations on the incoming raw bit stream. After the preprocessing is completed, the FPGA encapsulates the result into a structured data message and sends it to the CPU through the interconnect interface. After receiving the message through the same interface, the CPU performs a more flexible deep parsing task, different from that of the FPGA, to extract key information for monitoring. Finally, the CPU is responsible for visualizing and / or uploading the parsed information to the monitoring system, thereby completing the complete conversion process from raw data to readable and manageable information.

[0025] The aforementioned working principle brings significant and hierarchical technical benefits: First, by entrusting the most time-consuming low-level, fixed operations to the FPGA for hardware logic execution, ultra-high-speed processing of data streams is achieved, effectively overcoming the performance bottleneck of general-purpose processors in traditional solutions when handling such tasks, and ensuring high real-time performance of monitoring; Second, the heterogeneous division of labor between the FPGA and the CPU achieves task decoupling, allowing the CPU to focus on its strengths in complex protocol analysis and system management, significantly improving the overall system's processing efficiency and resource utilization rationality; Finally, the entire set of functions—data reception, hardware preprocessing, software parsing, and result display—is highly integrated into a single device entity, forming a fully functional and highly autonomous dedicated monitoring device, which provides a key hardware and architectural foundation for flexible deployment and centralized monitoring in the network.

[0026] Compared with existing technologies, this application provides an SDH data monitoring device and method. The device includes: a field-programmable gate array (FPGA), a central processing unit (CPU), and an interconnection interface connecting the FPGA and the CPU. The FPGA is used to receive SDH data streams from the SDH optical transmission channel, perform hardware-level preprocessing on the SDH data streams to obtain preprocessed data, encapsulate the preprocessed data into structured data packets, and send them to the CPU through the interconnection interface. The CPU is used to receive the structured data packets through the interconnection interface, perform deep parsing on the structured data packets to obtain parsed information, and visualize and / or upload the parsed information to the monitoring system. Through a heterogeneous fusion architecture of FPGA and CPU, the SDH data monitoring task is decoupled into two highly efficient and collaborative stages: First, the FPGA performs hardware-level line-speed preprocessing of the SDH data stream, thereby overcoming the performance bottleneck of general-purpose processors and achieving millisecond-level real-time perception of network events; second, the CPU performs in-depth analysis and display of the preprocessed structured messages. This division of labor fully leverages the advantages of each hardware component, significantly improving overall processing efficiency and resource utilization. Finally, the above functions are integrated into a complete dedicated device, enabling the integration of data access, processing, analysis, and display, providing a solid foundation for low-cost, flexible deployment and centralized monitoring of SDH networks.

[0027] As one implementation method, in this embodiment of the application, the preprocessing includes at least frame positioning, byte alignment, descrambling, and overhead byte extraction.

[0028] In this embodiment, the specific functions of each step in the hardware-level preprocessing are as follows: Frame localization is used to identify and lock the start boundary of STM frames in a continuous SDH data stream, providing an accurate frame synchronization reference for subsequent processing. Byte alignment is used to organize the identified frame data according to byte boundaries to ensure the accuracy of the data structure for subsequent byte-by-byte operations. Descrambling code is used to descramble frame payload data according to the algorithm specified in the SDH standard to recover the original user data; Overhead byte extraction is used to separate and extract key information bytes for monitoring, management and maintenance from the segment overhead (SOH) and channel overhead (POH) regions of the frame structure.

[0029] Through this combination of steps, the FPGA transforms the raw, unstructured bitstream into a preprocessed result containing valid payload data and key overhead information, which can be efficiently processed by the CPU.

[0030] In this embodiment, the FPGA's logic configuration file is stored in an off-chip non-volatile FLASH memory. When the device is powered on, the FPGA automatically loads its runtime image from the FLASH memory through Active Serial (AS) configuration mode to complete the initialization of the hardware logic. This method ensures the stability and reliability of the FPGA's processing functions, enabling the device to quickly enter a ready state after each startup.

[0031] As one implementation method, in this embodiment of the application, the parsed information includes at least SDH alarm information, channel line information at all levels, and bearer service protocol information.

[0032] In this embodiment, the specific composition and function of the information obtained by the CPU through deep parsing are as follows: SDH alarm information refers to information parsed from overhead bytes that characterizes the abnormal state of the transmission link and channel, such as loss of signal (LOS), loss of frame (LOF), loss of pointer (LOP), and various bit error alarms. This information is the direct basis for real-time fault location and network health assessment. Information on each level of channel refers to data about the transmission path topology, bandwidth configuration, and performance status obtained through the analysis of segment-level and channel-level overhead. For example, it may include the STM-N rate class, the multiplexing structure and cross-connection relationships of channels at each level from high-order VC-4 to low-order VC-12, and particularly supports the identification and correlation analysis of concatenated and virtual concatenated services, as well as the channel's bit error rate performance parameters. This information forms the basis for network resource management and quality of service analysis. The information on the service protocol carried refers to the type of upper-layer service protocol encapsulated in the SDH frame payload data, which is identified through further analysis. Examples include Ethernet, POS (Packet Over SDH, i.e., SDH carrying packet services) or ATM (Asynchronous Transfer Mode). This information helps maintenance personnel understand the actual service type carried on the link and achieve service-level monitoring and management.

[0033] By comprehensively analyzing and correlating the above multi-dimensional information, the CPU can construct a complete monitoring view from physical links to logical services, and from current status to historical performance, thereby providing core data support for efficient network operation and maintenance and intelligent analysis.

[0034] like Figure 2 As shown, in one embodiment, this application further includes: multiple SFP+ optical interfaces; multiple SFP+ optical interfaces for accessing SDH data streams of different rates; and an FPGA connected to multiple SFP+ optical interfaces for receiving SDH data streams of at least one of the STM-1, STM-4, STM-16, and STM-64 standard rates.

[0035] In this embodiment, multiple SFP+ optical interfaces refer to N SFP+ optical interfaces, where N is a positive integer greater than 1. The configuration and operation of multiple SFP+ optical interfaces are as follows: The front panel of the device integrates multiple physically independent SFP+ optical module slots, forming multiple SFP+ optical interfaces. These interfaces support hot-swapping at the physical layer and can be adapted to STM-1 (155 Mbit / s), STM-4 (622 Mbit / s), STM-16 (2.5 Gbit / s), and STM-64 (10 Gbit / s) SDH standard optical signals respectively by loading different types of optical modules at the link layer. The FPGA integrates configurable physical layer and link layer processing logic corresponding to different rates. When an optical interface is connected to an SDH signal, the FPGA can automatically identify or determine its operating rate through configuration and call the corresponding logic channel to perform hardware-level preprocessing on the data.

[0036] This design allows a single device to be flexibly deployed in different network locations from the access layer to the core layer without changing the hardware, receiving and processing SDH traffic at various rates. This greatly enhances the device's adaptability to different scenarios and ease of deployment, providing a hardware foundation for achieving unified end-to-end network monitoring.

[0037] In one implementation embodiment, the device adopts a standard 2U rack-mount physical structure to facilitate centralized deployment in a server room rack. In addition to multiple SFP+ optical interfaces, the front panel of the device also features a USB interface for local management, a Gigabit Ethernet electrical interface for network management, and an RJ45 console serial port for command-line configuration. Internally, the CPU motherboard provides a standard PCIe expansion slot for connecting additional coprocessor modules (such as GPUs); it also provides SATA and mSATA interfaces to support various hard drive storage solutions and supports DDR4 memory expansion. Multiple fans are installed inside the chassis to ensure the heat dissipation requirements of core components such as the FPGA and CPU under high loads. This integrated hardware design integrates all functions of data acquisition, processing, storage, and management within a limited space, providing a physical foundation for the stable, reliable operation and convenient deployment of the device.

[0038] As one implementation method, in this embodiment of the application, the FPGA is also used to detect alarm and / or bit error information in the SDH data stream in real time during the hardware-level preprocessing process, and report the alarm and / or bit error information to the CPU in an interrupt manner through the interconnect interface.

[0039] In this embodiment, the FPGA's real-time detection and interrupt reporting mechanism is implemented as follows: In the preprocessing data path of the FPGA, real-time detection logic for the SDH frame structure is deployed in parallel. This logic continuously monitors the input data stream. Once a preset abnormal condition is identified during frame location, overhead byte parsing, or descrambling (such as frame synchronization loss, alarm indicator bit activation in the overhead byte, or bit error determination based on checksum), a high-priority interrupt event is immediately triggered. This interrupt signal is quickly transmitted to the CPU through a dedicated pin of the interconnect interface or a message passing mechanism. The CPU's interrupt service routine then responds by accessing a specific status register mapped to its address space inside the FPGA to accurately read detailed information such as alarm type, occurrence channel, bit error count, and timestamp, and then handing it over to the upper-level management software for recording, analysis, and presentation.

[0040] This "detection-interruption-response" mechanism brings a significant improvement in real-time performance, avoiding the processing delays and resource consumption caused by the CPU passively polling the FPGA status. This allows any network anomaly to be detected and reported at the millisecond or even microsecond level, ensuring that network operators or upper-level management systems can detect link performance degradation and faults in near real-time, greatly shortening the mean time to repair faults and meeting the stringent real-time requirements of modern mission-critical networks for monitoring systems. At the same time, this mechanism frees the CPU from frequent status queries, allowing it to focus more on core tasks such as deep analysis, thus optimizing the overall resource allocation and processing efficiency of the system.

[0041] In one implementation method, in this embodiment of the application, the device accesses the SDH main transmission link through an optical splitter to obtain the SDH data stream in a bypass mirroring manner.

[0042] In this embodiment, as Figure 2 As shown, the optical splitter connects to each SFP+ optical interface. The specific method by which the device achieves bypass mirroring access through the optical splitter is as follows: In actual deployment, the optical splitter is inserted into the SDH primary transmission link to be monitored. The optical splitter distributes the optical signal in the primary link according to a certain ratio (such as 95:5). Most of the optical power continues to be transmitted along the primary link to ensure uninterrupted service. The small amount of optical power is mirrored and guided to any SFP+ optical interface of the device. The device receives this mirrored traffic through this interface and uses it as the source of the SDH data stream it processes. The entire access process is carried out only at the physical optical layer and does not involve any modification to the SDH frame structure or termination of service signals, thus achieving completely transparent data acquisition of the primary link.

[0043] This bypass mirroring access method is the physical foundation for this device to achieve non-intrusive, "zero-impact" monitoring of services. It enables the deployment, debugging, upgrading, or decommissioning of monitoring equipment to be carried out without interrupting the operator's critical services, greatly improving the flexibility and security of operation and maintenance. At the same time, it creates conditions for the device to perform 24 / 7 uninterrupted online performance monitoring and fault capture of the network, overcoming the limitations of traditional instruments that can only be temporarily connected and cannot provide continuous data. This method, combined with the heterogeneous processing architecture inside the device, achieves a unity of high-performance real-time processing and flexible and convenient deployment.

[0044] As one implementation method, in this embodiment of the application, the interconnect interface is a communication interface that conforms to the PCIe bus standard, which is used to provide the CPU with a channel to access the internal registers of the FPGA and to transmit structured data messages as well as alarm and / or error information reported by the FPGA.

[0045] In this embodiment, the communication interface conforming to the PCIe bus standard is implemented as follows: the interconnect interface strictly adheres to the PCIe bus standard at both the physical and protocol levels. At the physical level, the FPGA and CPU motherboard are connected via high-speed differential signal lines. At the logical level, the FPGA internally implements a PCIe endpoint controller, while the CPU identifies and controls it through the PCIe root union provided by its chipset or motherboard. This interface provides the CPU with two types of core channels: first, a configuration and register access channel, where the CPU can directly read and write the FPGA's internal control, status, and configuration registers through its standard memory-mapped I / O method, enabling flexible control over the FPGA's operating mode, parameters, and interrupts; second, a high-speed data transmission channel, based on the reliable transmission mechanism of PCIe, used for efficient and large-volume transmission of structured data packets encapsulated by the FPGA, and transmitting real-time alarm and error information in the form of in-band messages or doorbell interrupts. Data transmission can adopt a direct memory access method, where the FPGA actively writes data to a designated area of ​​the CPU's system memory, greatly reducing the CPU's data handling burden.

[0046] By employing a standardized PCIe interface as the interconnect link for heterogeneous computing cores, several significant advantages are brought: First, the high bandwidth and low latency characteristics perfectly match the FPGA's requirements for continuously delivering high-speed preprocessed data to the CPU and real-time event reporting, ensuring the overall system throughput and response speed. Second, the standardized memory mapping and interrupt mechanism simplifies the complexity of hardware-software co-design, allowing the CPU to control the FPGA and exchange data with it as conveniently and efficiently as accessing its own peripherals, improving system stability and maintainability. Third, the mature PCIe ecosystem provides a solid foundation for standardized device design, compatibility verification, and future performance expansion (such as upgrading to higher PCIe generations). This interface is key to achieving efficient and reliable collaboration between the FPGA and CPU, thereby fully realizing the performance potential of the heterogeneous converged architecture.

[0047] In one specific hardware implementation of this embodiment, the PCIe interface is physically implemented through an adapter card connector. One end of the adapter card connector is connected to the module carrying the FPGA, and the other end is inserted into the standard PCIe slot of the CPU motherboard. This not only provides a reliable high-speed electrical connection, but also allows the FPGA module to be designed, upgraded and maintained independently of the motherboard, enhancing the flexibility and scalability of the device hardware configuration.

[0048] In one embodiment of this application, the device further includes a storage unit; the storage unit is connected to the CPU and is used to store information parsed by the CPU, and the stored data supports subsequent playback and analysis.

[0049] In this embodiment, the storage unit works as follows: the storage unit is connected to the CPU through a standard high-speed data interface (such as SATA). After the CPU completes the deep parsing of the structured data packets, it writes the generated, timestamped monitoring information (such as alarm events, performance statistics, and protocol analysis results) into the persistent storage medium (such as solid-state drives or hard disk drives) in the storage unit according to a predetermined data format and storage strategy. The stored data is indexed and organized based on timelines and event chains, and can be queried, retrieved, and exported through the device's local or remote management interface.

[0050] By integrating storage units, this device has evolved from a "real-time monitoring terminal" into a "monitoring and analysis all-in-one machine" with historical data management capabilities. The technological benefits are mainly reflected in two aspects: First, it achieves localized and highly reliable retention of monitoring data, providing a complete data foundation for post-event tracing of network faults, long-term performance trend analysis, and compliance auditing, thus compensating for the lack of a historical perspective in purely real-time monitoring solutions. Second, the function of "supporting subsequent playback and analysis" allows maintenance personnel to reproduce network status and business traffic at any historical point in time, and perform correlation analysis based on events at specific times, greatly enhancing the accuracy of network fault diagnosis and the scientific nature of maintenance decisions. This function, integrated within the device, also avoids the network bandwidth pressure and storage costs associated with continuously uploading massive amounts of monitoring data to external systems.

[0051] As one implementation method, in this embodiment of the application, the device further includes a complex programmable logic device (CPLD); the CPLD is used to control the power-on timing and startup process of the CPU and FPGA.

[0052] In this embodiment, the CPLD serves as the hardware management unit of the system and is directly connected to the CPU. During the power-on process, the CPLD first sends reset and enable signals to the CPU according to the preset timing sequence. After the CPU starts up, it then controls the power-on and reset of other core components such as the FPGA according to the management logic of the CPLD or its own firmware program, ensuring that each hardware module starts up in sequence and stably, avoiding system instability caused by power competition or initialization conflicts, and improving the reliability and maintainability of the device.

[0053] In one implementation, in this embodiment of the application, the CPU is also used to run or connect to a Web service to visualize the parsed information.

[0054] In this embodiment, the CPU provides Web service visualization functionality as follows: Integrated Web service software runs on the CPU. This software dynamically generates visualization content based on the parsed monitoring information. Users can access the visualization through a browser on any terminal device within the local area network (such as a PC or tablet) by entering the device's IP address. The Web interface comprehensively displays real-time and historical monitoring data using rich graphical elements (such as topology diagrams, dashboards, trend curves, lists, and statistical charts). Specifically, this includes: real-time status of SDH link optical power and bit error rate, configuration and alarm lists for each channel level, distribution of bearer service protocols, historical performance trend analysis, and a retrieval entry point for stored playback data. "Running or connecting to Web services" encompasses two typical deployment modes: one is local device operation, where the Web service is directly deployed on the device's CPU, forming an independent monitoring node ready to use out of the box; the other is connecting to external Web services, where the device acts as a data acquisition and preprocessing unit, pushing parsed information to a more powerful independent server in the network via APIs for centralized display and comprehensive analysis.

[0055] By adopting web services for visualization, a fundamental improvement in operation and maintenance (O&M) has been achieved. It enables remote and cross-platform access to monitoring, eliminating the need for O&M personnel to be physically present at the equipment site or install dedicated client software. They can monitor network status anytime, anywhere via a browser, significantly improving O&M convenience and response speed. Simultaneously, the graphical display makes complex link statuses, alarm correlations, and performance trends intuitive and easy to understand, lowering the barrier to understanding monitoring data and facilitating rapid problem localization. Furthermore, this display method based on standard web technology facilitates integration with existing network management systems or O&M support systems, supporting flexible system expansion and customization to meet the differentiated O&M needs of networks of different sizes. This is a key human-machine interaction element in achieving the goal of "convenient deployment and centralized monitoring" for this device.

[0056] In this embodiment, the device is extremely easy to use and configure. During deployment, it is only necessary to configure a locally accessible IP address for the device through the gigabit management port on its front panel. Once completed, when the device is running a local web service, maintenance personnel can access the web service interface corresponding to the IP address through a browser on any terminal within the same network, thereby enabling remote monitoring and data viewing of the SDH network.

[0057] like Figure 3 As shown in the illustration, this application also provides an SDH data monitoring method, applied to an SDH data monitoring device. The device includes: a field-programmable gate array (FPGA), a central processing unit (CPU), and an interconnection interface connecting the FPGA and the CPU. The method includes: S1. The FPGA receives the SDH data stream from the SDH optical transmission channel, performs hardware-level preprocessing on the SDH data stream to obtain preprocessed data, encapsulates the preprocessed data into structured data packets, and sends them to the CPU through the interconnect interface. S2, the CPU receives structured data packets through the interconnection interface, performs deep parsing on the structured data packets to obtain the parsed information, and then visualizes and / or uploads the parsed information to the monitoring system.

[0058] It should be understood that the use of terms such as "system," "device," "unit," and / or "module" in this application is merely one method of distinguishing different components, elements, parts, sections, or assemblies at different levels. However, if other terms can achieve the same purpose, they may be replaced by other expressions.

[0059] The embodiments in this specification are described in a progressive manner, with each embodiment focusing on the related aspects. For any differences between the embodiments, or for the same or similar parts between the embodiments, please refer to each other.

[0060] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An SDH data monitoring device, characterized in that, Includes: a field-programmable gate array (FPGA), a central processing unit (CPU), and an interconnect interface connecting the FPGA and the CPU; The FPGA is used to receive SDH data streams from the SDH optical transmission channel, perform hardware-level preprocessing on the SDH data streams to obtain preprocessed data, encapsulate the preprocessed data into structured data packets, and send them to the CPU through the interconnect interface. The CPU is used to receive the structured data message through the interconnection interface, perform deep parsing on the structured data message to obtain the parsed information, and visualize and / or upload the parsed information to the monitoring system.

2. The device according to claim 1, characterized in that, The preprocessing includes at least frame positioning, byte alignment, descrambling, and overhead byte extraction.

3. The device according to claim 1 or 2, characterized in that, The parsed information includes at least SDH alarm information, information on each level of channel line, and information on the bearer service protocol.

4. The device according to claim 1, characterized in that, Also includes: Multiple SFP+ optical interfaces; Multiple SFP+ optical interfaces are used to access SDH data streams of different rates; The FPGA is connected to multiple SFP+ optical interfaces for receiving SDH data streams at at least one of the STM-1, STM-4, STM-16, and STM-64 standard rates.

5. The device according to claim 1, 2 or 4, characterized in that, The FPGA is also used to detect alarm and / or bit error information in the SDH data stream in real time during the hardware-level preprocessing process, and report the alarm and / or bit error information to the CPU via the interconnect interface in an interrupt manner.

6. The device according to claim 4, characterized in that, The device connects to the SDH main transmission link via an optical splitter and obtains the SDH data stream in a bypass mirroring manner.

7. The device according to claim 5, characterized in that, The interconnect interface is a communication interface conforming to the PCIe bus standard, used to provide the CPU with a channel to access the internal registers of the FPGA, and to transmit the structured data messages and alarm and / or error information reported by the FPGA.

8. The device according to claim 3, characterized in that, The device also includes a storage unit; The storage unit is connected to the CPU and is used to store the information parsed by the CPU. The stored data supports subsequent playback and analysis.

9. The device according to claim 3, characterized in that, The CPU is also used to run or connect to web services to visualize the parsed information.

10. An SDH data monitoring method, characterized in that, The method is applied to SDH data monitoring equipment, the equipment including: a field-programmable gate array (FPGA), a central processing unit (CPU), and an interconnection interface connecting the FPGA and the CPU, the method including: The FPGA receives SDH data streams from the SDH optical transmission channel, performs hardware-level preprocessing on the SDH data streams to obtain preprocessed data, encapsulates the preprocessed data into structured data packets, and sends them to the CPU through the interconnect interface. The CPU receives the structured data message through the interconnection interface, performs deep parsing on the structured data message to obtain the parsed information, and then visualizes and / or uploads the parsed information to the monitoring system.

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