PMU device time synchronization management method, system and equipment

Abstract

The invention relates to the technical field of clock synchronization, in particular to a PMU device time synchronization management method, system and equipment. The method comprises the following steps: acquiring temperature data and voltage data in the FPGA chip; obtaining a compensated clock period parameter based on the temperature data and the voltage data; adjusting a frequency division coefficient and a duty ratio of a phase-locked loop based on the compensated clock period parameter, and generating a system clock signal after frequency adjustment; based on the code element data stream of the IRIG-B code and the second pulse signal, judging the state of the IRIG-B code time synchronization signal; and switching the clock source of the PMU device based on the real-time state of the PMU device and the state of the IRIG-B code time synchronization signal. According to the invention, temperature and voltage data are obtained based on the FPGA to compensate clock period parameters, a system clock is corrected, the clock is stabilized, and then the IRIG-B code time synchronization signal state is judged, so that the clock source is intelligently switched, and the clock synchronization precision is improved.

Description

Technical Field

[0001] This invention relates to the field of clock synchronization technology, specifically to a time synchronization management method, system, and device for a PMU device. Background Technology

[0002] With the increasing application of power system automation and integrated circuit technology, the accuracy and reliability of time synchronization have become key factors in ensuring stable system operation and achieving efficient control. Many application scenarios, such as real-time monitoring of smart grids and precise operation of industrial control, place extremely stringent requirements on time synchronization.

[0003] However, current technologies suffer from a series of shortcomings in time synchronization that urgently need to be addressed, severely hindering system performance improvement and stable operation. First, the accuracy of time synchronization monitoring is severely insufficient. Existing PMU (Phasor Measurement Unit) time synchronization mechanisms have a time jump detection accuracy of only ±1 second. In actual operating environments, external clocks often experience microsecond-level instantaneous jumps. However, limited by current detection accuracy, the PMU cannot detect these microsecond-level jumps in a timely and accurate manner, leading to phase jumps or erratic sampling values ​​in the device's output data. More seriously, due to insufficient detection accuracy, the corresponding alarm mechanisms cannot be effectively triggered, exposing the lag in this monitoring capability. This clearly demonstrates that existing time management mechanisms have significant technical bottlenecks at the microsecond-level accuracy level, making it difficult to meet the requirements of applications with extremely high time synchronization accuracy, such as real-time monitoring of smart grids and industrial control. Second, there are deficiencies in the external B-code clock quality constraint. Current FPGA (Field Programmable Gate Array)-based time management solutions are insufficient in their accuracy of constraining the quality of external B-code clocks. Meanwhile, this solution exhibits certain limitations in handling complex environments. In complex real-world environments, external clock signals inevitably experience minor fluctuations and are subject to various interferences. Existing FPGA time management solutions cannot effectively address these issues, thus negatively impacting the overall system's time synchronization performance and reducing its stability and reliability. Furthermore, the system clock reliability suffers from significant deficiencies. The existing system design relies excessively on a single clock source and lacks a dynamic switching mechanism for multiple clock sources. Once an external clock interruption occurs, the system cannot achieve seamless transition, directly leading to compromised system synchronization stability. In critical application scenarios, such clock interruptions can have serious consequences, affecting the normal operation of the entire system. Finally, the device status indication is significantly inadequate. During device operation, when faced with various external emergencies, the indications for the device's synchronization, out-of-sync, timekeeping, and data validity / invalidity states lack clarity. Maintenance personnel cannot accurately obtain the detailed process of state transitions from the existing indications, greatly increasing the difficulty for them to perceive and accurately judge the device's operating status in real time, hindering timely problem detection and effective solutions.

[0004] In summary, current time synchronization technologies in power system automation and integrated circuit applications suffer from numerous problems, severely impacting system performance and stability. Therefore, conducting research and improvement on time synchronization technologies is of significant practical importance. Summary of the Invention

[0005] The purpose of this invention is to provide a PMU device time synchronization management method, system, and device to solve at least one of the above-mentioned technical problems.

[0006] The present invention achieves the above objectives through the following technical solutions: A method for time synchronization management of a PMU device includes: Acquire temperature and voltage data from inside the FPGA chip; obtain compensated clock cycle parameters based on the temperature and voltage data; The frequency division coefficient and duty cycle of the phase-locked loop are adjusted based on the compensated clock cycle parameters to generate a frequency-adjusted system clock signal. Based on the code data stream of IRIG-B code and the second pulse signal, determine the state of the IRIG-B code time signal; The clock source of the PMU is switched based on the real-time status of the PMU and the status of the IRIG-B code time synchronization signal.

[0007] A time synchronization management system for a PMU device, the system comprising: An environmental parameter adaptive clock compensation module is used to acquire temperature and voltage data inside the FPGA chip; and to acquire compensated clock cycle parameters based on the temperature and voltage data. The phase-locked loop clock frequency adjustment module is used to adjust the frequency division coefficient and duty cycle of the phase-locked loop based on the compensated clock period parameters, and generate a frequency-adjusted system clock signal. The microsecond-level transition detection module is used to determine the state of the IRIG-B code time signal based on the code data stream of the IRIG-B code and the second pulse signal; The multi-clock source intelligent switching control module is used to switch the clock source of the PMU device based on the real-time status of the PMU device and the status of the IRIG-B code time synchronization signal.

[0008] An electronic device includes a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the PMU device time synchronization management method as described above.

[0009] The beneficial effects of this invention are as follows: This invention features multiple advanced mechanisms and functions, including an environmental parameter adaptive clock compensation module that can collect on-chip temperature and voltage parameters of the FPGA in real time and dynamically adjust the clock frequency to effectively suppress clock jitter caused by environmental factors; a microsecond-level transition detection module that can identify microsecond-level time transitions of ≥10μs in IRIG-B code in real time and generate transition event records with timestamps and transition directions; a multi-clock source intelligent switching control module that ensures a reliable and stable clock output from the system; and a device operation status monitoring and alarm unit that enables precise migration of device status and transition processes. These features significantly improve the absolute accuracy and reliability of the time synchronization system, highly meeting the stringent time synchronization accuracy requirements of scenarios such as power automation control systems and high-speed communication networks. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of a PMU device time synchronization management method according to one embodiment of the present invention; Figure 2 This is a schematic diagram of a PMU device time synchronization management method according to another embodiment of the present invention; Figure 3 This is a schematic diagram illustrating the principle of a clock adaptive compensation mechanism based on FPGA internal environment parameters according to one embodiment of the present invention. Figure 4 This is a schematic diagram illustrating the principle of a microsecond-level transition detection and processing mechanism based on IRIG-B code according to one embodiment of the present invention. Figure 5 This is a schematic diagram of a microsecond-level jump scenario according to one embodiment of the present invention. Figure 1 ; Figure 6 This is a schematic diagram of a microsecond-level jump scenario according to one embodiment of the present invention. Figure 2 ; Figure 7 This is a schematic diagram illustrating the principle of a multi-clock source intelligent switching mechanism according to one embodiment of the present invention; Figure 8 This is a schematic diagram illustrating the effective clock signal identification according to one embodiment of the present invention; Figure 9 This is a schematic diagram of a synchronization state jump from a state of out of synchronization to a state setting according to one embodiment of the present invention. Figure 10 This is a schematic diagram of a step-out state transition to a timekeeping state setting according to one embodiment of the present invention; Figure 11 This is a schematic diagram illustrating the process of switching from synchronization state to timekeeping state and then back to out-of-synchronization state when the time synchronization signal is interrupted, according to one embodiment of the present invention. Figure 12 This is a schematic diagram illustrating the setting of a synchronization state transitioning to a timekeeping state and then back to a lost-synchronization state during a time jump, according to one embodiment of the present invention. Figure 13 This is a schematic diagram illustrating the synchronization state transition to a timekeeping state and then back to the synchronization state setting according to one embodiment of the present invention. Figure 14 This is a schematic diagram of the PMU device time synchronization management system according to one embodiment of the present invention; Figure 15 This is a schematic diagram of the hardware architecture of a PMU device time synchronization management system according to one embodiment of the present invention. Detailed Implementation

[0011] The invention will now be discussed with reference to exemplary embodiments. It should be understood that the described embodiments are merely intended to enable those skilled in the art to better understand and thus implement the invention, and are not intended to imply any limitation on the scope of the invention.

[0012] As used herein, the term "comprising" and its variations are to be interpreted as open-ended terms meaning "including but not limited to". The term "based on" is to be interpreted as "at least partially based on". The terms "one embodiment" and "an embodiment" are to be interpreted as "at least one embodiment".

[0013] Example 1 Figure 1 This is a schematic flowchart of a PMU device time synchronization management method according to one embodiment of the present invention. Figure 1 As shown, according to one embodiment of the present invention, a PMU device time synchronization management method includes the following steps: Step S102: Obtain temperature and voltage data inside the FPGA chip; obtain the compensated clock cycle parameters based on the temperature and voltage data; Step S104: Adjust the frequency division coefficient and duty cycle of the phase-locked loop based on the compensated clock cycle parameters to generate a frequency-adjusted system clock signal. Step S106: Based on the code data stream of the IRIG-B code and the second pulse signal, determine the state of the IRIG-B code time signal; Step S108: Based on the real-time status of the PMU device and the status of the IRIG-B code time synchronization signal, switch the clock source of the PMU device.

[0014] This embodiment proposes a time synchronization management method for a power system PMU device based on FPGA, including the following steps: First, the FPGA's on-chip ADC samples the chip temperature and core voltage at a second-level cycle. The temperature difference ΔT and voltage difference ΔV are obtained through a Q16.8 fixed-point three-stage pipeline operation. These are then substituted into a bivariate coupling formula to calculate the total compensation amount for the clock cycle's two parameters. The compensation result is then limited and an adjustment value is output. Next, this adjustment value is written to the PLL to correct the frequency division coefficient and duty cycle in real time, generating the system clock. This ensures the local clock stability is better than ±0.5ppm, effectively suppressing jitter caused by temperature drift and voltage fluctuations. Following clock stability, IRIG-B code elements are numbered and timestamped. The falling edge of the last "P" code per second is captured to generate a 1PPS signal. The actual arrival time of the PR code is measured using a local counter as a reference to further determine whether there are any transitions in the IRIG-B code time synchronization signal. Furthermore, based on the transition results, B-code interruption or recovery information, and the 3600s maximum allowable deviation threshold, intelligent switching is performed between the external IRIG-B code time, the RTC chip setting time, and the FPGA self-keeping time. Under any operating condition, the time base is guaranteed to be continuous and the data validity flag is clear. This enables the three-state closed-loop migration of out-of-step, keeping time, and synchronization, as well as fault traceability. It is suitable for occasions requiring microsecond-level synchronization, such as smart substations and wide-area power grid protection.

[0015] This invention uses FPGA to acquire temperature and voltage data to compensate for clock cycle parameters, corrects the system clock, and after stabilizing the clock, judges the IRIG-B code time synchronization signal status, and then intelligently switches the clock source. It can ensure continuous time reference and clear data validity mark under various operating conditions, realize the three-state closed-loop migration of out-of-step, time-keeping, and synchronization and fault traceability, and is suitable for microsecond-level synchronization applications.

[0016] According to one embodiment of the present invention, step S102 includes: The actual on-chip temperature data T is obtained based on temperature data and a temperature drift compensation algorithm, and the actual on-chip voltage data is obtained based on voltage data and a voltage fluctuation suppression model. ; The temperature drift compensation algorithm uses the following formula: In the formula, Sensitivity coefficient of temperature sensor (unit: / LSB); This is the sensor offset compensation value, which is determined from the chip datasheet. The on-chip temperature is read by the ADC register data read module.

[0017] The voltage fluctuation suppression model uses the following formula: In the formula, N is the ADC resolution, for example, 12 bits; ; This is the voltage measurement offset calibration value, which is obtained through factory calibration; ADC_VCCAUX is the analog-to-digital conversion value of the voltage read by the ADC register data reading module.

[0018] The total two-parameter compensation amount of the clock cycle is obtained based on the two-parameter compensation formula. : Based on clock cycle value (For example, when the frequency is 50MHz,) Based on 20ns, the compensated clock period is then calculated: in, This represents the clock cycle parameter after compensation; Indicates the reference value of the clock cycle; This represents the total compensation amount for the two parameters of the clock cycle; This represents the difference between the actual on-chip temperature and the reference temperature. , Indicates the reference temperature; Indicates the temperature compensation coefficient; This represents the difference between the actual on-chip voltage and the reference voltage. , Indicates the reference voltage; This represents the voltage compensation coefficient.

[0019] Preferably, the total compensation amount of the two clock cycle parameters is set to not exceed the preset compensation cycle limit (e.g., ±2ns); the clock cycle reference value is adaptively adjusted using the Q16.8 fixed-point format.

[0020] In this embodiment, the FPGA activates its on-chip 12-bit ADC at a 1-second cycle to acquire the temperature channel ADC_TEMP and the voltage channel ADC_VCCAUX. The actual on-chip temperature data T and voltage data are calculated using a temperature drift compensation algorithm and a voltage fluctuation suppression model. Subsequently, the difference between the reference temperature of 25°C and the reference voltage of 3.3V is taken to obtain ΔT and ΔV. These are then substituted into the two-parameter coupling formula to obtain the total compensation amount of the two parameters of the clock cycle. The result is then subjected to a ±2ns hard limit to prevent over-adjustment caused by extreme environmental disturbances. The entire operation is completed in a three-stage pipeline using the Q16.8 fixed-point format. The reference difference, coefficient product, and cumulative limit each occupy one clock cycle, and a compensation value within the range of 20ns ±2ns can be output in a single cycle. Ultimately, a stability of ±0.5ppm is achieved for the 50MHz system clock, providing a highly stable time base for subsequent transition detection and three-state switching.

[0021] This invention accurately acquires on-chip temperature and pressure data through temperature drift compensation and voltage fluctuation suppression. After dual-parameter coupling and amplitude limiting processing, the compensation value is output. Fixed-point pipelined operation is used to achieve a 50MHz system clock stability of ±0.5ppm, providing a highly stable time base for subsequent operations.

[0022] According to one embodiment of the present invention, step S106 includes: Step S1061: Assign a unique number to each IRIG-B code symbol and add a timestamp, capture the edge of the last symbol within one second, and generate a PPS signal with a duration equal to the symbol width. Step S1062: Using the second edge of the IRIG-B code as the counting reference, compare the counted value with a preset threshold to determine whether the IRIG-B code is reliable and synchronized. Step S1063: Detect time jumps of less than a second, including two types of scenarios: jumps of more than 10ms and jumps of less than 10ms; determine whether a jump exists, and if so, generate a jump event record and alarm signal accompanied by a microsecond-level timestamp.

[0023] Preferably, determining whether a transition exists includes: For transition scenarios with a magnitude of more than 10ms, count whether the number of symbols between adjacent "P" codes reaches the first threshold; if not, it is determined that a transition exists. For scenarios involving jumps on the order of less than 10ms, determine whether the B-code second-cycle count result exceeds a preset second quantity threshold; if it does, determine that a jump has occurred.

[0024] In this embodiment, step S106 is further defined as follows: First, the input IRIG-B code stream is parsed, a unique sequence number is assigned to each code element, and a 20ns precision timestamp is added. The falling edge of the last "P" code per second is captured, and a local 1PPS pulse with a width of 10ms is generated. Then, using this edge as a gate, the local counter is cleared and starts accumulating. If the counter value falls within ±10µs when the next PR code arrives, the B code is determined to be reliable and synchronized; otherwise, it is marked as out of sync. For transitions less than a second, a dual-track detection is used: for transitions greater than 10ms, the number of code elements between adjacent "P" codes is counted—standard IRIG-B should have 8 or 9. If the count is < 8 (first quantity threshold), a large transition is determined. For transitions less than 10ms, the result of the second-cycle counter is compared. If the deviation from the theoretical value by 1s exceeds the second quantity threshold, it is considered a microsecond-level transition. When either condition is triggered, the current counter value is immediately frozen and converted into a microsecond-level timestamp, the transition direction, amplitude, and code element number are recorded, and an alarm signal is output simultaneously to provide accurate event basis for subsequent three-state switching.

[0025] This invention uses dual-track detection to accurately identify sub-second jumps by parsing, stamping, generating pulses, and comparing multi-dimensional counts of IRIG-B symbols, recording events and issuing alarms, thus providing a precise basis for subsequent three-state switching.

[0026] According to one embodiment of the present invention, the states of the PMU device include: synchronization state, timekeeping state, and out-of-sync state; The states of the IRIG-B code time signal include: normal, interrupted, and transition. The switching logic for switching the clock source of the PMU device includes: In forced follow mode, the time is based on the RTC chip. When the IRIG-B code time synchronization signal is normal, the IRIG-B code time is used; When the IRIG-B code time synchronization signal is interrupted or changes, the FPGA self-keeping time is used; After the IRIG-B code interruption is recovered, if the time deviation from the self-synchronous time exceeds the first time threshold, the self-synchronous time output is maintained; otherwise, if the IRIG-B code signal is valid for the first consecutive time period, the IRIG-B code time is switched back.

[0027] Preferably, step S108 includes: When the PMU device successfully locks onto a valid external IRIG-B code time synchronization signal, it achieves real-time alignment between the local clock and the external time reference, and enters the synchronization state. When the device detects an interruption or jump in the external time synchronization signal in the synchronization state, it starts the local high-stability clock source to maintain the time counting and enters the timekeeping state. The device enters a state of out-of-synchronization when any of the following conditions exist: there is no external time synchronization signal after the device is powered on; the device continuously receives valid clock signals with a time difference greater than the preset time threshold during the timekeeping process, reaching the third quantity threshold; or the timekeeping process exceeds 1 hour.

[0028] In this embodiment, step S108 constructs a three-state machine of "synchronization-timekeeping-out-of-synchronization" and links it with the three signal states of "normal / interruption / transition" of the IRIG-B code: In forced follow mode, the RTC chip time is directly selected; when the B code is normal and valid for m consecutive seconds (first time interval), the device enters the synchronization state, the local clock is aligned with the external reference cycle by cycle, and PMU_STATUS=11 is output. Once an interruption or transition of the B code is detected, it immediately switches to the timekeeping state. The FPGA relies on a temperature- and voltage-compensated 50MHz high-stability clock to maintain a self-sustaining count and outputs PMU_STATUS=01 to ensure that the timestamp of the sampled data is not interrupted. If the B code recovers during the timekeeping period, the self-timekeeping is compared with the integer second count of the B code: if the difference exceeds 3600s, timekeeping is maintained to prevent large-span missynchronization; if the difference is within 3600s and valid for m consecutive seconds, the device re-enters the synchronization state. If the timekeeping exceeds 1 hour, or the time difference between n consecutive valid B codes and the local time is still >10µs, then it will revert to the out-of-synchronization state (PMU_STATUS=00), disconnect the invalid external reference, and wait for re-acquisition, thus achieving seamless and traceable switching of the clock source under any operating condition.

[0029] This invention constructs a three-state machine of "synchronization-timekeeping-out-of-synchronization" and links it with the three signal states of IRIG-B code. Through multiple clock source switching logics and condition judgments, it achieves seamless and traceable switching of clock sources under any operating condition, ensuring that the timestamp of the sampled data is not interrupted.

[0030] According to one embodiment of the present invention, the device status flag PMU_STATUS is used to represent the signal synchronization status and data availability, specifically, In synchronization mode, PMU_STATUS is "11", indicating that "signals are synchronized and data is available"; When out of sync, PMU_STATUS is "00", indicating "signals are not synchronized and data is unavailable"; In timekeeping mode, PMU_STATUS is "01", indicating that "signals are not synchronized, but data is available".

[0031] In this implementation, the 2-bit register PMU_STATUS inside the FPGA maps the tri-state machine results in real time: it is set to "11" only when IRIG-B is successfully locked and there is no transition for m consecutive seconds, broadcasting "signal synchronized, data available" to the external sampling core and merging unit. At this time, the error between the local clock and the external reference is ≤10µs, and the sampled data can directly participate in wide-area phasor calculation. If the timekeeping is interrupted due to B code or transition, it is set to "01". Although the high-stability clock after compensation is still used to maintain the counting and the data continues to be valid, it has declared "signal not synchronized" for the background to make a "degraded use" prompt. Once the timekeeping exceeds 1 hour or there are n consecutive large deviations, it is set to "00" and the data valid bits are pulled low to prevent the phasor data of the out-of-synchronization period from being misused by the protection algorithm, realizing single-line output of status and data reliability without additional handshake.

[0032] This invention maps the results of the tri-state machine in real time through the FPGA's internal 2-bit register PMU_STATUS, clearly representing the signal synchronization status and data availability with different status values, preventing data misuse, and realizing single-line output of status and data reliability.

[0033] Example 2 Figure 2 This is a schematic diagram of a PMU device time synchronization management method according to another embodiment of the present invention. Figure 2 As shown, according to one embodiment of the present invention, a PMU device time synchronization management method includes the following steps: Step S201: Real-time acquisition of FPGA internal temperature and voltage data; generation of dynamic adjustment parameters using a temperature drift compensation algorithm and a voltage fluctuation suppression model; adjustment of the phase-locked loop's frequency division coefficient and duty cycle to suppress clock jitter caused by environmental factors; specifically, Step S2011: Read and cache the original values ​​of temperature and voltage after analog-to-digital conversion; Step S2012: Based on the temperature drift compensation algorithm and the voltage fluctuation suppression model, the input environmental parameters are coupled and calculated to generate clock cycle adjustment parameters, and the clock cycle compensation amount is limited to a preset range according to the dynamic amplitude limiting fault tolerance mechanism. A three-stage pipeline architecture is adopted, which sequentially performs the benchmark difference calculation, coefficient multiplication operation and total compensation accumulation, and realizes efficient integer operation through Q16.8 fixed-point number format.

[0034] Step S2013: After receiving the adjustment parameters, dynamically adjust the frequency division coefficient and duty cycle of the internal phase-locked loop to achieve adaptive compensation of the clock signal frequency.

[0035] Step S202: Based on the code data stream of IRIG-B code and the pulse-per-second (PPS) signal, capture the microsecond-level transitions (≥10μs) of the time signal in real time, and generate transition event records and alarm signals with microsecond-level timestamps and transition directions; Microsecond-level transition detection technology uses high-precision timestamp marking technology and transition feature capture algorithms to provide real-time feedback on key parameters such as the time, amplitude, and direction of transitions, and generates transition event records and alarm signals accompanied by microsecond-level timestamps; specifically, Step S2021: Assign a unique number to each symbol and add a timestamp, capture the edge of the last symbol within one second, and generate a PPS signal with a duration equal to the symbol width. Step S2022: Using the second edge of the B code as the counting benchmark, compare the counted value with a preset threshold to determine whether the B code is reliable and synchronized. Step S2023: Detect time jumps of less than a second, including two types of scenarios: jumps of more than 10ms and jumps of less than 10ms. Among them, the magnitude jump of more than 10ms is determined by counting the number of code elements between adjacent "P" codes and combining the code element sequence number and timestamp information; the magnitude jump of less than 10ms is determined by comparing the B code second cycle count result with the preset threshold.

[0036] Step S203 integrates the external IRIG-B code time, RTC chip setting time, and FPGA self-keeping time, dynamically switching according to the clock source reliability and device operating status to ensure continuous and stable output of the system clock signal; the specific switching logic is as follows: In forced follow mode, the RTC chip time is used preferentially. When the IRIG-B code signal is normal, an external time reference is used directly. When the IRIG-B code is interrupted or transitions, switch to the FPGA self-keeping time. After B-code interruption recovery, if the time deviation from the self-timer exceeds 3600 seconds, the self-timer output will be maintained; otherwise, it will switch back to the B-code reference after confirmation by a valid signal for m seconds.

[0037] Step S204: Construct a three-state transition model of "out of step - keeping time - synchronization", and output device status flags and data validity indications in real time through clock deviation analysis and threshold discrimination; The device states include: synchronization state, timekeeping state, and out-of-synchronization state. In synchronization mode, the device enters the state when it successfully locks onto an external valid IRIG-B code time synchronization signal, thereby achieving real-time alignment between the local clock and the external time reference. In timekeeping mode, when the device detects an abnormal or interrupted external time synchronization signal while in synchronization mode, it enters the local high-stability clock source to maintain time counting. In the out-of-synchronization state, the device enters the state when there is no external time synchronization signal after power-on, or when n valid clock signals with a time difference greater than the preset threshold are received continuously during the timekeeping process, or when the timekeeping process exceeds 1 hour.

[0038] The 2-bit device status flag PMU_STATUS is used to indicate signal synchronization status and data availability. Specifically, In synchronization mode, PMU_STATUS is "11", indicating that "signals are synchronized and data is available"; When out of sync, PMU_STATUS is "00", indicating "signals are not synchronized and data is unavailable"; In timekeeping mode, PMU_STATUS is "01", indicating that "signals are not synchronized, but data is available".

[0039] This embodiment proposes a time synchronization management method for PMU devices. By real-time acquisition of raw data from the FPGA's internal temperature sensor and power monitoring unit, a multivariable coupled compensation mechanism is constructed, combining a temperature drift compensation algorithm and a voltage fluctuation suppression model. This mechanism dynamically adjusts the duty cycle and frequency division coefficient of the clock signal. This mechanism effectively compensates for clock jitter and phase shifts caused by temperature drift, power supply fluctuations, and process deviations, improving the frequency stability of the compensated clock signal and enhancing the stability and reliability of the clock source in complex environments. Through microsecond-level resolution IRIG-B code transition detection, the shortcomings of conventional second-level transition detection techniques are overcome. Real-time capture of microsecond-level time transitions in the B-code signal is achieved using high-precision timestamp marking technology and transition feature capture algorithms. Key parameters such as the time, amplitude, and direction of the transition are fed back in real time, and transition event records and alarm signals accompanied by microsecond-level timestamps are generated.

[0040] A multi-clock source fusion intelligent switching mechanism is adopted, integrating various heterogeneous clock sources such as external IRIG-B code time, RTC chip setting time, and FPGA-based self-keeping time calculation time. Based on the characteristics and reliability of different clock sources, and combined with the device's operating status, an intelligent evaluation and dynamic switching strategy for different clock sources is implemented to ensure that the system continuously acquires stable and reliable clock signals under complex operating conditions. A high-sensitivity real-time device status detection mechanism compares the external clock source time with the device's local time in real time, constructing a multi-dimensional status monitoring model covering the three states of "out of step - keeping time - synchronization". Based on clock signal deviation analysis, status threshold discrimination, and event sequence logic, it achieves accurate identification and dynamic tracking of the device's operating status, and outputs "clock synchronized" and "data available" status flags, providing timely and reliable status information for system control and data processing.

[0041] This invention achieves a comprehensive improvement in the performance of time synchronization systems, effectively suppressing clock jitter caused by environmental factors and significantly enhancing the stability and reliability of the clock source in complex environments. It accurately identifies microsecond-level time jumps, providing more detailed time monitoring capabilities for high-precision applications; ensures the system continuously outputs stable and reliable clock signals under complex operating conditions, avoiding time synchronization interruptions; and enables precise identification and dynamic tracking of device operating status, providing a reliable basis for system control and data processing. This invention significantly improves the absolute accuracy and reliability of time synchronization systems, fully meeting the application requirements of power automation control systems and high-speed communication networks.

[0042] Example 3 According to one embodiment of the present invention, a time synchronization management method for a PMU device adopts a clock adaptive compensation mechanism based on FPGA internal environmental parameters, a microsecond-level transition detection and processing mechanism based on IRIG-B code, and a multi-clock source intelligent switching mechanism. Figure 3 This is a schematic diagram illustrating the principle of a clock adaptive compensation mechanism based on FPGA internal environment parameters according to one embodiment of the present invention. Figure 3 As shown, the clock adaptive compensation mechanism based on the internal environmental parameters of the FPGA includes: the Ziguang analog-to-digital converter module GTP_ADC_E1, the ADC register data reading module, the dual-parameter compensation dynamic period calculation module, and the GTP_PLL clock frequency adjustment module. The analog-to-digital converter (ADC) module and the ADC register data reading module interact with each other. The ADC register data reading module is responsible for reading and buffering the environmental parameter data (raw temperature / voltage values) after analog-to-digital conversion, and inputting it to the dual-parameter compensation dynamic cycle calculation module through a parallel interface. The dual-parameter compensation dynamic cycle calculation module performs coupled calculations on the input environmental parameters based on a temperature drift compensation algorithm and a voltage fluctuation suppression model to generate clock cycle adjustment parameters. After receiving the adjustment parameters, the GTP_PLL clock frequency adjustment module dynamically adjusts the frequency division coefficient and duty cycle of the internal phase-locked loop to achieve adaptive compensation of the clock signal frequency. This mechanism, through the cascaded cooperation of the four modules, constructs a closed-loop feedback chain of "environmental parameter acquisition - data processing - compensation calculation - clock adjustment," ensuring that the FPGA's internal clock source maintains a stable and reliable output when parameters such as temperature and voltage change.

[0043] In this embodiment, the Unisoc Logos series FPGA products are used to provide analog-to-digital converter (GTP_ADC_E1) resources. By configuring the parameters in the parameter list of this module, precise control of the ADC working mode, reference source setting, range and input mode can be achieved.

[0044] The ADC register data read module generates an operation enable signal DEN, a data input signal DI, a read / write enable signal DWE, and a register address DADDR every second using a state machine and sends them to GTP_ADC_E1. Based on these signals, the module sequentially performs read and write operations on the status register of GTP_ADC_E1, thereby reading the on-chip temperature ADC_TEMP and the analog-to-digital conversion value of voltage ADC_VCCAUX.

[0045] The dual-parameter compensation dynamic cycle calculation module converts the acquired analog-to-digital conversion values ​​of the FPGA's internal temperature and voltage into actual temperature and voltage values ​​according to the conversion formula, thereby obtaining the actual on-chip temperature (T) and voltage (T). ) data; among which, The temperature conversion formula is as follows: In the formula, Sensitivity coefficient of temperature sensor (unit: / LSB); This is the sensor offset compensation value, which is determined from the chip datasheet. The on-chip temperature is read by the ADC register data read module.

[0046] The voltage conversion formula is as follows: In the formula, N is the ADC resolution, for example, 12 bits; Reference voltage (V); This is the voltage measurement offset calibration value, which is obtained through factory calibration; ADC_VCCAUX is the analog-to-digital conversion value of the voltage read by the ADC register data reading module.

[0047] Based on the conversion result value, combined with the temperature difference (Reference temperature, e.g., 25°C) and voltage difference (Reference voltage, e.g., 3.3V) The two-parameter compensation formula is constructed as follows: In the formula, This represents the total compensation amount for the two parameters of the clock cycle. This is the temperature compensation coefficient, and its value is determined by the FPGA process characteristics. This is the voltage compensation coefficient, which is obtained through actual measurement and calibration.

[0048] Based on clock cycle value (For example, when the frequency is 50MHz,) Based on a timeframe of 20ns, a compensation period limit (e.g., ±2ns) is set, and then the compensated clock period is calculated: Finally, the compensated clock cycle parameters are received via the phase-locked loop (PLL) inside the FPGA as control input to generate the frequency-adjusted system clock signal. .

[0049] In this embodiment, a multi-dimensional closed-loop sensing compensation system is employed. By integrating temperature / voltage sensors and a clock generation circuit to construct a closed-loop control architecture, it collects FPGA operating environment parameters (temperature / voltage) in real time and dynamically adjusts the clock signal based on the sensing data. This effectively suppresses the interference of environmental factors (such as temperature drift and voltage fluctuations) on clock accuracy, significantly improving the anti-environment interference capability compared to traditional open-loop systems. The dual-parameter decoupled compensation algorithm innovatively adopts a temperature / voltage dual-coefficient independent compensation model, quantifying the influence of temperature difference (∆T) and voltage difference (∆V) on the clock frequency (temperature compensation coefficient). / Voltage compensation coefficient This method achieves precise compensation through dual-parameter decoupled calculation, solving the problem of insufficient environmental adaptability in existing single-parameter compensation schemes and improving compensation accuracy to ±0.5ppm. By adopting a three-stage pipelined accelerated processing architecture, a three-stage hardware pipeline (baseline difference calculation → coefficient multiplication operation → total compensation accumulation) is designed in the compensation value calculation stage. Parallel processing reduces the single-cycle calculation latency to 1 / 3, improving processing efficiency by 3 times compared to traditional serial calculation schemes, meeting the nanosecond-level real-time requirements of high-precision time synchronization. A dynamic limiting fault tolerance mechanism is set, with a ±2ns dynamic limiting window for compensation. A hardware comparator monitors the compensation output in real time, automatically filtering over-compensation or under-compensation caused by abnormal environmental disturbances, ensuring that the clock cycle adjustment is within a safe range and avoiding the risk of system timing disorders due to extreme environmental parameters. By employing high-efficiency fixed-point arithmetic technology, and addressing the hardware implementation bottleneck of floating-point arithmetic, the Q16.8 fixed-point format is used to adaptively adjust the reference clock cycle. Integerization is used to reduce the computational latency by 70% while ensuring computational accuracy (error < 0.01%), significantly improving FPGA resource utilization efficiency and system real-time response capability.

[0050] Figure 4 This is a schematic diagram illustrating the principle of a microsecond-level transition detection and processing mechanism based on IRIG-B codes according to one embodiment of the present invention. Figure 4 As shown, according to one embodiment of the present invention, a microsecond-level time jump detection and processing mechanism based on IRIG-B code achieves high-precision time jump detection by refining the 1PPS signal; including: a B code signal processing module, a second synchronization state judgment module, a jump detection module, and a local second period dynamic adjustment module. The B-code signal processing module assigns a unique number to each code element of the B-code according to the code element information of the B-code and adds a timestamp. During the processing, it accurately captures the edge of the last code element within each second, and then generates a PPS signal with a duration equal to the code element width. This signal will be used as the reference trigger signal for time detection.

[0051] The second synchronization status judgment module conducts counting work with the second edge of the B-code as the counting reference. It compares the counted value with a pre-set threshold. If the counting result within one second is within the accuracy requirement range (for example, 1s ± 10μs), then this second is determined to be in a qualified state. If this situation that meets the accuracy requirement continues continuously for m seconds, it is considered that the B-code is reliable and synchronization has been achieved.

[0052] The jump detection module divides the sub-second time jump detection into two types of scenarios: (1) The first type is jumps in the order of magnitude above 10ms, which are manifested as the complete B-code of the next second arriving in advance when the code elements of the current second have not been fully loaded. This advance may occur at any moment in the previous second.

[0053] Figure 5 Schematic diagram of the microsecond-level jump scenario for an embodiment of the present invention Figure 1 , such as Figure 5 shown. Taking the positive jump in the order of magnitude above 10ms as an example, when jumping from 15.83s to 16.00s, there should be 9 code elements (0 or 1) between normal adjacent "P" codes, but the jump results in only 3 code elements remaining. In addition, the "PR" code of the next second may be continued after the middle "P" code of the previous second, or directly replace a certain middle "P" code of the previous second. According to the standard IRIG-B code element definition, except for the starting "P0" and "PR" code elements, the number of code elements between the remaining adjacent "P" codes should be 8 or 9, that is, 8 when the code element interval is in the range of 10 - 100ms, and 9 in other cases.

[0054] By counting the number of code elements between adjacent "P" codes and combining the code element sequence number and timestamp information, various types of jump situations are discriminated. Once a jump is detected, the data invalid flag is immediately raised, and a microsecond-level time jump indication signal is output.

[0055] (2) The other type is the jump scenario in the order of magnitude below 10ms.

[0056] Figure 6 Schematic diagram of the microsecond-level jump scenario for an embodiment of the present invention Figure 2 , such as Figure 6As shown, taking a positive transition on the order of less than 10ms as an example, if the actual arrival time of the "PR" code in the next second deviates from the theoretical time by more than a preset threshold (e.g., 10μs) after the falling edge of the last "P" code in the previous second, the code interval does not exceed the 10ms level, making it impossible to detect the transition by counting the number of code elements between adjacent "P" codes. To address this, the second-cycle count result of the B code output by the second synchronization state judgment module is used for judgment. That is, when the counter value at the second edge trigger time exceeds the preset precision threshold, a microsecond-level time transition can be determined, and a time transition flag signal is generated synchronously.

[0057] By adding a high-precision microsecond-level timestamp generation mechanism, when a time jump is detected, the system can capture and record the precise time node of the jump in real time (with a resolution of microseconds). Specifically, the system uses a built-in high-precision counter to sample the clock cycle at high frequency. At the moment the jump detection module triggers the jump flag, the current counter value is frozen and converted into a microsecond-level timestamp. This timestamp accurately locates the specific microsecond moment within the second when the jump occurred.

[0058] In terms of transition type identification, the system identifies positive and negative transitions by comparing the logical relationship between the current timestamp and the theoretical timestamp of the next second: if the actual arrival time of the next second is earlier than the theoretical time corresponding to the current timestamp, it is determined to be a positive transition (e.g., a sudden change from 15.83s to 16.00s); if the next second is later than the theoretical time, it is determined to be a negative transition (e.g., a sudden change from 16.83s to 16.00s). This mechanism achieves quantitative judgment of the transition direction through precise comparison of microsecond-level timestamps.

[0059] The local second cycle dynamic adjustment module integrates a variable period counter for local second cycle counting management. The local real-time second counting cycle employs a time-holding and deviation compensation engine to implement timing compensation algorithms and dynamic cycle adjustment. Specifically, the time-holding state machine periodically collects external clock deviations during the deviation accumulation phase and accumulates them to a 64-sampling window. During the dynamic filtering calculation phase, a sliding weighted average algorithm is used to filter the accumulated deviations and output a stable deviation value. Then, the cycle adjustment state machine dynamically corrects the local clock cycle based on the synchronization point trigger signal and the real-time deviation, and generates a disturbance-resistant local second cycle value through an exponential weighting algorithm and normalization processing. Based on the obtained local second cycle value, a dual-threshold window detection method is used to determine the time domain range of the local real-time second count value. A range-exceeding flag signal indicates whether the local real-time second count value exceeds a preset deviation window, and the synchronization point is captured based on the B-code synchronization status flag of the second synchronization status judgment module. When the external B code is continuous and stable, the local cycle completes m-level synchronization cycle locking with it and issues a synchronization lock flag. If the external B code undergoes a microsecond-level jump, even if the B code returns to normal after the jump, as long as the time deviation with the local device is greater than the preset value (such as ±10μs), the local cycle cannot complete synchronization locking with the external B code.

[0060] Figure 7 This is a schematic diagram illustrating the principle of a multi-clock source intelligent switching mechanism according to one embodiment of the present invention. Figure 7 As shown, the multi-clock source intelligent switching mechanism realizes the state machine transition from out-of-synchronization to timekeeping; its state transition mechanisms include: Initial state: After the device is initially reset, it is in a state of being out of step by default, and no external time reference synchronization is established at this time.

[0061] Synchronization state trigger condition: When the device successfully locks onto an external valid IRIG-B code pair time signal (i.e., continuously receives m complete code symbol sequences that conform to the protocol specifications), it immediately switches to the synchronization state to achieve real-time alignment between the local clock and the external time reference.

[0062] Timekeeping state triggering conditions: If the device detects an abnormality or interruption in the external time synchronization signal (no valid code element is received after a preset timeout period) while in synchronization state, it will start the local high-stability clock source to maintain the time count and enter the timekeeping state to ensure time continuity for a short period of time.

[0063] Out-of-step return condition: The device will forcibly return to the out-of-step state when any of the following conditions are met. (1) No valid external time synchronization signal was detected after power-on initialization; (2) During the timekeeping process, n abnormal clock signals with a time difference exceeding a preset threshold (e.g., 10μs) are continuously received (indicating that there is still an unacceptable synchronization deviation after the external signal is restored). (3) The timekeeping duration exceeds 1 hour (avoid long-term reliance on low-precision local clocks, which may lead to excessive cumulative error).

[0064] By strictly following the above state transition logic to realize state machine jumps, a closed-loop real-time device state monitoring mechanism is constructed to ensure reliable maintenance of time synchronization performance in complex electromagnetic environments.

[0065] Figure 8 This is a schematic diagram illustrating the effective clock signal identification according to one embodiment of the present invention; Figure 9 This is a schematic diagram illustrating the synchronization state setting transition from a state of being out of sync to a state according to one embodiment of the present invention. Figure 8-9 As shown, when the device initially has no external time synchronization signal or is out of sync due to signal interruption, if it continuously receives m error-free and complete valid IRIG-B code clock signals (initial synchronization scenario), or after the external signal interruption is recovered, the time difference between the signal and the device clock is ≤3600s and the subsequent m consecutive signals are valid (interruption recovery scenario), or after a jump of more than a second (a sudden change in year, month, day, hour, minute, second), the time difference between the external signal and the device clock is ≤10μs and the subsequent m consecutive signals are valid (second-level jump recovery scenario), or after detecting a microsecond-level jump of 10μs to 1s and entering the out-of-sync state, the timestamps of the m consecutive signals are compared with the local counter cycle by cycle, and the average deviation is calculated to be <10μs and the signal period is stable (microsecond-level jump processing scenario), the external time synchronization signal is determined to be reliable. Through the linkage of signal continuity verification, time deviation criterion, and dynamic filtering algorithm, the state machine is triggered to switch to the synchronization state, realizing the reliable transition of the device from out of sync to synchronization.

[0066] Figure 10 This is a schematic diagram illustrating the step-by-step transition from a synchronization failure state to a timekeeping state setting according to one embodiment of the present invention. Figure 10 As shown, when the device is out of sync and the external time synchronization signal is interrupted and then restored, if the time difference between the received external time synchronization signal and the local device clock exceeds a reliable threshold (e.g., 3600s), the system determines that the external signal cannot be directly used as a synchronization reference. At this time, it enters a transition verification phase. That is, after continuously detecting m valid IRIG-B code clock signals (containing complete symbol sequences and second pulse information) that have been verified, the device does not directly switch to the synchronization state, but instead uses a local high-stability clock source to maintain time counting while continuously monitoring the stability of the external signal, thus entering a timekeeping state. This mechanism, through the combination of time deviation threshold judgment and signal validity verification, avoids synchronization disorder caused by large time jumps.

[0067] Figure 11 This is a schematic diagram illustrating the process of switching from synchronization state to timekeeping state and then back to out-of-synchronization state when the time synchronization signal is interrupted, according to one embodiment of the present invention. Figure 12This is a schematic diagram illustrating the setting of a synchronization state transitioning to a timekeeping state and then back to a lost-synchronization state during a time jump, according to one embodiment of the present invention. Figure 11-12 As shown, when the device is in synchronization mode, if a sudden interruption or abnormal signal jump (including second-level and microsecond-level abrupt changes) is detected in the external time synchronization signal, it immediately enters timekeeping mode to ensure time continuity. During timekeeping, if the timekeeping duration exceeds 1 hour, or if the time difference between the device clock and m consecutive valid clock signals after the external signal is restored is greater than a preset threshold (e.g., 10μs, indicating that the external signal is abnormal and cannot pass timekeeping calibration), the external time reference is determined to be invalid, triggering the state machine to switch to out-of-synchronization state. This mechanism, through the three-level linkage of signal interruption detection, timekeeping time threshold, and deviation criterion, achieves robust state management of the time synchronization system under complex operating conditions, ensuring reliable exit from timekeeping mode and entry into out-of-synchronization state to wait for resynchronization when the signal is abnormal.

[0068] Figure 13 This is a schematic diagram illustrating a synchronization state transition to a timekeeping state and then back to the synchronization state setting according to one embodiment of the present invention. Figure 13 As shown, when the device is in timekeeping mode, if the time difference between the external time synchronization signal and the local device clock is less than a preset threshold (e.g., 10µs), it is determined that the external time reference has been successfully restored. The state machine is then immediately triggered to switch to synchronization mode, terminating the local clock maintenance mode and switching to real-time tracking of the external signal for time synchronization. This mechanism, through the combination of high-precision time deviation detection and signal validity verification, ensures rapid and reliable reconstruction of synchronization when the external signal is restored, avoiding accumulated errors caused by long-term operation in timekeeping mode.

[0069] A 2-bit device status flag, PMU_STATUS, is used to indicate signal synchronization status and data availability. When the state machine is out of sync, the device status flag PMU_STATUS is set to "00", and the corresponding status is defined as "signals are not synchronized and data is unavailable". At this time, the external time synchronization signal is invalid and the local clock has not entered the timekeeping mode. The output data is judged to be unreliable due to the lack of a valid time base. When the state machine is in the timekeeping state, the device status flag PMU_STATUS is set to "01", which corresponds to the state definition of "signal not synchronized, data available". This indicates that the external signal is abnormal, but the local high-stability clock has been enabled to maintain the time count, and the data output continues to be valid based on the timekeeping timestamp. When the state machine is in the synchronization state, the device status flag PMU_STATUS is set to "11", which corresponds to the state definition of "signal synchronized, data available". At this time, the external IRIG-B code signal is stably locked, the local clock is accurately synchronized with the external reference, and the output data has complete time validity.

[0070] The clock synchronization management method proposed in this invention is particularly suitable for power systems with high precision requirements (such as PMUs and merging units), but can also be extended to other relay protection devices, communication base stations, distributed sensor networks, and other fields. The FPGA chip used in the embodiments is only a preferred implementation method, and those skilled in the art can replace it with other types of logic devices according to actual needs.

[0071] Example 4 Figure 14 This is a schematic diagram of the PMU device time synchronization management system according to one embodiment of the present invention. Figure 14 As shown, according to one embodiment of the present invention, a PMU device time synchronization management system includes: An environmental parameter adaptive clock compensation module is used to acquire temperature and voltage data inside the FPGA chip; and to obtain the compensated clock cycle parameters based on the temperature and voltage data. The phase-locked loop clock frequency adjustment module is used to adjust the frequency division coefficient and duty cycle of the phase-locked loop based on the compensated clock period parameters, and generate a frequency-adjusted system clock signal. The microsecond-level transition detection module is used to determine the state of the IRIG-B code time signal based on the code data stream of the IRIG-B code and the second pulse signal; The multi-clock source intelligent switching control module is used to switch the clock source of the PMU device based on the real-time status of the PMU device and the status of the IRIG-B code time synchronization signal.

[0072] This embodiment proposes a PMU device time synchronization management system, using an FPGA as the sole carrier. Multiple hardware modules collaboratively complete the entire "sensing-correction-detection-decision" chain: An environmental parameter adaptive clock compensation module acquires temperature and voltage data at the second level via an on-chip ADC, and calculates a ±2ns-limited periodic compensation amount through a Q16.8 fixed-point three-stage pipeline; a phase-locked loop clock frequency adjustment module writes the compensation amount into the PLL in real time, outputting a 50MHz high-stability system clock to provide a time base with jitter below ±0.5ppm for subsequent logic; a microsecond-level transition detection module, driven by this clock, stamps the IRIG-B symbol numbers, using a dual threshold of "P" code interval counting and second edge counting to determine transitions ≥10µs, and generates a directional timestamp record; a multi-clock source intelligent switching control module seamlessly switches between RTC, IRIG-B, and FPGA self-timers based on transition, interrupt, or recovery signals, combined with a 3600s maximum deviation threshold and a continuous m-second validity rule, and outputs a 2-bit PMU_STATUS flag and a 1 PPS pulses enable microsecond-level synchronous management that allows for observable status, degradeable data, and traceable faults.

[0073] The PMU device time synchronization management system of the present invention uses FPGA as a carrier and completes the whole-link operation through multi-module collaboration to achieve microsecond-level synchronization management, and achieve the effects of observable status, degradeable data, and traceable faults.

[0074] Example 5 Figure 15 This is a schematic diagram of the hardware architecture of a PMU device time synchronization management system according to one embodiment of the present invention. Figure 15 As shown, according to one embodiment of the present invention, a PMU device time synchronization management system uses the Unisoc Logos series FPGA as the core processing chip. This series of devices, with its abundant logic resources and high-performance phase-locked loop (PLL) characteristics, provides a solid hardware foundation for the development of a high-precision time management module. The time synchronization management system includes: an IRIG-B time synchronization device, an environmental parameter clock source adaptive compensation module, a B-code parsing module, a microsecond-level transition detection module, a time management module, a self-timekeeping time calculation module, a staggered-synchronized-timekeeping state machine transition module, and a signal output module; wherein, The IRIG-B time synchronization device is used as a system time reference input unit, outputting IRIG-B time code signals to the B code parsing module to provide the system with a high-precision external standard time reference.

[0075] The environmental parameter clock source adaptive compensation module is used to: generate and provide the system clock signal T_SYS; sense changes in environmental parameters (such as temperature, voltage, etc.) in real time, and dynamically adjust the clock source output through the built-in compensation algorithm to effectively eliminate the interference of environmental factors on the clock signal, ensuring that the internal clock of the system can remain highly stable in complex environments.

[0076] The B-code parsing module is used to: receive external IRIG-B timecode signals and internal system clock signals; parse the code data, generate pulse-per-second (PPS) signals and IRIG-B standard time information through decoding logic; input the code data stream and PPS signal to the microsecond-level time jump detection module to provide the original signal basis for abnormal time jump analysis; and output the parsed IRIG-B standard time and PPS signals to the time management module and the self-timekeeping calculation module as the basic time reference for system time synchronization management and self-timekeeping algorithm operation.

[0077] The microsecond-level transition detection module is used to monitor microsecond-level abnormal transitions in the time signal in real time based on the timing characteristics of the input code data stream, pulse-per-second (PPS) signal, and IRIG-B time code signal. Through edge detection and timing analysis algorithms, it accurately captures the time and direction (positive / negative) of the transition, generates a transition flag signal with microsecond-level resolution, and outputs this status signal to the out-of-synchronization-timekeeping state machine transition module as one of the key triggering conditions for the state machine to determine and transition between device operating states.

[0078] The time management module is used to: receive the IRIG-B standard time and pulse-of-seconds (PPS) signal, perform timing analysis with a period of 950ms, monitor whether the B code signal experiences a second-level jump (≥1 second) under normal time synchronization conditions, and calculate the deviation value between the B code signal and the device's self-keeping time after the B code interruption is restored. A threshold comparator generates a "time deviation > 3600 seconds" flag and a "second-level jump occurred" flag, which are output to the out-of-synchronization-keeping state machine transition module, providing key time characteristic parameters for the intelligent determination of the device's operating status.

[0079] The self-keeping time calculation module is used to dynamically calculate the timekeeping time based on the IRIG-B standard time and the pulse-of-seconds (PPS) signal, using an internal self-keeping time period sampling and adjustment algorithm. When the external B-code signal is normal, it calibrates the local time base in real time; when a B-code interruption is detected, it automatically switches to self-keeping time mode and seamlessly takes over the time output, maintaining a continuous and stable time signal output through frequency compensation and phase calibration techniques, ensuring that the system maintains a reliable time base even in scenarios where external time synchronization fails.

[0080] The out-of-synchronization-time-keeping state machine transition module is used to: integrate microsecond-level jump detection flags, second-level time jump signals, and time deviation data after B-code interrupt recovery to determine the system's operating state (out-of-synchronization / synchronization / time-keeping three states) in real time. Based on the state determination results, it drives the state machine to execute corresponding state transition logic, dynamically controlling the processing flow and output path of time signals, thereby achieving accurate mapping of the device's operating state and adaptive adjustment of timing logic.

[0081] The signal output module integrates three types of input signals: self-keeping time, IRIG-B code time, and RTC chip time. It uses priority logic to intelligently select and control the clock signal output. When a forced follow enable signal is received, the RTC chip time is prioritized as the system time base. When the RTC forced follow mode is not enabled, if the external IRIG-B code signal is normal, the B code time is directly used as the device time. When a jump or interruption in the B code signal is detected, it automatically switches to the self-keeping time output mode. For B code interruption recovery scenarios, a time deviation threshold (3600 seconds) judgment mechanism is used: if the deviation between the recovered B code time and the keeping time exceeds the threshold, the B code signal is deemed unreliable, and the keeping time continues to be used; if the deviation is within the threshold, after confirmation by a continuous m-second valid B code signal, it switches back to the B code time base.

[0082] The signal output module ultimately sends key information such as device status (out of step / synchronized / timed), device time, and second pulse signal (PPS) to the time synchronization bus, realizing standardized output and status sharing of system time signals.

[0083] This invention, through the coordinated operation of hardware-level compensation mechanisms and intelligent decision-making algorithms, significantly improves the environmental adaptability and status observability of power system automation control equipment while ensuring microsecond-level time jump detection accuracy. It is applicable to smart substations, wide-area power grid protection, and high-precision time communication scenarios.

[0084] Example 6 According to one embodiment of the present invention, an electronic device includes a processor, a memory, and a computer program stored in the memory and executable on the processor. When the computer program is executed by the processor, it implements any of the PMU device time synchronization management methods of the present invention.

[0085] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the device described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0086] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

[0087] It should be understood that the sequence number of each step in the invention and embodiments of the present invention does not absolutely imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

Claims

1. A time synchronization management method for a PMU device, characterized in that, include: Acquire temperature and voltage data inside the FPGA chip; The compensated clock cycle parameters are obtained based on the temperature data and the voltage data; The frequency division coefficient and duty cycle of the phase-locked loop are adjusted based on the compensated clock cycle parameters to generate a frequency-adjusted system clock signal. Based on the code data stream of IRIG-B code and the second pulse signal, determine the state of the IRIG-B code time signal; The clock source of the PMU is switched based on the real-time status of the PMU and the status of the IRIG-B code time synchronization signal.

2. The PMU device time synchronization management method according to claim 1, characterized in that, Based on the temperature data and the voltage data, the compensated clock cycle parameters are obtained, including: The actual on-chip temperature data is obtained based on the temperature data and temperature drift compensation algorithm, and the actual on-chip voltage data is obtained based on the voltage data and voltage fluctuation suppression model. The compensated clock cycle parameter is obtained based on the voltage data using the following formula. in, This represents the clock cycle parameter after compensation; Indicates the reference value of the clock cycle; This represents the total compensation amount for the two parameters of the clock cycle; This represents the difference between the actual on-chip temperature and the reference temperature. Indicates the temperature compensation coefficient; This represents the difference between the actual on-chip voltage and the reference voltage. This represents the voltage compensation coefficient.

3. The PMU device time synchronization management method according to claim 2, characterized in that: The total compensation amount of the two clock cycle parameters does not exceed the preset compensation cycle limit; the clock cycle reference value is adaptively adjusted using the Q16.8 fixed-point format.

4. The PMU device time synchronization management method according to claim 1, characterized in that, Based on the IRIG-B code data stream and the second pulse signal, the state of the IRIG-B code time signal is determined, including: Each IRIG-B code symbol is assigned a unique number and a timestamp is added. The edge of the last symbol within one second is captured to generate a PPS signal with a duration equal to the symbol width. Using the second edge of the IRIG-B code as the counting benchmark, the counted value is compared with a pre-set threshold to determine whether the IRIG-B code is reliable and synchronized. It detects time jumps within seconds, including two scenarios: jumps on the order of more than 10ms and jumps on the order of less than 10ms; it determines whether a jump exists, and if so, generates a jump event record and alarm signal accompanied by a microsecond-level timestamp.

5. The PMU device time synchronization management method according to claim 4, characterized in that, Determining whether a transition exists includes: For transition scenarios with a magnitude of more than 10ms, count whether the number of symbols between adjacent "P" codes reaches the first threshold; if not, it is determined that a transition exists. For scenarios involving jumps on the order of less than 10ms, determine whether the B-code second-cycle count result exceeds a preset second quantity threshold; if it does, determine that a jump has occurred.

6. The PMU device time synchronization management method according to claim 1, characterized in that: The states of the PMU device include: synchronization state, timekeeping state, and out-of-synchronization state; The states of the IRIG-B code time synchronization signal include: normal, interrupted, and transition; The switching logic for switching the clock source of the PMU device includes: In forced follow mode, the time is based on the RTC chip. When the IRIG-B code time synchronization signal is normal, the IRIG-B code time is used; When the IRIG-B code time synchronization signal is interrupted or changes, the FPGA self-keeping time is used; After the IRIG-B code interruption is recovered, if the time deviation from the self-synchronous time exceeds the first time threshold, the self-synchronous time output is maintained; otherwise, if the IRIG-B code signal is valid for the first consecutive time period, the IRIG-B code time is switched back.

7. The PMU device time synchronization management method according to claim 6, characterized in that, Based on the real-time status of the PMU device and the status of the IRIG-B code time synchronization signal, the clock source of the PMU device is switched, including: When the PMU device successfully locks onto a valid external IRIG-B code time synchronization signal, it achieves real-time alignment between the local clock and the external time reference, and enters the synchronization state. When the device detects an interruption or jump in the external time synchronization signal in the synchronization state, it starts the local high-stability clock source to maintain the time counting and enters the timekeeping state. The device enters a state of out-of-synchronization when any of the following conditions exist: there is no external time synchronization signal after the device is powered on; the device continuously receives valid clock signals with a time difference greater than the preset time threshold during the timekeeping process, reaching the third quantity threshold; or the timekeeping process exceeds 1 hour.

8. The PMU device time synchronization management method according to claim 1, characterized in that: The device status flag PMU_STATUS is used to indicate signal synchronization status and data availability. Specifically, In synchronization mode, PMU_STATUS is "11", indicating that "signals are synchronized and data is available"; When out of sync, PMU_STATUS is "00", indicating "signals are not synchronized and data is unavailable"; In timekeeping mode, PMU_STATUS is "01", indicating that "signals are not synchronized, but data is available".

9. A time synchronization management system for a PMU device, characterized in that, The system includes: An environmental parameter adaptive clock compensation module is used to acquire temperature and voltage data inside the FPGA chip; and to acquire compensated clock cycle parameters based on the temperature and voltage data. The phase-locked loop clock frequency adjustment module is used to adjust the frequency division coefficient and duty cycle of the phase-locked loop based on the compensated clock period parameters, and generate a frequency-adjusted system clock signal. The microsecond-level transition detection module is used to determine the state of the IRIG-B code time signal based on the code data stream of the IRIG-B code and the second pulse signal; The multi-clock source intelligent switching control module is used to switch the clock source of the PMU device based on the real-time status of the PMU device and the status of the IRIG-B code time synchronization signal.

10. An electronic device, characterized in that, It includes a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the PMU device time synchronization management method as described in any one of claims 1-8.

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