Joint debugging method, system and device for multistage Hash interleaving module

Abstract

The invention relates to the technical field of chips, in particular to a joint debugging method, system and device for a multistage Hash interleaving module. The method mainly comprises the steps that a to-be-interleaved address field is received, the to-be-interleaved address field comprises a plurality of original addresses, each original address is interleaved according to a first Hash interleaving algorithm, and an intermediate address is generated; performing interleaving processing on each intermediate address according to a second Hash interleaving algorithm to generate a final address; converting the business demand into a verification code, and verifying the plurality of final addresses according to the verification code to obtain a verification result; and if the verification result does not meet the service requirement, correcting the second Hash interleaving algorithm, and obtaining a plurality of final addresses again according to the corrected second Hash interleaving algorithm and obtaining the verification result until the verification result meets the service requirement. According to the method, the specific mapping addresses of different transactions can be quickly obtained, so that the address allocated to each Slave IP meets the service requirements, and the manpower and time cost is remarkably reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip technical field, in particular to a kind of joint debugging method, system and device of multistage hash interleave module. BACKGROUND

[0002] In early system on chip (System on Chip, for short SoC), since the number of Master Intellectual Preprotity (Master IP for short) and Slave Intellectual Preprotity (Slave IP for short) in chip is less, complex address routing algorithm is not needed to complete the fast communication between transactions. However, with the complexity of chip increasing greatly, the number of Master IP and Slave IP in chip gradually increases, when Master IP and Slave IP carry out transaction transmission, Master IP will send a series of continuous addresses to Slave IP, after the distribution of routing bus, each Slave IP is distributed. However, in actual scenario, address distribution mode is changed according to business requirement, and a kind of address distribution mode cannot be suitable for all business requirements, so that the number of addresses distributed to each Slave IP does not meet the business requirement, reduces the efficiency of transaction transmission. For example, the number of addresses distributed to each Slave IP is not even, some Slave IP has a large number of addresses, and some Slave IP has only a few addresses, which greatly reduces the efficiency of transaction transmission.

[0003] In view of this, how to overcome the defects of the prior art is a problem to be solved in the technical field. SUMMARY

[0004] In view of the above defects or improvement needs of the prior art, the present application solves the problem of how to quickly distribute addresses to different Slave IP after the change of business requirement in the prior art, so that the addresses distributed to each Slave IP meet the business requirement.

[0005] The embodiment of the present application adopts the following technical scheme: In a first aspect, the present application provides a joint debugging method of a multi-level hash interleaving module, which specifically comprises: receiving an address segment to be interleaved, wherein the address segment to be interleaved comprises a plurality of original addresses, performing interleaving processing on each of the original addresses according to a first hash interleaving algorithm to generate an intermediate address, performing interleaving processing on each of the intermediate addresses according to a second hash interleaving algorithm to generate a final address, receiving a service requirement and converting the service requirement into a verification code, verifying a plurality of final addresses according to the verification code to obtain a verification result, and if the verification result does not meet the service requirement, modifying the second hash interleaving algorithm, reacquiring a plurality of final addresses according to the modified second hash interleaving algorithm and obtaining a verification result, until the verification result meets the service requirement.

[0006] Preferably, the receiving an address segment to be interleaved, wherein the address segment to be interleaved comprises a plurality of original addresses, performing interleaving processing on each of the original addresses according to a first hash interleaving algorithm to generate an intermediate address specifically comprises: parsing a configuration parameter to obtain a capacity threshold and a first hash interleaving algorithm, wherein the first hash interleaving algorithm comprises a first sub-hash interleaving algorithm and a second sub-hash interleaving algorithm; receiving an original address, performing interleaving processing on the original address according to the first sub-hash interleaving algorithm to generate a first hash address; receiving an original address, performing interleaving processing on the original address according to the second sub-hash interleaving algorithm to generate a second hash address; and splicing and reorganizing the first hash address and the second hash address into the intermediate address.

[0007] Preferably, the receiving an original address, performing interleaving processing on the original address according to the first sub-hash interleaving algorithm to generate a first hash address specifically comprises: receiving an original address, obtaining high N bits of the original address, performing an exclusive OR logical operation or an exclusive NOR logical operation on the high N bits to generate a first hash address.

[0008] Preferably, the receiving an original address, performing interleaving processing on the original address according to the second sub-hash interleaving algorithm to generate a second hash address specifically comprises: receiving an original address, comparing the original address with a capacity threshold; if the original address is less than or equal to the capacity threshold, obtaining low M bits of the original address, performing a flip logical operation on the original address to generate a second hash address; and if the original address is greater than the capacity threshold, obtaining low M bits of the original address, and directly taking the low M bits as a second hash address.

[0009] Preferably, a bit width of the intermediate address is the same as a bit width of the original address.

[0010] Preferably, the step of verifying the final address according to the verification code to obtain the verification result specifically includes: obtaining the target address ratio and tolerance value of each storage region according to business requirements; counting the total number of the final addresses; mapping the final address to the corresponding storage region according to the address range of each final address, and counting the actual address number of the final address corresponding to each storage region; calculating the actual address ratio of each storage region, wherein the actual address ratio is the ratio of the actual address number of each storage region to the total number; and obtaining the verification result based on the actual address ratio, the target address ratio, and the tolerance value.

[0011] Preferably, obtaining the verification result based on the actual address ratio, the target address ratio, and the tolerance value specifically includes: determining whether the absolute difference between the actual address ratio and the target address ratio of each storage region exceeds the tolerance value; if the absolute difference of all storage regions does not exceed the tolerance value, then the verification result meets the business requirement; if the absolute difference of at least one storage region exceeds the tolerance value, then the verification result does not meet the business requirement, and the weight of the storage region whose absolute difference exceeds the tolerance value is increased to correct the second hash interleaving algorithm.

[0012] Secondly, the present invention provides a joint debugging system for a multi-level hash interleaving module, specifically comprising: a first hash interleaving module for receiving an address segment to be interleaved, wherein the address segment to be interleaved includes multiple original addresses, and interleaving each of the original addresses according to a first hash interleaving algorithm to generate an intermediate address; a second hash interleaving module for interleaving each of the intermediate addresses according to a second hash interleaving algorithm to generate a final address; a logic conversion module for receiving business requirements and converting the business requirements into verification code, and verifying multiple final addresses according to the verification code to obtain a verification result; and an iteration control module for correcting the second hash interleaving algorithm if the verification result does not meet the business requirements, and re-acquiring multiple final addresses according to the corrected second hash interleaving algorithm to obtain a verification result, until the verification result meets the business requirements.

[0013] Thirdly, the present invention provides an apparatus for joint debugging of a multi-level hash interleaving module, specifically comprising at least one processor and a memory, wherein the at least one processor and the memory are connected via a data bus, the memory stores instructions that can be executed by at least one processor, and the instructions, after being executed by the processor, are used to complete the joint debugging method of the multi-level hash interleaving module in the first aspect.

[0014] Fourthly, the present invention also provides a non-volatile computer storage medium storing computer-executable instructions that are executed by one or more processors to perform the method provided by the method described in the first aspect.

[0015] Compared with existing technologies, the advantages of this invention are as follows: The original address is interleaved using a hash interleaving algorithm to obtain the final address. The final address is then compared with the business requirements to determine whether the second interleaving algorithm meets those requirements. The second hash interleaving algorithm is continuously changed, ensuring that each final address gets closer to the business requirements until the final address satisfies them. Using this method, the specific mapping addresses for different transactions can be quickly obtained after changes in business requirements, ensuring that the address allocated to each Slave IP meets the business requirements, significantly reducing manpower and time costs.

[0016] Furthermore, during chip iteration, the hash interleaving module will change. By continuously iterating and correcting the parameters of the changed hash interleaving module, the modified hash interleaving module can meet business requirements and accelerate chip debugging efficiency. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments of the present invention will be briefly described below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0018] Figure 1 A flowchart illustrating a joint debugging method for a multi-level hash interleaving module provided in an embodiment of the present invention; Figure 2 A flowchart illustrating another joint debugging method for a multi-level hash interleaving module provided in an embodiment of the present invention; Figure 3 A flowchart illustrating another joint debugging method for a multi-level hash interleaving module provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of a joint debugging system for a multi-level hash interleaving module provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of a SOC chip including a hash interleaving module, provided in an embodiment of the present invention; Figure 6 This is a schematic diagram illustrating a joint debugging example of a multi-level hash interleaving module provided in an embodiment of the present invention; Figure 7This is a schematic diagram of the structure of a joint debugging device for a multi-level hash interleaving module provided in an embodiment of the present invention; The reference numerals in the attached figures are as follows: 21: Processor; 22: Memory. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0020] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as openly inclusive, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples; that is, although they may be incorporated into embodiments or examples using the above terms for reasons such as order and position, it does not limit them to be incorporated in combination by a single embodiment or example.

[0021] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more. Furthermore, for example, the description may use the prefix "A" or "B" to describe the same type of nouns as two independent entities. In this case, the corresponding features defined with "A" and "B" are used only to distinguish between similar entities and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features.

[0022] Furthermore, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0023] In SoC chip design, hash interleaving modules can be introduced to increase the efficiency of transaction transmission. Hash interleaving modules are used to implement dynamic mapping of the address space (such as memory controllers, bus routing, etc.). Hash interleaving modules are usually divided into two levels. The first level hash interleaving module randomly breaks up a continuous range of addresses, and the second level hash interleaving module maps these random addresses to different slave IPs according to the chip requirements. Its design must meet the requirements of uniformity and continuity of address distribution.

[0024] However, with increasing chip demand, different chips require different hash interleaving modules, necessitating iterations of SoC chips containing hash interleaving modules. During chip iteration, typically only the first or second level hash interleaving module is modified. A change in either level alters the corresponding address shuffling or mapping rules, making it difficult to quickly obtain the specific mapped addresses for different transactions. Instead, the mapped addresses must be searched from the register-transfer level (RTL) model using polling, reducing transaction transmission efficiency. Furthermore, the algorithm implementation of the new hash interleaving module requires manual debugging and iteration. A systematic approach is lacking in the joint debugging of multi-level hash interleaving modules, making it difficult to locate global address mapping problems. These issues significantly increase manpower and time costs.

[0025] In summary, with the rapid development of chips, different chip requirements have emerged, necessitating continuous iteration of hash interleaving modules to meet these requirements. During chip iteration, typically only the first or second level hash interleaving module is modified. Even so, changes to any level of hash interleaving module make it difficult to quickly obtain the specific mapping addresses for different transactions. RTL-level simulation is required to obtain these specific mapping addresses, which takes a relatively long time in a SoC chip.

[0026] To address the aforementioned issues, the foregoing embodiments of this invention provide a joint debugging method for a multi-level hash interleaving module. By continuously debugging the hash interleaving module to meet business requirements, the specific mapping addresses of different transactions can be quickly obtained. In practical use, the hash interleaving algorithm of the hash interleaving module is first debugged based on the joint debugging method of the multi-level hash interleaving module. After debugging, the finally determined hash interleaving module is applied to the SoC chip, enabling the SoC chip to map a series of consecutive addresses to different Slave IPs, thus meeting business requirements. The joint debugging method of the multi-level hash interleaving module provided in this embodiment is applied to a joint debugging system with at least a first hash interleaving module and a second hash interleaving module. The first hash interleaving module and the second hash interleaving module perform address interleaving, ensuring that the generated final address meets the requirements.

[0027] like Figure 1 As shown, the joint debugging method for a multi-level hash interleaving module provided in this embodiment of the invention specifically includes the following steps: Step 101: Receive the address segment to be interleaved, wherein the address segment to be interleaved includes multiple original addresses, and perform interleaving processing on each of the original addresses according to the first hash interleaving algorithm to generate an intermediate address.

[0028] In a SoC chip, the Master IP typically acts as the transaction initiator, sending a series of consecutive addresses to the Slave IP. Through the allocation of the routing bus, the consecutive addresses are distributed to each Slave IP.

[0029] The Master IP can be a Peripheral Component Interconnect Express (PCIe) or a Central Processing Unit (CPU), etc. The Slave IP can be a storage area. The following explanation uses the Slave IP as a storage area as an example. In actual application scenarios, the Slave IP can also be other components, which are not specifically limited here.

[0030] In the chip system, each transaction initiator is equipped with the same hash interleaving module. In one embodiment, when multiple transaction initiators are transmitting transactions with the storage area, they will send a series of consecutive addresses to the storage area. This series of consecutive addresses will first be interleaved by the first hash interleaving module of the transaction initiator to obtain an intermediate address, and then the intermediate address will be transmitted to the second hash interleaving module.

[0031] The address segment to be interleaved is a series of consecutive addresses sent by the transaction initiator. This series of consecutive addresses includes multiple original addresses. The first hash interleaving module performs interleaving processing on each original address according to the hash interleaving algorithm. After interleaving, an original address corresponds to an intermediate address.

[0032] The hash interleaving modules use different hash interleaving algorithms: the first hash interleaving module uses the first hash interleaving algorithm, and the second hash interleaving module uses the second hash interleaving algorithm.

[0033] Step 102: Perform interleaving processing on each intermediate address according to the second hash interleaving algorithm to generate the final address.

[0034] Once the intermediate addresses are obtained, the second hash interleaving module performs interleaving processing on each intermediate address according to the second hash interleaving algorithm. After processing by the second hash interleaving algorithm, each intermediate address corresponds to a final address, and the bit width of the intermediate address is the same as that of the final address.

[0035] Step 103: Receive the business requirements and convert them into verification codes. Verify multiple final addresses according to the verification codes to obtain verification results.

[0036] In the joint debugging system, there is also a logic conversion module. On the one hand, the logic conversion module receives business requirements from the outside and converts the business requirements into verification code. On the other hand, the logic conversion module receives the final address from the second interleaving module and uses the verification code to make logical judgments on each final address to obtain the verification result.

[0037] Step 104: If the verification result does not meet the business requirements, then the second hash interleaving algorithm is modified, and multiple final addresses are re-obtained and verification results are obtained according to the modified second hash interleaving algorithm until the verification result meets the business requirements.

[0038] In the joint debugging system, there is also an iteration control module. This module receives the verification results from the logic transformation module and uses these results to determine whether to modify the second hash interleaving algorithm in the second hash interleaving module. When the verification results show that the second hash interleaving algorithm meets the business requirements, the iteration control module will directly end the iteration. When the verification results show that the second hash interleaving algorithm does not meet the business requirements, the iteration control module modifies the second hash interleaving algorithm, then obtains the final address generated by the modified second hash interleaving algorithm, performs a new round of logic judgment, and obtains a new verification result. The iteration will stop only when the verification results show that the second hash interleaving algorithm meets the business requirements.

[0039] In this embodiment, a hash interleaving algorithm is used to convert the original address into the final address. The second hash interleaving algorithm is evaluated by comparing the business requirements with the final address to determine if it meets the requirements. The second hash interleaving algorithm is continuously adjusted so that the final address gradually approaches the business requirements until the second hash interleaving algorithm meets the requirements. Using this method, even after the hash interleaving module is modified, the specific mapping addresses of different transactions can still be quickly obtained, ensuring that the address allocated to each Slave IP meets the business requirements, significantly reducing manpower and time costs.

[0040] In this embodiment, a fully automated closed-loop iteration is adopted, reducing manual intervention and improving debugging efficiency by more than 30%. Simultaneously, it can quickly locate the address after passing through two levels of hash interleaving modules, reducing the probability of system crashes caused by address mapping conflicts. This significantly shortens the time required for verification engineers and test engineers to debug the chip's system-level address routing, thereby reducing the chip's development cycle.

[0041] After the hash interleaving module is changed, one option is to obtain the specific mapping address through RTL-level simulation, but this takes a relatively long time (more than an hour). To shorten the debugging time, this embodiment directly uses an iterative method to simulate the model (simulation time is less than 10 minutes), without needing to go through RTL-level simulation, thus shortening the debugging time.

[0042] In this embodiment, the first hash interleaving module is used to receive an address segment to be interleaved, wherein the address segment to be interleaved includes multiple original addresses, and each of the original addresses is interleaved according to the first hash interleaving algorithm to generate an intermediate address. Figure 2 As shown, the interleaving process for each original address specifically includes the following steps: Step 201: Parse the configuration parameters to obtain the capacity threshold and the first hash interleaving algorithm, which includes a first sub-hash interleaving algorithm and a second sub-hash interleaving algorithm.

[0043] The first hash interleaving module includes an interleaving capacity selection area, an interleaving address range selection area, a first address interleaving translation area, a second address interleaving translation area, and an address integration area. The interleaving capacity selection area is used to parse the configuration parameters of the first hash interleaving module; the interleaving address range selection area is used to determine the address range of the original address; both the first and second address interleaving translation areas perform address translation; and the address integration area concatenates and combines two address segments.

[0044] The interleaving capacity selection area obtains the capacity threshold and the first hash interleaving algorithm by parsing the configuration parameters of the first hash interleaving module. The capacity threshold refers to the maximum range of address space that the first hash interleaving module can perform interleaving processing. The first hash interleaving algorithm includes a first sub-hash interleaving algorithm and a second sub-hash interleaving algorithm. These two algorithms are different and correspond to the specific execution algorithms when the first address interleaving translation area and the second address interleaving translation area convert addresses, respectively.

[0045] The first hash interleaving module supports multiple configurations. This embodiment of the invention provides five configurations (modes 1 to 5), each corresponding to a different combination of parameters. For example, in mode 1, the capacity threshold is 5G, the first sub-hash interleaving algorithm is a high 3-bit XOR operation, and the second sub-hash interleaving algorithm is a low 8-bit flip operation; in mode 2, the capacity threshold is 10G, the first sub-hash interleaving algorithm is a high 5-bit XOR operation, and the second sub-hash interleaving algorithm is a low 4-bit flip operation. It is understood that this invention is not limited to these configurations.

[0046] Step 202: Receive the original address, and perform interleaving processing on the original address according to the first sub-hash interleaving algorithm to generate the first hash address.

[0047] The first address interleaving conversion area receives the original address and obtains the first sub-hash interleaving algorithm according to the configuration parameters in the first hash interleaving module. Each original address is interleaved according to the first sub-hash interleaving algorithm to obtain the first hash address. One original address corresponds to one first hash address after interleaving.

[0048] Furthermore, the first address interleaving conversion area receives the original address, obtains the high N bits of the original address, performs an XOR or XNOR operation on the high N bits of the original address, and generates the first hash address. The bit width of the first hash interleaving address is N.

[0049] In one embodiment, an original address of 0xD6AC, written in binary encoding as 1101011010101100, undergoes a first sub-hash interleaving algorithm by XORing the high 8 bits of the original address. The first address interleaving conversion area obtains the high 8 bits of the original address as 11010110, with the leftmost 1 representing the most significant bit and the rightmost 0 representing the least significant bit. Starting from the most significant bit, XORing is performed on every two adjacent bits sequentially, and the results are arranged in order to form a new binary number of 0111101, which is only 7 bits. The most significant bit is padded with 0, and the address after interleaving by the first sub-hash interleaving algorithm is 00111101, which is the first hash address. Similarly, an original address of 0xE12F becomes 00010001 after processing by the first sub-hash interleaving algorithm.

[0050] Step 203: Receive the original address, and perform interleaving processing on the original address according to the second sub-hash interleaving algorithm to generate the second hash address.

[0051] The second address interleaving conversion area obtains the second sub-hash interleaving algorithm based on the configuration parameters in the first hash interleaving module. Each original address is interleaved according to the second sub-hash interleaving algorithm to obtain the second hash address. One original address corresponds to one second hash address after interleaving.

[0052] Furthermore, the interleaving address range selection area receives the original address and compares the original address with the capacity threshold; if the original address is less than or equal to the capacity threshold, the second address interleaving conversion area obtains the lower M bits of the original address, performs a flip logic operation on the lower M bits of the original address, and generates a second hash address; if the original address is greater than the capacity threshold, the second address interleaving conversion area obtains the lower M bits of the original address and directly uses the lower M bits as the second hash address, the bit width of the second hash address being M.

[0053] The capacity threshold can be determined based on the actual situation, and no specific limit is set here.

[0054] In one embodiment, one original address is 0xD6AC, which is 1101011010101100 in binary encoding, and the other original address is 0xE12F, which is 1110000100101111 in binary encoding. The second sub-hash interleaving algorithm flips the lower 8 bits of the original addresses, and the capacity threshold is 0xE000. First, the interleaving address range selection area compares these two original addresses with the capacity threshold. If 0xD6AC is smaller than the capacity threshold, the second address interleaving conversion area will obtain the lower 8 bits of 0xD6AC as 10101100 and flip these 8 bits to obtain 01010011, which will be used as the second hash address. If 0xE12F is larger than the capacity threshold, the second address interleaving conversion area will obtain the lower 8 bits of 0xE12F as 00101111, without performing any operation on these 8 bits, and directly use it as the second hash address.

[0055] Step 204: Concatenate the first hash address and the second hash address to reconstruct the intermediate address.

[0056] The address integration area receives the first hash address from the first address interleaving and conversion area and the second hash address from the second address interleaving and conversion area, and concatenates the first hash address and the second hash address into an intermediate address. One concatenation of the first hash address and the second hash address corresponds to one intermediate address.

[0057] Specifically, the first hash address obtained by 0xD6AC through the first address interleaving translation region is 00111101, and the first hash address obtained by 0xE12F through the first address interleaving translation region is 00010001; the second hash address obtained by 0xD6AC through the second address interleaving translation region is 01010011, and the second hash address obtained by 0xE12F through the second address interleaving translation region is 00101111. The address integration region concatenates 00111101 and 01010011 to obtain 0011110101010011, which is 0x3D53; and concatenates 00010001 and 00101111 to obtain 0001000100101111, which is 0x112F. Ultimately, the intermediate address obtained after interleaving 0xD6AC by the first hash interleaving module is 0x3D53, and the intermediate address obtained after interleaving 0xE12F by the first hash interleaving module is 0x112F.

[0058] In practical applications, the hash algorithm executed by the first address interleaving conversion area and the second address interleaving conversion area is not specifically limited. It can be a low-bit address permutation, performing bit reversal or XOR operation on the low N bits (e.g., the low 8 bits) of the address; it can be a middle address logical operation, performing addition, subtraction, multiplication, and division operations on the middle address; or it can be a high-bit hash mapping, inputting the high M bits into a hash function (e.g., CRC32) to generate a new high M-bit full address mix.

[0059] In this embodiment, the logic conversion module receives business requirements and converts them into verification codes. The verification codes are then used to verify multiple final addresses to obtain verification results. For example... Figure 3 As shown, verifying the final address according to the verification code to obtain the verification result includes the following steps: Step 301: Obtain the target address ratio and tolerance value for each storage region based on business requirements.

[0060] Business requirements are specific requirements for the mapping rules from addresses to storage areas. The core objective is to ensure that the final address meets the requirements through a hash interleaving algorithm, thereby optimizing performance, avoiding hotspots, and adapting to hardware characteristics.

[0061] In one embodiment, business requirements can align the allocation ratios across multiple storage regions with preset weights. The target address ratio defines the address allocation weights across multiple storage regions, with the sum of the ratios across all regions being 100%. The tolerance value specifies the allowable deviation range for each target address ratio, used to control the flexibility during actual allocation.

[0062] Specifically, such as Figure 5As shown, two transaction initiators, PCIe and CPU, issue two transactions. Each transaction contains a series of consecutive addresses. This series of consecutive addresses undergoes two address transformations within the first hash interleaving module to obtain an intermediate address. The intermediate address then undergoes one address transformation within the second hash interleaving module to obtain the final address. Finally, the final address is allocated to four memory regions via the chip system bus connection unit. The memory regions can include various types of memory, such as Double Data Rate (DDR), Static Random Access Memory (SRAM), or Flash EEPROM Memory (Flash).

[0063] In this embodiment of the invention, DDR is used as a specific example of a storage region, with four storage regions being DDR1, DDR2, DDR3, and DDR4. The service requirement is that the number of addresses in DDR1 is 40% of the total number of consecutive addresses issued by the PCIe and CPU, and the number of addresses in DDR2, DDR3, and DDR4 is 20% of the total number of consecutive addresses, with an error margin of less than 2%. The logic translation module will obtain target address proportions of 40%, 20%, 20%, and 20%, with a tolerance of 2%.

[0064] Step 302: Count the total number of the final addresses.

[0065] The logic conversion module receives multiple final addresses from the second hash interleaving module and counts the total number of final addresses.

[0066] In one embodiment, the PCIe initiates a transaction containing 100 consecutive addresses, and the CPU initiates a transaction containing 100 consecutive addresses. The total number of consecutive addresses issued by the PCIe and CPU is 200. This series of consecutive addresses is interleaved by a first hash interleaving module to generate intermediate addresses. These intermediate addresses are then interleaved by a second hash interleaving module to generate the final addresses, which are the same as the total number of consecutive addresses in this series, i.e., the total number of final addresses is 200.

[0067] Step 303: Based on the address range of each final address, map the final address to the corresponding storage area, and count the actual number of final addresses corresponding to each storage area.

[0068] Each storage region has a different storage range. The address range of each final address is compared with the storage region one by one. Whenever the address range of a final address belongs to one of the storage regions, the actual address count of that storage region is incremented by 1. Eventually, all final addresses can be mapped to the corresponding storage regions. Finally, the actual address count of each storage region is counted.

[0069] In one embodiment, the storage ranges of the four storage regions DDR1, DDR2, DDR3, and DDR4 are 0x0000~0x007F, 0x0080~0x00FF, 0x0100~0x017F, and 0x0180~0x01FF, respectively. One of the final addresses is 0x003F. Comparing this to the storage ranges of the four storage regions, it can be seen that 0x003F is mapped to DDR1, therefore the actual address count in DDR1 is 1. By comparing each final address with the storage range of the four storage regions one by one, all final addresses can be mapped to the four storage regions. The final count of the actual addresses in the four storage regions is 60, 42, 40, and 58, respectively.

[0070] Step 304: Calculate the actual address ratio for each storage region, wherein the actual address ratio is the ratio of the number of actual addresses in each storage region to the total number of addresses.

[0071] The logic transformation module obtains the total number of final addresses and the actual number of addresses in each storage region, and calculates the ratio of the actual number of addresses in each storage region to the total number of addresses to obtain the actual address ratio.

[0072] Specifically, the total number of final addresses is 200, and the actual number of addresses in the four storage regions are 60, 42, 40 and 58 respectively. The actual address ratios corresponding to the four storage regions can be calculated as 30%, 21%, 20% and 29%.

[0073] Step 305: Obtain the verification result based on the actual address ratio, the target address ratio, and the tolerance value.

[0074] When the actual address ratio of each storage region is obtained, the logic transformation module calculates the absolute difference between the actual address ratio and the target address ratio of each storage region, and determines whether the absolute difference exceeds the tolerance value. If the absolute difference of all storage regions does not exceed the tolerance value, it indicates that the second hash interleaving algorithm meets the business requirements; if the absolute difference of at least one storage region exceeds the tolerance value, it indicates that the second hash interleaving algorithm does not meet the business requirements, and the second hash interleaving algorithm in the second hash interleaving module needs to be modified.

[0075] Specifically, the logic conversion module obtains target address ratios of 40%, 20%, 0%, and 20%, with a tolerance of 2%. The actual address ratios for the four storage locations are 30%, 21%, 20%, and 29%. The absolute differences between the actual address ratios and target address ratios for the four storage locations are calculated to be 10%, 1%, 0%, and 9%. It is known that the absolute differences between the actual address ratios and target address ratios for DDR1 and DDR4 exceed the tolerance, indicating that the second hash interleaving algorithm does not meet the business requirements. Therefore, the weights of the landing points for DDR1 and DDR4 in the second hash interleaving algorithm are modified. After multiple iterations and corrections, the final actual address ratios for the four storage locations are 39%, 20%, 21%, and 20%. The absolute differences between the actual address ratios and target address ratios for the four storage locations are calculated to be 1%, 0%, 1%, and 0%. It is known that the absolute differences between the actual address ratios and target address ratios for all four storage locations do not exceed the tolerance, indicating that the second hash interleaving algorithm meets the business requirements, and the iteration stops.

[0076] In one embodiment, there are four storage areas. It's possible that only two storage areas fail to meet business requirements, or all four may fail. When modifying the hash interleaving algorithm, different modification strategies can be employed to accelerate the iteration speed of the hash interleaving model. These modification strategies include small-scale modification algorithms and large-scale modification algorithms. In one embodiment, if verification results show that two storage areas fail to meet business requirements, it indicates that the current hash interleaving algorithm is relatively close to the business requirements. In this case, a small-scale modification algorithm is used to optimize the logic of arithmetic operations (addition, subtraction, multiplication, and division) in the median address algorithm, making the two storage areas meet the business requirements. If verification results show that all four storage areas fail to meet business requirements, it indicates that the current hash algorithm is far from the business requirements. In this case, a large-scale modification algorithm is used to reconstruct the bitwise and modulo operations in the high-order address algorithm, optimizing the calculation methods of XOR, XNOR, modulo 4, and remainder 4, making all four storage areas meet the business requirements.

[0077] The joint debugging method for the multi-level hash interleaving module provided in this embodiment processes the original address using a hash interleaving algorithm to obtain the final address, and compares this final address with the business requirements to evaluate the effectiveness of the second hash interleaving algorithm. If the result does not meet the requirements, the second hash interleaving algorithm is dynamically adjusted so that the newly generated final address gradually approaches the target pattern. This process continues until the final address fully meets the business requirements. Using this method, even after the hash interleaving module is modified, the specific mapping addresses of different transactions can still be quickly obtained, ensuring that the address allocated to each Slave IP meets the business requirements, significantly reducing manpower and time costs.

[0078] Based on the joint debugging method for multi-level hash interleaving modules provided in the foregoing embodiments, this embodiment also provides a joint debugging system for multi-level hash interleaving modules, which organizes the steps in the foregoing embodiments into multiple functional modules for implementation in the joint debugging system. It is understood that the specific implementation methods provided in this embodiment are only used to illustrate the specific implementation process of the methods in certain specific scenarios in the foregoing embodiments, and are not intended to limit the scope of protection.

[0079] like Figure 4 As shown, the functional modules used in this embodiment are: a first hash interleaving module, a second hash interleaving module, a logic transformation module, and an iteration control module.

[0080] (1) The first hash interleaving module is used to receive the address segment to be interleaved, wherein the address segment to be interleaved includes multiple original addresses, and each original address is interleaved according to the first hash interleaving algorithm to generate an intermediate address.

[0081] (2) The second hash interleaving module is used to receive the intermediate address from the first hash interleaving module, and to perform interleaving processing on each intermediate address according to the second hash interleaving algorithm to generate the final address.

[0082] (3) Logic conversion module, used to receive business requirements and convert the business requirements into verification code, and verify multiple final addresses according to the verification code to obtain verification results.

[0083] (4) Iteration control module, used to receive verification results. If the verification results do not meet the business requirements, the second hash interleaving algorithm is corrected, and multiple final addresses are re-obtained and verification results are obtained according to the corrected second hash interleaving algorithm until the verification results meet the business requirements.

[0084] Specifically, such as Figure 6 As shown, the first hash interleaving module in the joint debugging system includes an interleaving capacity selection area, an interleaving address range selection area, an address interleaving conversion area, and an address integration area. The interleaving capacity selection area parses the configuration parameters of the first hash interleaving module and selects a capacity threshold, for example, 0x5000. Then, the interleaving address range selection area determines the address from the PCIe and CPU. For example, if a 16-bit address is input, and the address is less than or equal to 0x5000, interleaving is performed; otherwise, the address remains unchanged.

[0085] The address interleaving translation area has two parts, corresponding to the two address transformations within the first hash interleaving module. The first address interleaving translation area performs an XOR or XNOR operation on the high 8 bits of the input address. The second address interleaving translation area compares the input address with the capacity threshold, flipping the low 8 bits of input addresses less than or equal to the capacity threshold, while leaving input addresses greater than the capacity threshold unchanged. The two 8-bit addresses output from the address interleaving translation area are then concatenated in the address integration area to ensure they have the same address width as those issued by the PCIe and CPU.

[0086] The joint debugging system translates business requirements into executable verification logic code. This code determines whether the number of addresses falling within DDR1 is 40% of the total number of addresses issued by PCIe and the CPU, and whether DDR2, DDR3, and DDR4 are 20% of the total number of addresses, with an error requirement within 2%. The iterative control module modifies the second hash interleaving algorithm of the second hash interleaving module based on the results of the verification logic code, and replaces the original second hash interleaving module model code with the corrected code.

[0087] The first hash interleaving module is configured to perform an XOR operation in its first address interleaving translation area and a toggle operation in its second address interleaving translation area. When the PCIe and CPU issue an address range of 0x3000~0x6FFF, the first address interleaving translation area performs an XOR operation on the 0x3000~0x6FFF address range. After passing through the interleaving address range selection area, the second address interleaving translation area performs a toggle operation on the 0x3000~0x5000 address range, while leaving the 0x5000~0x6FFF address range unchanged. The resulting addresses are then concatenated and sent to the second hash interleaving module model. After passing through this model and the bus, the actual address proportions falling within the four DDR ranges are determined. It is found that the actual address proportions falling within DDR1 are approximately 30%, DDR2 approximately 21%, DDR3 approximately 20%, and DDR4 approximately 29%. At this point, the iterative control module modifies the weights of the landing points for DDR1 and DDR4 in the second hash interleaving algorithm of the second hash interleaving module. After multiple iterations, the final proportion of actual addresses falling into DDR1 is approximately 39%, DDR2 approximately 20%, DDR3 approximately 21%, and DDR4 approximately 20%. Meeting business requirements, a new second hash interleaving algorithm is output, and iteration stops. Simultaneously, in each iteration of the second hash interleaving module algorithm, the interleaved addresses can be visualized and output, reducing time and manpower costs.

[0088] The multi-level hash interleaving module joint debugging system provided in this embodiment processes the original address using a hash interleaving algorithm to generate a final address, and compares it with business requirements to verify the effectiveness of the second hash interleaving algorithm. If it does not meet the requirements, its parameters or structure are iteratively adjusted to make the final address gradually approach the business requirements until it fully meets them. Using this method, even after the hash interleaving module has been modified, the specific mapping addresses of different transactions can still be obtained quickly, ensuring that the address allocated to each Slave IP meets business requirements and significantly reducing manpower and time costs.

[0089] Based on the joint debugging method for multi-level hash interleaving modules provided in the foregoing embodiments, the present invention also provides an apparatus for joint debugging of multi-level hash interleaving modules that can be used to implement the above method, such as... Figure 7 The diagram shown is a schematic representation of the device architecture according to an embodiment of the present invention. The device for joint debugging of the multi-level hash interleaving module in this embodiment includes one or more processors 21 and a memory 22. Wherein, Figure 7 Take a processor 21 as an example.

[0090] Processor 21 and memory 22 can be connected via a bus or other means. Figure 7 Taking the example of a connection between China and Israel via a bus.

[0091] The memory 22, as a non-volatile computer-readable storage medium for the joint debugging of multi-level hash interleaving modules, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the joint debugging method of multi-level hash interleaving modules in the foregoing embodiments. The processor 21 executes various functional applications and data processing of the joint debugging device for multi-level hash interleaving modules by running the non-volatile software programs, instructions, and modules stored in the memory 22, thereby implementing the joint debugging method of multi-level hash interleaving modules in the foregoing embodiments.

[0092] Memory 22 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 22 may optionally include memory remotely located relative to processor 21, which can be connected to processor 21 via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0093] The program instructions / modules are stored in memory 22. When executed by one or more processors 21, they perform the joint debugging method of the multi-level hash interleaving module in the aforementioned embodiments, for example, executing the above-described... Figures 1-3 The steps shown.

[0094] This invention also provides a non-volatile computer storage medium storing computer-executable instructions that are executed by one or more processors, for example... Figure 7 One of the processors 21 can enable one or more of the processors to execute the joint debugging method of the multi-level hash interleaving module in the foregoing embodiments, for example, to execute the above-described Figures 1-3 The steps shown can also be implemented. Figure 4 The various modules and units mentioned above.

[0095] It is worth noting that the information interaction and execution process between the modules and units in the above-mentioned device and system are based on the same concept as the processing method embodiment of the present invention. For details, please refer to the description in the method embodiment of the present invention, and will not be repeated here.

[0096] Those skilled in the art will understand that all or part of the steps in the various methods of the embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, which may include: read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.

[0097] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A joint debugging method for a multi-level hash interleaving module, characterized in that, include: Receive an address segment to be interleaved, wherein the address segment to be interleaved includes multiple original addresses, and perform interleaving processing on each of the original addresses according to a first hash interleaving algorithm to generate an intermediate address; Each intermediate address is interleaved according to the second hash interleaving algorithm to generate the final address; Receive business requirements and convert them into verification codes, then verify multiple final addresses according to the verification codes to obtain verification results; If the verification result does not meet the business requirements, the second hash interleaving algorithm is modified, and multiple final addresses are re-obtained and verification results are obtained according to the modified second hash interleaving algorithm until the verification result meets the business requirements.

2. The joint debugging method for the multi-level hash interleaving module according to claim 1, characterized in that, Also includes: Parse the configuration parameters to obtain the capacity threshold and the first hash interleaving algorithm, which includes a first sub-hash interleaving algorithm and a second sub-hash interleaving algorithm; Receive the original address, and interleave the original address according to the first sub-hash interleaving algorithm to generate the first hash address; Receive the original address, and interleave the original address according to the second sub-hash interleaving algorithm to generate the second hash address; The first hash address and the second hash address are concatenated to form the intermediate address.

3. The joint debugging method for the multi-level hash interleaving module according to claim 2, characterized in that, Also includes: Receive the original address, obtain the high N bits of the original address, and perform an XOR or XNOR operation on the high N bits to generate the first hash address.

4. The joint debugging method for the multi-level hash interleaving module according to claim 2, characterized in that, Also includes: Receive the original address and compare it with the capacity threshold; If the original address is less than or equal to the capacity threshold, obtain the lower M bits of the original address, perform a flip logic operation on the original address, and generate a second hash address; If the original address is greater than the capacity threshold, the lower M bits of the original address are obtained and used directly as the second hash address.

5. The joint debugging method for a multi-level hash interleaving module according to claim 1, characterized in that, The bit width of the intermediate address is the same as the bit width of the original address.

6. The joint debugging method for a multi-level hash interleaving module according to claim 1, characterized in that, Also includes: Based on business requirements, obtain the target address ratio and tolerance value for each storage region; Count the total number of the final addresses; Based on the address range of each final address, the final address is mapped to the corresponding storage area, and the actual number of final addresses corresponding to each storage area is counted. Calculate the actual address ratio for each storage region, where the actual address ratio is the ratio of the number of actual addresses in each storage region to the total number of addresses; The verification results are obtained based on the actual address ratio, the target address ratio, and the tolerance value.

7. The joint debugging method for a multi-level hash interleaving module according to claim 6, characterized in that, Also includes: Determine whether the absolute difference between the actual address ratio and the target address ratio of each storage region exceeds the tolerance value; If the absolute difference of all storage regions does not exceed the tolerance value, then the verification result meets the business requirements. If the absolute difference of at least one storage region exceeds the tolerance value, the verification result does not meet the business requirements. The weight of the storage region whose absolute difference exceeds the tolerance value is increased to correct the second hash interleaving algorithm.

8. A joint debugging system for a multi-level hash interleaving module, characterized in that, include: The first hash interleaving module is used to receive an address segment to be interleaved, wherein the address segment to be interleaved includes multiple original addresses, and each of the original addresses is interleaved according to the first hash interleaving algorithm to generate an intermediate address; The second hash interleaving module is used to interleave each of the intermediate addresses according to the second hash interleaving algorithm to generate the final address; The logic conversion module is used to receive business requirements and convert them into verification codes, and then verify multiple final addresses according to the verification codes to obtain verification results. If the verification result does not meet the business requirements, the iteration control module modifies the second hash interleaving algorithm, re-obtains multiple final addresses and verifies the results according to the modified second hash interleaving algorithm, until the verification result meets the business requirements.

9. A joint debugging device for a multi-level hash interleaving module, characterized in that, include: At least one processor; And a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the processor for performing the joint debugging method of the multi-level hash interleaving module according to any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it causes the computer to perform the joint debugging method of the multi-level hash interleaving module as described in any one of claims 1 to 7.

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