Semiconductor structure and manufacturing method thereof

Abstract

A semiconductor structure includes a first dielectric layer, a second dielectric layer, a landing pad, and a contact plug. The second dielectric layer is disposed on the first dielectric layer. The first dielectric layer has a top surface contacting the second dielectric layer, and the top surface is an uneven top surface. The landing pad is embedded in the first dielectric layer. The contact plug penetrates through the second dielectric layer and a portion of the first dielectric layer directly contacts the contact plug. The semiconductor structure can avoid the formation of an overlarge critical dimension.

Description

Technical Field

[0001] This invention relates to a semiconductor structure and a method for manufacturing the semiconductor structure. More specifically, this invention relates to a semiconductor structure having a container capable of self-aligning to a landing pad and a method for manufacturing the same. Background Technology

[0002] The capacitance of memory nodes in dynamic random access memory (DRAM) is crucial to their performance. Insufficient capacitance leads to shorter refresh times and insufficient voltage differentials during data retrieval. Therefore, a capacitor-over-bitline (COB) architecture has been proposed to eliminate limitations on the size and shape of memory nodes. This configuration places memory nodes on the bitline instead of between multiple layers, meaning that multiple memory nodes are not flat and are designed in a three-dimensional configuration.

[0003] However, the addition of cell-on-board (COB) architectures increases the number of memory nodes on the bit line, thus requiring memory node contact holes with a higher aspect ratio due to the increased distance between the substrate source and the memory node. Space efficiency becomes even more critical as the design scale for highly integrated memory devices shrinks from approximately 1 mm in the 1 Mbit-grade DRAM generation to 0.15 mm in the 1 Gbit-grade DRAM generation. Using landing pads instead of etching memory node contact holes has been proposed as a remedy.

[0004] In highly integrated devices, an interlayer pathway, referred to in the art as a "plug" or "stud," is typically included for electrical coupling between various active components and transmission lines. To facilitate plug alignment, a "landing pad" is formed at the bottom, serving as a positioning point for the plug as it passes through the upper layer. The landing pad connects to the underlying circuitry or interconnects and is typically made of metal. Therefore, the manufacturing process for plugs or studs is quite complex.

[0005] Therefore, an improved method is needed for semiconductor memory devices with metal emboli or landing pads. Furthermore, a DRAM device with a high aspect ratio (i.e., the ratio of aperture height to its width) is needed to minimize signal transmission delay. Summary of the Invention

[0006] This invention provides a semiconductor structure comprising a first dielectric layer, a second dielectric layer, a landing pad, and a contact plug. The second dielectric layer is disposed on the first dielectric layer, wherein the first dielectric layer has a top surface that contacts the second dielectric layer, and the top surface is an uneven surface. The landing pad is embedded in the first dielectric layer. The contact plug penetrates the second dielectric layer, and a portion of the first dielectric layer directly contacts the contact plug.

[0007] In some embodiments, the uneven top surface includes a recess, and the sidewalls of the recess are convex.

[0008] In some embodiments, the uneven top surface includes two highest points, a lowest point located between the two highest points, and a connection surface connecting each of the two highest points to the lowest point.

[0009] In some embodiments, the connecting surface is a curved surface.

[0010] In some embodiments, the uneven top surface includes a contact surface that contacts the contact plug, and the contact surface is an inclined surface.

[0011] In some embodiments, the material of the first dielectric layer is different from the material of the second dielectric layer.

[0012] In some embodiments, the first dielectric layer includes silicon nitride, silicon oxynitride, silicon carbonitride, or a combination thereof.

[0013] In some embodiments, the second dielectric layer comprises borosilicate glass, silicon dioxide, phosphosilicate glass, fluorosilicate glass, organosilicon glass, or a combination thereof.

[0014] In some embodiments, the contact plug is substantially vertically aligned with the landing pad.

[0015] This invention provides a method for manufacturing a semiconductor structure, comprising the following steps: forming a plurality of landing pads spaced apart from each other; depositing a first dielectric layer on the landing pads; forming a sacrificial layer on the first dielectric layer such that the top surface of the sacrificial layer is flush with the highest top surface of the first dielectric layer; forming a plurality of openings in the first dielectric layer to expose the landing pads; removing the sacrificial layer; forming a second dielectric layer covering the first dielectric layer and the landing pads; and forming a plurality of contact plugs penetrating the second dielectric layer and directly contacting the landing pads through the openings.

[0016] In some embodiments, after the first dielectric layer is deposited on the landing pad, the first dielectric layer has an uneven top surface.

[0017] In some embodiments, the uneven top surface is a wavy surface.

[0018] In some embodiments, the uneven top surface includes a plurality of highest points and a plurality of lowest points, each of the highest points corresponding to a landing pad, and each of the lowest points located between any two adjacent highest points.

[0019] In some embodiments, forming a sacrificial layer on a first dielectric layer such that the top surface of the sacrificial layer is flush with the highest top surface of the first dielectric layer includes: depositing a sacrificial layer over the first dielectric layer; and planarizing the sacrificial layer.

[0020] In some embodiments, the material of the first dielectric layer is different from the material of the second dielectric layer.

[0021] In some embodiments, the second dielectric layer comprises borosilicate glass, silicon dioxide, phosphosilicate glass, fluorosilicate glass, organosilicon glass, or a combination thereof.

[0022] In some embodiments, the first dielectric layer includes silicon nitride, silicon oxynitride, silicon carbonitride, or a combination thereof.

[0023] In some embodiments, each of the openings has an upper width and a lower width that is narrower than the upper width.

[0024] In some embodiments, each contact plug is substantially vertically aligned with a corresponding one of the landing pads.

[0025] Therefore, through the semiconductor structure and manufacturing method of the present invention, the contact plug can be automatically aligned with the landing pad, thereby avoiding the problems of increased resistance and / or capacitor leakage.

[0026] The foregoing has provided a fairly broad overview of the technical features and advantages of the present invention, enabling a better understanding of the detailed description of the invention below. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same objectives as the present invention through modifications or designs of other structures or processes. Those skilled in the art will also understand that such equivalent constructions do not depart from the spirit and scope of the invention as defined by the appended claims. Attached Figure Description

[0027] The present invention can be more fully understood by reading the following detailed description of the embodiments and referring to the accompanying drawings.

[0028] Figure 1 This is a schematic cross-sectional view of a semiconductor structure according to various embodiments of the present invention.

[0029] Figures 2 to 4 This is a schematic cross-sectional view of a semiconductor structure according to various embodiments of the present invention during an intermediate stage of the manufacturing process.

[0030] Figure 5 This is a schematic cross-sectional view of a semiconductor structure according to various embodiments of the present invention. Detailed Implementation

[0031] The embodiments or examples of the disclosed content shown in the accompanying drawings are described in a specific language. It should be understood that this is not intended to limit the scope of the invention. Any variations or modifications to the embodiments and any further applications of the principles described herein are to be apparent to those skilled in the art. Component symbols may be repeated in various embodiments, but even if they have the same component symbols, features in one embodiment are not necessarily used in another embodiment.

[0032] It should be understood that although the terms "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections should not be limited to these terms. These terms are only used to distinguish an element, component, region, layer, or section from another region, layer, or section. Therefore, the first element, component, region, layer, or section described below may be referred to as a second element, component, region, layer, or section without departing from the teachings of the inventive concept of this invention.

[0033] The terminology used in this invention is for the purpose of describing specific exemplary embodiments only and is not intended to limit the scope of the invention. As used herein, the singular forms “a” and “described” are also used to include the plural forms, unless otherwise expressly indicated herein. It should be understood that the word “comprising” as used in the specification refers specifically to the presence of the stated feature, integer, step, operation, element, or component, but does not exclude the presence of one or more other features, integers, steps, operations, elements, components, or groups thereof.

[0034] As the integration of semiconductor memory devices such as Dynamic Random Access Memory (DRAM) increases, design rules and manufacturing margins are typically reduced. Even with reduced margins, capacitor values ​​must still be maintained to ensure the proper operation of DRAM devices.

[0035] To provide suitable capacitance, a three-dimensional configuration capacitor was developed to improve capacitance per unit area. Within this structure, trench capacitors, stacked capacitors, and trench-stacked combination capacitors were proposed. Stacked capacitors are widely used due to their use of conventional manufacturing processes. In particular, stacked capacitors employing capacitors over bit lines (COB) are the most widely used because they can easily increase the effective area of ​​the capacitor.

[0036] To achieve more powerful functionality, current industry demands are driving continuous increases in the capacity of single semiconductor wafers. The trend towards increased circuit density is achieved by increasing the miniaturization of individual components, the number of surface layers, and the depth of contact openings between surface layers. Unfortunately, despite simplified design rules, improvements in interlayer alignment (i.e., the alignment of points between adjacent surface layers) have not been as rapid. The problem is that very deep contact openings often have a taper, which further significantly reduces alignment tolerances.

[0037] Therefore, continuous improvement of the contact structure is needed, including the formation of contact plugs and contact openings, to improve the alignment accuracy between semiconductor layers. This invention provides a semiconductor structure and its manufacturing method for achieving self-alignment of the contact plug and landing pad, thereby reducing alignment errors, avoiding capacitor leakage, and further improving the performance of the semiconductor structure.

[0038] Figure 1 This is a schematic cross-sectional view of a semiconductor structure 10 according to various embodiments of the present invention. (See also...) Figure 1 The semiconductor structure 10 includes a first dielectric layer 110, a second dielectric layer 120, a landing pad 130, and a contact plug 140. In some embodiments, the first dielectric layer 110 includes silicon nitride, silicon oxynitride, silicon carbon nitride, or a combination thereof. The semiconductor structure 10 can be applied to, for example, a cell array of dynamic random access memory (DRAM), but the invention is not limited thereto.

[0039] Please continue reading. Figure 1 A second dielectric layer 120 is disposed on the first dielectric layer 110. In some embodiments, the material of the second dielectric layer 120 is different from the material of the first dielectric layer 110. In some embodiments, the second dielectric layer 120 includes borophosphosilicate glass, silicon oxide, phosphosilicate glass, fluorosilicate glass, organosilicate glass, or a combination thereof.

[0040] Specifically, the first dielectric layer 110 has a top surface 112 that contacts the second dielectric layer, and the top surface 112 is an uneven top surface 112. The uneven top surface 112 of the first dielectric layer 110 has a plurality of highest points 115 and a plurality of lowest points 114. In some embodiments, the uneven top surface 112 includes recesses, and the sidewalls of the recesses are convex surfaces. In some embodiments, the uneven top surface 112 of the first dielectric layer 110 has a petal-like shape.

[0041] Please continue reading. Figure 1 Landing pad 130 is embedded in the first dielectric layer 110. Landing pad 130 can electrically connect a bitline structure or a wordline structure (not shown) beneath it to contact plug 140. In some embodiments, landing pad 130 comprises a conductive material, such as tungsten (W), titanium nitride (TiN), polycrystalline silicon, titanium (Ti), ruthenium (Ru), tungsten nitride (WN), tantalum (Ta), copper (Cu), molybdenum (Mo), platinum (Pt), nickel (Ni), cobalt (Co), aluminum (Al), and tantalum nitride (TaN), but the invention is not limited to these examples. In some embodiments, landing pad 130 may comprise a void-free structure (not shown).

[0042] Please continue reading. Figure 1The contact plug 140 extends through the second dielectric layer 120, and a portion of the first dielectric layer 110 directly contacts the landing pad 130. The contact plug 140 can electrically connect a capacitor structure (not shown) coupled thereto to the landing pad 130. In some embodiments, the contact plug 140 is substantially perpendicularly aligned to the landing pad 130. In some embodiments, the contact plug 140 may be made of a conductive material, such as tungsten (W), titanium nitride (TiN), polycrystalline silicon, titanium (Ti), ruthenium (Ru), tungsten nitride (WN), tantalum (Ta), tantalum nitride (TaN), and aluminum (Al), but the invention is not limited to these examples. In some exemplary embodiments, the contact plug 140 may include multiple layers. In some embodiments, the contact plug 140 has a uniform width. In other embodiments, the contact plug 140 has a cross-sectional shape that is wider at the top and narrower at the bottom.

[0043] Please note now. Figure 1 In some embodiments, the uneven top surface 112 of the first dielectric layer 110 includes two highest points 115, a lowest point 114 located between the two highest points 115, and a connection surface 116 connecting each of the two highest points 115 and the lowest point 114. In some embodiments, the connection surface 116 is a curved surface. In some embodiments, the uneven top surface 112 of the first dielectric layer 110 has a contact surface 117 that contacts the contact plug 140, and the contact surface 117 is an inclined surface rather than a curved surface.

[0044] In other embodiments, the semiconductor structure 10 may further include a bit line structure (not shown) disposed below the landing pad 130 and a capacitor (not shown) electrically coupled to the contact plug 140.

[0045] Another aspect of the present invention provides for manufacturing such as Figure 1 The method of the semiconductor structure 10 shown. Figures 2 to 4 This is a schematic cross-sectional view of a semiconductor structure according to various embodiments of the present invention during an intermediate stage of the manufacturing process. Figure 5 This is a schematic cross-sectional view of a semiconductor structure according to various embodiments of the present invention.

[0046] See Figure 2Multiple landing pads 130 spaced apart from each other are formed. In some embodiments, the formation process of the landing pads 130 may include photolithography, etching, and deposition processes known in the art. In some embodiments, the landing pads 130 may include a void-free structure (not shown). To achieve a void-free structure, forming the landing pads 130 may require several deposition and etching processes. In some embodiments, a deposition / etch / deep process is used to deposit material of the landing pads 130 into the gap (not shown) between two adjacent bit line structures (not shown). The deposition / etch / deep process includes depositing material of the landing pads 130, then etching away some of the material of the landing pads 130 to enlarge the opening of the gap (not shown), and then redepositing material of the landing pads 130. In some embodiments, the deposition temperature used in the deposition process ranges from about 280°C to about 320°C. For example, the deposition temperature used in the deposition process may be 280°C, 290°C, 300°C, 310°C, or 320°C. The etching process following the deposition process includes the use of any suitable dry etching process and / or wet etching process. The material of the landing pad 130 can be stacked with a variety of materials including metal nitrides or metals, such as tungsten (W), titanium nitride (TiN), polycrystalline silicon, titanium (Ti), ruthenium (Ru), tungsten nitride (WN), tantalum (Ta), copper (Cu), molybdenum (Mo), platinum (Pt), nickel (Ni), cobalt (Co), aluminum (Al), and / or tantalum nitride (TaN).

[0047] See Figure 2A first dielectric layer 110 is deposited on the landing pad 130. In some embodiments, after the first dielectric layer 110 is deposited on the landing pad 130, the first dielectric layer 110 has an uneven top surface 112. Specifically, the undulations of the first dielectric layer 110 are consistent with the undulations of the landing pad 130, and can closely cover the landing pad 130. In some embodiments, the uneven top surface 112 of the first dielectric layer 110 is a wavy surface. In other words, the uneven top surface 112 of the first dielectric layer 110 includes a plurality of peaks 113, a plurality of troughs 114 alternating with the peaks 113, and a connecting surface 116 connecting adjacent peaks 113 and troughs 114. In some embodiments, the connecting surface 116 is a curved surface. In some embodiments, each peak 113 corresponds to each landing pad 130, and each trough 114 is located between any two landing pads 130. In some embodiments, the distance D from the crest 113 of the uneven top surface 112 to the top surface 132 of the landing pad 130 is about 25 μm to about 35 μm.

[0048] In some embodiments, the first dielectric layer 110 comprises silicon nitride, silicon oxynitride, silicon carbon nitride, or a combination thereof. In some embodiments, the first dielectric layer 110 may be formed via a deposition process. In some embodiments, the deposition process includes chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin-coating, or other suitable processes.

[0049] See Figure 2A sacrificial layer 210 is formed on and covers the first dielectric layer 110. In some embodiments, the sacrificial layer 210 may comprise a patternable carbon-containing material, such as an organic polymer, like polyimide. In other embodiments, the sacrificial layer 210 may comprise a suitable non-photosensitive patternable material. The sacrificial layer 210 preferably comprises a material different from the first dielectric layer 110. In some embodiments, the sacrificial layer 210 may be formed via a deposition process. In some embodiments, the deposition process includes chemical vapor deposition (CVD), physical vapor deposition (PVD), flowable chemical vapor deposition (FCVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), spin-coating, or other suitable processes.

[0050] See Figure 3 The sacrificial layer 210 is planarized to expose the highest top surface of the first dielectric layer 110. More specifically, the top surface of the sacrificial layer 210 is flush with the highest top surface of the first dielectric layer 110 after planarization. In some embodiments, the planarization step can be performed by chemical mechanical polishing (CMP), an etch-back process, or an oxide buffing process.

[0051] See Figure 4 Multiple openings 230 are formed in the first dielectric layer 110 to expose the landing pad 130. In some embodiments, each of the multiple openings 230 has an upper width 231 and a lower width 232, with the lower width 232 being narrower than the upper width 231. In some embodiments, the openings 230 can be formed in the first dielectric layer 110 using a dry etching process or a wet etching process to expose the landing pad 130. It is understood that the peaks 113 of the uneven top surface 112 of the first dielectric layer 110 are removed, but the troughs 114 are not removed, so the remaining portion of the uneven top surface 112 of the first dielectric layer 110 will include multiple highest points 115 and troughs 114 (or multiple lowest points 114). Furthermore, the sidewalls of the openings 230 are etched to form relatively flat, sloping surfaces.

[0052] See Figure 4 Remove the sacrificial layer 210. In some embodiments, the remaining sacrificial layer 210 may be removed by an etching process, a stripping process, or an ashing process.

[0053] See Figure 5 A second dielectric layer 120 is formed to cover the first dielectric layer 110 and the landing pad 130. In some embodiments, the material of the second dielectric layer 120 is different from the material of the first dielectric layer 110. In some embodiments, the second dielectric layer 120 includes borophosphosilicate glass, silicon oxide, phosphosilicate glass, fluorosilicate glass, organosilicate glass, or a combination thereof. In some embodiments, the second dielectric layer 120 may be formed via a deposition process. In some embodiments, the deposition process includes chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin-coating, or other suitable processes. In some embodiments, the thickness of the second dielectric layer 120 is from about 1000 nm to about 1200 nm.

[0054] See Figure 5 A plurality of contact plugs 140 are formed through the second dielectric layer 120 and directly contact the landing pad 130 through the opening 230. In some embodiments, each of the plurality of contact plugs 140 is substantially vertically aligned with the corresponding landing pad 130. In some embodiments, each of the plurality of contact plugs 140 has an aspect ratio of about 35 to 40.

[0055] More specifically, a plurality of openings 240 are formed by an etching process that penetrates the second dielectric layer 120 and a portion of the first dielectric layer 110 to expose the corresponding landing pads 130. In some embodiments, the aspect ratio of the openings 240 is approximately 35 to 40. In some embodiments, each opening 240 has a uniform width. In other embodiments, the cross-sectional shape of each opening 240 may be wider at the top and narrower at the bottom.

[0056] The conductive material is then filled into the opening 240 to form a plurality of contact plugs 140 that directly contact the landing pad 130, thereby forming a semiconductor structure 50. In some embodiments, the conductive material may include tungsten (W), titanium nitride (TiN), polycrystalline silicon, titanium (Ti), ruthenium (Ru), tungsten nitride (WN), tantalum (Ta), copper (Cu), molybdenum (Mo), platinum (Pt), nickel (Ni), cobalt (Co), aluminum (Al), and tantalum nitride (TaN), but the invention is not limited to these examples. In some embodiments, the contact plugs 140 have a uniform width. In other embodiments, the cross-sectional shape of the contact plugs 140 is wider at the top and narrower at the bottom.

[0057] A conventional semiconductor structure may include a first dielectric layer, a second dielectric layer, a landing pad, and a contact plug, similar to the semiconductor structure of the present invention. Specifically, the second dielectric layer is disposed on the first dielectric layer. The landing pad is embedded in the first dielectric layer. The contact plug penetrates the second dielectric layer and a portion of the first dielectric layer, and is in direct contact with the landing pad. Notably, the top surface of the first dielectric layer is substantially a flat surface. In some embodiments, the first dielectric layer comprises silicon nitride, silicon oxynitride, silicon carbonitride, or a combination thereof. In some embodiments, the second dielectric layer comprises borosilicate glass, silicon dioxide, phosphosilicate glass, fluorosilicate glass, organosilicon glass, or a combination thereof.

[0058] During the formation of the contact plug, because the material of the first dielectric layer differs from that of the second dielectric layer, and the etchant's selectivity ratio for the second and first dielectric layers is approximately 1:9, the etching time is extended to further etch the first dielectric layer. This results in an excessively large critical dimension (CD) of the opening in the intended contact plug. Consequently, leakage current issues arise after the contact plug is formed, affecting the operational reliability of conventional semiconductor structures. On the other hand, shortening the etching time to avoid an excessively large critical dimension (CD) after etching leads to an increased resistance in the subsequently formed contact plug.

[0059] Therefore, in various embodiments of the present invention, the first dielectric layer is etched before forming the opening of the contact plug, thereby shortening the etching time for forming the opening of the contact plug and avoiding the formation of excessively large critical dimensions. Furthermore, various embodiments of the present invention can also provide a self-aligned manufacturing method that avoids misalignment.

[0060] Although the invention has been described in considerable detail with reference to certain embodiments, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

[0061] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the invention without departing from the scope or spirit of the invention. In view of the foregoing, the present invention is intended to cover modifications and variations of the invention falling within the appended claims.

[0062] [Symbol Explanation] 10: Semiconductor Structure 110: First dielectric layer 112: Top surface, uneven top surface 113: Peak 114: Lowest point, trough 115: Highest point 116: Connecting surface 117: Contact Surface 120: Second dielectric layer 130: Landing mat 132: Top surface 140: Contact embolism 210: Sacrificial Layer 230: Opening 231: Top Width 232: Bottom width 240: Opening 50: Semiconductor Structure D: Distance.

Claims

1. A semiconductor structure, characterized in that, include: First dielectric layer; A second dielectric layer is disposed on the first dielectric layer, wherein the first dielectric layer has a top surface that contacts the second dielectric layer, and the top surface is an uneven top surface; The landing pad is embedded in the first dielectric layer; as well as A contact plug penetrates the second dielectric layer and a portion of the first dielectric layer directly contacts the contact plug.

2. The semiconductor structure according to claim 1, wherein the uneven top surface includes a recess, and the sidewalls of the recess are convex.

3. The semiconductor structure of claim 1, wherein the uneven top surface comprises two highest points, a lowest point located between the two highest points, and a connection surface connecting each of the two highest points to the lowest point.

4. The semiconductor structure according to claim 3, wherein the connection surface is a curved surface.

5. The semiconductor structure according to claim 1, wherein the uneven top surface includes a contact surface that contacts the contact plug, and the contact surface is an inclined surface.

6. The semiconductor structure according to claim 1, wherein the material of the first dielectric layer is different from the material of the second dielectric layer.

7. The semiconductor structure of claim 6, wherein the first dielectric layer comprises silicon nitride, silicon oxynitride, silicon carbonitride, or a combination thereof.

8. The semiconductor structure according to claim 6, wherein the second dielectric layer comprises borosilicate glass, silicon dioxide, phosphosilicate glass, fluorosilicate glass, organosilicon glass, or a combination thereof.

9. The semiconductor structure of claim 1, wherein the contact plug is substantially perpendicularly aligned with the landing pad.

10. A method for manufacturing a semiconductor structure, characterized in that, include: Multiple landing pads are formed, spaced apart from each other; A first dielectric layer is deposited on the plurality of landing pads; A sacrificial layer is formed on the first dielectric layer such that the top surface of the sacrificial layer is flush with the highest top surface of the first dielectric layer; Multiple openings are formed in the first dielectric layer to expose the multiple landing pads; Remove the sacrificial layer; A second dielectric layer is formed to cover the first dielectric layer and the plurality of landing pads; as well as Multiple contact plugs are formed that penetrate the second dielectric layer and make direct contact with the multiple landing pads through the multiple openings.

11. The method of manufacturing a semiconductor structure according to claim 10, wherein after depositing the first dielectric layer on the plurality of landing pads, the first dielectric layer has an uneven top surface.

12. The method for manufacturing a semiconductor structure according to claim 11, wherein the uneven top surface is a wavy surface.

13. The method of manufacturing a semiconductor structure according to claim 11, wherein the uneven top surface includes a plurality of highest points and a plurality of lowest points, each of the plurality of highest points corresponding to one of the landing pads, and each of the plurality of lowest points being located between any two adjacent of the plurality of highest points.

14. The method of manufacturing a semiconductor structure according to claim 10, wherein forming the sacrificial layer on the first dielectric layer such that the top surface of the sacrificial layer is flush with the highest top surface of the first dielectric layer comprises: The sacrificial layer is deposited to cover the first dielectric layer; as well as Flatten the sacrificial layer.

15. The method for manufacturing a semiconductor structure according to claim 10, wherein the material of the first dielectric layer is different from the material of the second dielectric layer.

16. The method for manufacturing a semiconductor structure according to claim 15, wherein the second dielectric layer comprises borosilicate glass, silicon dioxide, phosphosilicate glass, fluorosilicate glass, organosilicon glass, or a combination thereof.

17. The method for manufacturing a semiconductor structure according to claim 15, wherein the first dielectric layer comprises silicon nitride, silicon oxynitride, silicon carbonitride, or a combination thereof.

18. The method of manufacturing a semiconductor structure according to claim 10, wherein each of the plurality of openings has an upper width and a lower width narrower than the upper width.

19. The method of manufacturing a semiconductor structure according to claim 10, wherein each of the plurality of contact plugs is substantially perpendicularly aligned with a corresponding one of the plurality of landing pads.

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