Three-dimensional memory and preparation method thereof

Abstract

The invention provides a three-dimensional memory and a preparation method thereof, relates to the technical field of semiconductor chips, and aims to improve the yield of the three-dimensional memory. The preparation method comprises the following steps: preparing a semiconductor structure; removing the part, covering the side wall of the grid line gap, in the second dielectric layer; forming a filling structure in the grid line gap; removing the substrate; and forming a source layer on one side of the laminated structure from which the substrate is removed. The semiconductor structure comprises a substrate and a laminated structure arranged on the substrate. The laminated structure comprises first dielectric layers and gate layers which are alternately arranged. The semiconductor structure further comprises a gate line gap and a second dielectric layer, the gate line gap penetrates through the laminated structure in the direction perpendicular to the substrate and extends into the substrate, and the second dielectric layer is located between the first dielectric layer and the gate layer and covers the side wall of the gate line gap. The invention is used for preparing the three-dimensional memory.

Description

[0001] This application is a divisional application of the Chinese Invention Patent Application with the application date of November 15, 2021, the application number of 202111348316.6, and the application title of "Three-dimensional memory and method of manufacturing the same". TECHNICAL FIELD

[0002] The present disclosure relates to the technical field of semiconductor chip, and particularly relates to a three-dimensional memory and a method of manufacturing the same. BACKGROUND

[0003] As the feature size of the memory cell approaches the lower limit of the process, the planar process and manufacturing technology become challenging and costly, which causes the storage density of the 2D or planar NAND flash memory to approach the upper limit.

[0004] To overcome the limitations of the 2D or planar NAND flash memory, the industry has developed a memory with a three-dimensional structure (3D NAND) to improve the storage density by arranging the memory cells three-dimensionally above the substrate.

[0005] How to improve the reliability of the preparation process of the three-dimensional memory and improve the yield of the three-dimensional memory is a problem to be solved at present. SUMMARY

[0006] Embodiments of the present disclosure provide a three-dimensional memory and a method of manufacturing the same.

[0007] To achieve the above-mentioned purpose, embodiments of the present disclosure adopt the following technical solutions: In one aspect, a method of manufacturing a three-dimensional memory is provided. The method includes: preparing a semiconductor structure; removing a portion of a second dielectric layer covering a side wall of a gate line gap; forming a filling structure in the gate line gap; removing a substrate; and forming a source layer on a side of the stack structure opposite to the substrate. The semiconductor structure includes a substrate, a stack structure, and a second dielectric layer. The stack structure includes a plurality of first dielectric layers and a plurality of gate layers arranged alternately. The second dielectric layer is arranged between the gate layers and the first dielectric layers. The semiconductor structure further includes a gate line gap, which penetrates the stack structure in a direction perpendicular to the substrate and extends into the substrate. The second dielectric layer also covers the side wall of the gate line gap.

[0008] In some embodiments, between adjacent first dielectric layers in a direction perpendicular to the substrate, there is a recess. Before removing the portion of the second dielectric layer covering the side wall of the gate line gap, the method further includes: forming a protective layer in the recess. The protective layer covers the side surface of the gate layer exposed by the gate line gap.

[0009] In some embodiments, forming a protective layer within the recess includes: forming an initial protective layer within the grid line slot, the initial protective layer filling the recess and covering the sidewalls and bottom of the grid line slot; removing the portion of the initial protective layer covering the sidewalls and bottom of the grid line slot, retaining the portion filling the recess, to form the protective layer.

[0010] In some embodiments, the second dielectric layer further covers the surface of the stacked structure remote from the substrate and the bottom of the gate wire gaps. Before forming a protective layer within the recess, the fabrication method further includes removing a portion of the second dielectric layer that covers the surface of the stacked structure remote from the substrate and the bottom of the gate wire gaps.

[0011] In some embodiments, the fabrication of the semiconductor structure includes: forming an initial stacked structure on the substrate; forming a gate line gap penetrating the initial stacked structure along a direction perpendicular to the substrate; removing a gate sacrificial layer in the initial stacked structure through the gate line gap to form a gate layer gap communicating with the gate line gap; and sequentially forming a second dielectric layer and a gate layer within the gate layer gap through the gate line gap. The initial stacked structure includes a plurality of alternating first dielectric layers and a plurality of gate sacrificial layers.

[0012] In some embodiments, forming the gate layer includes: forming an initial gate layer that fills the gate layer gap and covers the sidewalls of the gate line gap and the surface of the stacked structure away from the substrate; removing the portion of the initial gate layer that covers the sidewalls of the gate line gap and the surface of the stacked structure away from the substrate; and removing the portion of the initial gate layer that fills the gate layer gap near the gate line gap to form the gate layer.

[0013] In some embodiments, between forming the second dielectric layer and forming the gate layer, the fabrication method further includes: forming an initial adhesive layer within the gate layer gap, the initial adhesive layer covering the second dielectric layer; and during the process of removing the initial gate layer to form the gate layer, removing the portion of the initial adhesive layer exposed by the gate layer to form an adhesive layer.

[0014] In some embodiments, forming a filling structure within the grid line slots includes: forming an isolation layer within the grid line slots, the isolation layer covering the sidewalls of the grid line slots to form a filling gap; and forming a filling portion within the filling gap.

[0015] In some embodiments, the semiconductor structure further includes a third dielectric layer and a semiconductor layer disposed between the substrate and the stacked structure, the third dielectric layer being closer to the substrate than the semiconductor layer. Removing the substrate includes: etching the substrate down to the third dielectric layer to expose a portion of the isolation layer of the filled structure extending into the substrate; between removing the substrate and forming the source layer, the fabrication method further includes: etching the exposed portions of the third dielectric layer and the isolation layer down to the semiconductor layer to expose a filling portion of the filled structure; the source layer covers the exposed portion of the filling portion and contacts the filling portion.

[0016] In some embodiments, the semiconductor structure further includes a channel structure extending into the substrate, the channel structure including a channel via and a functional layer and a channel layer sequentially formed within the channel via. Etching the substrate to the third dielectric layer further exposes portions of the functional layer of the channel structure extending into the substrate. During the etching of the portions exposed by the third dielectric layer and the isolation layer to the semiconductor layer, the exposed portions of the functional layer are also etched to expose the portions of the channel layer extending into the substrate. The source layer also covers the exposed portions of the channel layer and is electrically connected to the channel layer.

[0017] In some embodiments, the materials of the third dielectric layer and the isolation layer of the filling mechanism both include silicon oxide; the materials of the semiconductor layer and the filling portion of the filling structure both include polycrystalline silicon.

[0018] In some embodiments, the material of the second dielectric layer includes a high dielectric constant material.

[0019] On the other hand, a method for fabricating a three-dimensional memory is provided. The method includes: providing a substrate; forming an initial stacked structure on the substrate; forming a gate line gap; removing a gate sacrificial layer in the initial stacked structure through the gate line gap to form a gate layer gap communicating with the gate line gap; forming a second dielectric layer; filling the initial gate layer, the initial gate layer filling the gate layer gap and covering the sidewalls of the gate line gap; removing a portion of the initial gate layer covering the sidewalls of the gate line gap and a portion of the initial gate layer near the gate line gap to form a recess; forming a protective layer within the recess, the protective layer covering the side of the gate layer exposed by the gate line gap; removing a portion of the second dielectric layer covering the sidewalls of the gate line gap; forming a filling structure within the gate line gap; removing the substrate; and forming a source layer on the side of the stacked structure where the substrate has been removed. The initial stacked structure includes a plurality of alternately arranged first dielectric layers and a plurality of gate sacrificial layers. The gate line gap penetrates the initial stacked structure in a direction perpendicular to the substrate and extends into the substrate. The second dielectric layer covers the sidewalls of the gate layer gap and the sidewalls of the gate line slot.

[0020] The method for fabricating a three-dimensional memory provided in the above embodiments of this disclosure includes removing a portion of the sidewall of the second dielectric layer covering the gate line gaps. This allows the first dielectric layer to directly contact the filling structure. The bonding force between the first dielectric layer and the filling structure is greater than the bonding force between the first dielectric layer and the second dielectric layer, thereby reducing the risk of gaps forming between the first dielectric layer and the filling structure, reducing damage to the stacked structure (first dielectric layer) during subsequent substrate removal, improving the reliability of the three-dimensional memory fabrication process, and increasing the yield of the three-dimensional memory.

[0021] In another aspect, a three-dimensional memory is provided. The three-dimensional memory includes a source layer, a stacked structure, a channel structure, a second dielectric layer, and a gate isolation structure. The stacked structure is disposed on one side of the source layer and includes multiple overlapping first dielectric layers and multiple gate layers. Along a direction perpendicular to the source layer, the channel structure penetrates the stacked structure and extends into the source layer. The channel structure includes a functional layer and a semiconductor layer, and the semiconductor layer and the source layer are electrically connected. The second dielectric layer is disposed between the gate layers and the first dielectric layers. Along a direction perpendicular to the source layer, the gate isolation structure penetrates the stacked structure and extends into the source layer, and the gate isolation structure is in contact with the first dielectric layer.

[0022] In some embodiments, a recess is formed between adjacent first dielectric layers along a direction perpendicular to the substrate. The gate isolation structure fills the recess.

[0023] In some embodiments, the material of the second dielectric layer includes a high dielectric constant material.

[0024] It is understood that the beneficial effects that the three-dimensional memory provided in the above embodiments of this disclosure can achieve can be referred to the beneficial effects that the three-dimensional memory preparation method described above can achieve, and will not be repeated here. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0026] Figure 1 A three-dimensional memory provided in the embodiments of this disclosure; Figure 2 Another three-dimensional memory provided in the embodiments of this disclosure; Figures 3A-3E This is a flowchart illustrating a method for fabricating a three-dimensional memory according to some embodiments; Figures 4A-4L The diagram shows the structural figures corresponding to each step in the fabrication method of a three-dimensional memory according to some embodiments. Figure 5 This is a structural diagram of a three-dimensional memory according to some embodiments; Figure 6 This is a structural diagram of a three-dimensional memory according to some embodiments. Detailed Implementation

[0027] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0028] In the description of this disclosure, it should be understood that the terms "upper", "lower", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0029] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0030] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0031] In describing some embodiments, the term "connection" and its derivative expressions may be used. For example, the term "connection" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0032] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0033] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0034] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0035] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0036] The term "three-dimensional memory" refers to a semiconductor device formed by strings of memory cell transistors (referred to herein as "memory cell strings," such as NAND memory cell strings) arranged in an array on the main surface of a substrate and extending in a direction perpendicular to the substrate. As used herein, the term "perpendicularly" means nominally perpendicular to the main surface of the substrate (i.e., the lateral surface).

[0037] The steps provided in the embodiments of this disclosure are not exclusive, and other steps may be performed before, after, or between any of the steps. Furthermore, some of the steps may be performed simultaneously, or they may be performed in a sequence different from that described in the embodiments.

[0038] Some embodiments of this disclosure provide a three-dimensional memory 100, see [reference] Figure 1 The three-dimensional memory 100 includes a substrate 10 and a third dielectric layer 11, a semiconductor layer 12, and a stacked structure 21 sequentially formed on the substrate 10. The stacked structure 21 includes a first dielectric layer 131 and a gate layer 19 sequentially disposed. The three-dimensional memory 100 also includes a gate line slot 16 extending into the substrate 10, a second dielectric layer 17 disposed between the first dielectric layer 131 and the gate layer 19, and an adhesive layer 18 disposed between the gate layer 19 and the second dielectric layer 17. The second dielectric layer 17 covers the sidewalls of the gate line slot 16.

[0039] In the aforementioned three-dimensional memory 100, during the etching process for removing the substrate 10, the third dielectric layer 11 and the semiconductor layer 12 can be configured as etching stop layers. Specifically, the etching rate of the material of the third dielectric layer 11 can be different from that of the material of the semiconductor layer 12. For example, the material of the third dielectric layer 11 includes silicon oxide, and the material of the semiconductor layer 12 includes polysilicon. The bonding strength between the second dielectric layer 17 and the third dielectric layer 11 and the semiconductor layer 12 is low; under stress, gaps 1001 may even appear between the second dielectric layer 17 and the third dielectric layer 11 and the semiconductor layer 12.

[0040] In the subsequent process of fabricating the three-dimensional memory, the substrate 10 and the third dielectric layer 11 need to be removed sequentially by wet etching from the side of the substrate 10 away from the stacked structure 21. A source layer 24 (e.g., ...) is then formed on the surface exposed after removing the substrate 10 and the third dielectric layer 11 (the side of the semiconductor layer 12 away from the stacked structure 21). Figure 2 (As shown).

[0041] During the process of removing the substrate 10 by wet etching, the etching solution may flow in from the gap and come into contact with the semiconductor layer 12, thereby removing part of the semiconductor layer 12 and exposing part of the first dielectric layer 131.

[0042] During the process of removing the third dielectric layer 11 by wet etching, the etching solution comes into contact with the exposed first dielectric layer 131 and removes part of the exposed first dielectric layer 131, resulting in a groove 1002 appearing on the surface of the first dielectric layer 131.

[0043] A portion of the formed source layer 24 is located within the aforementioned groove 1002. This may result in the formation of... Figure 2 The three-dimensional memory shown has a small gap between the bottom gate layer 191 and the source layer 24, resulting in a low breakdown voltage between them and a risk of short circuit between the gate layer 191 and the source layer 24. This indicates poor fabrication process stability of the aforementioned three-dimensional memory.

[0044] To solve the above problems, see Figure 3A The present disclosure provides a method for fabricating a three-dimensional memory, which includes steps S100 to S500.

[0045] S100: Fabrication of semiconductor structure 100.

[0046] See Figure 3B and Figures 4A-4D In some embodiments, the steps for fabricating the semiconductor structure include steps S110 to S160. Wherein, Figure 3B This is a step-by-step diagram of a semiconductor structure fabrication method; Figures 4A-4D These are cross-sectional views corresponding to each step in the semiconductor structure fabrication method.

[0047] S110: See also Figure 4A The third dielectric layer 11, the semiconductor layer 12, and the initial stacked structure 13 are sequentially formed on the substrate 10.

[0048] In some embodiments, the material of the substrate 10 may include at least one of single-crystal silicon (Si), single-crystal germanium (Ge), III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art.

[0049] In other embodiments, substrate 10 may be a composite substrate. For example, see [link to relevant documentation]. Figure 4A The substrate 10 may include a base 101, and a sacrificial insulating layer 102 and a sacrificial polysilicon layer 103 sequentially formed on the base 101. The material of the base 101 may include at least one of single-crystal silicon (Si), single-crystal germanium (Ge), a III-V compound semiconductor material, a IIVI compound semiconductor material, or other semiconductor materials known in the art. The material of the sacrificial insulating layer 102 may include silicon oxide. The material of the sacrificial polysilicon layer 103 may include polysilicon.

[0050] A third dielectric layer 11 is formed on the substrate 110, and a semiconductor layer 12 is formed on the third dielectric layer 11. It should be understood that both the third dielectric layer 11 and the semiconductor layer 12 can serve as etch stop layers, configured to stop etching at the corresponding film layer during the subsequent step S400 removal of the substrate 10. The materials (etch selectivity ratio) of the third dielectric layer 11 and the semiconductor layer 12 are different so that etching can stop at their interface.

[0051] For example, the third dielectric layer 11 and the semiconductor layer 12 may be formed using one of the following thin film deposition processes: chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). When the substrate 10 includes a substrate 101, a sacrificial insulating layer 102, and a sacrificial polysilicon layer 103, the material of the third dielectric layer 11 may include silicon oxide, and the material of the semiconductor layer 12 may include polysilicon.

[0052] The initial stacked structure 13 includes a plurality of alternating first dielectric layers 131 and a plurality of gate sacrificial layers 132 formed on the semiconductor layer 12. The initial stacked structure 13 may be formed by one or more of CVD, PVD, and ALD.

[0053] In the initial stacked structure 13, the number of stacked layers of the first dielectric layer 131 and the gate sacrificial layer 132 can be 8, 32, 64, 128, etc., and is not limited here. The more layers the initial stacked structure 13 has, the higher the integration density and the more memory cells it forms.

[0054] In some embodiments, the first dielectric layer 131 and the gate sacrificial layer 132 are made of different materials to give them different etching selectivity ratios. During the subsequent step S130, which removes the gate sacrificial layer 132 from the initial stacked structure 130, the first dielectric layer 131 is not etched away. For example, the first dielectric layer 131 may be made of silicon oxide, and the gate sacrificial layer 132 may be made of silicon nitride.

[0055] In some embodiments, the step of fabricating the semiconductor structure further includes S111.

[0056] S111: See also Figure 4B , and construct the channel structure 14.

[0057] Fabricating the channel structure 14 may specifically include: forming a channel hole 141 that penetrates the initial stacked structure 13, the third dielectric layer 11, and the semiconductor layer 12, and extends into the substrate 10. Figure 4A The sidewalls of the channel structure 14 extending vertically; a functional layer 142 and a channel layer 143 are sequentially formed on the sidewalls of the channel hole 141.

[0058] For example, a channel hole 141 can be formed in the initial stacked structure 13 using a dry / wet etching process, with the channel hole 141 extending in a direction perpendicular to the substrate 10. When the substrate 10 includes a substrate 101, a sacrificial insulating layer 102, and a sacrificial polysilicon layer 103, the channel hole 141 can extend to the sacrificial polysilicon layer 103 of the substrate 10, which can serve as an etch stop layer controlling the gouging variation of the channel hole 141. For instance, etching of the channel hole 141 can be stopped by the sacrificial polysilicon layer 103 without allowing the channel hole 141 to extend further into the sacrificial insulating layer 102 and the substrate 101.

[0059] For example, a barrier layer 1421, a charge storage layer 1422, a tunneling layer 1423, and a channel layer 143 can be sequentially formed on the inner wall of the channel hole 141 using one or more processes selected from CVD, PVD, and ALD. The barrier layer 1421, charge storage layer 1422, and tunneling layer 1423 constitute the functional layer 142. An air gap 144 can be formed in the middle of the channel layer 143 to reduce the stress on the channel layer 143.

[0060] The barrier layer 1421, charge storage layer 1422, tunneling layer 1423 and channel layer 143 can be made of silicon oxide, silicon nitride and polysilicon, respectively, to form an "ONOP" structure.

[0061] In some embodiments, fabricating the channel structure 14 may further include forming a channel plug (not shown) at one end of the barrier layer 1421, charge storage layer 1422, tunneling layer 1423, and channel layer 143 away from the substrate 10. The material of the channel plug may be the same as that of the channel layer 143. The channel plug is configured to form the drain of the channel structure 140.

[0062] In some embodiments, forming the channel structure 14 may also include forming a virtual channel structure 15, which is formed in the step region A and serves to provide support for the semiconductor structure 100. The virtual channel structure 15 is made of a dielectric material, such as silicon oxide.

[0063] S120: See Figure 4C A gate line slot 16 is formed through the initial stacked structure 13 along a direction perpendicular to the substrate.

[0064] For example, gate line slots 16 can be formed in the initial stacked structure 13 using a dry / wet etching process. The gate line slots 16 extend in a direction perpendicular to the substrate 10 and extend into the substrate 10. There is a certain distance between the gate line slots 16 and the channel structure 14. The depth to which the gate line slots 16 extend into the substrate 10 can be the same as or different from the depth to which the channel structure 14 extends into the substrate 10.

[0065] S130: See also Figure 4C The gate sacrificial layer 132 in the initial stacked structure 13 is removed through the gate line gap 16 to form a gate layer gap 133 that is connected to the gate line gap 16.

[0066] For example, using the gate line gap 16 as a channel, a wet etching process is used to remove the gate sacrificial layer 132 in the initial stacked structure 13, and a gate layer gap 133 is formed at the location of the gate sacrificial layer 132. Under the support of the channel structure 14 and the virtual channel 15, the first dielectric layer 131 of the initial stacked structure 13 will not collapse into the gate layer gap 133.

[0067] S140: See also Figure 4D A second dielectric layer 17 and a gate layer 19 are sequentially formed within the gate layer gap 133 through the gate line gap 16.

[0068] For example, the second dielectric layer 17 can be formed by thin film deposition processes such as CVD, PVD, and ALD. The second dielectric layer 17 covers the inner wall of the gate layer gap 133, the sidewalls and bottom wall of the gate line slot 16, the surface of the initial stacked structure 13 away from the substrate 10, and the surface of the channel structure 14 exposed by the gate line slot 16. The material of the second dielectric layer 17 may include a material with a high dielectric constant, such as aluminum oxide.

[0069] The gate layer 19 can also be formed by thin film deposition processes such as CVD, PVD, and ALD. The gate layer 19 is located within the gate layer gap 133. The material of the gate layer 19 may include at least one conductive material selected from tungsten, cobalt, copper, aluminum, doped crystalline silicon, or silicides.

[0070] In some embodiments, between forming the second dielectric layer 17 and the gate layer 19, S140 further includes forming an initial adhesive layer within the gate layer gap 133, the initial adhesive layer covering the second dielectric layer 17. Exemplarily, the initial adhesive layer 18 can be formed by a thin-film deposition process such as CVD, PVD, or ALD. The material of the initial adhesive layer 18 may include tantalum nitride or titanium nitride. The initial adhesive layer 127 helps to increase the adhesion between the second dielectric layer 17 and the gate layer 19.

[0071] In some embodiments, see Figure 4D The portion of the gate layer 19 near the edge of the gate line gap 16 is removed, so that the edge of the gate layer 19 near the gate line gap 16 is recessed relative to the edge of the first dielectric layer 131 near the gate line gap 16, thereby forming a recess 20 at the edge of the gate layer 19 near the gate line gap 16; that is, a recess exists between adjacent first dielectric layers 131 along a direction perpendicular to the substrate 10. Thus, see reference Figure 3C The above step S140 forming the gate layer 19 may include steps S141 to S143.

[0072] S141: Forming an initial gate layer. The initial gate layer fills the gate layer gap 133 and covers the sidewalls of the gate line gap 16 and the surface of the stacked structure 21 away from the substrate 10.

[0073] For example, the initial gate layer can be formed by thin film deposition processes such as CVD, PVD, and ALD.

[0074] It should be understood that the initial adhesive layer is located between the second dielectric layer 17 and the initial gate layer.

[0075] S142: Remove the sidewalls covering the gate line gap 16 and the portion of the stacked structure 21 away from the substrate 10 in the initial gate layer.

[0076] For example, the sidewalls covering the gate line gap 16 and the portion of the stacked structure 21 away from the substrate 10 in the initial gate layer can be removed by an etching process.

[0077] S143: Remove a portion of the initial gate layer that fills the gate layer gap 133 to form a gate layer 19, and simultaneously form the aforementioned recess 20.

[0078] For example, the recess 20 can be formed by removing the portion of the initial gate layer near the gate line gap 16 and the portion of the adhesive layer 18 near the gate line gap 16 through an etching process.

[0079] In some embodiments, during the process of removing a portion of the initial gate layer in S142 and S143 described above, the portion of the initial adhesive layer exposed by the initial gate layer is also removed to form adhesive layer 18.

[0080] For example, during S142, when removing the sidewalls of the initial gate layer covering the gate line gap 16, a portion of the initial adhesive layer covering the sidewalls of the gate line gap 16 is also removed. During S143, when removing the portion of the initial gate layer filling the gate layer gap 133, a portion of the initial adhesive layer near the gate line gap 16 is also removed.

[0081] In other embodiments, after the gate layer 19 is formed in S140, the portion of the initial adhesive layer covering the sidewalls and bottomwalls of the gate line gap 16, as well as the portion of the initial adhesive layer covering the sidewalls of the recess 20, can be removed by a sequential etching process.

[0082] After the above steps S110~S140, the following is formed: Figure 4D The semiconductor structure 100 includes a substrate 10, and a third dielectric layer 11, a semiconductor layer 12, and a stacked structure 21 sequentially disposed on the substrate 10. The stacked structure 21 includes a plurality of alternating first dielectric layers 131 and a plurality of gate layers 19. The semiconductor structure 100 also includes a gate line gap 16 extending into the substrate 10 and a second dielectric layer 17; the second dielectric layer 17 is located between the gate layers 19 and the first dielectric layers 131, and covers the bottom and sidewalls of the gate line gap 16 and the surface of the initial stacked structure 13 away from the substrate 10.

[0083] In some embodiments, see Figure 3B After the semiconductor structure 100 is formed in step S140, the semiconductor fabrication method further includes step S150.

[0084] S150: See also Figure 4E Remove the portion of the second dielectric layer 17 covering the surface of the stacked structure 13 and the bottom of the gate line slots 16.

[0085] For example, the portion of the second dielectric layer 17 covering the surface of the stacked structure 13 away from the substrate 10 and the bottom of the gate line gap 16 can be removed by a dry etching process.

[0086] In the case where there is a recess 20 between adjacent first dielectric layers 131, see [reference] Figure 3B The method for preparing the three-dimensional memory further includes step S160.

[0087] S160: See also Figure 4F and Figure 4G A protective layer 22 is formed within the depression 20.

[0088] like Figure 4GAs shown, the protective layer 22 covers the side of the gate layer 19 exposed by the gate line gap 16. The protective layer 22 can protect the side of the gate layer 19 exposed by the gate line gap 16, and prevent damage to the gate layer 19 during the subsequent step S200 process of removing the portion of the second dielectric layer 17 covering the sidewall of the gate line gap 16.

[0089] In some embodiments, see Figure 3D The formation of the protective layer 22 in the recess 20 in the above-mentioned S160 may include steps S161 to S162.

[0090] S161: See also Figure 4F An initial protective layer 22' is formed within the grid line gap 16.

[0091] For example, the initial protective layer 22' can be formed by thin film deposition processes such as CVD, PVD, and ALD. The material of the protective layer 22 may include dielectric materials such as silicon oxide or silicon nitride. The initial protective layer 22' fills the recess 20 and covers the sidewalls and bottom of the gate line slot 16.

[0092] S162: See also Figure 4G Remove the portion of the sidewalls and bottom of the initial protective layer 22' that covers the grid line gaps 16, leaving the portion that fills the recess 20, to form the protective layer 22.

[0093] For example, the portion of the initial protective layer 22' covering the sidewalls and bottom of the gate line slot 16 can be removed by an etching process to form a protective layer 22 within the recess 20. The protective layer 22 can protect the sidewalls of the gate layer 19 exposed by the gate line slot 16, preventing damage to the gate layer 19 during the subsequent step S200 process of removing the portion of the second dielectric layer 17 covering the sidewalls of the gate line slot 16.

[0094] S200: See also Figure 4H Remove the portion of the sidewall covering the gate line slot 16 in the second dielectric layer 17.

[0095] In some embodiments, a wet etching process can be used to remove the portion of the sidewalls covering the gate line slots 16 in the second dielectric layer 17. The process is simple, has little impact on existing processes, is low in cost, and the etching process does not affect the sidewalls of the stacked structure 21 near the gate line slots 16.

[0096] S300: A filling structure 23 is formed within the grid line gap 16.

[0097] In some embodiments, see Figure 3E S300 forms a filling structure 23 within the grid line gap 16, including steps S310 to S330.

[0098] S310: See also Figure 4I An isolation layer 231 is formed within the grid line slot 16. The isolation layer 231 covers the inner surface (sidewalls and bottom) of the grid line slot 16, forming a filling gap.

[0099] In some embodiments, the isolation layer 231 can be formed by thin film deposition processes such as CVD, PVD, and ALD, with the gap filled within the isolation layer 231. The material of the isolation layer 231 is a dielectric material; for example, the material of the isolation layer 231 can be silicon oxide or silicon nitride.

[0100] It should be understood that the isolation layer 231 material formed by the thin film deposition process also covers the surface of the stacked structure 21 away from the substrate 10.

[0101] S320: A filling portion 232 is formed within the filling gap.

[0102] In some embodiments, the filling portion 232 can be formed by thin film deposition processes such as CVD, PVD, and ALD. The material of the filling portion 232 may include at least one of tungsten, cobalt, copper, aluminum, doped crystalline silicon, or silicide.

[0103] In other embodiments, the material of the filling portion 232 may also include a dielectric material, such as silicon oxide or silicon nitride.

[0104] The filling part 232 can improve the structural strength of the filling structure 23 and enhance the stress resistance of the filling structure 23.

[0105] In some other embodiments, the filling structure 23 may also include only the isolation layer 231, thus only the above-described step S310 may be included.

[0106] S330: Remove the portion of the isolation layer 231 covering the surface of the stacked structure 21 away from the substrate 10.

[0107] For example, the portion of the isolation layer 231 covering the surface of the stacked structure 21 away from the substrate 10 can be removed by dry etching.

[0108] S400: Remove substrate 10.

[0109] In some embodiments, Figure 4I The three-dimensional memory in the image is flipped 180 degrees and the substrate 10 is removed. Removing the substrate 10 includes etching the substrate 10 to the third dielectric layer 11 to expose a portion of the isolation layer 231 of the filling structure 23 extending into the substrate 10.

[0110] When the substrate 10 includes a substrate 101, a sacrificial insulating layer 102, and a sacrificial polysilicon layer 103, the substrate 101 of the substrate 110 can be removed using CMP or dry / wet etching processes. Further, the sacrificial insulating layer 102 can be removed using a wet etching process with the sacrificial polysilicon layer 103 as the etch stop layer. The sacrificial polysilicon layer 103 can be removed using a wet etching process with the third dielectric layer 11 as the etch stop layer.

[0111] For example, a wet etching process can be used to remove the sacrificial polysilicon layer 113 of the substrate 110, and the etching can be stopped at the third dielectric layer 11 by selecting a predetermined etchant.

[0112] In the etching process for removing substrate 10, semiconductor layer 12 and third dielectric layer 11 can be configured as etching stop layers. Specifically, the etching rate of the material of third dielectric layer 11 can be different from the etching rate of the material of semiconductor layer 12. Furthermore, the etching rate of the material of layers in substrate 10 that are in contact with third dielectric layer 11, such as sacrificial polysilicon layer 103, can be different from the etching rate of the material of third dielectric layer 11. For example, the material of third dielectric layer 11 includes silicon oxide, and the materials of semiconductor layer 12 and sacrificial polysilicon layer 103 are the same, both being polysilicon. Based on the above, in Figure 4I In the three-dimensional memory 100, when the substrate 10 is subsequently removed by an etching process, and / or other materials with an etching rate similar to that of the substrate 10 are removed, the third dielectric layer 11 can be exposed without further etching the semiconductor layer 12; when the third dielectric layer 11 is subsequently removed by an etching process, and / or other materials with an etching rate similar to that of the third dielectric layer 11 are removed, the semiconductor layer 12 can be exposed without further etching the film layer disposed on the side of the semiconductor layer 12 away from the substrate 10, such as the first dielectric layer 131.

[0113] Furthermore, a laser annealing process can be performed during the formation of the source layer 24. After laser annealing, the semiconductor layer 12 can serve as an interface layer, which can enhance the bonding between the source layer 24 and the stacked structure 21.

[0114] In some embodiments, the third dielectric layer 11, the isolation layer 231 of the filling structure 23, and the barrier layer 1411 of the channel structure 14 are made of the same material, for example, all three are made of silicon oxide. Removing the sacrificial polysilicon layer 113 from the substrate 110 using a wet etching process exposes the portion of the isolation layer 231 of the filling structure 23 extending into the substrate 10, and exposes the portion of the functional layer 131 of the channel structure 14 extending into the substrate 10. The three-dimensional memory processed by step S400 is as follows: Figure 4J As shown.

[0115] In some embodiments, after removing the substrate 10 in S400, the preparation method further includes S410.

[0116] S410: See also Figure 4K The exposed portions of the third dielectric layer 11 and the isolation layer 231 are etched to the semiconductor layer 12 to expose the filling portion 232 of the filling structure 23.

[0117] For example, a wet etching process can be used to remove the third dielectric layer 11, and the etching can be stopped at the semiconductor layer 12 by selecting a predetermined etchant.

[0118] In some embodiments, the semiconductor layer 12, the filling portion 232 of the filling structure 23, and the channel layer 143 of the channel structure 14 are made of the same material, for example, all three are made of polysilicon. Removing the third dielectric layer 11 using a wet etching process exposes the portion of the filling portion 232 of the filling structure 23 extending into the substrate 10 (the portion extending out of the semiconductor layer 12), and exposes the portion of the channel layer 143 of the channel structure 14 extending into the substrate 10 (the portion extending out of the semiconductor layer 12). The three-dimensional memory processed by step S410 is as follows: Figure 4K As shown.

[0119] S500: See Figure 4L A source layer 24 is formed on one side of the stacked structure 21 where the substrate 10 has been removed.

[0120] For example, a source layer 24 may be formed on the surface of the semiconductor layer 12, the fill portion 232 of the fill structure 23, and the channel layer 143 of the channel structure 14, away from the stacked structure 21. The source layer 24 covers and contacts the exposed portion of the fill portion 232. The source layer 24 also covers and is electrically connected to the exposed portion of the channel layer 143.

[0121] The above steps S100~S500 are used to form the following: Figure 5 The three-dimensional memory 100, wherein, Figure 5 The three-dimensional memory 100 shown is compared to Figure 4L The three-dimensional memory shown has been flipped 180 degrees.

[0122] See Figure 5 The three-dimensional memory 100 includes a source layer 24, a semiconductor layer 12, a stacked structure 21, a channel structure 14, a second dielectric layer 17, and a gate isolation structure 30. The semiconductor layer 12 is disposed on one side of the source layer 24. The stacked structure 21 is disposed on the side of the semiconductor layer 12 away from the source layer 24, and includes a plurality of overlapping first dielectric layers 131 and a plurality of gate layers 19.

[0123] The three-dimensional memory 100 also includes a second dielectric layer 17, which is located between the first dielectric layer 131 and the gate layer 19.

[0124] The gate isolation structure 30 extends through the stacked structure 21 in a direction perpendicular to the source layer 24 and into the source layer 24, and the gate isolation structure 30 is in contact with the first dielectric layer 131.

[0125] For example, the gate isolation structure 30 may include an isolation layer 231 and a filling portion 232 disposed sequentially; the isolation layer 231 contacts the sidewall of the first dielectric layer 131 near the gate gap 16 and the sidewall of the semiconductor layer 12 near the gate gap 16; the filling portion 232 extends into the source layer 24 and contacts the source layer 24.

[0126] In the aforementioned three-dimensional memory 100, the second dielectric layer 17 does not cover the sidewalls of the gate line slots 16, allowing the isolation layer 231 to directly contact the sidewalls of the first dielectric layer 131 near the gate line slots 16, and the semiconductor layer 12 to directly contact the sidewalls of the semiconductor layer 12 near the gate line slots 16. Compared to the bonding force between the semiconductor layer 12 and the second dielectric layer 17, the bonding force between the isolation layer 231 and the first dielectric layer 131 and the semiconductor layer 12 is higher. Therefore, the risk of gaps forming between the isolation layer 231 and the first dielectric layer 131, and between the isolation layer 231 and the semiconductor layer 12, can be reduced.

[0127] In some embodiments, a recess 20 is provided between adjacent first dielectric layers 131 along a direction perpendicular to the substrate 10. The three-dimensional memory 100 also includes a protective layer 22 disposed within the recess 20.

[0128] In some embodiments, see Figure 6 The aforementioned three-dimensional memory 100 further includes an array interconnect layer 40 disposed on the side of the stacked structure 21 away from the source layer 24, and peripheral devices 200 bonded to the array interconnect layer 40.

[0129] In some embodiments, the peripheral device 200 may include a peripheral circuit 210 and a peripheral interconnect layer 220 disposed on the peripheral circuit 210 near the array interconnect layer 50, wherein the peripheral circuit 210 and the peripheral interconnect layer 220 are electrically connected. The array interconnect layer 50 and the peripheral interconnect layer 220 are bonded.

[0130] In some embodiments, see Figure 6 The peripheral circuit 210 may include a second substrate 25 and a transistor array 26 formed on the second substrate 25. The peripheral circuit 230 may include any active (or passive) components of the circuit, such as page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), or transistors, diodes, resistors, capacitors, etc.

[0131] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A three-dimensional memory, characterized in that, include: Semiconductor layer; A stacked structure is disposed on one side of the semiconductor layer along a first direction, and includes a first dielectric layer and a gate layer that are stacked along the first direction, wherein the first direction is perpendicular to the semiconductor layer; A second dielectric layer is disposed between the first dielectric layer and the gate layer; and A gate line isolation structure extends along the first direction through the stacked structure and the semiconductor layer; wherein... The gate line isolation structure includes an isolation layer and a conductive portion disposed along a second direction perpendicular to the first direction. The isolation layer includes a first portion located within the semiconductor layer, the first portion being situated between the semiconductor layer and the conductive portion in the second direction and in contact with both the semiconductor layer and the conductive portion. The isolation layer is a single-layer structure.

2. The memory according to claim 1, characterized in that, The material of the isolation layer is silicon oxide or silicon nitride.

3. The memory according to claim 1 or 2, characterized in that, The material of the second dielectric layer is a high dielectric constant material.

4. The memory according to claim 1, characterized in that, The memory further includes a channel structure that extends through the stacked structure and the semiconductor layer along the first direction. The channel structure includes a functional layer and a channel layer, and the functional layer is in contact with the semiconductor layer.

5. The memory according to claim 4, characterized in that, The memory further includes a source layer located on the side of the semiconductor layer away from the stacked structure along the first direction, and the channel layer being in contact with the source layer.

6. The memory according to claim 5, characterized in that, The channel layer includes a bottom surface extending along the second direction and a sidewall extending along the first direction, the bottom surface and a portion of the sidewall being in contact with the source layer.

7. The memory according to claim 4 or 5, characterized in that, The gate isolation structure extends into the source layer along the first direction, and the gate isolation structure includes a first sub-section located in the source layer and a second sub-section located in the stacked structure, wherein the dimension of the first sub-section along the second direction is smaller than the dimension of the second sub-section along the second direction.

8. The memory according to claim 4, characterized in that, The functional layer includes a barrier layer, a tunneling layer, and a charge storage layer located between the barrier layer and the tunneling layer. The charge storage layer extends continuously along the first direction and penetrates the stacked structure.

9. The memory according to claim 4, characterized in that, The conductive portion includes a portion that contacts the source layer.

10. The memory according to claim 1, characterized in that, The second dielectric layer includes an end that contacts the gate line isolation structure, wherein the ends of two second dielectric layers that contact the same first dielectric layer are spaced apart in the first direction.

11. The memory according to claim 1, characterized in that, The memory further includes a third dielectric layer, which is disposed between the gate layer and the gate line isolation structure along the second direction, and located between adjacent first dielectric layers along the first direction.

12. The memory according to claim 11, characterized in that, The material of the third dielectric layer is silicon oxide or silicon nitride, and the material of the third dielectric layer is the same as that of the isolation layer.

13. The memory according to claim 11, characterized in that, The material of the third dielectric layer is silicon oxide or silicon nitride, and the material of the third dielectric layer is different from the material of the isolation layer.

14. The memory according to claim 1, characterized in that, The conductive part includes polycrystalline silicon.

15. The memory according to any one of claims 1 to 14, characterized in that, The gate isolation structure is in contact with the first dielectric layer.

16. A three-dimensional memory, characterized in that, include: Source layer; A stacked structure is disposed on one side of the source layer along a first direction, and includes a first dielectric layer and a gate layer that are stacked along the first direction; A gate line isolation structure extends through the stacked structure along the first direction and into the source layer, wherein the gate line isolation structure is in contact with the first dielectric layer; A second dielectric layer is disposed between the first dielectric layer and the gate layer, and includes an end that contacts the gate line isolation structure; as well as A third dielectric layer is disposed between the gate isolation structure and the gate layer, and includes a first surface and a second surface disposed along the first direction and extending along the second direction; wherein, The first direction is perpendicular to the source layer, and the second direction is perpendicular to both the first direction and the source layer. The ends of the two second dielectric layers that are in contact with the same first dielectric layer are spaced apart in the first direction, and The first surface is in contact with the second dielectric layer, and the second surface is in contact with the second dielectric layer.

17. The memory according to claim 16, characterized in that, The material of the first dielectric layer is different from the material of the second dielectric layer, and The material of the second dielectric layer is different from the material of the gate isolation structure.

18. The memory according to claim 17, characterized in that, The first dielectric layer is made of silicon oxide, and the second dielectric layer is made of a high dielectric constant material.

19. The memory according to claim 16, characterized in that, The gate isolation structure includes a first sub-section located in the source layer and a second sub-section located in the stacked structure, wherein the dimension of the first sub-section along the second direction is smaller than the dimension of the second sub-section along the second direction.

20. The memory according to claim 16, characterized in that, The gate isolation structure includes an isolation layer and a conductive portion disposed along the second direction, wherein the conductive portion includes a portion that contacts the source layer.

21. The memory according to claim 16 or 20, characterized in that, The memory further includes a semiconductor layer disposed along the first direction between the source layer and the stacked structure, and... The gate isolation structure includes an isolation layer and a conductive portion disposed along the second direction, wherein the isolation layer includes a portion in contact with the semiconductor layer.

22. The memory according to claim 20, characterized in that, The material of the isolation layer is silicon oxide or silicon nitride.

23. The memory according to claim 20 or 21, characterized in that, The conductive part includes polycrystalline silicon.

24. The memory according to claim 16, characterized in that, The memory also includes a channel structure that extends along the first direction through the stacked structure into the source layer. The channel structure includes a functional layer and a channel layer, and the channel layer is in contact with the source layer.

25. The memory according to claim 24, characterized in that, The functional layer includes a barrier layer, a tunneling layer, and a charge storage layer located between the barrier layer and the tunneling layer. The charge storage layer extends continuously along the first direction and penetrates the stacked structure.

26. The memory according to claim 24, characterized in that, The channel layer includes a bottom surface extending along the second direction and a sidewall extending along the first direction, the bottom surface and a portion of the sidewall being in contact with the source layer.

27. The memory according to claim 16, characterized in that, The gate isolation structure includes an isolation layer and a conductive portion disposed along the second direction. The isolation layer is in contact with the first dielectric layer, and the material of the third dielectric layer is the same as that of the isolation layer.

28. The memory according to claim 16, characterized in that, The gate isolation structure includes an isolation layer and a conductive portion disposed along the second direction. The isolation layer is in contact with the first dielectric layer, and the material of the third dielectric layer is different from that of the isolation layer.

29. A method for fabricating a three-dimensional memory, characterized in that, include: Fabrication of a semiconductor structure, the semiconductor structure comprising: Substrate; A semiconductor layer and a stacked structure disposed on the substrate, the stacked structure comprising a plurality of first dielectric layers and gate layers alternately disposed along a first direction, the first direction being perpendicular to the substrate; A gate line gap, the gate line gap penetrating the stacked structure and the semiconductor layer in a direction perpendicular to the substrate, and extending into the substrate; and A second dielectric layer is disposed between the first dielectric layer and the gate layer, and covers the sidewall of the gate line gap; Remove the portion of the sidewalls in the second dielectric layer that covers the gate line gaps, and expose the sidewalls of the semiconductor layer; A filling structure is formed within the gate line gap, wherein the filling structure includes an isolation layer and a conductive portion disposed along a second direction, the isolation layer includes a first portion that contacts the semiconductor layer, the first portion being located between the semiconductor layer and the conductive portion in the second direction and in contact with the semiconductor layer and the conductive portion, and the isolation layer is a single-layer structure; Remove the substrate and expose the semiconductor layer; A source layer is formed on the side of the stacked structure where the substrate is removed.

30. The preparation method according to claim 29, characterized in that, There is a recess between adjacent first dielectric layers along the first direction; Before removing the portion of the sidewalls covering the gate wire gaps in the second dielectric layer, the fabrication method further includes: A protective layer is formed within the recess, the protective layer covering the side of the gate layer exposed by the gate line gap.

31. The preparation method according to claim 30, characterized in that, A protective layer is formed within the recess, comprising: An initial protective layer is formed within the grid line slots, the initial protective layer filling the depressions and covering the sidewalls and bottom of the grid line slots; Remove the portion of the initial protective layer that covers the sidewalls and bottom of the grid line gaps, leaving the portion that fills the recesses, to form the protective layer.

32. The preparation method according to claim 30, characterized in that, The second dielectric layer also covers the surface of the stacked structure away from the substrate and the bottom of the gate gap; Before forming a protective layer within the depression, the preparation method further includes: Remove the portion of the second dielectric layer covering the surface of the stacked structure away from the substrate and the bottom of the gate line gap.

33. The preparation method according to claim 29, characterized in that, The fabrication of the semiconductor structure includes: An initial stacked structure is formed on the substrate; the initial stacked structure includes a plurality of first dielectric layers and a plurality of gate sacrificial layers alternately disposed along the first direction; Forming a grid line gap that penetrates the initial stacked structure along the first direction; The gate sacrificial layer in the initial stacked structure is removed through the gate line gap to form a gate layer gap communicating with the gate line gap; A second dielectric layer and a gate layer are sequentially formed within the gate layer gap through the gate line gap.

34. The preparation method according to claim 33, characterized in that, Forming the gate layer includes: An initial gate layer is formed, which fills the gate layer gap and covers the sidewalls of the gate line gap and the surface of the initial stacked structure away from the substrate; Remove the sidewalls covering the gate line gaps and the portion of the stacked structure away from the substrate in the initial gate layer; The initial gate layer, which partially filled the gaps between the gate layers, is removed to form the gate layer.

35. The preparation method according to any one of claims 29 to 34, characterized in that, A filling structure is formed within the grid line gaps, including: An isolation layer is formed within the grid line slots, and the isolation layer covers the sidewalls of the grid line slots to form a filling gap; A conductive portion is formed within the filling gap.

Images