Metal oxide semiconductor field effect transistor and method of manufacturing the same

Abstract

The application relates to a metal oxide semiconductor field effect tube and a preparation method thereof. The metal oxide semiconductor field effect tube comprises at least one cell structure; the cell structure comprises: a substrate; a drift region with a first conductive type; a first well region with a second conductive type; a JFET region; a second well region with the second conductive type; a shielding layer located on a side of the JFET region away from the drift region and having the second conductive type; a gate covering part of a surface of the first well region away from the drift region, part of a surface of the second well region away from the drift region and the shielding layer; a source metal layer covering the remaining surface of the first well region away from the drift region, the remaining surface of the second well region away from the drift region and the gate; and a conductive contact structure penetrating the gate in a direction perpendicular to the substrate and connected with the shielding layer and the source metal layer respectively. The metal oxide semiconductor field effect tube provided by the application has low risk of mis-conduction in the process of turning off and can realize zero-voltage turn-off.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a metal-oxide-semiconductor field-effect transistor and its fabrication method. Background Technology

[0002] Silicon carbide MOSFETs are widely used in high-frequency applications such as on-board chargers, server high-frequency power supplies, and new energy power generation converters due to their advantages of high temperature resistance, high voltage resistance, and fast switching speed.

[0003] However, during the MOSFET turn-off process, the large current generated by the discharge of the gate-drain parasitic capacitance (i.e., Miller capacitance) can easily cause gate voltage oscillation, leading to the device being falsely turned on. Summary of the Invention

[0004] Therefore, it is necessary to provide a metal-oxide-semiconductor field-effect transistor and its fabrication method that can reduce the risk of device mis-turn-on and achieve zero-voltage turn-off.

[0005] In a first aspect, this application provides a metal-oxide-semiconductor field-effect transistor, comprising at least one cell structure; the cell structure includes:

[0006] The substrate has a first type of conductivity;

[0007] A drift region, located on the substrate, has a first conductivity type;

[0008] The first well region, located on the side of the drift region away from the substrate, has a second conductivity type;

[0009] The JFET region is located on the side of the drift region away from the substrate and on the side of the first well region in a first direction, and has a first conductivity type; the first direction is perpendicular to the direction from the substrate to the JFET region;

[0010] The second well region is located on the side of the drift region away from the substrate and on the side of the JFET region away from the first well region, and has a second conductivity type;

[0011] A shielding layer, located on the side of the JFET region away from the drift region, has a second conductivity type;

[0012] The gate covers a portion of the surface of the first well region away from the drift region, a portion of the surface of the second well region away from the drift region, and the shielding layer;

[0013] A source metal layer covers the remaining surface of the first well region on the side away from the drift region, the remaining surface of the second well region on the side away from the drift region, and the gate.

[0014] A conductive contact structure extends through the gate along a direction perpendicular to the substrate and is connected to the shielding layer and the source metal layer, respectively.

[0015] In one embodiment, the doping concentration of the shielding layer is greater than the doping concentration of the first well region and greater than the doping concentration of the second well region.

[0016] In one embodiment, the projected area of ​​the shielding layer on the substrate is smaller than the projected area of ​​the JFET region on the substrate.

[0017] In one embodiment, the metal-oxide-semiconductor field-effect transistor includes a plurality of cell structures arranged in an array;

[0018] The plurality of cell structures arranged along a first direction have a first shielding layer, which extends along a second direction; the plurality of cell structures arranged along the second direction have a second shielding layer, which extends along the first direction; the second direction is perpendicular to the direction from the substrate to the JFET region and is perpendicular to the first direction.

[0019] The first shielding layer intersects with the second shielding layer.

[0020] In one embodiment, the plurality of said cell structures arranged along a first direction have a first conductive contact structure that extends along a second direction;

[0021] The plurality of said cell structures arranged along the second direction have a second conductive contact structure, the second conductive contact structure extending along the first direction;

[0022] The first conductive contact structure intersects with the second conductive contact structure.

[0023] In one embodiment, the plurality of cell structures arranged along a first direction have a first conductive contact structure, and the plurality of cell structures arranged along a second direction have a second conductive contact structure.

[0024] The metal-oxide-semiconductor field-effect transistor further includes a third conductive contact structure, which penetrates the target gate region along a direction perpendicular to the substrate; the target gate region is a gate covering the intersection area of ​​the first shielding layer and the second shielding layer.

[0025] The conductive contact structures are spaced apart.

[0026] In one embodiment, the cell structure further includes:

[0027] A first insulating layer is located between the gate and the shielding layer;

[0028] A second insulating layer is located between the gate and the source metal layer.

[0029] In one embodiment, the cell structure further includes:

[0030] A third insulating layer is located between the gate and the conductive contact structure.

[0031] In one embodiment, the cell structure further includes:

[0032] A drain metal layer is located on the side of the substrate away from the drift region.

[0033] Secondly, this application also provides a method for fabricating a metal-oxide-semiconductor field-effect transistor, comprising:

[0034] Provide a substrate of the first conductivity type;

[0035] A drift region of a first conductivity type is formed on the substrate;

[0036] The drift region is etched to form alternating first and second trenches;

[0037] A first well region of a second conductivity type is formed in the drift region based on the first trench, and a second well region of a second conductivity type is formed in the drift region based on the second trench; the drift region between the first well region and the second well region serves as the JFET region;

[0038] A shielding layer of a second conductivity type is formed on the side of the JFET region away from the drift region;

[0039] A gate is formed on a portion of the surface of the first well region away from the drift region, a portion of the surface of the second well region away from the drift region, and the exposed surface of the shielding layer;

[0040] The gate is etched to form a third trench, which exposes the shielding layer;

[0041] A conductive contact structure is formed within the third trench;

[0042] A source metal layer is formed on the remaining surface of the first well region away from the drift region, the remaining surface of the second well region away from the drift region, the exposed surface of the gate, and the side of the conductive contact structure away from the shielding layer.

[0043] In the aforementioned metal-oxide-semiconductor field-effect transistor and its fabrication method, by setting a shielding layer of a second conductivity type above the JFET region, and connecting the shielding layer to the source metal layer through a conductive contact structure penetrating the gate, the coupling strength between the gate and source can be increased, while the coupling strength between the gate and drain can be decreased. This increases the parasitic capacitance Cgs between the gate and source and decreases the parasitic capacitance Cgd between the gate and drain. Thus, at the moment of device turn-off, the displacement current generated by the discharge of Cgd is weakened by the increased Cgs, insufficient to cause oscillation of the gate voltage, and the gate remains at a low potential, preventing false turn-on. This provides a structural basis for achieving zero-voltage turn-off. Based on this, by reasonably adjusting the doping concentration of the channel, the device threshold voltage can be reduced to the zero-voltage turn-off range, achieving zero-voltage turn-off. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 A schematic diagram of the cross-sectional structure of a metal-oxide-semiconductor field-effect transistor provided in one embodiment;

[0046] Figure 2 Provided as an embodiment Figure 1 One of the top-view cross-sectional views obtained by cutting along the dashed line Aa in the middle;

[0047] Figure 3 Provided as an embodiment Figure 1 The second top-view cross-section obtained by cutting along the dashed line Aa in the middle;

[0048] Figure 4 Provided as an embodiment Figure 1 Third top-view cross-section obtained by cutting along the dashed line Aa in the middle;

[0049] Figure 5 A comparison of the CV characteristic curves of the MOSFET of this application and a MOSFET without a shielding layer provided in one embodiment;

[0050] Figure 6 A flowchart illustrating a method for fabricating a MOSFET according to one embodiment;

[0051] Figure 7 This is a cross-sectional schematic diagram of the structure obtained in step S300 of the MOSFET fabrication method provided in one embodiment;

[0052] Figure 8This is a cross-sectional schematic diagram of the structure obtained in step S400 of the MOSFET fabrication method provided in one embodiment;

[0053] Figure 9 This is a top view of the structure obtained in step S400 of the MOSFET fabrication method provided in one embodiment;

[0054] Figure 10 This is a cross-sectional schematic diagram of the structure obtained in step S500 of the MOSFET fabrication method provided in one embodiment;

[0055] Figure 11 This is a top view of the structure obtained in step S500 of the MOSFET fabrication method provided in one embodiment;

[0056] Figure 12 This is a cross-sectional schematic diagram of the structure obtained in step S600 of the MOSFET fabrication method provided in one embodiment;

[0057] Figure 13 This is a top view of the structure obtained in step S700 of the MOSFET fabrication method provided in one embodiment;

[0058] Figure 14 A top cross-sectional view of a metal-oxide-semiconductor field-effect transistor provided for another embodiment.

[0059] Explanation of reference numerals in the attached figures:

[0060] 100 - Substrate, 200 - Drift region, 310 - First well region, 320 - Second well region, 400 - JFET region, 410 - First JFET region, 420 - Second JFET region, 500 - Shielding layer, 510 - First shielding layer, 520 - Second shielding layer, 600 - Gate, 610 - Gate dielectric layer, 620 - Gate oxide layer, 700 - Source metal layer, 710 - Source doped region, 720 - Drain doped region, 810 - First contact region, 820 - Second contact region, 910 - First insulating layer, 920 - Second insulating layer, 930 - Third insulating layer, 1000 - Drain metal layer, 1100 - Conductive contact structure, 1110 - First conductive contact structure, 1120 - Second conductive contact structure, 1130 - Third conductive contact structure, 1210 - First trench, 1220 - Second trench, 1300 - Trench gate. Detailed Implementation

[0061] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0062] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0063] It is understood that the terms "first," "second," etc., used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first well region may be referred to as a second well region, and similarly, a second well region may be referred to as a first well region. Both the first well region and the second well region are well regions, but they are not the same well region.

[0064] It is understandable that "at least one" refers to one or more, and "multiple" refers to two or more. "At least a part of an element" refers to part or all of an element.

[0065] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0066] In one embodiment, this application provides a metal-oxide-semiconductor field-effect transistor, such as... Figure 1 As shown, it includes at least one cell structure. The cell structure includes a substrate 100, a drift region 200, a first well region 310, a JFET region 400, a second well region 320, a shielding layer 500, a gate 600, a source metal layer 700, and a conductive contact structure 1100. Figure 1 (Not shown in the text).

[0067] The substrate 100, drift region 200, and JFET region 400 have a first conductivity type, while the first well region 310, second well region 320, and shielding layer 500 have a second conductivity type. The first conductivity type is the opposite of the second conductivity type; for example, the first conductivity type is N-type, and the second conductivity type is P-type.

[0068] The substrate 100 can be silicon carbide doped with ions of a first conductivity type. The drift region 200 is located on the substrate 100 and can be formed on the substrate 100 by an epitaxial growth process. The material of the drift region 200 can be the same as the substrate 100, or any suitable epitaxial layer material known in the art. The first well region 310, the JFET region 400, and the second well region 320 are all located within the drift region 200 on the side away from the substrate 100, and are sequentially arranged along a first direction as the first well region 310, the JFET region 400, and the second well region 320. The shielding layer 500 is located on the side of the JFET region 400 away from the drift region 200. The first well region 310, the second well region 320, the JFET region 400, and the shielding layer 500 can be formed by ion implantation into the drift region 200 with different doping concentrations. The ion doping concentration, depth, and length of the first well region 310 and the second well region 320 are the same.

[0069] The gate 600 covers a portion of the surface of the first well region 310 away from the drift region 200, a portion of the surface of the second well region 320 away from the drift region 200, and the shielding layer 500. The gate 600 may include a gate dielectric layer 610 and a gate oxide layer 620, wherein the gate dielectric layer 610 covers a portion of the surface of the first well region 310 away from the drift region 200, a portion of the surface of the second well region 320 away from the drift region 200, and the shielding layer 500. The gate oxide layer 620 is located between the gate dielectric layer 610 and the first well region 310, between the gate dielectric layer 610 and the JFET region 400, and between the gate dielectric layer 610 and the second well region 320. As an example, the gate dielectric layer 610 may be made of polysilicon, and the gate oxide layer 620 may be made of silicon dioxide.

[0070] The source metal layer 700 covers the remaining surface of the first well region 310 away from the drift region 200, the remaining surface of the second well region 320 away from the drift region 200, and the gate 600. The material of the source metal layer 700 can be a conductive material commonly used in the art, such as conductive metals such as copper, aluminum, and titanium.

[0071] The conductive contact structure 1100 extends through the gate 600 in a direction perpendicular to the substrate 100 and is connected to the shielding layer 500 and the source metal layer 700, respectively. The material of the conductive contact structure 1100 can be a commonly used conductive material, such as conductive metals such as copper, aluminum, and titanium.

[0072] In this embodiment, by providing a shielding layer 500 of a second conductivity type above the JFET region 400, and connecting the shielding layer 500 to the source metal layer 700 through a conductive contact structure 1100 penetrating the gate 600, the coupling strength between the gate 600 and the source can be increased, while the coupling strength between the gate 600 and the drain can be decreased. This increases the parasitic capacitance Cgs between the gate 600 and the source and decreases the parasitic capacitance Cgd between the gate 600 and the drain. Thus, at the moment of device turn-off, the displacement current generated by the discharge of Cgd is weakened by the increased Cgs, which is insufficient to cause oscillation of the gate 600 voltage. The gate 600 remains at a low potential and will not be falsely turned on, providing a structural basis for achieving zero-voltage turn-off. Based on this, the device threshold voltage can be reduced to the zero-voltage turn-off range by reasonably adjusting the doping concentration of the channel, thereby achieving zero-voltage turn-off.

[0073] In one embodiment, such as Figure 1 As shown, the cell structure also includes a source doped region 710 of a first conductivity type and a first contact region 810 of a second conductivity type. The source doped region 710 is located in the first well region 310 on the side away from the drift region 200, and the first contact region 810 extends from the side of the source doped region 710 away from the JFET region 400 in a first direction to the JFET region 400 along the side of the source doped region 710 close to the drift region 200.

[0074] In one embodiment, such as Figure 1 As shown, the cell structure also includes a drain doped region 720 of a first conductivity type and a second contact region 820 of a second conductivity type. The drain doped region 720 is located in the second well region 320 on the side away from the drift region 200, and the second contact region 820 extends from the drain doped region 720 on the side away from the JFET region 400 in a first direction to the JFET region 400 along the side of the drain doped region 720 close to the drift region 200.

[0075] In one embodiment, such as Figure 1 As shown, the cell structure also includes a first insulating layer 910 and a second insulating layer 920. The first insulating layer 910 is located between the gate dielectric layer 610 and the shielding layer 500, and is used to isolate the gate dielectric layer 610 and the shielding layer 500 to prevent the gate 600 from being short-circuited with the source. The second insulating layer 920 is located between the gate dielectric layer 610 and the source metal layer 700, and is used to isolate the gate dielectric layer 610 and the source metal layer 700 to prevent the gate 600 from being short-circuited with the source.

[0076] In one embodiment, such as Figures 2-4 As shown, the cell structure also includes a third insulating layer 930, which is located between the gate dielectric layer 610 and the conductive contact structure 1100, and is used to isolate the gate dielectric layer 610 and the conductive contact structure 1100.

[0077] In one embodiment, such as Figure 1 As shown, the cell structure also includes a drain metal layer 1000. The drain metal layer 1000 is located on the side of the substrate 100 away from the drift region 200.

[0078] In one embodiment, the doping concentration of the shielding layer 500 is greater than the doping concentration of the first well region 310 and also greater than the doping concentration of the second well region 320. The shielding layer 500 of the second conductivity type, the JFET region 400 of the first conductivity type, and the first well region 310 of the second conductivity type constitute a parasitic transistor (PNP). Correspondingly, the shielding layer 500 of the second conductivity type, the JFET region 400 of the first conductivity type, and the second well region 320 of the second conductivity type also constitute a parasitic transistor. By setting the doping concentration of the shielding layer 500 to be greater than the doping concentration of the well region, the current amplification factor of the parasitic transistor can be reduced, and the conduction bias condition of the parasitic transistor can be weakened, avoiding mis-conduction by the parasitic transistor. This reduces the switching losses of the metal-oxide-semiconductor field-effect transistor and improves its stability.

[0079] In one embodiment, the projected area of ​​the shielding layer 500 on the substrate 100 is smaller than the projected area of ​​the JFET region 400 on the substrate 100. Thus, the gate 600 can cover the portion of the JFET region 400 away from the drift region 200, ensuring that the metal-oxide-semiconductor field-effect transistor can conduct normally.

[0080] In one embodiment, a metal-oxide-semiconductor field-effect transistor (MOSFET) includes a plurality of cell structures arranged in an array. The plurality of cell structures have the same structure, that is, each cell structure includes a substrate 100, a drift region 200, a first well region 310, a JFET region 400, a second well region 320, a shielding layer 500, a gate 600, a source metal layer 700, and a conductive contact structure 1100.

[0081] In a first direction, adjacent cell structures can be separated by a first isolation structure; in a second direction, adjacent cell structures can be separated by a second isolation structure. Multiple cell structures arranged along the first direction have a first JFET region 410, and multiple cell structures arranged along the second direction have a second JFET region 420. The first JFET region 410 and the second JFET region 420 intersect. The first JFET region 410 and the second JFET region 420 form a mesh structure, and the first well region 310 and the second well region 320 are respectively located within the mesh of the mesh structure.

[0082] like Figure 2As shown, a plurality of cell structures arranged along a first direction have a first shielding layer 510, which extends along a second direction. A plurality of cell structures arranged along the second direction have a second shielding layer 520, which extends along the first direction. The second direction is perpendicular to the direction from the substrate 100 to the JFET region 400 and perpendicular to the first direction. The first shielding layer 510 and the second shielding layer 520 intersect. The overall shape of the first shielding layer 510 and the second shielding layer 520 is a mesh. Correspondingly, the gate 600 covering the first shielding layer 510 and the gate 600 covering the second shielding layer 520 also form a mesh.

[0083] In this embodiment, multiple cell structures are arranged in an array, and the JFET region 400, shielding layer 500, and gate 600 of each cell structure are in a grid pattern, achieving uniform electric field shielding. On the one hand, the JFET region 400 can keep the coupling strength between the gate 600 and the source consistent throughout the chip, avoiding gate 600 potential oscillation caused by excessively small local Cgs. On the other hand, the JFET region 400 can reduce the electric field coupling between the gate 600 and the drain (drift region 200, JFET region 400), thereby reducing the parasitic capacitance Cgd. The displacement current generated by Cgd discharge at the moment of turn-off is greatly weakened, reducing the risk of false turn-on caused by differences in parasitic capacitance of the cell structure and improving the safety of the device under high-frequency switching conditions.

[0084] In one embodiment, such as Figure 3 As shown, a plurality of cell structures arranged along a first direction have a first conductive contact structure 1110, which extends along a second direction. A plurality of cell structures arranged along the second direction have a second conductive contact structure 1120, which extends along the first direction. The first conductive contact structure 1110 and the second conductive contact structure 1120 intersect.

[0085] It is understood that the cross-sectional shape of the first conductive contact structure 1110 and the second conductive contact structure 1120 is elongated. The elongated cross-section can significantly increase the contact area with the mesh shielding layer 500, reduce the contact resistance, and reduce local heat generation and loss during current conduction. In addition, the first conductive contact structure 1110 and the second conductive contact structure 1120 intersect to form a mesh structure, which can reduce the number of conductive contact structures to be fabricated and simplify the process steps such as photolithography and via etching.

[0086] In one embodiment, such as Figure 4As shown, the plurality of cell structures arranged along the first direction have a first conductive contact structure 1110, and the plurality of cell structures arranged along the second direction have a second conductive contact structure 1120. The metal-oxide-semiconductor field-effect transistor also includes a third conductive contact structure 1130, which penetrates the target gate 600 region along a direction perpendicular to the substrate 100. The target gate 600 region is the gate 600 covering the intersection region of the first shielding layer 510 and the second shielding layer 520. The conductive contact structures are spaced apart.

[0087] In this embodiment, the cross-sectional shape of the first conductive contact structure 1110, the second conductive contact structure 1120 and the third conductive contact structure 1130 is square and they are spaced apart, which can reduce the overall contact resistance.

[0088] In one embodiment, a simulation comparison test was performed on the metal-oxide-semiconductor field-effect transistor provided in this application and a MOSFET without a shielding layer. The resulting capacitance-voltage characteristic curve (CV characteristic curve) is shown below. Figure 5 As shown, the horizontal axis represents voltage, and the vertical axis represents capacitance. According to... Figure 5 It can be seen that the gate-source parasitic capacitance Cgs of the MOSFET provided in this application is significantly larger than that of a conventional MOSFET, while the gate-drain parasitic capacitance Cgd of the MOSFET provided in this application is significantly smaller than that of a conventional MOSFET. The gate-source parasitic capacitance Cgs of the MOSFET provided in this application is 271pF, and the gate-drain parasitic capacitance Cgd is 0.015pF, while the gate-source parasitic capacitance Cgs of the MOSFET without a shielding layer is 48pF, and the gate-drain parasitic capacitance Cgd is 0.64pF. That is, the ratio of Cgd to Cgs in this application is approximately 0.00005, which is much smaller than the ratio of Cgd to Cgs in the MOSFET without a shielding layer (approximately 0.013). Because the gate-source parasitic capacitance Cgs of the MOSFET provided in this application is larger, when the MOSFET is turned off, the displacement current generated by the discharge of the gate-drain parasitic capacitance Cgd will be weakened by the gate-source parasitic capacitance Cgs, and will not cause gate voltage oscillation. Compared with the MOSFET without a shielding layer, the MOSFET provided in this application has a significantly lower risk of gate mis-turn-on and is easier to achieve zero-voltage turn-off.

[0089] In one embodiment, this application also provides a method for fabricating a metal-oxide-semiconductor field-effect transistor, such as... Figure 6 As shown, it includes the following S100-S900.

[0090] S100 provides a substrate of the first conductivity type.

[0091] S200, a drift region of the first conductivity type is formed on the substrate.

[0092] like Figure 7 As shown, the drift region 200 can be formed on the substrate 100 using an epitaxial growth process.

[0093] S300, the etched drift area, forms alternating first and second trenches.

[0094] like Figure 7 As shown, photolithography and etching processes can be used to etch the drift region 200 to form alternating first trenches 1210 and second trenches 1220.

[0095] S400, a first well region of a second conductivity type is formed in the drift region based on a first trench, and a second well region of a second conductivity type is formed in the drift region based on a second trench; the drift region between the first well region and the second well region serves as the JFET region.

[0096] like Figure 8 and Figure 9 As shown, an ion implantation process can be used to form a first well region 310 of a second conductivity type within a drift region 200 based on a first trench 1210, and a second well region 320 of the second conductivity type within a drift region 200 based on a second trench 1220. In a first direction, the drift region 200 between the first well region 310 and the second well region 320 serves as a first JFET region 410, and in a second direction, the drift region 200 between the first well region 310 and the second well region 320 serves as a second JFET region 420. The first JFET region 410 and the second JFET region 420 intersect.

[0097] S500 forms a shielding layer of a second conductivity type on the side of the JFET region away from the drift region.

[0098] like Figure 10 and Figure 11 As shown, an ion implantation process can be used to form a shielding layer 500 on the side of the JFET region 400 away from the drift region 200.

[0099] S600, a gate is formed on the portion of the first well region away from the drift region, the portion of the second well region away from the drift region, and the exposed surface of the shielding layer.

[0100] like Figure 12 As shown, the gate 600 can be formed on the part of the first well region 310 away from the drift region 200, the part of the second well region 320 away from the drift region 200, and the exposed surface of the shielding layer 500 by processes such as deposition, photolithography, and etching.

[0101] S700, etch the gate to form a third trench, the third trench exposes the shielding layer.

[0102] like Figure 13 As shown, an etching process can be used to etch the gate 600 to form a third trench, which exposes the shielding layer 500.

[0103] S800 forms a conductive contact structure within the third trench.

[0104] The conductive contact structure 1100 can be formed in the third trench using processes such as deposition and grinding. The bottom of the conductive contact structure 1100 is in contact with the shielding layer 500.

[0105] S900 forms a source metal layer on the remaining surface of the first well region away from the drift region, the remaining surface of the second well region away from the drift region, the exposed surface of the gate, and the side of the conductive contact structure away from the shielding layer.

[0106] like Figure 1 As shown, a source metal layer 700 is formed on the remaining surface of the first well region 310 away from the drift region 200, the remaining surface of the second well region 320 away from the drift region 200, the exposed surface of the gate 600, and the side of the conductive contact structure away from the shielding layer 500.

[0107] In this embodiment, a shielding layer 500 of a second conductivity type is formed on the side of the JFET region 400 away from the drift region 200. A gate 600 is formed on a portion of the surface of the first well region 310 away from the drift region 200, a portion of the surface of the second well region 320 away from the drift region 200, and the exposed surface of the shielding layer 500. Then, the gate 600 is etched to form a third trench, which exposes the shielding layer 500. A conductive contact structure 1100 is formed within the third trench. Subsequently, the remaining surfaces of the first well region 310 away from the drift region 200, the remaining surfaces of the second well region 320 away from the drift region 200, the exposed surface of the gate 600, and the conductive contact structure away from the shielding layer 500 are then formed. On one side of layer 500, a source metal layer 700 is formed. Thus, the shielding layer 500 can be connected to the source metal layer 700 through the conductive contact structure 1100 penetrating the gate 600. This increases the coupling strength between the gate 600 and the source, and decreases the coupling strength between the gate 600 and the drain. This increases the parasitic capacitance Cgs between the gate 600 and the source, and decreases the parasitic capacitance Cgd between the gate 600 and the drain. Therefore, at the moment of device turn-off, the displacement current generated by the discharge of Cgd is weakened by the increased Cgs, insufficient to cause oscillation in the gate 600 voltage. The gate 600 remains at a low potential, preventing false turn-on, thus providing a structural basis for achieving zero-voltage turn-off. Based on this, by appropriately adjusting the doping concentration of the channel, the device threshold voltage can be reduced to the zero-voltage turn-off range, achieving zero-voltage turn-off.

[0108] In one embodiment, the metal-oxide-semiconductor field-effect transistor provided in this application can also be a trench-type metal-oxide-semiconductor field-effect transistor, such as... Figure 14 As shown, the shielding layer 500 is located at the bottom of the trench gate 1300, and / or the trench gate 1300 is located on the side near the substrate 100 and connected to the source metal layer 700 through a conductive contact structure 1100 penetrating the trench gate 1300. This shielding layer 500 can increase the coupling strength between the trench gate 1300 and the source, and decrease the coupling strength between the trench gate 1300 and the drain, thereby increasing the parasitic capacitance Cgs between the trench gate 1300 and the source, and decreasing the parasitic capacitance Cgd between the trench gate 1300 and the drain. Thus, at the moment of device turn-off, the displacement current generated by the discharge of Cgd will be weakened by the increased Cgs, insufficient to cause oscillation of the trench gate 1300 voltage. The trench gate 1300 remains at a low potential and will not be falsely turned on, providing a structural basis for achieving zero-voltage turn-off. Based on this, the device threshold voltage can be reduced to the zero-voltage turn-off range by reasonably adjusting the doping concentration of the channel, achieving zero-voltage turn-off.

[0109] In the description of this specification, references to terms such as "some embodiments," "other embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0110] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0111] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A metal oxide semiconductor field effect transistor, characterized by, The MOSFET includes at least one cell structure; the cell structure includes: a substrate having a first conductivity type; a drift region on the substrate having the first conductivity type; a first well region on a side of the drift region away from the substrate having a second conductivity type; a JFET region on a side of the drift region away from the substrate and on a side of the first well region in a first direction having the first conductivity type; the first direction being perpendicular to a direction from the substrate to the JFET region; a second well region on a side of the drift region away from the substrate and on a side of the JFET region away from the first well region having the second conductivity type; a shield layer on a side of the JFET region away from the drift region having the second conductivity type; a gate covering a portion of a surface of the first well region on a side away from the drift region, a portion of a surface of the second well region on a side away from the drift region, and the shield layer; a source metal layer covering a remaining surface of the first well region on a side away from the drift region, a remaining surface of the second well region on a side away from the drift region, and the gate; a conductive contact structure penetrating the gate in a direction perpendicular to the substrate and connected with the shield layer and the source metal layer, respectively.

2. The MOSFET of claim 1, wherein, A doping concentration of the shield layer is greater than a doping concentration of the first well region and greater than a doping concentration of the second well region.

3. The MOSFET of claim 1, wherein: An area of a normal projection of the shield layer on the substrate is less than an area of a normal projection of the JFET region on the substrate.

4. The MOSFET of claim 1, wherein: The MOSFET includes a plurality of cell structures arranged in an array; wherein a plurality of the cell structures arranged in a first direction have a first shield layer extending in a second direction; a plurality of the cell structures arranged in the second direction have a second shield layer extending in the first direction; the second direction being perpendicular to a direction from the substrate to the JFET region and perpendicular to the first direction; the first shield layer intersects the second shield layer.

5. The MOSFET of claim 4, wherein: A plurality of the cell structures arranged in the first direction have a first conductive contact structure extending in the second direction; a plurality of the cell structures arranged in the second direction have a second conductive contact structure extending in the first direction; the first conductive contact structure intersects the second conductive contact structure.

6. The MOSFET of claim 4, wherein: A plurality of the cell structures arranged in the first direction have a first conductive contact structure, and a plurality of the cell structures arranged in the second direction have a second conductive contact structure; The MOSFET further includes a third conductive contact structure penetrating a target gate region in a direction perpendicular to the substrate; the target gate region being a gate covering an intersection region of the first shield layer and the second shield layer; wherein each conductive contact structure is spaced apart.

7. The MOSFET of claim 1, wherein: The cell structure further includes: a first insulating layer between the gate and the shield layer; a second insulating layer between the gate and the source metal layer.

8. The MOSFET of claim 1, wherein: The cell structure further includes: a third insulating layer between the gate and the conductive contact structure.

9. The MOSFET of claim 1, wherein, The cell structure further comprises: a drain metal layer on a side of the substrate away from the drift region.

10. A method of manufacturing a metal oxide semiconductor field effect transistor, characterized by, comprises: providing a substrate of a first conductivity type; forming a drift region of the first conductivity type on the substrate; etching the drift region to form first and second trenches arranged alternately and spaced apart; forming a first well region of a second conductivity type in the drift region based on the first trenches and a second well region of the second conductivity type in the drift region based on the second trenches; a drift region between the first and second well regions as a JFET region; forming a shield layer of the second conductivity type on a side of the JFET region away from the drift region; forming a gate on a part of a surface of the first well region away from the drift region, a part of a surface of the second well region away from the drift region, and an exposed surface of the shield layer; etching the gate to form a third trench exposing the shield layer; forming a conductive contact structure in the third trench; forming a source metal layer on a remaining surface of the first well region away from the drift region, a remaining surface of the second well region away from the drift region, an exposed surface of the gate, and a side of the conductive contact structure away from the shield layer.

Images