Semiconductor structure and preparation method thereof
By setting flush sacrificial pattern sidewalls in the semiconductor structure, the gate load problem caused by the height difference of the active region in shallow trench isolation structures is solved, thereby improving semiconductor performance and process window.
Patent Information
- Application Number
- CN202411111001.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-13
- Publication Date
- 2026-02-27
AI Technical Summary
In the prior art, the height difference between the upper surface of the shallow trench isolation structure and the upper surface of the active region leads to a load problem on the gate in the semiconductor structure, which affects performance.
By forming multiple spaced sacrificial patterns in the substrate and forming flush sidewalls on their sidewalls, the height difference problem of the sacrificial pattern sidewalls is solved, thereby alleviating the gate load problem.
It improves the performance of the semiconductor structure, increases the process window from gate to interconnect structure, and improves the overall performance of the semiconductor structure.
Smart Images
Figure CN121586285A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, specifically to a semiconductor structure and its fabrication method. Background Technology
[0002] In existing substrates, the active region is isolated within the substrate by forming a shallow trench isolation (STI) structure. The upper surface of the shallow trench isolation structure is higher than the upper surface of the active region, resulting in a height difference (SH) between the upper surface of the shallow trench isolation structure and the upper surface of the active region. When a gate structure including the gate and sidewalls located on the gate sidewalls is formed on the upper surface of the substrate, the height difference between the sidewalls on the upper surface of the active region and the sidewalls on the shallow trench isolation structure causes a severe loading problem for the gate, which seriously affects the performance of the semiconductor structure. Summary of the Invention
[0003] The purpose of this application is to provide a semiconductor structure and its fabrication method, which can eliminate the problem of height difference on the upper surface of the sidewall of the sacrificial pattern sidewall caused by the height difference between the upper surface of the shallow trench isolation structure and the upper surface of the active region, thereby improving the height uniformity of the sidewall in the semiconductor structure, alleviating the gate load problem, and improving the performance of the semiconductor structure.
[0004] To achieve the objectives of this application, the following technical solution is provided:
[0005] In a first aspect, this application provides a method for fabricating a semiconductor structure, comprising:
[0006] A substrate is provided in which a shallow trench isolation structure is formed, the shallow trench isolation structure isolating an active region within the substrate; the top surface of the shallow trench isolation structure is not flush with the top surface of the active region;
[0007] Multiple sacrificial patterns are formed at intervals, with the top surfaces of each sacrificial pattern being flush; at least a portion of the sacrificial patterns cross the boundary between adjacent shallow trench isolation structures and the active region; the boundary includes a boundary line and / or an interface.
[0008] Sidewalls are formed on the sidewalls of each of the sacrificial shapes, and the top surface of the sidewalls located on the sidewalls of the sacrificial shapes is flush with the sidewalls.
[0009] The semiconductor structure fabrication method of this application solves the problem of height difference between the top surfaces of the sidewalls of the sacrificial patterns caused by the height difference between the top surface of the shallow trench isolation structure and the top surface of the active region, by setting multiple spaced sacrificial patterns with their top surfaces flush. This alleviates the gate load problem and improves the performance of the semiconductor structure.
[0010] In one embodiment, forming a plurality of spaced-apart sacrificial patterns includes:
[0011] A sacrificial layer is formed, which covers the top surface of the shallow trench isolation structure and the top surface of the active region;
[0012] The sacrificial layer is planarized to make its top surface flush.
[0013] The planarized sacrificial layer is patterned to obtain multiple spaced sacrificial patterns.
[0014] In one embodiment, the sacrificial layer is planarized using a chemical mechanical polishing process.
[0015] In one embodiment, the sacrificial layer includes a hard mask layer.
[0016] In one embodiment, forming sidewalls on the sidewalls of each of the sacrificial patterns includes:
[0017] A sidewall material layer is formed, which covers the sidewall of the sacrificial pattern, the top surface of the sacrificial pattern, the exposed surface of the shallow trench isolation structure, and the exposed surface of the active area;
[0018] Remove the sidewall material layer from the top surface of the sacrificial pattern, the exposed surface of the shallow trench isolation structure, and the exposed surface of the active area to obtain the sidewall covering the sidewall of the sacrificial pattern.
[0019] In one embodiment, after forming a sidewall on the sidewall of each of the sacrificial patterns, and the sidewall being flush with the top surface of the sidewall of the sacrificial pattern, the method further includes:
[0020] Remove the sacrificial pattern to obtain the sacrificial gap;
[0021] A gate is formed, which fills the sacrificial gap.
[0022] In one embodiment, at least one of the gates spans the boundary between an adjacent shallow trench isolation structure and the active region, with the top surface of the gate flush with the top surface of the sidewall.
[0023] Secondly, this application also provides a semiconductor structure, comprising:
[0024] A substrate having a shallow trench isolation structure therein, the shallow trench isolation structure isolating an active region within the substrate; the top surface of the shallow trench isolation structure is not flush with the top surface of the active region;
[0025] Multiple gates spaced apart, at least one of the gates spanning the boundary between an adjacent shallow trench isolation structure and an active region; the boundary includes a boundary line and / or an interface.
[0026] Sidewalls, located on the sidewalls of each of the gates, are flush with the top surface of the sidewalls located on the sidewalls of the gates.
[0027] The semiconductor structure of this application solves the problem of height difference between the gate sidewalls caused by the height difference between the top surface of the shallow trench isolation structure and the top surface of the active region by setting the top surface of the gate sidewalls to be flush with the top surface of the sidewalls. This alleviates the gate load problem, increases the process window from the gate to the interconnect structure, and improves the performance of the semiconductor structure.
[0028] In one embodiment, the top surface of the gate is flush with the top surface of the sidewall.
[0029] In one embodiment, the gate and the sidewall covering the gate together constitute a gate structure; the substrate includes a core region and an input / output region located around the core region, and both the core region and the input / output region have a plurality of gate structures, wherein the spacing between adjacent gate structures in the core region is smaller than the spacing between adjacent gate structures in the input / output region. Attached Figure Description
[0030] To more clearly illustrate the technical solutions in the embodiments or conventional technologies of this disclosure, the accompanying drawings used in the description of the embodiments or conventional technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0031] Figure 1 This is a schematic diagram of a cross-sectional structure of a semiconductor structure provided in related technologies;
[0032] Figure 2 This is a flowchart of a method for fabricating a semiconductor structure provided in one embodiment;
[0033] Figure 3 This is a flowchart of step S12 in a method for fabricating a semiconductor structure provided in one embodiment;
[0034] Figure 4This is a flowchart of step S13 in a method for fabricating a semiconductor structure provided in one embodiment;
[0035] Figure 5 This is a flowchart of steps S14 to S15 in a method for fabricating a semiconductor structure provided in one embodiment;
[0036] Figure 6 This is a schematic cross-sectional view of the structure obtained in step S11 of a semiconductor structure fabrication method provided in one embodiment;
[0037] Figure 7 This is a schematic cross-sectional view of the structure obtained in step S121 of a semiconductor structure fabrication method provided in one embodiment;
[0038] Figure 8 This is a schematic cross-sectional view of the structure obtained in step S122 of a semiconductor structure fabrication method provided in one embodiment;
[0039] Figure 9A , Figure 9B This is a schematic cross-sectional view of the structure obtained in step S123 of a semiconductor structure fabrication method provided in different embodiments;
[0040] Figure 10 This is a schematic cross-sectional view of the structure obtained in step S131 of a semiconductor structure fabrication method provided in one embodiment;
[0041] Figure 11 This is a schematic cross-sectional view of the structure obtained in step S132 of a semiconductor structure fabrication method provided in one embodiment;
[0042] Figure 12 This is a schematic cross-sectional view of the structure obtained in step S14 of a semiconductor structure fabrication method provided in one embodiment;
[0043] Figure 13A , Figure 13B This is a schematic cross-sectional view of the structure obtained in step S15 of a semiconductor structure fabrication method provided in different embodiments;
[0044] Figure 14 This is a top view of a semiconductor structure provided in another embodiment;
[0045] Figure 15 Another embodiment provides a semiconductor structure such as Figure 13A A schematic diagram of the cross-sectional structure along the x-direction shown;
[0046] Figure 16 Another embodiment provides a semiconductor structure such as Figure 13A The diagram shows a cross-sectional structure along the y-direction.
[0047] Explanation of reference numerals in the attached figures
[0048] 10. Substrate; 20. Shallow trench isolation structure; 30. Active region; 40. Sacrificial pattern; 401. Sacrificial layer; 402. Sacrificial gap; 50. Sidewall; 501. Sidewall material layer; 60. Gate. Detailed Implementation
[0049] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.
[0051] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
[0052] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.
[0053] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0054] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of the invention, thus allowing for variations in the illustrated shape due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the invention.
[0055] By forming a shallow trench isolation (STI) structure within the substrate, the active region is isolated within the substrate. The top surface of the shallow trench isolation structure is not flush with the top surface of the active region, resulting in a height difference (SH) between them. When a gate structure, including the gate and sidewalls located on the gate sidewalls, is formed on the top surface of the substrate, a height difference will exist between the sidewalls on the top surface of the active region and the sidewalls of the shallow trench isolation structure. Figure 1As shown, the height difference will cause an imbalance in the load on the local surfaces of the chip after the sidewalls are grown, resulting in a serious loading problem on the gate, which will seriously affect the performance of the semiconductor structure.
[0056] One improvement is to introduce PREB (Photo Resist Etch Back) technology, which alleviates the gate load problem by step-by-step etching away the hard mask pattern with sidewalls formed on the sidewalls by adjusting the etching selectivity. However, in the above solution, due to the different densities of the hard mask patterns in the core region and the input / output (IO) region, there is a large height difference between the coated photoresist in these two regions. Furthermore, PREB can only solve the load problem of the dummy gate and the height of the dummy gate hard mask pattern (dummy gate HM), but cannot solve the load problem caused by the sidewall height during gate filling.
[0057] Please see Figure 2 This application provides a method for preparing a semiconductor structure, which may include the following steps S11 to S13.
[0058] S11: Provide a substrate in which a shallow trench isolation structure is formed, the shallow trench isolation structure isolating the active region within the substrate; the top surface of the shallow trench isolation structure is not flush with the top surface of the active region.
[0059] S12: Form multiple sacrificial patterns arranged at intervals, with the top surfaces of each sacrificial pattern being flush; at least some of the sacrificial patterns cross the boundary between the adjacent shallow trench isolation structure and the active region; the boundary includes the boundary line and / or the interface.
[0060] S13: A side wall is formed on the side wall of each sacrificial figure, and the top surface of the side wall located on the side wall of the sacrificial figure is flush with the side wall.
[0061] In this embodiment, by setting multiple spaced sacrificial patterns with their top surfaces flush, the problem of height difference between the top surface of the shallow trench isolation structure and the top surface of the active region, which in turn leads to a height difference between the top surfaces of the sidewalls of the sacrificial patterns, is solved. This alleviates the gate load problem and improves the performance of the semiconductor structure.
[0062] For example, the sacrifice pattern can include, but is not limited to, the pattern formed after etching the hard mask layer.
[0063] In some embodiments, please refer to Figure 3 In step S12, forming multiple spaced-apart sacrificial patterns may include the following steps S121 to S123.
[0064] S121: A sacrificial layer is formed, which covers the top surface of the shallow trench isolation structure and the top surface of the active region.
[0065] S122: Planarize the sacrificial layer to make its top surface flush.
[0066] S123: The planarized sacrificial layer is patterned to obtain multiple spaced sacrificial patterns.
[0067] For example, a chemical mechanical polishing process can be used to planarize the sacrificial layer.
[0068] In some embodiments, please refer to Figure 4 In step S13, forming sidewalls on the sidewalls of each sacrificial pattern may include the following steps S131 to S132.
[0069] S131: Form a sidewall material layer that covers the sidewalls of the sacrificial pattern, the top surface of the sacrificial pattern, the exposed surface of the shallow trench isolation structure, and the exposed surface of the active area.
[0070] S132: Remove the sidewall material layer from the top surface of the sacrificial pattern, the exposed surface of the shallow trench isolation structure, and the exposed surface of the active area to obtain a sidewall covering the sidewall of the sacrificial pattern.
[0071] In some embodiments, please refer to Figure 5 After step S13, the method for preparing the semiconductor structure may further include the following steps S14 to S15.
[0072] S14: Remove the sacrifice pattern to obtain the sacrifice gap.
[0073] S15: Form the gate, and fill the sacrificial gap with the gate.
[0074] For example, at least one gate spans the boundary between an adjacent shallow trench isolation structure and the active region, with the top surface of the gate flush with the top surface of the sidewall.
[0075] It should be understood that, although Figures 2-5 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figures 2-5 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages does not have to be sequential, but can be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.
[0076] To more clearly illustrate the fabrication methods of the semiconductor device structures in the above embodiments, the following embodiments are provided in conjunction with... Figures 5-16 I understand.
[0077] In step S11, please refer to Figure 2 Step S11 in the middle and Figure 6 A substrate 10 is provided, and a shallow trench isolation structure 20 is formed in the substrate 10. The shallow trench isolation structure 20 isolates an active region 30 in the substrate 10. The top surface of the shallow trench isolation structure 20 is not flush with the top surface of the active region 30.
[0078] As an example, substrate 10 may include, but is not limited to, at least one of silicon substrate, gallium nitride (GaN) substrate, silicon carbide (SiC) substrate, sapphire substrate, silicon on insulator (SOI) substrate, silicon on diamond (SOD) substrate, and strained silicon substrate deposited on germanium-silicon wafer; specifically, in this embodiment, substrate 10 is a silicon substrate.
[0079] As an example, the shallow trench isolation structure 20 can be formed by depositing, patterning, and etching a substrate 10 using a silicon nitride mask to form shallow trenches (not shown), and filling the shallow trenches with deposited oxide to form the shallow trench isolation structure 20.
[0080] As an example, an active region (not shown) and a drain region (not shown) can be formed within the active region 30. Specifically, doped ions can be implanted into the substrate 10 using an ion implantation process to form the source and drain regions. The doped ions can be P-type ions or N-type ions; the source and drain regions are arranged alternately.
[0081] In another example, after providing the substrate 10, the method for fabricating the semiconductor device structure may further include a step of cleaning the substrate 10. By cleaning the substrate 10, impurities present on the surface of the substrate 10 can be removed, preventing these impurities from affecting subsequent processes and thus ensuring device performance. Specifically, the substrate 10 can be cleaned using a cleaning solution or by purging it with a gas such as nitrogen. It should be noted that when cleaning the substrate 10 with a cleaning solution, a step of drying the substrate 10 is also included after cleaning. Specifically, this drying process may include, but is not limited to, purging the substrate 10 with a gas such as nitrogen.
[0082] In yet another example, after providing the substrate 10, the method for fabricating the semiconductor device structure may further include creating alignment marks on the substrate 10. Thus, the alignment marks created on the substrate 10 can serve as alignment reference marks for subsequent fabrication processes or measurements, ensuring the accuracy of subsequent fabrication processes or measurements.
[0083] In step S12, please refer to Figure 2 Step S12 in the middle and Figure 3 , Figures 7 to 9B Multiple sacrificial patterns 40 are arranged at intervals, with the top surfaces of each sacrificial pattern 40 being flush; at least some of the sacrificial patterns 40 span the boundary between the adjacent shallow trench isolation structure 20 and the active region 30; the boundary includes the boundary line and / or the interface.
[0084] As an example, at least a portion of the sacrificial pattern 40 spans the boundary between adjacent shallow trench isolation structures 20 and active regions 30 to provide generation space for at least one subsequent gate to span the boundary between adjacent shallow trench isolation structures 20 and active regions 30. In a specific example, a sacrificial pattern 40 can only span one boundary between adjacent shallow trench isolation structures 20 and active regions 30; the boundary includes at least one of an interface and a boundary line, and the active regions 30 and shallow trench isolation structures 20 form a structure with an interface, such as... Figure 9A As shown, the active region 30 and the shallow trench isolation structure 20 form a structure with a boundary line, as shown in the figure. Figure 9B As shown in the figure. By setting at least a portion of the sacrificial pattern 40 across the boundary between the adjacent shallow trench isolation structure 20 and the active region 30, with the top surface of the sacrificial pattern flush with it, and then forming a sidewall flush with the top surface of the sidewall of the sacrificial pattern, the problem of the height difference between the top surfaces of the sidewalls of the sacrificial pattern is solved, thereby alleviating the gate load problem and improving the performance of the semiconductor structure.
[0085] It should be noted that, as those skilled in the art will know, under normal circumstances, a gate can only span the boundary between one adjacent shallow trench isolation structure 20 and the active region 30, and a gate will not span two active regions 30. A sacrificial pattern 40 is used to replace a gate. Therefore, a sacrificial pattern 40 can only span the boundary between one adjacent shallow trench isolation structure 20 and the active region 30, and a sacrificial pattern 40 will not span two active regions 30.
[0086] In some embodiments, please continue reading Figure 3 , Figures 7 to 9B Step S12 may include steps S121 to S123.
[0087] In step S121, a sacrificial layer 401 is formed, which covers the top surface of the shallow trench isolation structure 20 and the top surface of the active region 30, such as... Figure 7 As shown in the image.
[0088] As an example, the sacrificial layer 401 can be formed using, but is not limited to, molecular beam epitaxy (MBE), physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD). The sacrificial layer 401 may include, but is not limited to, a hard mask layer. Specifically, the hard mask layer may be, but is not limited to, an insulating layer, such as at least one of silicon oxide, silicon nitride, or silicon oxynitride. The sacrificial layer 401 may include a monolayer structure or a stacked structure. For example, in this embodiment, the sacrificial layer 401 is a monolayer structure.
[0089] In step S122, the sacrificial layer 401 is planarized to make its top surface flush, such as... Figure 8 As shown in the image.
[0090] As an example, chemical mechanical polishing (CMP) can be used, but is not limited to, to planarize the sacrificial layer 401 so that its top surface is planar. CMP is a combination of mechanical grinding and chemical etching, using ultrafine ion polishing and the chemical etching effect of the slurry to form a smooth plane on the surface of the polished medium. CMP can achieve global planarization, planarizing the surfaces of all types of materials and multilayer materials. It also reduces the stringent requirements on film morphology caused by smaller design dimensions and increased wiring layers, avoiding reactive ion etching and plasma etching of difficult-to-etch metals or alloys. This improves the reliability, speed, and yield of devices and circuits of 0.25µm and below, improves material step coverage, and removes surface defects.
[0091] In step S123, the planarized sacrificial layer 401 is patterned to obtain multiple spaced sacrificial patterns 40, such as... Figure 9A and Figure 9B As shown in the image.
[0092] As an example, the planarized sacrificial layer 401 can be patterned using, but is not limited to, photolithography and wet etching processes or dry etching processes to obtain multiple spaced sacrificial patterns 40. Specifically, in this embodiment, the planarized sacrificial layer 401 can be patterned using photolithography and dry etching processes to obtain multiple spaced sacrificial patterns 40.
[0093] In step S13, please refer to Figure 1 Step S13 in the middle and Figure 4 , Figures 10 to 11 Side walls 50 are formed on the side walls of each sacrificial figure 40, and the top surface of the side walls 50 located on the side walls of the sacrificial figure 40 is flush with the side walls 40.
[0094] In some embodiments, please continue reading Figures 10 to 11 Step S13 may include steps S131 to S132.
[0095] In step S131, a sidewall material layer 501 is formed, which covers the sidewalls of the sacrificial pattern 40, the top surface of the sacrificial pattern 40, the exposed surface of the shallow trench isolation structure 20, and the exposed surface of the active region 30, such as... Figure 10 As shown in the image.
[0096] As an example, the sidewall material layer 501 can be formed using, but is not limited to, molecular beam epitaxy, physical vapor deposition, chemical vapor deposition, or atomic layer deposition. The sidewall material layer 501 can be any dielectric layer. For example, the sidewall material layer can include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a structure comprising silicon oxide, silicon nitride, and silicon oxide (ONO) layers stacked sequentially from the inside out.
[0097] In step S132, the sidewall material layer 501 located on the top surface of the sacrificial pattern 40, the exposed surface of the shallow trench isolation structure 20, and the exposed surface of the active region 30 is removed to obtain a sidewall 50 covering the sidewalls of the sacrificial pattern 40, as shown below. Figure 11 As shown in the image.
[0098] As an example, photolithography and wet etching processes or dry etching processes can be used to remove the sidewall material layer 501 located on the top surface of the sacrificial pattern 40, the exposed surface of the shallow trench isolation structure 20 and the exposed surface of the active region 30, so as to obtain the sidewall 50 covering the sidewall of the sacrificial pattern 40. Specifically, in this embodiment, step S132 may include the following steps S1321 to S1326.
[0099] S1321: A hard mask layer (not shown) is formed on the top surface of the sidewall material layer 501.
[0100] S1322: A photoresist layer (not shown) is formed on the top surface of the hard mask layer.
[0101] S1323: Expose and develop the photoresist layer to obtain a patterned photoresist layer.
[0102] S1324: Etching a hard mask layer based on a patterned photoresist layer to obtain a patterned hard mask layer; specifically, the hard mask layer can be etched using, but is not limited to, a dry etching process. In a specific embodiment, the obtained structure is placed in a dry etching machine, and a reactive gas is input into the dry etching machine. The reactive gas reacts with the hard mask layer to obtain a patterned hard mask layer.
[0103] S1325: Remove the patterned photoresist layer; etch the sidewall material layer 501 based on the patterned hard mask layer to obtain the sidewall 50; specifically, the patterned photoresist layer can be removed using, but is not limited to, an ashing process. The ashing process utilizes highly reactive single atoms in oxygen plasma to react with hydrocarbon polymers in the photoresist, thereby generating volatile reactants, ultimately removing the photoresist layer. The ashing process can handle large sample volumes, is simple to operate, and is very safe; the sidewall material layer 501 can be etched using, but is not limited to, a dry etching process.
[0104] S1326: Remove the patterned hard mask layer; specifically, the patterned hard mask layer may be removed using, but is not limited to, chemical mechanical polishing or etching processes.
[0105] In step S14, please refer to Figure 5 Step S14 in the middle and Figure 12 Remove the sacrificial pattern 40 to obtain the sacrificial gap 402.
[0106] As an example, the sacrificial pattern 40 can be removed using, but is not limited to, photolithography and wet etching processes or dry etching processes to obtain the sacrificial gap 402. In a specific embodiment, the top surface of the obtained structure is photolithographically formed into a mask and then placed in a wet etching tank. The chemical reaction is achieved by controlling the solution ratio, temperature, and reaction time. After the reaction is completed, the obtained structure is removed from the tank, rinsed to remove residual liquid from the surface, and then dewatered and dried to complete the entire process of removing the sacrificial pattern 40. The parameters that can be controlled in this process include the solution ratio, temperature, and reaction time.
[0107] In step S15, please refer to Figure 5 Step S15 in the middle and Figures 13A-13B A gate 60 is formed, and the gate 60 fills the sacrificial gap 402.
[0108] As an example, forming the gate 60 may include the following steps S151 to S152.
[0109] S151: Fill the sacrificial gap 402 with a gate material layer (not shown); specifically, the gate material layer may include at least one of a polysilicon layer or a metal layer; the gate material layer may be formed using, but is not limited to, a chemical vapor deposition process.
[0110] S152: Remove the gate material layer outside the sacrificial gap 402 to form the gate 60; specifically, the gate material layer can be polished using a chemical mechanical polishing process.
[0111] This application also provides a semiconductor structure, please refer to... Figures 2 to 12 See Figures 13A to 16 The semiconductor structure may include a substrate 10, a plurality of spaced gates 60 and sidewalls 50. The substrate 10 has a shallow trench isolation structure 20, which isolates an active region 30 within the substrate. The top surface of the shallow trench isolation structure 20 is not flush with the top surface of the active region 30. At least one of the spaced gates 60 spans the boundary between an adjacent shallow trench isolation structure 20 and the active region 30. The sidewalls 50 are located on the sidewalls of each gate 60, and the top surfaces of the sidewalls 50 located on the sidewalls of the gates 60 are flush.
[0112] In this embodiment, by setting the top surface of the sidewall of the gate sidewall to be flush, the problem of height difference in the sidewall of the gate caused by the height difference between the top surface of the shallow trench isolation structure and the top surface of the active region is solved, thereby alleviating the gate load problem, increasing the process window from the gate to the interconnect structure, and improving the performance of the semiconductor structure.
[0113] As an example, substrate 10 may include, but is not limited to, at least one of silicon substrate, gallium nitride (GaN) substrate, silicon carbide (SiC) substrate, sapphire substrate, silicon on insulator (SOI) substrate, silicon on diamond (SOD) substrate, and strained silicon substrate deposited on germanium-silicon wafer; in this embodiment, substrate 10 is a silicon substrate.
[0114] As an example, the shallow trench isolation structure 20 can be formed by depositing, patterning, and etching a substrate 10 using a silicon nitride mask to form shallow trenches (not shown), and filling the shallow trenches with deposited oxide to form the shallow trench isolation structure 20.
[0115] As an example, an active region (not shown) and a drain region (not shown) can be formed within the active region 30. Specifically, a particle implantation process can be used to implant doped ions into the substrate 10 to form the source and drain regions. The doped ions can be P-type ions or N-type ions. The source and drain regions are arranged alternately.
[0116] As an example, the multiple spaced gates 60 may include, but are not limited to, at least one of metal gates or polysilicon gates.
[0117] As an example, the sidewall 50 can be made of any dielectric layer. For example, the sidewall 50 can include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a structure comprising silicon oxide, silicon nitride, and silicon oxide (ONO) layers stacked sequentially from the inside out.
[0118] In some embodiments, at least one gate 60 spans the boundary between an adjacent active region 30 and a shallow trench isolation structure 20.
[0119] As an example, at least one gate 60 spans the boundary between an adjacent active region 30 and the shallow trench isolation structure 20, the boundary including an interface or boundary line. In a specific example, a gate 60 can only span one boundary between an adjacent shallow trench isolation structure 20 and the active region 30; the boundary between the adjacent active region 30 and the shallow trench isolation structure 20 is an interface structure as shown below. Figure 13A As shown in the diagram, the boundary line is located at the junction of the adjacent active region 30 and the shallow trench isolation structure 20. Figure 13B As shown in the figure. By setting at least one gate 60 across the boundary between the adjacent active region 30 and the shallow trench isolation structure 20, and with the top surface of the gate 60 flush with the top surface of the sidewall, the problem of the height difference between the top surfaces of the sidewall is solved, thereby alleviating the gate load problem and improving the performance of the semiconductor structure.
[0120] In some embodiments, please refer to Figures 13A to 16 The gate 60 and the sidewall 50 covering the gate 60 together constitute the gate structure. The substrate 10 may include a core region (not shown) and an input / output region (not shown) located around the core region. Both the core region and the input / output region have multiple gate structures. The spacing between adjacent gate structures in the core region is smaller than the spacing between adjacent gate structures in the input / output region. Specifically, the core region is used to form the core device structure, and the input / output region is used to form logic circuits, etc., connected to the core device structure.
[0121] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0122] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A method of fabricating a semiconductor structure, characterized by, The method comprises the following steps: providing a substrate, a shallow trench isolation structure is formed in the substrate, and the shallow trench isolation structure separates an active region in the substrate; a top surface of the shallow trench isolation structure is not flush with a top surface of the active region; forming a plurality of spaced-apart sacrificial patterns, a top surface of each of the sacrificial patterns is flush; at least part of the sacrificial patterns span a junction between adjacent shallow trench isolation structures and active regions; the junction includes a junction line and / or a junction surface; forming a side wall on a sidewall of each of the sacrificial patterns, a top surface of the side wall on the sidewall of the sacrificial pattern is flush.
2. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The method of forming a plurality of spaced-apart sacrificial patterns comprises: forming a sacrificial layer, the sacrificial layer covers a top surface of the shallow trench isolation structure and a top surface of the active region; planarizing the sacrificial layer so that a top surface of the sacrificial layer is flush; patterning the planarized sacrificial layer to obtain a plurality of spaced-apart sacrificial patterns.
3. The method of claim 2, wherein the semiconductor structure is prepared by a method comprising: The planarization of the sacrificial layer is performed by a chemical mechanical polishing process.
4. The method of claim 2, wherein the semiconductor structure is prepared by a method comprising: The sacrificial layer comprises a hard mask layer.
5. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The method of forming a side wall on a sidewall of each of the sacrificial patterns comprises: forming a side wall material layer, the side wall material layer covers a sidewall of the sacrificial pattern, a top surface of the sacrificial pattern, an exposed surface of the shallow trench isolation structure, and an exposed surface of the active region; removing the side wall material layer on the top surface of the sacrificial pattern, the exposed surface of the shallow trench isolation structure, and the exposed surface of the active region to obtain the side wall covering the sidewall of the sacrificial pattern.
6. The method of producing a semiconductor structure according to any one of claims 1 to 5, wherein After the top surface of the side wall on the sidewall of the sacrificial pattern is flush, the method further comprises: removing the sacrificial pattern to obtain a sacrificial gap; forming a gate, the gate fills the sacrificial gap.
7. The method of claim 6, wherein the semiconductor structure is prepared by a method comprising: At least one of the gates spans a junction between adjacent shallow trench isolation structures and active regions, and a top surface of the gate is flush with a top surface of the side wall.
8. A semiconductor structure, characterized by The method comprises the following steps: providing a substrate, a shallow trench isolation structure is formed in the substrate, and the shallow trench isolation structure separates an active region in the substrate; a top surface of the shallow trench isolation structure is not flush with a top surface of the active region; a plurality of spaced-apart gates, at least one of the gates spans a junction between adjacent shallow trench isolation structures and active regions; the junction includes a junction line and / or a junction surface; a side wall on a sidewall of each of the gates, a top surface of the side wall on the sidewall of the gate is flush.
9. The semiconductor structure of claim 8, wherein, The top surface of the gate is flush with the top surface of the side wall.
10. The semiconductor structure of claim 8 or 9, wherein, The gate and the side wall covering the gate together form a gate structure; the substrate comprises a core region and an input / output region outside the core region, a plurality of the gate structures are included in the core region and the input / output region, a spacing between adjacent gate structures in the core region is smaller than a spacing between adjacent gate structures in the input / output region.