Array substrate, manufacturing method and display panel

Abstract

The invention discloses an array substrate, a manufacturing method and a display panel, and the manufacturing method comprises the steps: sequentially arranging a first metal layer, a first semiconductor layer, a second metal layer and a photoresist layer above a substrate in a stacked manner, and carrying out the etching of the first metal layer, the first semiconductor layer and the second metal layer through a halftone mask technology, the first metal layer forms a patterned data line and a source electrode, the first semiconductor layer forms a patterned first active layer, the second metal layer forms a patterned drain electrode, the data line is electrically connected with the source electrode, and the first active layer is located between the source electrode and the drain electrode; forming a first insulating layer over the substrate; and forming a scanning line and a grid electrode above the first insulating layer, wherein the grid electrode is electrically connected with the scanning line. The first metal layer, the first semiconductor layer and the second metal layer are etched by adopting the halftone mask process, only one illumination is needed, the photomask cost is saved, at least two masks can be saved, the manufacturing process is simplified, and the production efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display area, and particularly to an array substrate, a manufacturing method and a display panel. BACKGROUND

[0002] With the development of display technology, thin and light display panels are favored by consumers, especially thin and light liquid crystal display (LCD) panels.

[0003] An existing display device includes a thin film transistor array substrate (TFT Array Substrate), a color filter substrate (CF Substrate), and liquid crystal molecules filled between the thin film transistor array substrate and the color filter substrate. When the display device is working, driving voltages are respectively applied to the pixel electrode of the thin film transistor array substrate and the common electrode of the color filter substrate, or driving voltages are respectively applied to the common electrode and the pixel electrode of the thin film transistor array substrate, the rotation direction of the liquid crystal molecules between the two substrates is controlled, and the backlight provided by the backlight module of the display device is refracted to display the picture.

[0004] In recent years, high-resolution display panels have gradually become the development trend of the industry. The resolution (Pixels per inch, PPI) of the display panel is related to the pixel aperture ratio of the array substrate, and the pixel aperture ratio of the array substrate is related to the size of the thin film transistor of each pixel unit. The larger the area occupied by the thin film transistor, the lower the pixel aperture ratio, and the lower the resolution of the display panel. Therefore, the prior art proposes a vertical thin film transistor, which reduces the size of the thin film transistor to improve the pixel aperture ratio and improve the resolution.

[0005] Figure 1 is a structural schematic diagram of the existing vertical thin film transistor array substrate. As shown in Figure 1 The vertical thin film transistor array substrate includes a data line 111 and a source electrode 112 disposed on a substrate 10, an active layer 121 disposed on the source electrode 112, a drain electrode 131 disposed on the active layer 121, a first insulating layer 101 (gate insulating layer) covering the data line 111, the source electrode 112, the active layer 121, and the drain electrode 131, a gate electrode 142 disposed on the first insulating layer 101, a planar layer 102 covering the first insulating layer 101 and the gate electrode 142, a common electrode 151 disposed on the planar layer 102, a second insulating layer 103 covering the common electrode 151, a pixel electrode 161 disposed on the second insulating layer 103, and the pixel electrode 161 being conductively connected to the drain electrode 131 through a contact hole.

[0006] Figures 2a-2c The preparation process of the prior vertical thin film transistor array substrate is shown in FIG. 1. Figures 2a-2c As shown in FIG. 1, the preparation process of the prior vertical thin film transistor array substrate is: forming data lines 111 and source electrodes 112 by a first patterning process, forming an active layer 121 by a second patterning process, forming drain electrodes 131 by a third patterning process, forming gate electrodes 142 by a fourth patterning process, forming common electrodes 151 by a fifth patterning process, forming contact holes by a sixth patterning process, and forming pixel electrodes 161 by a seventh patterning process. According to the structure and preparation process of the prior vertical thin film transistor, it can be seen that the thin film transistor of this structure has 9 film layers, and 7 patterning processes and 7 mask plates are required. The complex process leads to low production efficiency and high production cost, and the error accumulation affects the alignment accuracy, resulting in low yield. SUMMARY

[0007] In order to overcome the shortcomings and deficiencies in the prior art, the purpose of the present application is to provide an array substrate and a manufacturing method, and a display panel, so as to solve the problem of complex preparation process of the prior vertical thin film transistor array substrate.

[0008] The purpose of the present application is achieved by the following technical solutions: The present application provides a manufacturing method of an array substrate, comprising: providing a substrate; stacking a first metal layer, a first semiconductor layer, a second metal layer and a photoresist layer on the substrate in sequence, performing photoetching on the photoresist layer using a half-tone mask, and performing first etching on the first metal layer, the first semiconductor layer and the second metal layer with the photoresist layer after photoetching as a shield, so that the first metal layer forms patterned data lines and source electrodes, and the data lines are electrically connected to the source electrodes; performing ashing on the photoresist layer, performing second etching on the first semiconductor layer and the second metal layer with the photoresist layer after ashing as a shield, and then removing the photoresist layer after ashing, so that the first semiconductor layer forms a patterned first active layer, and the second metal layer forms a patterned drain electrode, and the first active layer is located between the source electrode and the drain electrode; forming a first insulating layer on the substrate to cover the data lines, the source electrodes, the first active layer and the drain electrode; forming a third metal layer on the first insulating layer, and etching the third metal layer to form patterned scan lines and gate electrodes, and the gate electrodes are electrically connected to the scan lines; A planar layer covering the scan line and the gate is formed above the first insulating layer, and a pixel electrode is made above the planar layer, the pixel electrode being conductively connected with the drain electrode.

[0009] Further, the width of the first active layer is greater than the width of the drain electrode, and the width of the source electrode is greater than the width of the first active layer.

[0010] Further, when the first metal layer, the first semiconductor layer and the second metal layer are etched for the first time, the manufacturing method comprises: The first metal layer, the first semiconductor layer and the second metal layer are etched simultaneously using a first etching solution.

[0011] Further, when the first semiconductor layer and the second metal layer are etched for the second time, the manufacturing method comprises: The second metal layer is etched using a second etching solution first, and then the first semiconductor layer is etched using a third etching solution.

[0012] Further, the manufacturing method comprises: After the data line, the source electrode, the first active layer and the drain electrode are formed, a second active layer is made on the side surface of the source electrode, the first active layer and the drain electrode, and the source electrode, the first active layer and the drain electrode are all in contact with the second active layer.

[0013] Further, the manufacturing method comprises: A common electrode and a second insulating layer are made above the planar layer, and the pixel electrode and the common electrode are insulated and spaced apart from each other by the second insulating layer.

[0014] The application also provides an array substrate, which is made by the manufacturing method of the array substrate as described above, and the array substrate comprises: a substrate; a data line and a source electrode on the substrate, the data line being electrically connected with the source electrode; a first active layer on the source electrode and a drain electrode on the first active layer, the first active layer being between the source electrode and the drain electrode; a first insulating layer on the substrate and covering the data line, the source electrode, the first active layer and the drain electrode; a scan line and a gate on the first insulating layer, the gate being electrically connected with the scan line; a planar layer on the first insulating layer and covering the scan line and the gate; A pixel electrode disposed on the flat layer, the pixel electrode being conductively connected with the drain electrode.

[0015] Further, the width of the first active layer is greater than the width of the drain electrode, and the width of the source electrode is greater than the width of the first active layer.

[0016] Further, the array substrate comprises: A second active layer located on the side surface of the source electrode, the first active layer and the drain electrode, and the source electrode, the first active layer and the drain electrode are in contact with the second active layer.

[0017] The application also provides a display panel comprising the array substrate as described above.

[0018] The application has the advantages that: by sequentially stacking the first metal layer, the first semiconductor layer and the second metal layer above the substrate, and etching the first metal layer, the first semiconductor layer and the second metal layer by using the half-tone mask process, only one light irradiation is needed, the mask cost is saved, at least two mask plates can be saved, the manufacturing process is simplified, the production efficiency is improved, the production cost is reduced, the channel of the vertical TFT is narrow, the channel width is controllable and stable, and the uniformity is improved. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 FIG. 1 is a structural schematic diagram of a prior art vertical thin film transistor array substrate.

[0020] Figures 2a-2c FIG. 4 is a preparation process of the prior art vertical thin film transistor array substrate.

[0021] Figure 3 FIG. 6 is a cross-sectional structural schematic diagram of the array substrate in the embodiment one of the application.

[0022] Figure 4 FIG. 7 is a planar structural schematic diagram of the array substrate in the embodiment one of the application.

[0023] Figures 5a-5m FIG. 8 is a preparation process of the array substrate in the embodiment one of the application.

[0024] Figure 6 FIG. 10 is a cross-sectional structural schematic diagram of the first active layer in the embodiment two of the application.

[0025] Figure 7 FIG. 13 is a cross-sectional structural schematic diagram of the array substrate in the embodiment three of the application.

[0026] Figures 8a-8c FIG. 15 is a preparation process of the array substrate in the embodiment three of the application.

[0027] Figure 9is a structural schematic view of the display device in a black state according to the present application.

[0028] Figure 10 is a structural schematic view of the display device in a white state according to the present application. DETAILED DESCRIPTION

[0029] To further clarify the technical means and effects taken by the present application to achieve the predetermined purposes, the following describes the specific embodiments of the array substrate and manufacturing method, display panel according to the present application, structure, features and effects thereof in detail in combination with the accompanying drawings and preferred embodiments as follows: [Embodiment One] Figure 3 is a structural schematic view of the array substrate in Embodiment One according to the present application. Figure 4 is a structural schematic view of the array substrate in Embodiment One according to the present application.

[0030] As shown in Figure 3 and Figure 4 , Embodiment One of the present application provides an array substrate, comprising: The substrate 10 can be made of glass, quartz, silicon, acrylic or polycarbonate, etc. The substrate 10 can also be a flexible substrate. Suitable materials for flexible substrates include, for example, polyether sulfone (PES), polyethylene naphthalate (PEN), polyethylene (PE), polyimide (PI), polyvinyl chloride (PVC), polyethylene terephthalate (PET) or combinations thereof.

[0031] The data line 111 and the source electrode 112 are disposed on the substrate 10, and the data line 111 is electrically connected to the source electrode 112. The data line 111 and the source electrode 112 are both disposed on the upper surface of the substrate 10 and in contact with the upper surface of the substrate 10. The data line 111 and the source electrode 112 are made of metal, such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or combinations of the above-mentioned metals, such as Al / Mo, Cu / Mo, etc.

[0032] A first active layer 121 and a drain 131 are disposed on the source 112. The first active layer 121 is located between the source 112 and the drain 131. The first active layer 121 is disposed on and in contact with the upper surface of the source 112, and the drain 131 is disposed on and in contact with the upper surface of the first active layer 121. When a positive voltage is applied to the gate 142, electrons in the first active layer 121 are attracted to the channel to form a conductive channel, connecting the source 112 and the drain 131, thus making the source 112 and the drain 131 conductive. The first active layer 121 can be made of polycrystalline silicon or metal oxides (such as indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), zinc tin oxide (ZnSnO), gallium tin oxide (GaSnO), gallium zinc oxide (GaZnO), indium gallium zinc oxide (IGZO), or indium gallium zinc tin oxide (IGZTO), etc.); the drain 131 is made of metal, such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or a combination of the above metals such as Al / Mo, Cu / Mo, etc.

[0033] A first insulating layer 101 is disposed on the substrate 10 and covers the data line 111, the source 112, the first active layer 121 and the drain 131. The first insulating layer 101 is a gate insulating layer and the material of the first insulating layer 101 is silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two.

[0034] Scan line 141 provided on the first insulating layer 101 Figure 4 A scan line 141 and a gate 142 are electrically connected to the scan line 141. The scan line 141 and the gate 142 are disposed on the upper surface of the first insulating layer 101 and are in contact with the upper surface of the first insulating layer 101. Multiple scan lines 141 and multiple data lines 111 are mutually insulated and intersected to form multiple pixel units P. Each pixel unit P contains a thin-film transistor 3. The thin-film transistor 3 is composed of a source 112, a first active layer 121, a drain 131, and a gate 142. The first insulating layer 101 has a slope in the region corresponding to the first active layer 121 and the drain 131. The gate 142 is disposed at the slope to form a vertical thin-film transistor. The scan line 141 and the gate 142 are made of metal, such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or combinations of the above metals such as Al / Mo, Cu / Mo, etc.

[0035] A planar layer 102 is disposed on the first insulating layer 101 and covers the scan line 141 and the gate 142. The planar layer 102 is made of silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.

[0036] A pixel electrode 161 is disposed on the planar layer 102. Each pixel unit P is provided with one pixel electrode 161. The pixel electrode 161 is conductively connected to the drain 131, i.e., the pixel electrode 161 is conductively connected to the corresponding scan line 141 and the data line 111 through the corresponding thin film transistor 3. The pixel electrode 161 is made of transparent conductive material, such as indium tin oxide (ITO), indium zinc oxide (IZO), cadmium tin oxide (CTO), aluminum zinc oxide (AZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), cadmium oxide (CdO), hafnium oxide (HfO), indium gallium zinc oxide (InGaZnO), indium gallium zinc magnesium oxide (InGaZnMgO), indium gallium magnesium oxide (InGaMgO), or indium gallium aluminum oxide (InGaAlO).

[0037] Further, the planar layer 102 is further provided with a common electrode 151 and a second insulating layer 103. The pixel electrode 161 and the common electrode 151 are insulated and spaced apart from each other by the second insulating layer 103. In this embodiment, the common electrode 151 is located below the pixel electrode 161. Of course, in other embodiments, the pixel electrode 161 can be located below the common electrode 151. The common electrode 151 is made of transparent conductive material, such as indium tin oxide (ITO), indium zinc oxide (IZO), cadmium tin oxide (CTO), aluminum zinc oxide (AZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), cadmium oxide (CdO), hafnium oxide (HfO), indium gallium zinc oxide (InGaZnO), indium gallium zinc magnesium oxide (InGaZnMgO), indium gallium magnesium oxide (InGaMgO), or indium gallium aluminum oxide (InGaAlO).

[0038] In this embodiment, the width of the first active layer 121 is greater than the width of the drain 131, and the width of the source 112 is greater than the width of the first active layer 121, i.e., the projection of the first active layer 121 on the substrate 10 completely covers the projection of the drain 131 on the substrate 10, and the projection of the source 112 on the substrate 10 completely covers the projection of the first active layer 121 on the substrate 10. Optionally, the edge of the first active layer 121 is 1-2 um beyond the edge of the drain 131, so that when the gate driving signal is applied to the gate 142, the first active layer 121 can well conduct the source 112 and the drain 131. The edge of the source 112 is beyond the edge of the first active layer 121, which can better shield the light for the first active layer 121, avoiding the occurrence of leakage current of the first active layer 121 due to light.

[0039] Figures 5a-5m is a preparation flow of the array substrate in Embodiment One of the present application. As shown in Figures 5a-5m The present application also provides a manufacturing method of an array substrate, for manufacturing the array substrate as described above. The manufacturing method comprises: As shown in Figure 5a The substrate 10 can be made of glass, quartz, silicon, acrylic or polycarbonate, etc. The substrate 10 can also be a flexible substrate. Suitable materials for the flexible substrate include, for example, polyether sulfone (PES), polyethylene naphthalate (PEN), polyethylene (PE), polyimide (PI), polyvinyl chloride (PVC), polyethylene terephthalate (PET) or a combination thereof.

[0040] As shown in Figure 5a and Figure 5b The first metal layer 11, the first semiconductor layer 12, the second metal layer 13 and the photoresist layer 1 are sequentially stacked above the substrate 10. The photoresist layer 1 is subjected to photolithography using a half-tone mask 2. The half-tone mask 2 has a light-transmitting area, a semi-light-transmitting area and a light-blocking area, so that the photoresist layer 1 forms a complete reserved area, a partial reserved area and a complete removed area. The photoresist layer 1 is made of a positive photoresist material. Therefore, the complete reserved area corresponds to the light-blocking area, the partial reserved area corresponds to the semi-light-transmitting area, and the complete removed area corresponds to the light-transmitting area. Of course, the photoresist layer 1 can also be made of a negative photoresist material. Therefore, the complete reserved area corresponds to the light-transmitting area, the partial reserved area corresponds to the semi-light-transmitting area, and the complete removed area corresponds to the light-blocking area.

[0041] As shown in Figure 5cAs shown, the first metal layer 11, the first semiconductor layer 12, and the second metal layer 13 are etched for the first time using the photoresist layer 1 after photolithography as a mask, so that the first metal layer 11 forms patterned data lines 111 and source electrodes 112, and the data lines 111 and source electrodes 112 are electrically connected. The data lines 111 and source electrodes 112 are formed in the regions of the first metal layer 11 corresponding to the fully preserved region and the partially preserved region of the photoresist layer 1. The first metal layer 11 and the second metal layer 13 are made of metals, such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or combinations of the above metals, such as Al / Mo, Cu / Mo, etc. The first semiconductor layer 12 can be made of polycrystalline silicon or metal oxides (such as indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), zinc tin oxide (ZnSnO), gallium tin oxide (GaSnO), gallium zinc oxide (GaZnO), indium gallium zinc oxide (IGZO) or indium gallium zinc tin oxide (IGZTO).

[0042] In this embodiment, by using the photoresist layer 1 after photolithography as a shield, and simultaneously etching the first metal layer 11, the first semiconductor layer 12, and the second metal layer 13 with the first etchant, production efficiency can be further improved. Of course, different etchants can also be used to etch the first metal layer 11, the first semiconductor layer 12, and the second metal layer 13 separately, but this would require three etching operations.

[0043] like Figures 5d-5g As shown, the photoresist layer 1 is ashed to remove a portion of the retained area of ​​the photoresist layer 1, retaining the completely retained area. Using the ashed photoresist layer 1 as a mask, the first semiconductor layer 12 and the second metal layer 13 are etched a second time. Then, the ashed photoresist layer 1 is removed, resulting in a patterned first active layer 121 formed in the first semiconductor layer 12, and a patterned drain 131 formed in the second metal layer 13. The first active layer 121 is located between the source 112 and the drain 131. The regions of the first semiconductor layer 12 and the second metal layer 13 corresponding to the completely retained area of ​​the photoresist layer 1 each form the first active layer 121 and the drain 131.

[0044] In the embodiment, the width of the first active layer 121 is greater than the width of the drain 131, and the width of the source 112 is greater than the width of the first active layer 121, that is, the projection of the first active layer 121 on the substrate 10 completely covers the projection of the drain 131 on the substrate 10, and the projection of the source 112 on the substrate 10 completely covers the projection of the first active layer 121 on the substrate 10. Optionally, the edge of the first active layer 121 is 1-2 um beyond the edge of the drain 131, so that when the gate driving signal is applied to the gate 142, the first active layer 121 can well turn on the source 112 and the drain 131. The edge of the source 112 is beyond the edge of the first active layer 121, which can better shield the light for the first active layer 121, avoiding the leakage current of the first active layer 121 due to light. The time for the second etching of the first semiconductor layer 12 and the second metal layer 13 can be controlled to control the CDBias (etching bias), for example, the CD Bias of the second metal layer 13 is controlled to be 2 um, and the CD Bias of the first semiconductor layer 12 is controlled to be 1 um, so as to ensure that the width of the first active layer 121 is greater than the width of the drain 131, and the edge of the first active layer 121 is exposed to the edge of the drain 131.

[0045] In the embodiment, the second etching liquid is used to etch only the second metal layer 13, and then the third etching liquid is used to etch only the first semiconductor layer 12, so that the time for the second etching of the first semiconductor layer 12 and the second metal layer 13 can be controlled, and the width of the first active layer 121 is greater than the width of the drain 131. The second etching liquid can only etch the second metal layer 13, and the third etching liquid can only etch the first semiconductor layer 12. For example, the first metal layer 11 and the second metal layer 13 are both made of copper, and the first semiconductor layer 12 is made of indium gallium zinc oxide (IGZO); or the first metal layer 11 and the second metal layer 13 are both made of aluminum, and the first semiconductor layer 12 is made of indium gallium zinc tin oxide (IGZTO), which is resistant to aluminum acid, and the first semiconductor layer 12 is etched by oxalic acid.

[0046] As shown in FIG. 1, Figure 5h A first insulating layer 101 covering the data line 111, the source 112, the first active layer 121 and the drain 131 is formed above the substrate 10, the first insulating layer 101 is a gate insulating layer, and the material of the first insulating layer 101 is silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two.

[0047] As shown in FIG. 1, Figure 5i A third metal layer 14 is formed above the first insulating layer 101, and the third metal layer 14 is etched to form a patterned scan line 141 Figure 4) and a gate 142, the gate 142 is electrically connected with a scan line 141, the scan line 141 and the gate 142 are arranged on the upper surface of the first insulating layer 101 and are in contact with the upper surface of the first insulating layer 101, a plurality of scan lines 141 and a plurality of data lines 111 are insulated and crossed with each other to define a plurality of pixel units P, one thin film transistor 3 is arranged in each pixel unit P, the thin film transistor 3 is composed of a source 112, a first active layer 121, a drain 131 and a gate 142. The first insulating layer 101 has an inclined surface in the region corresponding to the first active layer 121 and the drain 131, and the gate 142 is arranged at the inclined surface to form a vertical thin film transistor. Among them, the scan line 141 and the gate 142 are made of metal, such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni) and the like, or a combination of the above-mentioned metals, such as Al / Mo, Cu / Mo and the like.

[0048] As shown in Figure 5j , a planar layer 102 covering the scan line 141 and the gate 142 is formed above the first insulating layer 101, the material of the planar layer 102 is silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two.

[0049] As shown in Figure 5k , a first transparent conductive layer 15 is formed above the planar layer 102, the first transparent conductive layer 15 is etched to form a patterned common electrode 151, the first transparent conductive layer 15 is made of transparent conductive material, such as indium tin oxide (ITO), indium zinc oxide (IZO), cadmium tin oxide (CTO), aluminum zinc oxide (AZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), cadmium oxide (CdO), hafnium oxide (HfO), indium gallium zinc oxide (InGaZnO), indium gallium zinc magnesium oxide (InGaZnMgO), indium gallium magnesium oxide (InGaMgO) or indium gallium aluminum oxide (InGaAlO) and the like.

[0050] Figure 5l As shown in , a second insulating layer 103 is formed above the planar layer 102, the second insulating layer 103, the planar layer 102 and the first insulating layer 101 are etched at the same time, so that the second insulating layer 103, the planar layer 102 and the first insulating layer 101 form a contact hole 104 in the region corresponding to the drain 131, and the drain 131 is exposed from the contact hole 104. Among them, the material of the second insulating layer 103 is silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two.

[0051] Figure 5mAs shown, a second transparent conductive layer 16 is formed above the second insulating layer 103, the second transparent conductive layer 16 is etched, and the second transparent conductive layer 16 forms a patterned pixel electrode 161, which is electrically connected with the drain 131 through the contact hole 104. The pixel electrode 161 and the common electrode 151 are insulated and spaced apart from each other by the second insulating layer 103. The second transparent conductive layer 16 is made of a transparent conductive material, such as indium tin oxide (ITO), indium zinc oxide (IZO), cadmium tin oxide (CTO), aluminum zinc oxide (AZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), cadmium oxide (CdO), hafnium oxide (HfO), indium gallium zinc oxide (InGaZnO), indium gallium zinc magnesium oxide (InGaZnMgO), indium gallium magnesium oxide (InGaMgO), or indium gallium aluminum oxide (InGaAlO).

[0052] Of course, in other embodiments, the pixel electrode 161 can also be located below the common electrode 151, that is, the pixel electrode 161 is made first, then the second insulating layer 103 is covered, and finally the common electrode 151 is made on the second insulating layer 103.

[0053] [Embodiment Two] Figure 6 is a schematic diagram of a cross-sectional structure of the first active layer in Embodiment Two of the present application. As shown, Figure 6 Embodiment Two of the present application provides an array substrate and a manufacturing method, which are basically the same as those in Embodiment One ( Figures 3 to 5m ) of the present application, with the difference being that: In the present embodiment, the first semiconductor layer 12 includes an indium gallium zinc oxide layer 121a and an indium gallium zinc tin oxide layer 121b, the indium gallium zinc tin oxide layer 121b is laminated above the indium gallium zinc oxide layer 121a, so that when the second metal layer 13 is etched for the second time, the first semiconductor layer 12 can be avoided from being etched; and the conductivity of the first active layer 121 when turned on can be improved, and the performance of the thin film transistor can be improved.

[0054] Those skilled in the art should understand that the remaining structures and working principles of the present embodiment are the same as those of Embodiment One, which will not be described here.

[0055] [Embodiment Three] Figure 7 is a schematic diagram of a cross-sectional structure of an array substrate in Embodiment Three of the present application. As shown, Figure 7 Embodiment Two of the present application provides an array substrate, which is basically the same as those in Embodiments One ( Figures 3 to 5m ) and Two ( Figure 6 ) of the present application, with the difference being that: In the embodiment, the array substrate further comprises a second active layer 171 located at the side of the source electrode 112, the first active layer 121 and the drain electrode 131, the source electrode 112, the first active layer 121 and the drain electrode 131 all contact the second active layer 171, and the second active layer 171 is located at the side of the first active layer 121 and the drain electrode 131 close to the gate electrode 142. By adding the second active layer 171 and contacting the source electrode 112, the first active layer 121 and the drain electrode 131, the current of the source electrode 112 can flow to the drain electrode 131 through the first active layer 121 and the second active layer 171, and the on-conductance of the thin film transistor is further increased. When the gate electrode 142 applies a positive voltage, the electrons in the first active layer 121 and the second active layer 171 are respectively attracted to the channel region or the pre-channel region, forming a conductive double channel to connect the source electrode 112 and the drain electrode 131, so that the source electrode 112 and the drain electrode 131 are turned on.

[0056] Figures 8a-8c is the preparation process of the array substrate in the third embodiment of the present application. As shown in Figures 8a-8c , the present application also provides a manufacturing method of an array substrate and the manufacturing method in the first embodiment Figures 3 to 5m ), the second embodiment Figure 6 ) is basically the same as the manufacturing method in the first embodiment, and the difference is that: After the data line 111, the source electrode 112, the first active layer 121 and the drain electrode 131 are formed, the second active layer 171 is manufactured at the side of the source electrode 112, the first active layer 121 and the drain electrode 131, and the source electrode 112, the first active layer 121 and the drain electrode 131 all contact the second active layer 171. Specifically, as shown in Figure 8b , the second semiconductor layer 17 covering the data line 111, the source electrode 112, the first active layer 121 and the drain electrode 131 is formed above the substrate 10, the second semiconductor layer 17 is etched, the second active layer 171 contacting the source electrode 112, the first active layer 121 and the drain electrode 131 is formed from the second semiconductor layer 17, and the second active layer 171 covers the side of the first active layer 121 and the drain electrode 131 close to the gate electrode 142. The second semiconductor layer 17 can be made of polycrystalline silicon or metal oxide (such as indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), zinc tin oxide (ZnSnO), gallium tin oxide (GaSnO), gallium zinc oxide (GaZnO), indium gallium zinc oxide (IGZO) or indium gallium zinc tin oxide (IGZTO) and the like).

[0057] Those skilled in the art should understand that the remaining structure and working principle of the embodiment are the same as those of the first embodiment and the second embodiment, and will not be described here.

[0058] Figure 9is a structural schematic view of the display device of the present application in a black state. Figure 10 is a structural schematic view of the display device of the present application in a white state. Figure 9 and Figure 10 As shown in the figure, the present application further provides a display panel, which comprises the array substrate as described above, an opposite substrate 20 arranged opposite to the array substrate, and a liquid crystal layer 30 arranged between the array substrate and the opposite substrate 20. The opposite substrate 20 is provided with an upper polarizer 41, and the array substrate is provided with a lower polarizer 42. The light transmission axis of the upper polarizer 41 is perpendicular to the light transmission axis of the lower polarizer 42. The liquid crystal molecules in the liquid crystal layer 30 are positive liquid crystal molecules (liquid crystal molecules with positive dielectric anisotropy). In the initial state, the positive liquid crystal molecules are in a flat posture. The alignment direction of the positive liquid crystal molecules close to the opposite substrate 20 is parallel to the alignment direction of the positive liquid crystal molecules close to the array substrate. It can be understood that the array substrate and the opposite substrate 20 are further provided with an alignment layer on the side facing the liquid crystal layer 30, so as to align the positive liquid crystal molecules in the liquid crystal layer 30.

[0059] In the embodiment, the opposite substrate 20 is a color film substrate. The opposite substrate 20 is provided with a black matrix 21 and a color resistance layer 22. The black matrix 21 corresponds to the data lines 111, the scan lines 141, the thin film transistors 3, and the peripheral non-display area. The black matrix 21 separates the plurality of color resistance layers 22. The color resistance layer 22 comprises color resistance materials of red (R), green (G), and blue (B), and corresponds to form sub-pixels of red (R), green (G), and blue (B).

[0060] In the present document, the orientation words such as up, down, left, right, front, back, etc. are defined according to the position of the structure in the figure and the position between the structures in the figure, only for the purpose of expressing the technical solution clearly and conveniently. It should be understood that the use of the orientation words should not limit the scope of the present application. It should also be understood that the terms "first" and "second" used in the present document are only used for differentiation in name, and do not limit the quantity and order.

[0061] The above is only a preferred embodiment of the present application, and does not limit the present application in any form. Although the present application has been disclosed as above with the preferred embodiment, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to the disclosed technical content without departing from the scope of the technical solution of the present application, and the equivalent embodiments with equivalent changes. Any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application are still within the protection scope of the present application.

Claims

1. A method for fabricating an array substrate, characterized in that, The application relates to a manufacturing method of a thin film transistor, which comprises the following steps: providing a substrate (10); sequentially arranging a first metal layer (11), a first semiconductor layer (12), a second metal layer (13) and a photoresist layer (1) above the substrate (10), performing photoetching on the photoresist layer (1) by using a half-tone mask (2), and performing first etching on the first metal layer (11), the first semiconductor layer (12) and the second metal layer (13) by taking the photoresist layer (1) after photoetching as a shield, so that the first metal layer (11) forms patterned data lines (111) and a source electrode (112), and the data lines (111) are electrically connected with the source electrode (112); performing ashing treatment on the photoresist layer (1), performing second etching on the first semiconductor layer (12) and the second metal layer (13) by taking the photoresist layer (1) after ashing treatment as a shield, and then removing the photoresist layer (1) after ashing treatment, so that the first semiconductor layer (12) forms a patterned first active layer (121), and the second metal layer (13) forms a patterned drain electrode (131), and the first active layer (121) is located between the source electrode (112) and the drain electrode (131); forming a first insulating layer (101) covering the data lines (111), the source electrode (112), the first active layer (121) and the drain electrode (131) above the substrate (10); forming a third metal layer (14) above the first insulating layer (101), etching the third metal layer (14), so that the third metal layer (14) forms patterned scan lines (141) and a gate electrode (142), and the gate electrode (142) is electrically connected with the scan lines (141); forming a planar layer (102) covering the scan lines (141) and the gate electrode (142) above the first insulating layer (101), and manufacturing a pixel electrode (161) above the planar layer (102), and the pixel electrode (161) is conductively connected with the drain electrode (131).

2. The method of manufacturing an array substrate according to claim 1, wherein The width of the first active layer (121) is greater than the width of the drain electrode (131), and the width of the source electrode (112) is greater than the width of the first active layer (121).

3. The method of manufacturing an array substrate according to claim 1, wherein When the first etching is performed on the first metal layer (11), the first semiconductor layer (12) and the second metal layer (13), the manufacturing method comprises the following steps: simultaneously etching the first metal layer (11), the first semiconductor layer (12) and the second metal layer (13) by using a first etching solution.

4. The method of manufacturing an array substrate according to claim 1, wherein When the second etching is performed on the first semiconductor layer (12) and the second metal layer (13), the manufacturing method comprises the following steps: firstly etching only the second metal layer (13) by using a second etching solution, and then etching only the first semiconductor layer (12) by using a third etching solution.

5. The method of manufacturing an array substrate according to any one of claims 1 to 4, wherein The manufacturing method comprises the following steps: After forming the data line (111), the source electrode (112), the first active layer (121) and the drain electrode (131), a second active layer (171) is formed on the side of the source electrode (112), the first active layer (121) and the drain electrode (131), and the source electrode (112), the first active layer (121) and the drain electrode (131) are in contact with the second active layer (171).

6. The method of manufacturing an array substrate according to any one of claims 1 to 4, wherein The manufacturing method comprises: A common electrode (151) and a second insulating layer (103) are formed above the planar layer (102), and the pixel electrode (161) and the common electrode (151) are insulated and spaced apart by the second insulating layer (103).

7. An array substrate, characterized by, The array substrate is manufactured by using the manufacturing method of the array substrate according to any one of claims 1-6, and the array substrate comprises: a substrate (10); a data line (111) and a source electrode (112) arranged on the substrate (10), and the data line (111) is electrically connected with the source electrode (112); a first active layer (121) arranged on the source electrode (112) and a drain electrode (131) arranged on the first active layer (121), and the first active layer (121) is located between the source electrode (112) and the drain electrode (131); a first insulating layer (101) arranged on the substrate (10) and covering the data line (111), the source electrode (112), the first active layer (121) and the drain electrode (131); a scan line (141) and a gate electrode (142) arranged on the first insulating layer (101), and the gate electrode (142) is electrically connected with the scan line (141); a planar layer (102) arranged on the first insulating layer (101) and covering the scan line (141) and the gate electrode (142); a pixel electrode (161) arranged on the planar layer (102), and the pixel electrode (161) is conductively connected with the drain electrode (131).

8. The array substrate of claim 7, wherein, The width of the first active layer (121) is greater than the width of the drain electrode (131), and the width of the source electrode (112) is greater than the width of the first active layer (121).

9. The array substrate of claim 7, wherein, The array substrate comprises: a second active layer (171) located on the side of the source electrode (112), the first active layer (121) and the drain electrode (131), and the source electrode (112), the first active layer (121) and the drain electrode (131) are in contact with the second active layer (171).

10. A display panel, characterized by, The array substrate comprises: a second active layer (171) located on the side of the source electrode (112), the first active layer (121) and the drain electrode (131), and the source electrode (112), the first active layer (121) and the drain electrode (131) are in contact with the second active layer (171).

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