Array substrate, manufacturing method and display device

Abstract

The invention discloses an array substrate, a manufacturing method and a display device. The array substrate comprises a substrate; the scanning line, the grid electrode, the grid electrode insulating layer, the active layer and the protection layer are arranged on the substrate, the protection layer comprises a first protection layer and a second protection layer, the first protection layer is located at a channel of the active layer, the second protection layer is located at the edge of the grid electrode, and one part of the second protection layer and one part of the grid electrode are mutually overlapped; the source electrode and the drain electrode are separated from each other through the first protection layer and are conductively connected through the active layer, and the source electrode and the drain electrode are at least partially overlapped with the second protection layer at the edge of the grid electrode. The first protection layer is arranged at the channel of the active layer, the second protection layer is arranged at the edge of the grid electrode, and the source electrode and the drain electrode at least partially cover the second protection layer at the edge of the grid electrode, so that the channel of the active layer can be protected, and the problem of line breakage of the source electrode and the drain electrode at the edge of the grid electrode can be avoided.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to an array substrate, its manufacturing method, and a display device. Background Technology

[0002] With the development of display technology, thin and light display panels are increasingly favored by consumers, especially thin and light liquid crystal display (LCD) panels. An existing display device includes a thin film transistor array substrate (TFT array substrate), a color filter substrate (CF substrate), and liquid crystal molecules filled between the TFT array substrate and the color filter substrate. When the display device is in operation, driving voltages are applied to the pixel electrodes of the TFT array substrate and the common electrode of the color filter substrate, or to the common electrode and pixel electrodes of the TFT array substrate, respectively. This controls the rotation direction of the liquid crystal molecules between the two substrates, refracting the backlight provided by the backlight module of the display device to display an image.

[0003] Back channel etch (BCE) and etch stop layer (ESL) are two common thin-film transistor (TFT) array substrate structures. BCE array substrates have a relatively simpler fabrication process and are easier to achieve high pixel aperture ratios (reducing power consumption). However, because the TFT channel is exposed, the etchant and stripping solution contacting the source and drain layers, coupled with Cu wiring (Cu is prone to diffusion and corrosion), makes it difficult to control the stability of the TFT device. ESL array substrates add an etch stop layer to protect the TFT channel, allowing the use of higher-yield Al wiring, and resulting in better TFT device stability. Currently, ESL array substrates have two structures: a hole-type ESL structure and an island-type ESL structure.

[0004] Figure 1 This is a schematic diagram of the longitudinal cross-section of an existing punch-hole ESL structure thin-film transistor. Figure 2 This is a top-view schematic diagram of an existing punch-hole ESL (Electro-Silicon Lens) thin-film transistor. (See attached diagram.) Figure 1 and Figure 2As shown, the fabrication process of a punch-hole ESL thin-film transistor is as follows: First, a gate 2, a gate insulating layer 3, and an active layer 4 are fabricated on a substrate 1. Then, an ESL layer 7 is deposited on the surface of the gate insulating layer 3, and holes are made in the ESL layer 7 on both sides of the active layer 4. Next, the patterns of the source 5 and drain 6 are fabricated, and the source 5 and drain 6 are connected to the active layer 4 through vias on both sides of the active layer 4. However, due to the influence of the mask and photolithography fabrication precision, the size and spacing of the holes are limited, which means that the size of the active layer 4 and the gate 2 needs to be made wider to meet the hole requirements. Therefore, the wider size of the active layer 4 and the gate 2 will limit the aperture ratio of the pixel.

[0005] In recent years, high-resolution display panels have gradually become an industry trend. The resolution (Pixelsper inch, PPI) of a display panel is related to the pixel aperture ratio of the array substrate, which in turn is related to the size of the thin-film transistor in each pixel unit. The larger the area occupied by the thin-film transistor, the lower the pixel aperture ratio and the lower the resolution of the display panel. To address this, existing technologies have proposed another island-shaped ESL structure. Figure 3 This is a schematic diagram of the longitudinal section of an existing island-shaped ESL thin-film transistor. Figure 4 This is a top-view planar structural diagram of an existing island-shaped ESL thin-film transistor. (See diagram below.) Figure 3 and Figure 4 As shown, the thin-film transistor with an island-shaped ESL structure only needs to have an ESL layer 7 in the TFT channel region, without the restriction of opening holes, which can optimize the layout space and further improve the pixel aperture ratio.

[0006] Figure 5 This is a schematic diagram of the actual longitudinal cross-section of an existing island-shaped ESL thin-film transistor. Figure 6 This is a schematic diagram of the actual top-view planar structure of an existing island-shaped ESL thin-film transistor. (See diagram below.) Figure 5 and Figure 6 As shown, during the actual attempt to fabricate a thin-film transistor with an island-shaped ESL structure, a pit 8 was encountered on the gate insulating layer 3 at the edge of the gate 2. This may be due to the metal of the gate 2 interfering with the distribution of the plasma electric field during the etching of the ESL layer 7. The pit 8 on the gate insulating layer 3 will affect the subsequent coverage of the source 5 and drain 6, resulting in a "broken line" problem in the source 5 and drain 6. Summary of the Invention

[0007] In order to overcome the shortcomings and deficiencies of the prior art, the present invention aims to provide an array substrate and its manufacturing method, as well as a display device, to solve the problem that the source and drain wires of thin film transistors with island-shaped ESL structures in the prior art are prone to breakage.

[0008] The objective of this invention is achieved through the following technical solution: This invention provides an array substrate, comprising: Substrate; A first metal layer is disposed above the substrate, and the first metal layer includes a scan line and a gate, wherein the gate is electrically connected to the scan line. A gate insulating layer is disposed above the first metal layer and covers the scan line and the gate; A semiconductor layer is disposed above the gate insulating layer, and the semiconductor layer includes an active layer corresponding to the gate. A protective layer is disposed above the gate insulating layer and the semiconductor layer. The protective layer includes a first protective layer and a second protective layer. The first protective layer is located at the channel of the active layer, and the second protective layer is located at the edge of the gate. A portion of the second protective layer overlaps with a portion of the gate, and another portion of the second protective layer extends beyond the edge of the gate, and another portion of the gate extends beyond the edge of the second protective layer. A second metal layer is disposed above the gate insulating layer, the semiconductor layer, and the protective layer. The second metal layer includes a data line, a source, and a drain. The data line is electrically connected to the source. The source and the drain are spaced apart from each other by the first protective layer and are electrically connected by the active layer. The source at least partially overlaps with the second protective layer at the edge of the gate, and the drain at least partially overlaps with the second protective layer at the edge of the gate.

[0009] Furthermore, the active layer is provided with a second protective layer on both sides, and the two ends of the first protective layer are respectively connected to the two second protective layers to form an "I" shaped structure, or there is a gap between the two ends of the first protective layer and the second protective layer.

[0010] Furthermore, the two ends of the second protective layer extend beyond the edges of the source and the drain.

[0011] Furthermore, the protective layer includes a third protective layer located at the intersection of the scan line and the data line. A portion of the third protective layer overlaps with a portion of the scan line, and another portion of the third protective layer extends beyond the edge of the scan line. Another portion of the scan line extends beyond the edge of the third protective layer, and the data line at least partially overlaps with the third protective layer at the edge of the scan line.

[0012] Furthermore, the third protective layer has a block structure and covers the overlapping area of ​​the scan lines and the data lines.

[0013] Furthermore, the array substrate includes: A pixel electrode and a common electrode block that cooperates with the pixel electrode, wherein the pixel electrode is in contact with the drain electrode.

[0014] This application also provides a method for fabricating an array substrate, used to fabricate the array substrate described above, the method comprising: Provide substrate; A first metal layer is disposed above the substrate, and the first metal layer is etched to form patterned scan lines and gates, wherein the gates are electrically connected to the scan lines; A gate insulating layer is disposed above the substrate, the gate insulating layer covering the gate and the scan line; A semiconductor layer is disposed above the gate insulating layer, and the semiconductor layer is etched to form a patterned active layer, the active layer corresponding to the gate; A protective layer is disposed above the gate insulating layer. The protective layer is etched to form a patterned first protective layer and a second protective layer. The first protective layer is located at the channel of the active layer, and the second protective layer is located at the edge of the gate. A portion of the second protective layer overlaps with a portion of the gate, and another portion of the second protective layer extends out of the edge of the gate, and another portion of the gate extends out of the edge of the second protective layer. A second metal layer is disposed above the gate insulating layer. The second metal layer is etched to form patterned data lines, a source, and a drain. The data lines are electrically connected to the source. The source and the drain are spaced apart from each other by the first protective layer and are electrically connected by the active layer. The source overlaps at least partially with the second protective layer at the edge of the gate, and the drain overlaps at least partially with the second protective layer at the edge of the gate.

[0015] Furthermore, the active layer is provided with a second protective layer on both sides, and the two ends of the first protective layer are respectively connected to the two second protective layers to form an "I" shaped structure, or there is a gap between the two ends of the first protective layer and the second protective layer.

[0016] Furthermore, during the etching of the protective layer, a patterned third protective layer is also formed. The third protective layer is located at the intersection of the scan line and the data line. A portion of the third protective layer overlaps with a portion of the scan line, and another portion of the third protective layer extends beyond the edge of the scan line. Another portion of the scan line extends beyond the edge of the third protective layer, and the data line at least partially overlaps with the third protective layer at the edge of the scan line.

[0017] This application also provides a display device, including the array substrate described above.

[0018] The beneficial effects of this invention are as follows: By setting a first protective layer at the channel of the active layer, the channel of the active layer can be protected; and by setting a second protective layer at the edge of the gate, both the source and drain are at least partially covered by the second protective layer at the edge of the gate, i.e., the source and drain are separated by the second protective layer at the edge of the gate, so as to avoid the problem of broken lines between the source and drain at the edge of the gate, thereby improving the yield of the array substrate. Since the first and second protective layers are etched from the same protective layer, it does not increase the process difficulty, and the second protective layer is only set at the edge of the gate, so it does not affect the aperture ratio of the pixel, making its aperture ratio the same as that of the island ESL structure. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the longitudinal cross-section of an existing punch-hole ESL structure thin-film transistor.

[0020] Figure 2 This is a top-view schematic diagram of the existing punch-hole ESL structure thin-film transistor.

[0021] Figure 3 This is a schematic diagram of the longitudinal section of an existing island-shaped ESL thin-film transistor.

[0022] Figure 4 This is a top-view planar structural diagram of an existing island-shaped ESL thin-film transistor.

[0023] Figure 5 This is a schematic diagram of the actual longitudinal cross-section of an existing island-shaped ESL thin-film transistor.

[0024] Figure 6 This is a schematic diagram of the actual top-view planar structure of a thin-film transistor with an existing island-shaped ESL structure.

[0025] Figure 7 This is a schematic diagram of the longitudinal cross-sectional structure of the array substrate at the thin-film transistor in Embodiment 1 of the present invention.

[0026] Figure 8 This is one of the top-view planar structural diagrams of the thin-film transistor in Embodiment 1 of the present invention.

[0027] Figure 9 This is the second top-view planar structural diagram of the thin-film transistor in Embodiment 1 of the present invention.

[0028] Figure 10 These are electron microscope planar views and partial magnified views of the thin-film transistor in Embodiment 1 of the present invention.

[0029] Figure 11 These are electron microscope planar and cross-sectional views of the thin-film transistor in Embodiment 1 of the present invention.

[0030] Figures 12a-12i This is a schematic diagram of the process flow of the array substrate in Embodiment 1 of the present invention.

[0031] Figure 13 This is one of the top-view planar structural diagrams of the thin-film transistor in Embodiment 2 of the present invention.

[0032] Figure 14 This is the second top-view planar structural diagram of the thin-film transistor in Embodiment 2 of the present invention.

[0033] Figure 15 This is a schematic diagram of the display device in the dark state according to the present invention.

[0034] Figure 16 This is a schematic diagram of the display device in the bright state in this invention. Detailed Implementation

[0035] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following detailed description, in conjunction with the accompanying drawings and preferred embodiments, provides a detailed explanation of the specific implementation methods, structures, features, and effects of the array substrate and manufacturing method, and display device proposed according to the present invention: [Example 1] Figure 7 This is a schematic diagram of the longitudinal cross-sectional structure of the array substrate at the thin-film transistor in Embodiment 1 of the present invention. Figure 8 This is one of the top-view planar structural diagrams of the thin-film transistor in Embodiment 1 of the present invention. Figure 9 This is the second top-view planar structural diagram of the thin-film transistor in Embodiment 1 of the present invention.

[0036] like Figures 7 to 9 As shown, an array substrate provided in Embodiment 1 of the present invention includes: The substrate 10 may be made of materials such as glass, quartz, silicon, acrylic or polycarbonate. The substrate 10 may also be a flexible substrate. Suitable materials for flexible substrates include, for example, polyethersulfone (PES), polyethylene naphthalate (PEN), polyethylene (PE), polyimide (PI), polyvinyl chloride (PVC), polyethylene terephthalate (PET) or combinations thereof.

[0037] First metal layer 11 (reference) Figure 12aA first metal layer 11 is disposed above the substrate 10. The first metal layer 11 includes scan lines (not shown) and a gate 111, which is electrically connected to the scan lines. The first metal layer 11 can be made of metals such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), or combinations of the above metals such as Al / Mo, Cu / Mo, etc.

[0038] A gate insulating layer 101 is disposed above the first metal layer 11 and covers the scan line and the gate 111. The gate insulating layer 101 is made of silicon oxide (SiOx), silicon nitride (SiNx), or a combination of the two.

[0039] Semiconductor layer 12 (reference) Figure 12b The semiconductor layer 12 is disposed above the gate insulating layer 101, and the semiconductor layer 12 includes an active layer 121 corresponding to the gate 111. The semiconductor layer 12 may be made of a metal oxide (e.g., indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), zinc tin oxide (ZnSnO), gallium tin oxide (GaSnO), gallium zinc oxide (GaZnO), indium gallium zinc oxide (IGZO), or indium gallium zinc tin oxide (IGZTO).

[0040] Protective layer 13 (reference) Figure 12c A protective layer 13 is disposed above the gate insulating layer 101 and the semiconductor layer 12. The protective layer 13 includes a first protective layer 131 and a second protective layer 132. The first protective layer 131 is located at the channel of the active layer 121, and the second protective layer 132 is located at the edge of the gate 111. A portion of the second protective layer 132 overlaps with a portion of the gate 111, and another portion of the second protective layer 132 extends beyond the edge of the gate 111, while another portion of the gate 111 extends beyond the edge of the second protective layer 132. The first protective layer 131 has an island-like structure and is used to protect the channel region of the active layer 121 to facilitate the formation of a thin-film transistor with an island-like ESL structure. The second protective layer 132 is only disposed at the edge region of the gate 111 and partially covers the gate 111, while no protective layer 13 is disposed in the pixel aperture region. Since the first protective layer 131 and the second protective layer 132 are both etched from the same protective layer 13, it does not increase the difficulty of the process. Moreover, the second protective layer 132 is only disposed at the edge of the gate 111 and does not affect the aperture ratio of the pixel, so that its aperture ratio is the same as that of the island ESL structure.

[0041] In this embodiment, second protective layers 132 are provided on both opposite sides of the active layer 121. The two second protective layers 132 are in a "two" - shaped structure. The two ends of the first protective layer 131 are respectively connected to the two second protective layers 132 to form a "work" - shaped structure, that is, the extending direction of the first protective layer 131 is perpendicular to the extending direction of the second protective layer 132. Among them, the width a of the first protective layer 131 is about 3 - 20 μm, the width b of the second protective layer 132 is 6 - 30 μm, the width of the overlapping area between the second protective layer 132 and the gate 111 is 3 - 15 μm, and the width of the second protective layer 132 extending beyond the edge of the gate 111 is 3 - 15 μm.

[0042] A second metal layer 14. The second metal layer 14 is provided above the gate insulating layer 101, the semiconductor layer 12, and the protective layer 13. The second metal layer 14 includes data lines 141, source electrodes 142, and drain electrodes 143. Multiple scanning lines and multiple data lines 141 are insulated and cross - defined to form multiple pixel units. The data lines 141 are electrically connected to the source electrodes 142. The source electrodes 142 and the drain electrodes 143 are spaced apart from each other by the first protective layer 131 and are electrically connected through the active layer 121. That is, the gate 111, the active layer 121, the source electrodes 142, and the drain electrodes 143 together form a thin - film transistor (TFT) on the array substrate. At least part of the source electrode 142 overlaps with the second protective layer 132 at the edge of the gate 111, and at least part of the drain electrode 143 overlaps with the second protective layer 132 at the edge of the gate 111. That is, at least part of the source electrode 142 and at least part of the drain electrode 143 are separated by the second protective layer 132 at the edge of the gate 111 to avoid the problem of disconnection of the source electrode 142 and the drain electrode 143 at the edge of the gate 111, ensuring that at least part of the source electrode 142 and the drain electrode 143 (the area provided on the upper surface of the second protective layer 132) are connected together.

[0043] A first insulating layer 102 provided above the second metal layer 14 and covering the data lines 141, the source electrodes 142, and the drain electrodes 143. A planarization layer 103 provided above the first insulating layer 102. The material of the first insulating layer 102 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of the two. The material of the planarization layer 103 is an organic insulator (such as silicone - based, acrylic - based).

[0044] A first transparent conductive layer 15 provided above the planarization layer 103. The first transparent conductive layer 15 includes a common electrode 151. Among them, the material of the first transparent conductive layer 15 can be a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0045] A third metal layer 16 provided above the first transparent conductive layer 15 (refer to Figure 12gThe third metal layer 16 includes a common electrode trace 161 that is electrically in contact with the common electrode 151. The common electrode trace 161 is used to apply a common signal to the common electrode 151. The third metal layer 16 can be made of metals such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or combinations of the above metals such as Al / Mo, Cu / Mo, etc.

[0046] A second insulating layer 104 is disposed above the first transparent conductive layer 15 and the third metal layer 16. The second insulating layer 104, the planarization layer 103, and the first insulating layer 102 together have a contact hole TH corresponding to the drain electrode 143, which is exposed through the contact hole TH. The material of the second insulating layer 104 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.

[0047] A second transparent conductive layer 17 is disposed above the second insulating layer 104. The second transparent conductive layer 17 includes a pixel electrode 171 corresponding to a pixel unit. The pixel electrode 171 is a block electrode corresponding to the pixel unit and has a slit. The pixel electrode 171 is electrically connected to the corresponding drain electrode 143 through a contact hole TH. The pixel electrode 171 cooperates with the common electrode 151 to form a driving electric field. The material of the second transparent conductive layer 17 can be a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0048] In one embodiment, the protective layer 13 includes a third protective layer (not shown). The third protective layer is located at the intersection of the scan line and the data line 141. A portion of the third protective layer overlaps with a portion of the scan line, and another portion of the third protective layer extends beyond the edge of the scan line. The data line 141 at least partially overlaps with the third protective layer at the edge of the scan line. It is understood that in this embodiment, the protective layer 13 is retained only in the active layer 121 channel region, the region where the gate 111 edge overlaps with the source 142 and drain 143, and the region where the data line 141 overlaps with the scan line. In other areas of the array substrate, the protective layer 13 is not required. Since the metal of the scan line may also interfere with the distribution of the plasma electric field, causing pits in the gate insulating layer 101 at the edge of the scan line, the third protective layer is provided at the intersection of the scan line and the data line 141 to avoid the problem of data line 141 breaking. Optionally, the third protective layer has a block structure and covers the overlapping area of ​​the scan line and the data line 141. The edge of the third protective layer extends 6-30 μm beyond the edge of the overlapping area of ​​the scan line and data line 141. Of course, the shape of the third protective layer at the intersection of the scan line and data line 141 can also be a "two" shape, distributed on the edges of opposite sides of the scan line.

[0049] Figure 10 These are electron microscope planar views and partial magnified views of the thin-film transistor in Embodiment 1 of the present invention. Figure 11 These are electron microscope planar and cross-sectional views of the thin-film transistor in Embodiment 1 of the present invention. Figure 10 and Figure 11 As shown, in the region without ESL (protective layer 13) protection, the gate insulating layer 101 ( Figure 11 GI) in the first metal layer 11 ( Figure 11 There are pits at the edge of the M1), while in the area protected by ESL (protective layer 13), there are no pits at the edge of the first metal layer 11 of the gate insulating layer 101. Therefore, when setting the data line 141, the source 142 and the drain 143, the problem of the data line 141 being broken at the edge where it intersects with the scan line can be avoided, as well as the problem of the source 142 and the drain 143 being broken at the edge of the gate 111 can be avoided.

[0050] Figures 12a-12i This is a schematic diagram of the process flow of the array substrate in Embodiment 1 of the present invention. Figures 12a-12i As shown, this application also provides a method for fabricating an array substrate, used to fabricate the array substrate described above. The fabrication method includes: like Figure 12a As shown, a substrate 10 is provided, which may be made of materials such as glass, quartz, silicon, acrylic or polycarbonate. The substrate 10 may also be a flexible substrate. Suitable materials for flexible substrates include, for example, polyethersulfone (PES), polyethylene naphthalate (PEN), polyethylene (PE), polyimide (PI), polyvinyl chloride (PVC), polyethylene terephthalate (PET) or combinations thereof.

[0051] A first metal layer 11 is disposed above the substrate 10. The first metal layer 11 is etched to form patterned scan lines and gate 111, and the gate 111 is electrically connected to the scan lines. The first metal layer 11 can be a metal such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), or a combination of the above metals such as Al / Mo, Cu / Mo, etc.

[0052] A gate insulating layer 101 is disposed above the substrate 10, and the gate insulating layer 101 covers the gate 111 and the scan line. The material of the gate insulating layer 101 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of the two.

[0053] like Figure 12bAs shown, a semiconductor layer 12 is provided above the gate insulating layer 101. The semiconductor layer 12 is etched to form a patterned active layer 121, and the active layer 121 corresponds to the gate 111. Among them, the semiconductor layer 12 can be made of metal oxides (such as indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), zinc tin oxide (ZnSnO), gallium tin oxide (GaSnO), gallium zinc oxide (GaZnO), indium gallium zinc oxide (IGZO) or indium gallium zinc tin oxide (IGZTO), etc.).

[0054] As Figure 12c As shown, a protective layer 13 is provided above the gate insulating layer 101. The protective layer 13 is etched to form a patterned first protective layer 131 and a second protective layer 132. The first protective layer 131 is located at the channel of the active layer 121, and the second protective layer 132 is located at the edge of the gate 111. A part of the second protective layer 132 overlaps with a part of the gate 111, another part of the second protective layer 132 extends out of the edge of the gate 111, and another part of the gate 111 extends out of the edge of the second protective layer 132. The first protective layer 131 is an island structure and is used to protect the channel region of the active layer 121 to facilitate the formation of a thin film transistor with an island-shaped ESL structure; the second protective layer 132 is only provided in the edge region of the gate 111 and partially covers the gate 111, and no protective layer 13 needs to be provided in the pixel opening area. Since both the first protective layer 131 and the second protective layer 132 are etched from the same protective layer 13, it does not increase the process difficulty, and the second protective layer 132 is only provided at the edge of the gate 111 and does not affect the aperture ratio of the pixel, making its aperture ratio the same as that of the island-shaped ESL structure.

[0055] In this embodiment, second protective layers 132 are provided on both opposite sides of the active layer 121. The two second protective layers 132 are in a "two" - shaped structure. The two ends of the first protective layer 131 are respectively connected to the two second protective layers 132 to form a "work" - shaped structure, that is, the extending direction of the first protective layer 131 is perpendicular to the extending direction of the second protective layer 132. Among them, the width a of the first protective layer 131 is about 3 - 20 μm, the width b of the second protective layer 132 is 6 - 30 μm, the width of the overlapping area between the second protective layer 132 and the gate 111 is 3 - 15 μm, and the width of the part where the second protective layer 132 extends out of the edge of the gate 111 is 3 - 15 μm.

[0056] As Figure 12dAs shown, a second metal layer 14 is disposed above the gate insulating layer 101. The second metal layer 14 is etched to form patterned data lines 141, source electrodes 142, and drain electrodes 143. Multiple scan lines and multiple data lines 141 are mutually insulated and intersected to form multiple pixel units. The data lines 141 are electrically connected to the source electrodes 142. The source electrodes 142 and drain electrodes 143 are separated from each other by a first protective layer 131 and are electrically connected by an active layer 121. That is, the gate electrode 111, the active layer 121, the source electrodes 142, and the drain electrodes 143 together constitute a thin-film transistor (TFT) on the array substrate. The source 142 overlaps at least partially with the second protective layer 132 at the edge of the gate 111, and the drain 143 overlaps at least partially with the second protective layer 132 at the edge of the gate 111. That is, at least a portion of the source 142 and at least a portion of the drain 143 are separated by the second protective layer 132 at the edge of the gate 111 to avoid the problem of the source 142 and drain 143 being disconnected at the edge of the gate 111, and to ensure that at least a portion of the source 142 and drain 143 (the portion located on the upper surface of the second protective layer 132) are connected together.

[0057] like Figure 12e As shown, a first insulating layer 102 is formed above the second metal layer 14, covering the data line 141, the source electrode 142, and the drain electrode 143, and a planarization layer 103 is formed above the first insulating layer 102. The material of the first insulating layer 102 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of the two, and the material of the planarization layer 103 is an organic insulator (e.g., organosiloxane-based, acrylic-based).

[0058] like Figure 12f As shown, a first transparent conductive layer 15 is formed above the planarization layer 103. The first transparent conductive layer 15 is etched to form a patterned common electrode 151. The material of the first transparent conductive layer 15 can be a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0059] like Figure 12g As shown, a third metal layer 16 is formed above the first transparent conductive layer 15. The third metal layer 16 is etched to form a patterned common electrode trace 161. The common electrode trace 161 is in electrical contact with the common electrode 151 and is used to apply a common signal to the common electrode 151. The third metal layer 16 can be made of metals such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), or combinations of the above metals such as Al / Mo, Cu / Mo, etc.

[0060] like Figure 12hAs shown, a second insulating layer 104 is formed above the planarization layer 103, covering the common electrode 151 and the common electrode trace 161. The second insulating layer 104, the planarization layer 103, and the first insulating layer 102 are etched to form a contact hole TH corresponding to the drain 143, with the drain 143 exposed through the contact hole TH. The material of the second insulating layer 104 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.

[0061] like Figure 12i As shown, a second transparent conductive layer 17 is formed above the second insulating layer 104. The second transparent conductive layer 17 is etched to form patterned pixel electrodes 171. The pixel electrodes 171 are block electrodes corresponding to pixel units and have slits. The pixel electrodes 171 are electrically connected to the corresponding drain electrode 143 through contact holes TH. The pixel electrodes 171 and the common electrode 151 cooperate with each other to form a driving electric field. The material of the second transparent conductive layer 17 can be a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0062] In one embodiment, a patterned third protective layer is formed during the etching of the protective layer 13. This third protective layer is located at the intersection of the scan line and the data line 141. A portion of the third protective layer overlaps with a portion of the scan line, and another portion of the third protective layer extends beyond the edge of the scan line. The data line 141 at least partially overlaps with the third protective layer at the edge of the scan line. It is understood that in this embodiment, the protective layer 13 is retained only in the active layer 121 channel region, the region where the gate 111 edge overlaps with the source 142 and drain 143, and the region where the data line 141 overlaps with the scan line. In other areas of the array substrate, the protective layer 13 is not required. Since the metal of the scan line may also interfere with the distribution of the plasma electric field, causing pits in the gate insulating layer 101 at the edge of the scan line, the third protective layer is provided at the intersection of the scan line and the data line 141 to avoid the problem of data line breakage. Optionally, the third protective layer has a block structure and covers the overlapping area of ​​the scan line and the data line 141. The edge of the third protective layer extends 6-30 μm beyond the edge of the overlapping area of ​​the scan line and data line 141. Of course, the shape of the third protective layer at the intersection of the scan line and data line 141 can also be a "two" shape, distributed on the edges of opposite sides of the scan line.

[0063] [Example 2] Figure 13 This is one of the top-view planar structural diagrams of the thin-film transistor in Embodiment 2 of the present invention. Figure 14This is the second top-view planar structural schematic diagram of the thin-film transistor in Embodiment 2 of the present invention. (See attached diagram.) Figure 13 and Figure 14 As shown, the array substrate and fabrication method provided in Embodiment 2 of the present invention are the same as those in Embodiment 1. Figures 7 to 12i The array substrate and fabrication method are basically the same as those in the previous example, the difference being: like Figure 13 As shown, there are gaps between the two ends of the first protective layer 131 and the second protective layer 132, that is, the first protective layer 131 does not need to be connected to the second protective layer 132.

[0064] like Figure 14 As shown, the two ends of the second protective layer 132 extend beyond the edges of the source 142 and the drain 143. That is, the areas of the source 142 and the drain 143 located at the edge of the gate 111 are completely separated by the second protective layer 132, which can completely avoid the problem of the source 142 and the drain 143 breaking at the edge of the gate 111, thereby improving the conductivity of the source 142 and the drain 143.

[0065] Those skilled in the art should understand that the remaining structures and working principles of this embodiment are the same as those of Embodiment 1, and will not be repeated here.

[0066] Figure 15 This is a schematic diagram of the display device in the dark state according to the present invention. Figure 16 This is a schematic diagram of the display device in the present invention in the illuminated state. (See attached diagram.) Figure 15 and Figure 16 As shown, this application also provides a display panel, including an array substrate, a color filter substrate 20 disposed opposite to the array substrate, and a liquid crystal layer 30 located between the array substrate and the color filter substrate 20. The array substrate is the array substrate described above.

[0067] The liquid crystal layer 30 uses positive liquid crystal molecules, that is, liquid crystal molecules with positive dielectric anisotropy, such as... Figure 15 As shown, in the initial state, the positive liquid crystal molecules in the liquid crystal layer 30 are aligned parallel to the color filter substrate 20 and the array substrate, and the alignment direction of the positive liquid crystal molecules near the color filter substrate 20 is opposite to that of the positive liquid crystal molecules near the array substrate. Of course, in other embodiments, the liquid crystal layer 30 can also use negative liquid crystal molecules, and the negative liquid crystal molecules in the liquid crystal layer 30 can be aligned perpendicular to the color filter substrate 20 and the array substrate, that is, similar to the alignment method of VA display mode.

[0068] On the side of the color filter substrate 20 facing the liquid crystal layer 30, there are multiple color resist layers 22 corresponding to pixel units and black matrices (BM) 21 that space the multiple color resist layers 22 apart from each other. A black matrix 21 is provided between any two adjacent columns and two adjacent rows of pixel units. The color resist layers 22 include red (R), green (G), and blue (B) color resist materials, which respectively form red, green, and blue pixel units. The black matrices 21 are located between the red, green, and blue pixel units, so that adjacent pixel units are separated from each other by the black matrices 21.

[0069] Furthermore, an upper polarizer 51 is provided on the side of the color filter substrate 20 away from the liquid crystal layer 30, and a lower polarizer 52 is provided on the side of the array substrate away from the liquid crystal layer 30. The light transmission axis of the upper polarizer 51 and the light transmission axis of the lower polarizer 52 are perpendicular to each other.

[0070] The color filter substrate 20 and the array substrate can be made of transparent substrates such as glass, acrylic, and polycarbonate. The common electrode block 151 and the pixel electrode 171 can be made of transparent electrodes such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0071] The present invention also provides a display device, including a display panel and a backlight module 40, wherein the backlight module 40 is located below the display panel and is used to provide a backlight source for the display panel.

[0072] The backlight module 40 can be an edge-lit backlight module or a direct-lit backlight module. Preferably, the backlight module 40 adopts a collimated backlight (CBL) mode, which can collect light and ensure display effect.

[0073] In this document, the directional terms such as up, down, left, right, front, and back are defined according to the position of the structures in the accompanying drawings and the relative positions of the structures, and are only used for clarity and convenience in expressing the technical solution. It should be understood that the use of these directional terms should not limit the scope of protection claimed in this application. It should also be understood that the terms "first" and "second," etc., used herein are only used for distinction in name and are not used to limit the number or order.

[0074] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content without departing from the scope of the technical solution of the present invention, which are equivalent embodiments with equivalent changes. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the technical solution of the present invention shall still fall within the protection scope of the technical solution of the present invention.

Claims

1. An array substrate, characterized in that, include: Substrate (10); A first metal layer (11) is disposed above the substrate (10). The first metal layer (11) includes a scan line and a gate (111). The gate (111) is electrically connected to the scan line. A gate insulating layer (101) is disposed above the first metal layer (11) and covers the scan line and the gate (111); A semiconductor layer (12) is disposed above the gate insulating layer (101), and the semiconductor layer (12) includes an active layer (121) corresponding to the gate (111); A protective layer (13) is disposed above the gate insulating layer (101) and the semiconductor layer (12). The protective layer (13) includes a first protective layer (131) and a second protective layer (132). The first protective layer (131) is located at the channel of the active layer (121), and the second protective layer (132) is located at the edge of the gate (111). A portion of the second protective layer (132) overlaps with a portion of the gate (111), and another portion of the second protective layer (132) extends out of the edge of the gate (111). Another portion of the gate (111) extends out of the edge of the second protective layer (132). A second metal layer (14) is disposed above the gate insulating layer (101), the semiconductor layer (12), and the protective layer (13). The second metal layer (14) includes a data line (141), a source (142), and a drain (143). The data line (141) is electrically connected to the source (142). The source (142) and the drain (143) are spaced apart from each other by the first protective layer (131) and electrically connected by the active layer (121). The source (142) overlaps at least partially with the second protective layer (132) at the edge of the gate (111), and the drain (143) overlaps at least partially with the second protective layer (132) at the edge of the gate (111).

2. The array substrate according to claim 1, characterized in that, The active layer (121) has a second protective layer (132) on each of its opposite sides. The two ends of the first protective layer (131) are respectively connected to the two second protective layers (132) to form an "I" shaped structure. Alternatively, there is a gap between the two ends of the first protective layer (131) and the second protective layer (132).

3. The array substrate according to claim 1, characterized in that, The two ends of the second protective layer (132) extend beyond the edges of the source (142) and the drain (143).

4. The array substrate according to claim 1, characterized in that, The protective layer (13) includes a third protective layer located at the intersection of the scan line and the data line (141). A portion of the third protective layer overlaps with a portion of the scan line, and another portion of the third protective layer extends beyond the edge of the scan line. The data line (141) overlaps at least partially with the third protective layer at the edge of the scan line.

5. The array substrate according to claim 4, characterized in that, The third protective layer has a block structure and covers the overlapping area of ​​the scan line and the data line (141).

6. The array substrate according to any one of claims 1-5, characterized in that, The array substrate includes: A pixel electrode (171) and a common electrode block (151) that cooperates with the pixel electrode (171), wherein the pixel electrode (171) is in contact with the drain electrode (143).

7. A method for fabricating an array substrate, characterized in that, The method for fabricating an array substrate as described in any one of claims 1-6 includes: Provide substrate (10); A first metal layer (11) is disposed above the substrate (10), and the first metal layer (11) is etched to form patterned scan lines and gates (111), wherein the gates (111) are electrically connected to the scan lines; A gate insulating layer (101) is disposed above the substrate (10), and the gate insulating layer (101) covers the gate (111) and the scan line; A semiconductor layer (12) is disposed above the gate insulating layer (101), and the semiconductor layer (12) is etched to form a patterned active layer (121), the active layer (121) corresponding to the gate (111); A protective layer (13) is provided above the gate insulating layer (101). The protective layer (13) is etched to form a patterned first protective layer (131) and a second protective layer (132). The first protective layer (131) is located at the channel of the active layer (121), and the second protective layer (132) is located at the edge of the gate (111). A portion of the second protective layer (132) overlaps with a portion of the gate (111), and another portion of the second protective layer (132) extends beyond the edge of the gate (111). Another portion of the gate (111) extends beyond the edge of the second protective layer (132). A second metal layer (14) is disposed above the gate insulating layer (101). The second metal layer (14) is etched to form patterned data lines (141), a source (142), and a drain (143). The data lines (141) are electrically connected to the source (142). The source (142) and the drain (143) are spaced apart from each other by the first protective layer (131) and electrically connected by the active layer (121). The source (142) overlaps at least partially with the second protective layer (132) at the edge of the gate (111). The drain (143) overlaps at least partially with the second protective layer (132) at the edge of the gate (111).

8. The method for fabricating an array substrate according to claim 7, characterized in that, The active layer (121) has a second protective layer (132) on each of its opposite sides. The two ends of the first protective layer (131) are respectively connected to the two second protective layers (132) to form an "I" shaped structure. Alternatively, there is a gap between the two ends of the first protective layer (131) and the second protective layer (132).

9. The method for fabricating an array substrate according to claim 7, characterized in that, When the protective layer (13) is etched, a patterned third protective layer is also formed. The third protective layer is located at the intersection of the scan line and the data line (141). A portion of the third protective layer overlaps with a portion of the scan line. Another portion of the third protective layer extends beyond the edge of the scan line. Another portion of the scan line extends beyond the edge of the third protective layer. The data line (141) overlaps at least partially with the third protective layer at the edge of the scan line.

10. A display device, characterized in that, Includes the array substrate as described in any one of claims 1-6.

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