Method for improving electric leakage of isolation region of high-voltage device

Abstract

The invention provides a method for improving electric leakage of an isolation region of a high-voltage device, which comprises the following steps of: 1, providing a substrate, dividing the substrate into a low-voltage device region, a medium-voltage device region and a high-voltage device region by an isolation region formed in the substrate, and forming a medium-voltage device oxide layer on the substrate; 2, removing a part of the medium-voltage device oxide layer, and only reserving the medium-voltage device oxide layer in a high-voltage device isolation region in the medium-voltage device region and the isolation region; 3, forming a high-voltage device grid side wall material layer on the substrate; 4, removing a part of the high-voltage device grid side wall material layer, and only reserving the high-voltage device grid side wall material layer in the high-voltage device grid groove and the high-voltage device isolation region; and step 5, forming a refractory silicide barrier layer in a designated area of the substrate, wherein the designated area does not contain a high-voltage device isolation area. Under the condition that the chip area is not increased and data is not modified, the isolation effect electric leakage level which is the same as that of removing the active area auxiliary layer is achieved, the method is compatible with an existing process, and no newly-added mask is needed.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a method for improving the leakage of the isolation region of a high-voltage device. BACKGROUND

[0002] OLED (Organic Light Emitting Diode) is a current injection compound light emitting type as the third generation of display technology, and its main advantages are high brightness, high contrast, wide viewing angle, fast response speed, low operating voltage, strong adaptability, high energy conversion efficiency, simple manufacturing process, etc. Due to the huge technical advantages and application prospects of OLED, it has attracted widespread attention from the academic and industrial circles.

[0003] OLED is a current driving type, and the current density of OLED depends on the driving voltage at both ends. The higher the voltage, the greater the current density. The OLED technology combined with advanced technology nodes needs to integrate low-voltage SRAM and high-voltage driving devices. The isolation distance between different types of high-voltage device regions needs to be increased due to high voltage, but it will affect the chemical mechanical polishing of the active area, and it is necessary to add enough active area dummy layers. The increase of the active area dummy layer can effectively improve the process problem, but the upper part of the active area dummy layer will form a refractory silicide layer as shown in Figure 1 , which has low resistance and leads to voltage distribution, resulting in a decrease in the corresponding isolation effect and an increase in the leakage of the high-voltage device isolation region.

[0004] Since the refractory silicide barrier layer directly covering the active area dummy layer needs to expand the distance between the actual active areas, the chip area increases, and it can only be realized by manually implementing part of the area, and cannot be automatically implemented in all cases while maintaining the chip area, as shown in Figure 1 , it can be seen that the leakage current increases as the distance between the active area dummy layer and the isolation boundary decreases. SUMMARY

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a method for improving the leakage of the isolation region of a high-voltage device, which solves the problem of the formation of a refractory silicide layer on part of the upper part of the active area dummy layer of the high-voltage device isolation region in the prior art, resulting in leakage of the high-voltage device isolation region.

[0006] To achieve the above-mentioned purpose and other related purposes, the present application provides a method for improving the leakage of the isolation region of a high-voltage device, comprising:

[0007] Step 1: providing a substrate, the isolation region formed in the substrate divides the substrate into a low-voltage device region, a medium-voltage device region and a high-voltage device region, and a medium-voltage device oxide layer is formed on the substrate;

[0008] Step two, remove part of the medium voltage device oxide layer, only keep the medium voltage device oxide layer in the medium voltage device region and the high voltage device isolation region in the isolation region;

[0009] Step three, form a high voltage device gate sidewall material layer on the substrate;

[0010] Step four, remove part of the high voltage device gate sidewall material layer, only keep the high voltage device gate sidewall material layer in the high voltage device gate trench and the high voltage device isolation region;

[0011] Step five, form a refractory silicide barrier layer on the substrate in the designated region, which does not contain the high voltage device isolation region.

[0012] Preferably, the high voltage device isolation region in the isolation region is formed with a plurality of active region auxiliary layers.

[0013] Preferably, the isolation region is formed by a shallow trench isolation process.

[0014] Preferably, the medium voltage device oxide layer is formed on the substrate by a deposition process, and the material of the medium voltage device oxide layer includes silicon oxide.

[0015] Preferably, in step two, a patterned first hard mask layer is first formed on the substrate, and then the medium voltage device oxide layer on the low voltage device region, the high voltage device region, and the remaining isolation region except the high voltage device isolation region is removed by a first etching process with the patterned first hard mask layer as a mask.

[0016] Preferably, after step two, the patterned first hard mask layer is removed.

[0017] Preferably, before step three, a gate trench is formed in the high voltage device region.

[0018] Preferably, the high voltage device gate sidewall material layer is formed on the substrate by a deposition process, and the material of the high voltage device gate sidewall material layer includes silicon nitride.

[0019] Preferably, in step four, a patterned second hard mask layer is first formed on the substrate, and then the high voltage device gate sidewall material layer on the low voltage device region, the medium voltage device region, the high voltage device region except in the high voltage device gate trench, and the remaining isolation region except the high voltage device isolation region is removed by a second etching process with the patterned second hard mask layer as a mask.

[0020] Preferably, after step four, the patterned second hard mask layer is removed.

[0021] The method for improving the leakage of the high-voltage device isolation region provided by the application has the following beneficial effects: by forming the medium-voltage device oxide layer and the high-voltage device gate sidewall material layer on the active region auxiliary layer of the high-voltage isolation region, the formation of the refractory silicide on the upper part of the active region auxiliary layer can be effectively blocked, the same isolation effect and leakage level as removing the active region auxiliary layer can be achieved without increasing the chip area and modifying the data, the process requirements of the active region chemical mechanical polishing can be met, the existing process is compatible, and no new mask plate is added. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0023] Figure 1 A schematic diagram showing that the formation of the refractory silicide layer on the upper part of the active region auxiliary layer of the high-voltage device isolation region in the prior art causes the leakage of the high-voltage device isolation region;

[0024] Figure 2 A flowchart showing the method for improving the leakage of the high-voltage device isolation region provided by the embodiments of the present application. DETAILED DESCRIPTION

[0025] The embodiments of the present application will be described below through specific, concrete examples, and those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in the specification. The present application can also be implemented or applied through other different specific embodiments, and each detail in the specification can be modified or changed based on different views and applications without departing from the spirit of the present application.

[0026] The technical solutions in the present application will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0027] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application. In addition, the terms "first", "second", "third" are only for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0028] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal communication of two elements, it can be wireless connection, or it can be wired connection. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0029] Please refer to Figure 2 , which shows the flowchart of the method for improving the leakage of the isolation region of the high-voltage device provided by the embodiment of the present application.

[0030] As shown in Figure 2 , the method for improving the leakage of the isolation region of the high-voltage device comprises the following steps:

[0031] Step 1: providing a substrate, the isolation region formed in the substrate divides the substrate into a low-voltage device region, a medium-voltage device region and a high-voltage device region, and forming a medium-voltage device oxide layer on the substrate;

[0032] Step 2: removing part of the medium-voltage device oxide layer, and retaining the medium-voltage device oxide layer only in the medium-voltage device region and the high-voltage device isolation region in the isolation region;

[0033] Step 3: forming a high-voltage device gate side wall material layer on the substrate;

[0034] Step 4: removing part of the high-voltage device gate side wall material layer, and retaining the high-voltage device gate side wall material layer only in the high-voltage device gate trench and the high-voltage device isolation region;

[0035] Step 5: forming a refractory silicide barrier layer in a specified region of the substrate, and the specified region does not contain the high-voltage device isolation region.

[0036] In step one, the substrate is a silicon substrate, a germanium substrate, or a silicon-on-insulator substrate, etc. Alternatively, the substrate material can also include other materials, such as a gallium arsenide or other group III-V compound. Those skilled in the art can select the substrate material according to the type of device structure formed on the substrate, and thus the type of substrate should not limit the scope of the present application.

[0037] The substrate has a plurality of isolation regions formed therein, which divide the substrate into a plurality of regions, including a low voltage device region, a medium voltage device region, and a high voltage device region. The high voltage device isolation region in the isolation region has a plurality of active region auxiliary layers formed therein.

[0038] The isolation region can be composed of any insulating material, such as silicon dioxide (SiO2), or a "high-K" dielectric having a high dielectric constant, which can be higher than 3.9, for example. In some cases, the isolation region can be composed of an oxide material. The material suitable for composing the isolation region can include, for example, silicon dioxide (SiO2), hafnium oxide (HfO2), alumina (Al2O3), yttria (Y2O3), tantalum oxide (Ta2O5), titanium dioxide (TiO2), praseodymium oxide (Pr2O3), zirconium oxide (ZrO2), erbium oxide (ErOx), and other materials having similar properties that are currently known or later developed.

[0039] The isolation region is formed, for example, by a shallow trench isolation (STI) process, which includes, but is not limited to, a shallow trench etching, an oxide filling, and an oxide planarization.

[0040] The shallow trench etching includes, but is not limited to, an isolation oxide layer, a nitride deposition, a shallow trench isolation using a mask, and an STI shallow trench etching. The STI oxide filling includes, but is not limited to, a trench liner oxide silicon, a trench CVD (chemical vapor deposition) oxide filling, or a PVD (physical vapor deposition) oxide filling. The planarization of the silicon wafer surface can be achieved by various methods. The planarization of the silicon wafer can be achieved by filling the gap using SOG (spin-on-glass), which can be composed of 80% solvent and 20% silicon dioxide. After deposition, the SOG is baked, the solvent is evaporated, and the silicon dioxide is left in the gap. The entire surface can also be etched back to reduce the thickness of the entire silicon wafer. The planarization can also be effectively achieved by a CMP process (also known as a chemical mechanical polishing process), which includes, but is not limited to, polishing the trench oxide (which can be performed by chemical mechanical polishing) and removing the nitride.

[0041] The medium voltage device oxide layer is formed on the substrate by a deposition process, for example. The material of the medium voltage device oxide layer includes, for example, silicon oxide.

[0042] In step two, a patterned first hard mask layer is formed on the substrate, and then the first etching is performed to remove the medium pressure device oxide layer on the rest of the isolation regions except the high pressure device region, the high pressure device region and the high pressure device isolation region, with the patterned first hard mask layer as a mask. After step two, the patterned first hard mask layer is removed.

[0043] In step three, a gate trench is formed in the high pressure device region before forming the high pressure device gate sidewall material layer on the substrate. As an example, the high pressure device gate sidewall material layer is formed on the substrate by a deposition process, and the high pressure device gate sidewall material layer in the high pressure device gate trench serves as a barrier to avoid the bottom of the gate trench from being affected by subsequent processes. As an example, the material of the high pressure device gate sidewall material layer includes silicon nitride.

[0044] In step four, a patterned second hard mask layer is formed on the substrate, and then the second etching is performed to remove the high pressure device gate sidewall material layer on the rest of the isolation regions except the high pressure device region except the high pressure device gate trench and the high pressure device isolation region, with the patterned second hard mask layer as a mask. After step four, the patterned second hard mask layer is removed.

[0045] In step five, a refractory silicide barrier layer is formed on the specified region of the substrate, such as the gate top and the source / drain region on both sides of the gate, by a deposition process.

[0046] Since the medium pressure device oxide layer and the high pressure device gate sidewall material layer have been formed on the high pressure device isolation region in a bottom-up manner, for the high pressure device isolation region, it is not necessary to form a refractory silicide barrier layer to prevent the formation of refractory silicide on the upper part of the active area auxiliary layer.

[0047] It should be noted that the drawings provided in the embodiments only schematically illustrate the basic concepts of the present application, and only the components related to the present application are shown in the drawings, rather than the number, shape and size of the components when actually implemented. The actual implementation of each component can be randomly changed, and the component layout pattern can be more complex.

[0048] In summary, the method for improving the leakage of the high pressure device isolation region provided by the present application can effectively prevent the formation of refractory silicide on the upper part of the active area auxiliary layer by forming a medium pressure device oxide layer and a high pressure device gate sidewall material layer on the active area auxiliary layer of the high pressure isolation region. The isolation effect and leakage level are the same as removing the active area auxiliary layer without increasing the chip area and modifying the data, which can meet the process requirements of the active area chemical mechanical polishing and is compatible with the existing process without adding new masks. Therefore, the present application effectively overcomes the shortcomings of the prior art and has high industrial utilization value.

[0049] The above embodiments are only illustrative of the principles and effects of the present application, and are not intended to limit the present application. Any modification or change made by those skilled in the art without departing from the spirit and scope of the present application shall be covered by the claims of the present application.

Claims

1. A method for improving leakage current in the isolation area of ​​high-voltage devices, characterized in that, The method includes: Step 1: Provide a substrate, wherein an isolation region is formed in the substrate to divide the substrate into a low-voltage device region, a medium-voltage device region and a high-voltage device region, and form a medium-voltage device oxide layer on the substrate; Step 2: Remove part of the oxide layer of the medium-voltage device, leaving only the oxide layer of the medium-voltage device in the medium-voltage device area and the high-voltage device isolation area in the isolation area; Step 3: Form a high-voltage device gate sidewall material layer on the substrate; Step 4: Remove part of the gate sidewall material layer of the high-voltage device, leaving only the gate sidewall material layer of the high-voltage device in the gate trench and the isolation region of the high-voltage device; Step 5: Form a refractory silicide barrier layer in a designated area of ​​the substrate, wherein the designated area does not contain the isolation area of ​​the high-voltage device.

2. The method according to claim 1, characterized in that, The isolation area of ​​the high-voltage device in the isolation zone has multiple active auxiliary layers.

3. The method according to claim 1, characterized in that, The isolation zone is formed using a shallow trench isolation process.

4. The method according to claim 1, characterized in that, The medium-voltage device oxide layer is formed on the substrate by a deposition process, and the material of the medium-voltage device oxide layer includes silicon oxide.

5. The method according to claim 1, characterized in that, In step two, a patterned first hard mask layer is first formed on the substrate, and then the patterned first hard mask layer is used as a mask to remove the medium-voltage device oxide layer located on the low-voltage device region, the high-voltage device region and the remaining isolation regions except the high-voltage device isolation region by a first etching process.

6. The method according to claim 5, characterized in that, After step two is completed, the patterned first hard mask layer is removed.

7. The method according to claim 1, characterized in that, Before performing step three, a gate trench is formed in the high-voltage device region.

8. The method according to claim 1, characterized in that, The high-voltage device gate sidewall material layer is formed on the substrate by a deposition process, and the material of the high-voltage device gate sidewall material layer includes silicon nitride.

9. The method according to claim 1, characterized in that, In step four, a patterned second hard mask layer is first formed on the substrate. Then, using the patterned second hard mask layer as a mask, the high-voltage device gate sidewall material layer located in the low-voltage device region, the medium-voltage device region, the high-voltage device region except in the high-voltage device gate trench, and the remaining isolation regions except the high-voltage device isolation region are removed by a second etching process.

10. The method according to claim 9, characterized in that, After step four is completed, the patterned second hard mask layer is removed.

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