ESD protection structure, forming method thereof and semiconductor device
By constructing complex doped layers and interconnect structures in LDMOS, the problem of insufficient protection performance of LDMOS in ESD events is solved, achieving faster ESD discharge and stronger protection effect.
Patent Information
- Application Number
- CN202511800216.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-02
- Publication Date
- 2026-02-27
AI Technical Summary
Laterally diffused metal-oxide-semiconductor transistors (LDMOS) have low ESD protection performance when facing ESD events, which can easily lead to gate breakdown, thermal runaway and permanent damage.
By forming a drift region on the substrate and setting different doped layers and bulk regions within the drift region to form a complex doped layer and interconnect structure, an ESD protection structure is constructed, including a first interconnect as an anode and a second interconnect as a cathode, thereby improving the instantaneous discharge speed of the ESD protection structure.
This improves the instantaneous discharge speed of the ESD protection structure against ESD, enhances ESD protection performance, and avoids device damage caused by ESD events.
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Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of semiconductor, in particular to an ESD protection structure, a forming method thereof and a semiconductor device. BACKGROUND
[0002] Lateral double diffusion MOS (LDMOS) is the main device in the field of radio frequency communication, power management and automotive electronics, due to its good breakdown voltage control, low on-resistance and performance suitable for high power amplifier.
[0003] However, LDMOS is relatively fragile in the face of ESD (Electrostatic Discharge) events, especially in the moment when the power or RF port withstands the peak voltage, because of its own low ESD protection structure performance, it is easy to cause gate breakdown, thermal runaway and even permanent damage. Therefore, how to provide a technical solution to improve the performance of the ESD protection structure has become a technical problem that technicians in the field need to solve. SUMMARY
[0004] The technical problem solved by the present application is to improve the performance of the ESD protection structure by providing an ESD protection structure, a forming method thereof and a semiconductor device.
[0005] To solve the above problems, the embodiment of the present application provides a forming method of an ESD protection structure, comprising: providing a substrate; forming a drift region on the substrate; forming a first doped layer and a second doped layer in the drift region, the first doped layer and the second doped layer are different in doping type; forming a first body region and a second body region in the drift region, the first body region is located on a side of the first doped layer away from the second doped layer, and the second body region is located on a side of the second doped layer away from the first doped layer; forming a third doped layer, a fourth doped layer and a fifth doped layer in the first body region, the fourth doped layer is located between the third doped layer and the fifth doped layer, the fifth doped layer is close to the first doped layer, the third doped layer, the fourth doped layer and the fifth doped layer are staggered in doping type, and the fourth doped layer is different from the first doped layer in doping type; forming a sixth doped layer and a seventh doped layer in the second body region, the sixth doped layer is close to the second doped layer, the sixth doped layer and the seventh doped layer are the same in doping type, and the fourth doped layer is the same as the sixth doped layer in doping type; forming a first connecting line connecting the first doped layer and the sixth doped layer as an anode of the ESD protection structure; forming a second connecting line connecting the second doped layer, the third doped layer and the fourth doped layer as a cathode of the ESD protection structure; and forming a third connecting line connecting the fifth doped layer and the seventh doped layer.
[0006] Optionally, after the drift region is formed, before the first doped layer and the second doped layer are formed, a first recess is formed in the drift region; a first isolation layer filling the first recess is formed, the first doped layer and the second doped layer are located on two sides of the first isolation layer; in the step of forming the first recess, a second recess and a third recess are also formed in the drift region, the second recess is located on one side of the first recess, and the third recess is located on the other side of the first recess; in the step of forming the first isolation layer filling the first recess, a second isolation layer filling the second recess and a third isolation layer filling the third recess are also formed, the first doped layer is located between and in contact with the first isolation layer and the second isolation layer, and the second doped layer is located between and in contact with the first isolation layer and the third isolation layer.
[0007] Optionally, after forming the second isolation layer and the third isolation layer, before forming the first doped layer and the second doped layer, a first gate structure and a second gate structure are formed on the drift region, the first gate structure is located on a side of the second isolation layer away from the first isolation layer, and the second gate structure is located on a side of the third isolation layer away from the first isolation layer; wherein a part of the first body region extends to below the first gate structure, so that the first gate structure spans the first body region and the drift region, and a part of the second body region extends to below the second gate structure, so that the second gate structure spans the second body region and the drift region.
[0008] Optionally, the step of forming the first gate structure and the second gate structure comprises: forming a first gate dielectric layer and a second gate dielectric layer on the drift region; forming a first gate electrode on the first gate dielectric layer and a second gate electrode on the second gate dielectric layer; forming a first gate sidewall covering the first gate electrode and a second gate sidewall covering the second gate electrode. Optionally, the step of forming the first gate structure and the second gate structure comprises: forming a first gate dielectric layer and a second gate dielectric layer on the drift region; forming a first gate electrode on the first gate dielectric layer and a second gate electrode on the second gate dielectric layer; forming a first gate sidewall covering the first gate electrode and a second gate sidewall covering the second gate electrode.
[0009] Optionally, after forming the first body region and the second body region, before forming the third doped layer, the fourth doped layer and the fifth doped layer in the first body region, a fourth recess and a fifth recess are formed in the first body region, and a sixth recess is formed in the second body region; a fourth isolation layer, a fifth isolation layer and a sixth isolation layer corresponding to the fourth recess, the fifth recess and the sixth recess are formed, the third doped layer and the fourth doped layer are located on two sides of the fourth isolation layer, the fourth doped layer and the fifth doped layer are located on two sides of the fifth isolation layer, and the sixth doped layer and the seventh doped layer are located on two sides of the sixth isolation layer.
[0010] Optionally, the forming method further comprises: a method for forming the first doped layer, wherein in the step of forming the first recess, a seventh recess is further formed in the drift region, an epitaxial layer is formed in the seventh recess, and stress doping is performed on the first doped layer to increase the stress of the first doped layer.
[0011] Optionally, the stress doping dopant comprises one or more of germanium, silicon germanium, gallium arsenide and indium gallium arsenide.
[0012] To solve the above problems, an ESD protection structure is provided, comprising: a substrate; a drift region located on the substrate; a first doped layer and a second doped layer located in the drift region and isolated from each other; a first body region and a second body region in the drift region, the first body region being located on a side of the first doped layer away from the second doped layer, and the second body region being located on a side of the second doped layer away from the first doped layer; a third doped layer, a fourth doped layer and a fifth doped layer, which are isolated from each other and located in the first body region, the fourth doped layer being located between the third doped layer and the fifth doped layer, and the fifth doped layer being close to the first doped layer; a sixth doped layer and a seventh doped layer, which are isolated and located in the second body region, the sixth doped layer being close to the second doped layer; a first connecting line connecting the first doped layer and the sixth doped layer; a second connecting line connecting the second doped layer, the third doped layer and the fifth doped layer; and a third connecting line connecting the fifth doped layer and the seventh doped layer.
[0013] Optionally, the ESD protection structure further comprises: a first isolation layer in the drift region, the first doped layer and the second doped layer being located on two sides of the isolation layer; a second isolation layer and a third isolation layer in the drift region, the first doped layer being located between and in contact with the first isolation layer and the second isolation layer, and the second doped layer being located between and in contact with the first isolation layer and the third isolation layer; a fourth isolation layer and a fifth isolation layer in the first body region; a sixth isolation layer in the second body region, the third doped layer and the fourth doped layer being located on two sides of the fourth isolation layer, the fourth doped layer and the fifth doped layer being located on two sides of the fifth isolation layer, and the sixth doped layer and the seventh doped layer being located on two sides of the sixth isolation layer; a first gate structure and a second gate structure on the drift region, the first gate structure being located on a side of the second isolation layer away from the first isolation layer, and the second gate structure being located on a side of the third isolation layer away from the first isolation layer; wherein a part of the first body region extends below the first gate structure, so that the first gate structure spans the first body region and the drift region, and a part of the second body region extends below the second gate structure, so that the second gate structure spans the second body region and the drift region.
[0014] To solve the above problems, the embodiment of the present application provides a semiconductor device, which is made by BCD process and contains any one of the above ESD protection structures; wherein the second doped layer, the fourth doped layer and the seventh doped layer in the ESD protection structure are formed by reusing the doping process of the source-drain doped layer in the BCD process; the mask of the second doped layer, the fourth doped layer and the seventh doped layer in the ESD protection structure is formed by adjusting the pattern based on the mask of the source-drain doped layer in the BCD process; the first body region and the second body region in the ESD protection structure are formed by reusing the forming process of the body region in the BCD process; and the mask of the first body region and the second body region in the ESD protection structure is formed by adjusting the pattern based on the mask of the body region in the BCD process.
[0015] Compared with the prior art, the technical scheme of the embodiment of the present application has the following advantages: The forming method of the ESD protection structure in the embodiment of the present application comprises the following steps: providing a substrate; forming a drift region; forming a first doped layer and a second doped layer; forming a first body region and a second body region; forming a third doped layer, a fourth doped layer and a fifth doped layer which are isolated from each other in the first body region, wherein the doping types of the third doped layer, the fourth doped layer and the fifth doped layer are staggered; forming a sixth doped layer and a seventh doped layer which are isolated from each other in the second body region; forming a first connecting line which connects the first doped layer and the sixth doped layer and serves as an anode of the ESD protection structure; forming a second connecting line which connects the second doped layer, the third doped layer and the fourth doped layer and serves as a cathode of the ESD protection structure; and forming a third connecting line which connects the fifth doped layer and the seventh doped layer; the sixth doped layer, the seventh doped layer and the second body region constitute a first semiconductor transistor of the ESD protection structure, the first doped layer, the drift region and the second body region constitute a second semiconductor transistor of the ESD protection structure, and the fourth doped layer, the first body region and the drift region constitute a third semiconductor transistor of the ESD protection structure; the first doped layer and the sixth doped layer are connected by the first connecting line, the second doped layer, the third doped layer and the fourth doped layer are connected by the second connecting line, and the fifth doped layer and the seventh doped layer are connected by the third connecting line, so that the performance of the ESD protection structure is improved. BRIEF DESCRIPTION OF DRAWINGS
[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of the provided drawings.
[0017] Figure 1 is a structural schematic diagram of an ESD protection structure; Figures 2 to 6 is a structural schematic diagram corresponding to each step in the forming method of the ESD protection structure of the first embodiment of the present application; Figures 7 to 9 is a structural schematic diagram corresponding to each step in the forming method of the ESD protection structure of the second embodiment of the present application; Figure 10 is an ESD circuit structural schematic diagram of the ESD protection structure of the embodiment of the present application. DETAILED DESCRIPTION
[0018] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.
[0019] The background technology mentions the problem of low performance of the ESD protection structure, and the reasons are analyzed in detail below.
[0020] Reference Figure 1 is a circuit structural schematic diagram of an ESD protection structure.
[0021] The ESD protection structure comprises a first semiconductor device 100, a second semiconductor device 101, a first type resistor 102, and a second type resistor 103. The first semiconductor device 100 comprises a first emitter, a first base, and a first collector. The second semiconductor device 101 comprises a second emitter, a second base, and a second collector. The first emitter is connected to one end of the second type resistor 103, and the first collector is connected to one end of the first type resistor 102. The second collector is connected to the other end of the second type resistor 103 and the first base, the second base is connected to one end of the first type resistor 102, and the second emitter is connected to the other end of the first type resistor 102. The first emitter and one end of the second type resistor 103 are grounded at a position 105, and the second emitter and the other end of the first type resistor 102 are connected at a position 104. The type of the first semiconductor device 100 is NPN transistor, and the type of the second semiconductor device 101 is PNP transistor.
[0022] Continue to refer to Figure 1 With ESD as a positive charge pulse (referred to as ESD positive pulse), the working principle of the ESD protection structure is described: The ESD positive pulse from position 104, through the first type resistor 102, opens the first semiconductor device 100, the first current through the first semiconductor device 100, due to the existence of the second type resistor 103, the second base voltage of the second semiconductor device 101 is pulled low, so that the second emitter and the second base of the second semiconductor device 101 exist a voltage difference, thereby opening the second semiconductor device 101, the current through the second semiconductor device 101 is called the second current, the second current, on the one hand, flows to position 105 (ground) through the second type resistor 103, on the other hand, the second current flows to the first base of the first semiconductor device 100, so that the first current through the first semiconductor device 100 increases, further opening the first semiconductor device 100, the increased first current continues to flow to the second semiconductor device 101, further pulling the voltage difference between the second emitter and the second base of the second semiconductor device 101, further opening the second semiconductor device 101, increasing the second current, so that the ESD positive pulse from position 104 is guided to position 105 through the first semiconductor device 100 and the second semiconductor device 101, in order to achieve the purpose of ESD release.
[0023] The performance of the ESD protection structure is low, that is, the triggering speed is slow when ESD occurs, which is not conducive to the release of ESD, and the reasons are as follows: (1) The trigger mechanism of the ESD protection structure depends on the electric field generated by the intrinsic breakdown of the LDMOS device in the active region, which triggers the conduction of the PNP transistor, but this process is not instantaneous, especially when the LDMOS is designed as a high-voltage device, the drift region is longer, and the electric field distribution is slower, the breakdown delay can be more than several nanoseconds.
[0024] (2) The PNP transistor of the ESD protection structure itself has a response lag to ESD, especially when the ESD is not too high, which leads to slow response of the PNP structure.
[0025] (3) The ESD protection structure is not sensitive to fast ESD pulses. The rising edge of ESD usually rises very fast, and the ESD protection structure does not conduct when the ESD voltage rises, so that the semiconductor device in the active region is damaged or destroyed by ESD, especially in RF or high-speed interfaces, which leads to signal distortion or gate breakdown.
[0026] In summary, the performance of the ESD protection structure is low.
[0027] To solve the technical problem, the embodiment of the present application provides a forming method of an ESD protection structure, comprising: providing a substrate; forming a drift region on the substrate; forming a first doped layer and a second doped layer in the drift region, the first doped layer and the second doped layer are different in doping type; forming a first body region and a second body region in the drift region, the first body region is located on a side of the first doped layer away from the second doped layer, and the second body region is located on a side of the second doped layer away from the first doped layer; forming a third doped layer, a fourth doped layer and a fifth doped layer in the first body region, the fourth doped layer is located between the third doped layer and the fifth doped layer, the fifth doped layer is close to the first doped layer, the third doped layer, the fourth doped layer and the fifth doped layer are staggered in doping type, and the fourth doped layer is different from the first doped layer in doping type; forming a sixth doped layer and a seventh doped layer in the second body region, the sixth doped layer is close to the second doped layer, the sixth doped layer and the seventh doped layer are the same in doping type, and the fourth doped layer is the same as the sixth doped layer in doping type; forming a first connecting line connecting the first doped layer and the sixth doped layer as an anode of the ESD protection structure; forming a second connecting line connecting the second doped layer, the third doped layer and the fourth doped layer as a cathode of the ESD protection structure; and forming a third connecting line connecting the fifth doped layer and the seventh doped layer.
[0028] By using the forming method, the sixth doped layer, the seventh doped layer and the second body region form a first semiconductor transistor of the ESD protection structure, the first doped layer, the drift region and the second body region form a second semiconductor transistor of the ESD protection structure, the fourth doped layer, the first body region and the drift region form a third semiconductor transistor of the ESD protection structure, the first doped layer and the sixth doped layer are connected by the first connecting line, the second doped layer, the third doped layer and the fourth doped layer are connected by the second connecting line, and the fifth doped layer and the seventh doped layer are connected by the third connecting line, so that the ESD protection structure improves the instantaneous discharge speed of ESD, and the performance of the ESD protection structure is improved.
[0029] To make the purpose, technical scheme and advantages of the embodiment of the present application clearer, the technical scheme of the embodiment of the present application will be described clearly and completely below with reference to the drawings in the embodiment of the present application. Obviously, the described embodiment is only a part of the embodiments of the present application, rather than all the embodiments. The following embodiments and features in the embodiments can be combined with each other without conflict.
[0030] Figures 2 to 6 The following is a structure diagram corresponding to each step in the forming method of the ESD protection structure of the first embodiment of the present application.
[0031] refer to Figure 2 Provides a base of 200.
[0032] The substrate 200 is used to provide a process platform for the formation of ESD protection structures.
[0033] In this embodiment, the material of the substrate 200 is intrinsic silicon, that is, pure, undoped single-crystal silicon.
[0034] Continue to refer to Figure 2 A drift region 201 is formed on the substrate 200.
[0035] The drift region 201 is used to provide a process basis for the formation of semiconductor devices in the ESD protection structure.
[0036] The types of drift regions 201 include: P-type drift regions and N-type drift regions. In this embodiment, the type of drift region 201 is an N-type drift region.
[0037] In this embodiment, the step of forming the drift region 201 includes: The drift is formed within the substrate 200 by, for example, phosphorus ion implantation using an ion implantation process and a mask.
[0038] The substrate 200 is subjected to an annealing process.
[0039] It should be noted that the type of ion used for N-type implantation can be selected according to actual needs; for example, group V elements can also be selected.
[0040] refer to Figure 3 A first groove 202a is formed in the drift region 201.
[0041] In this embodiment, during the step of forming the first groove 202a, a second groove 202b and a third groove 202c are also formed in the drift region 201. The second groove 202b is located on one side of the first groove 202a, and the third groove 202c is located on the other side of the first groove 202a. That is, in the same process step, the first groove 202a, the second groove 202b, and the third groove 202c are formed in the drift region 201.
[0042] The first groove 202a is used to provide a process basis for forming the first isolation layer 203a; the second groove 202b is used to provide a process basis for forming the second isolation layer 203b (e.g., Figure 4 (As shown) provides the process basis; the third groove 202c (as shown) Figure 4 As shown, this provides a process basis for forming the third isolation layer 203c.
[0043] In the embodiment, the step of forming the first groove 202a, the second groove 202b and the third groove 202c comprises: The first groove 202a, the second groove 202b and the third groove 202c are formed in the drift region 201 by using exposure, development, etching and other processes, the second groove 202b is located on one side of the first groove 202a, and the third groove 202c is located on the other side of the first groove 202a.
[0044] It should be noted that the first groove 202a is formed in the drift region 201 after the drift region 201 is formed, and before the first doped layer 206a and the second doped layer 206b are formed.
[0045] Referring to Figure 4 The first isolation layer 203a filling the first groove 202a is formed.
[0046] In the embodiment, the first isolation layer 203a filling the first groove 202a is formed, and the second isolation layer 203b filling the second groove 202b and the third isolation layer 203c filling the third groove 202c are also formed in the step of forming the first isolation layer 203a.
[0047] The first isolation layer 203a is used to provide electrical isolation for the first doped layer 206a and the second doped layer 206b, the second isolation layer 203b is used to provide electrical isolation for the first doped layer 206a and the first gate structure, and the third isolation layer 203c is used to provide electrical isolation for the second doped layer 206b and the second gate structure.
[0048] The material of the first isolation layer 203a comprises one or more of silicon oxide, silicon nitride and silicon oxynitride, the material of the second isolation layer 203b comprises one or more of silicon oxide, silicon nitride and silicon oxynitride, and the material of the third isolation layer 203c comprises one or more of silicon oxide, silicon nitride and silicon oxynitride. In the embodiment, the materials of the first isolation layer 203a, the second isolation layer 203b and the third isolation layer 203c are all silicon oxide.
[0049] In the embodiment, the step of forming the first isolation layer 203a, the second isolation layer 203b and the third isolation layer 203c comprises: A first isolation material layer (not shown) covering the substrate 200 is formed by using a chemical vapor deposition process. On the first isolation material layer, a first isolation layer 203a filling the first groove 202a, a second isolation layer 203b filling the second groove 202b and a third isolation layer 203c filling the third groove 202c are formed by using exposure, development, etching and other processes.
[0050] With reference to the above Figure 4 A first gate structure and a second gate structure are formed on the drift region 201.
[0051] In the embodiment, the first gate structure includes a first gate dielectric layer 204a, a first gate electrode 205a on the first gate dielectric layer 204a, and a first gate sidewall (not shown) covering the sidewall of the first gate electrode 205a; the second gate structure includes a second gate dielectric layer 204b, a second gate electrode 205b on the second gate dielectric layer 204b, and a second gate sidewall (not shown) covering the sidewall of the second gate electrode 205b.
[0052] In the embodiment, the materials of the first gate dielectric layer and the second gate dielectric layer are both silicon oxide, the materials of the first gate electrode 205a and the second gate electrode 205b are both tungsten, and the materials of the first gate sidewall and the second gate sidewall are both silicon oxide.
[0053] In the embodiment, the first gate structure is located on the side of the second isolation layer 203b away from the first isolation layer 203a, and the second gate structure is located on the side of the third isolation layer 203c away from the first isolation layer 203a.
[0054] In the embodiment, the first gate structure and the second gate structure are formed in the same process step. The main steps include: A gate dielectric material layer (not shown) is formed on the substrate 200 by using a chemical vapor deposition process. The first gate dielectric layer 204a and the second gate dielectric layer 204b on the drift region 201 are formed by using exposure, development, etching and other processes on the gate dielectric material layer.
[0055] A gate electrode material layer (not shown) is formed on the substrate 200 by using a physical vapor deposition process. The first gate electrode 205a on the first gate dielectric layer 204a and the second gate electrode 205b on the second gate dielectric layer 204b are formed by using exposure, development, etching and other processes on the gate electrode material layer.
[0056] A gate side wall material layer (not shown) is formed on the substrate 200 by a chemical vapor deposition process. The gate side wall material layer is subjected to exposure, development, etching and other processes to form a first gate side wall covering the first gate electrode 205a and a second gate side wall covering the second gate electrode 205b.
[0057] With continued reference to Figure 4 A first doped layer 206a and a second doped layer 206b are formed in the drift region 201.
[0058] The first doped layer 206a and the second doped layer 206b are of different types, i.e., the first doped layer 206a is P-type heavily doped and the second doped layer 206b is N-type heavily doped.
[0059] In this embodiment, the first doped layer 206a and the second doped layer 206b are formed in the drift region 201 by the following steps: P-type doped ions are implanted into the drift region 201 by an ion implantation process with mask shielding to form the first doped layer 206a in the drift region 201.
[0060] N-type doped ions are implanted into the drift region 201 by an ion implantation process with mask shielding to form the second doped layer 206b in the drift region 201.
[0061] The substrate 200 is subjected to an annealing process.
[0062] In this embodiment, the first doped layer 206a and the second doped layer 206b are located on both sides of the first isolation layer 203a; the first doped layer 206a is located between and in contact with the first isolation layer 203a and the second isolation layer 203b, and the second doped layer 206b is located between and in contact with the first isolation layer 203a and the third isolation layer 203c.
[0063] With continued reference to Figure 4 A first body region 207a and a second body region 207b are formed in the drift region 201.
[0064] The first body region 207a and the second body region 207b are of the same type, i.e., both are P-type doped.
[0065] In this embodiment, the step of forming the first body region 207a and the second body region 207b in the drift region 201 is performed in the same process step, which comprises: The P-type ions are implanted into the drift region 201 by an ion implantation process with a mask to form the first body region 207a and the second body region 207b in the drift region 201.
[0066] An annealing process is performed on the substrate 200.
[0067] In this embodiment, the first body region 207a is located on the side of the first doped layer 206a away from the second doped layer 206b, and the second body region 207b is located on the side of the second doped layer 206b away from the first doped layer 206a.
[0068] In this embodiment, a portion of the first body region 207a extends under the first gate structure so that the first gate structure spans the first body region 207a and the drift region 201, and a portion of the second body region 207b extends under the second gate structure so that the second gate structure spans the second body region 207b and the drift region 201.
[0069] Continuing to refer to Figure 4 A fourth recess 202d and a fifth recess 202e are formed in the first body region 207a, and a sixth recess 202f is formed in the second body region 207b.
[0070] The fourth recess 202d is used to provide a process basis for forming a fourth isolation layer 203d, the fifth recess 202e is used to provide a process basis for forming a fifth isolation layer 203e, and the sixth recess 202f is used to provide a process basis for forming a sixth isolation layer 203f.
[0071] In this embodiment, the step of forming the fourth recess 202d, the fifth recess 202e, and the sixth recess 202f comprises: The fourth recess 202d and the fifth recess 202e are formed in the first body region 207a, and the sixth recess 202f is formed in the second body region 207b by an exposure and development etching process and the like.
[0072] Continuing to refer to Figure 5 The fourth isolation layer 203d, the fifth isolation layer 203e, and the sixth isolation layer 203f are formed to fill the fourth recess 202d, the fifth recess 202e, and the sixth recess 202f, respectively.
[0073] The fourth isolation layer 203d is used for electrical isolation between the third doped layer 206c and the fourth doped layer 206d, the fifth isolation layer 203e is used for electrical isolation between the fourth doped layer 206d and the fifth doped layer 206e, and the sixth isolation layer 203f is used for electrical isolation between the sixth doped layer 206f and the seventh doped layer 206g.
[0074] The material of the fourth isolation layer 203d includes one or more of silicon oxide, silicon nitride and silicon oxynitride, the material of the fifth isolation layer 203e includes one or more of silicon oxide, silicon nitride and silicon oxynitride, and the material of the sixth isolation layer 203f includes one or more of silicon oxide, silicon nitride and silicon oxynitride. In this embodiment, the materials of the fourth isolation layer 203d, the fifth isolation layer 203e and the sixth isolation layer 203f are all silicon oxide.
[0075] In this embodiment, the steps of forming the first isolation layer 203a, the second isolation layer 203b and the third isolation layer 203c include: A second isolation material layer (not shown) covering the substrate 200 is formed by a chemical vapor deposition process. The second isolation material layer is processed by exposure, development, etching and the like to form the fourth isolation layer 203d filling the fourth groove 202d, the fifth isolation layer 203e filling the fifth groove 202e and the sixth isolation layer 203f filling the sixth groove 202f.
[0076] In this embodiment, the third doped layer 206c and the fourth doped layer 206d are located on both sides of the fourth isolation layer 203d, the fourth doped layer 206d and the fifth doped layer 206e are located on both sides of the fifth isolation layer 203e, and the sixth doped layer 206f and the seventh doped layer 206g are located on both sides of the sixth isolation layer 203f.
[0077] Reference Figure 5 The third doped layer 206c, the fourth doped layer 206d and the fifth doped layer 206e are formed in the first body region 207a and are isolated from each other, and the sixth doped layer 206f and the seventh doped layer 206g are formed in the second body region 207b and are isolated.
[0078] The type of the third doped layer 206c includes P-type and N-type, the type of the fourth doped layer 206d includes P-type and N-type, the type of the fifth doped layer 206e includes P-type and N-type, in the embodiment, the types of the third doped layer 206c and the fifth doped layer 206e are the same, both of which are P-type heavy doping, the types of the third doped layer 206c and the fourth doped layer 206d are different, the type of the fourth doped layer 206d is different from the type of the first doped layer 206a, and the type of the fourth doped layer 206d is N-type heavy doping.
[0079] The type of the sixth doped layer 206f includes P-type and N-type, the type of the seventh doped layer 206g includes P-type and N-type, the types of the sixth doped layer 206f and the seventh doped layer 206g are the same, and the type of the fourth doped layer 206d is the same as the type of the sixth doped layer 206f, in the embodiment, the types of the sixth doped layer 206f and the seventh doped layer 206g are both N-type heavy doping.
[0080] In the embodiment, the steps of forming the third doped layer 206c, the fourth doped layer 206d, the fifth doped layer 206e, the sixth doped layer 206f and the seventh doped layer 206g include: The ion implantation process and mask shielding are adopted to implant P-type doped ions in the first body region 207a to form the isolated third doped layer 206c and the fifth doped layer 206e in the first body region 207a.
[0081] The ion implantation process and mask shielding are adopted to implant N-type doped ions in the first body region 207a and the second body region 207b to form the isolated fourth doped layer 206d in the first body region 207a and the isolated sixth doped layer 206f and the seventh doped layer 206g in the second body region 207b.
[0082] The annealing process is performed on the substrate 200.
[0083] In the embodiment, the fourth doped layer 206d is located between the third doped layer 206c and the fifth doped layer 206e, the fifth doped layer 206e is close to the first doped layer 206a, and the types of the third doped layer 206c, the fourth doped layer 206d and the fifth doped layer 206e are staggered, and the sixth doped layer 206f is close to the second doped layer 206b.
[0084] Reference Figure 6, the first connecting line 208a connecting the first doped layer 206a and the sixth doped layer 206f, the second connecting line 208b connecting the second doped layer 206b, the third doped layer 206c and the fourth doped layer 206d, and the third connecting line 208c connecting the fifth doped layer 206e and the seventh doped layer 206g are formed.
[0085] The first connecting line 208a is used as an anode of the ESD protection structure, and the second connecting line 208b is used as a cathode of the ESD protection structure.
[0086] The material of the first connecting line 208a includes one or more of tungsten, copper, aluminum and molybdenum, the material of the second connecting line 208b includes one or more of tungsten, copper, aluminum and molybdenum, and the material of the third connecting line 208c includes one or more of tungsten, copper, aluminum and molybdenum. In this embodiment, the materials of the first connecting line 208a, the second connecting line 208b and the third connecting line 208c are tungsten.
[0087] A connecting material layer (not shown) is formed on the substrate 200 by a physical vapor deposition process. The connecting material layer is subjected to exposure, development and etching processes to form the first connecting line 208a connecting the first doped layer 206a and the sixth doped layer 206f, the second connecting line 208b connecting the second doped layer 206b, the third doped layer 206c and the fourth doped layer 206d, and the third connecting line 208c connecting the fifth doped layer 206e and the seventh doped layer 206g.
[0088] Reference Figures 7 to 9 is a structural schematic diagram of an ESD protection structure forming method of a second embodiment of the present application.
[0089] The Figures 7 to 9 and Figure 4 It can be seen that the main difference between the second embodiment and the first embodiment of the present application is the forming method of the first doped layer.
[0090] For the sake of simplicity, only the forming step of the first doped layer 300a is described in the ESD protection structure forming method of the second embodiment of the present application. The other steps of the ESD protection structure can be derived according to the ESD protection structure forming method of the first embodiment of the present application, and will not be described here.
[0091] Reference Figure 7 A seventh recess 202g is formed in the drift region 201, and an epitaxial layer (not shown) is formed in the seventh recess 202g. The first doped layer 300a is subjected to stress doping to increase the stress of the first doped layer 300a, thereby improving the performance of the ESD protection structure.
[0092] The stress-doped doping material includes one or more of germanium, silicon germanium, gallium arsenide, and indium gallium arsenide, and in this embodiment, the stress-doped doping material is silicon germanium.
[0093] In this embodiment, the seventh recess 202g is formed simultaneously in the step of forming the first recess 202a.
[0094] For the process of forming the seventh recess 202g, reference can be made to the related description in the foregoing embodiments.
[0095] Reference is made to Figure 8 The second isolation layer 203b and the third isolation layer 203c are formed in the second recess 202b and the third recess 202c, respectively.
[0096] For the process of forming the second isolation layer 203b and the third isolation layer 203c in the second recess 202b and the third recess 202c, respectively, reference can be made to the related description in the foregoing embodiments.
[0097] Reference is made to Figure 9 In the seventh recess 202g, an epitaxial layer (not shown) is formed. In this embodiment, the P-type heavy doping and the stress doping are performed simultaneously in the process of forming the epitaxial layer to form a first doping layer 300a.
[0098] An annealing process is performed on the substrate 200.
[0099] To solve the above problem, an ESD protection structure is provided in an embodiment of the present application, which comprises: a substrate; a drift region on the substrate; a first doping layer and a second doping layer isolated in the drift region; a first body region and a second body region in the drift region, the first body region being located on a side of the first doping layer away from the second doping layer, and the second body region being located on a side of the second doping layer away from the first doping layer; a third doping layer, a fourth doping layer and a fifth doping layer isolated from each other and located in the first body region, the fifth doping layer being located between the third doping layer and the fourth doping layer, and the fourth doping layer being close to the first doping layer; a sixth doping layer and a seventh doping layer isolated in the second body region, the sixth doping layer being close to the second doping layer; a first connecting line connecting the first doping layer and the sixth doping layer; a second connecting line connecting the second doping layer, the third doping layer and the fifth doping layer; a third connecting line connecting the fourth doping layer and the seventh doping layer.
[0100] Reference is made to Figure 5 The ESD protection structure comprises: a substrate 200.
[0101] For further information of the substrate 200, reference can be made to the relevant description in the foregoing embodiments.
[0102] With reference to Figure 5 The ESD protection structure comprises a drift region 201 located on the substrate 200.
[0103] For further information of the drift region 201, reference can be made to the relevant description in the foregoing embodiments.
[0104] With reference to Figure 5 The ESD protection structure comprises a first isolation layer 203a located in the drift region 201, a second isolation layer 203b and a third isolation layer 203c located in the drift region 201, a fourth isolation layer 203d and a fifth isolation layer 203e located in the first body region 207a, and a sixth isolation layer 203f located in the second body region 207b.
[0105] For further information of the first isolation layer 203a to the sixth isolation layer 203f, reference can be made to the relevant description in the foregoing embodiments.
[0106] With reference to Figure 5 The ESD protection structure comprises a first doped layer 206a and a second doped layer 206b located in the drift region 201.
[0107] In this embodiment, the first doped layer 206a and the second doped layer 206b are located on both sides of the isolation layer, the first doped layer 206a is located between and in contact with the first isolation layer 203a and the second isolation layer 203b, and the second doped layer 206b is located between and in contact with the first isolation layer 203a and the third isolation layer 203c.
[0108] For further information of the first doped layer 206a and the second doped layer 206b, reference can be made to the relevant description in the foregoing embodiments.
[0109] With reference to Figure 5 The ESD protection structure comprises a first body region 207a and a second body region 207b located in the drift region 201.
[0110] In this embodiment, the first body region 207a is located on the side of the first doped layer 206a away from the second doped layer 206b, and the second body region 207b is located on the side of the second doped layer 206b away from the first doped layer 206a.
[0111] Further information about the first body region 207a and the second body region 207b can be found in the foregoing embodiments.
[0112] With reference to Figure 5 , the ESD protection structure comprises: a third doped layer 206c, a fourth doped layer 206d and a fifth doped layer 206e which are isolated from each other and located in the first body region 207a; a sixth doped layer 206f and a seventh doped layer 206g which are isolated and located in the second body region 207b.
[0113] In this embodiment, the fourth doped layer 206d is located between the third doped layer 206c and the fifth doped layer 206e, and the fifth doped layer 206e is close to the first doped layer 206a; the sixth doped layer 206f is close to the second doped layer 206b; the third doped layer 206c and the fourth doped layer 206d are located on both sides of the fourth isolation layer 203d, the fourth doped layer 206d and the fifth doped layer 206e are located on both sides of the fifth isolation layer 203e, and the sixth doped layer 206f and the seventh doped layer 206g are located on both sides of the sixth isolation layer 203f.
[0114] Further information about the third doped layer 206c to the seventh doped layer 206g can be found in the foregoing embodiments.
[0115] With reference to Figure 5 , the ESD protection structure comprises: a first gate structure and a second gate structure located on the drift region 201.
[0116] In this embodiment, the first gate structure is located on the side of the second isolation layer 203b away from the first isolation layer 203a, and the second gate structure is located on the side of the third isolation layer 203c away from the first isolation layer 203a. Wherein, a part of the first body region 207a extends to below the first gate structure, so that the first gate structure spans the first body region 207a and the drift region 201, and a part of the second body region 207b extends to below the second gate structure, so that the second gate structure spans the second body region 207b and the drift region 201.
[0117] Further information about the first gate structure and the second gate structure can be found in the foregoing embodiments.
[0118] With reference to Figure 6The ESD protection structure comprises a first connecting line 208a connecting the first doped layer 206a and a sixth doped layer 206f; a second connecting line 208b connecting the second doped layer 206b, a third doped layer 206c and a fourth doped layer 206d; and a third connecting line 208c connecting the fifth doped layer 206e and a seventh doped layer 206g.
[0119] For more information about the first connecting line 208a, the second connecting line 208b and the third connecting line 208c, refer to the relevant description in the foregoing embodiments.
[0120] To solve the above problem, the embodiment of the present application provides a semiconductor device, which is manufactured by using a BCD process and any one of the foregoing ESD protection structures.
[0121] It should be noted that the BCD process is a process of integrating three different element manufacturing technologies on the same chip, and the three different elements include a bipolar transistor (Bipolar), a complementary metal oxide semiconductor (CMOS) and a double diffused metal oxide semiconductor (DMOS).
[0122] The Bipolar is abbreviated as B, the CMOS is abbreviated as C, and the DMOS is abbreviated as D, which are collectively referred to as BCD.
[0123] In the BCD process, source-drain doped layers and body regions of bipolar transistors, complementary metal oxide semiconductors and double diffused metal oxide semiconductors are formed.
[0124] In the embodiment, the second doped layer 206b, the fourth doped layer 206d and the seventh doped layer 206g in the ESD protection structure are formed by reusing the doping process of the source-drain doped layer in the BCD process; the mask of the second doped layer 206b, the fourth doped layer 206d and the seventh doped layer 206g in the ESD protection structure is formed by adjusting the pattern based on the mask of the source-drain doped layer in the BCD process, that is, the second doped layer 206b, the fourth doped layer 206d and the seventh doped layer 206g in the ESD protection structure and the source-drain doped layer in the BCD process use the same mask, and only the pattern of the second doped layer 206b, the fourth doped layer 206d and the seventh doped layer 206g in the ESD protection structure is added on the mask of the source-drain doped layer in the BCD process, and the second doped layer 206b, the fourth doped layer 206d and the seventh doped layer 206g in the ESD protection structure and the source-drain doped layer in the BCD process are formed by using the same doping process.
[0125] In the embodiment, the first body region 207a and the second body region 207b in the ESD protection structure are formed by reusing the forming process of the body region in the BCD process; the mask of the first body region 207a and the second body region 207b in the ESD protection structure is formed by adjusting the pattern based on the mask of the body region in the BCD process, that is, the first body region 207a and the second body region 207b in the ESD protection structure and the body region in the BCD process use the same mask, and only the pattern of the first body region 207a and the second body region 207b in the ESD protection structure is added on the mask of the body region in the BCD process, and the first body region 207a and the second body region 207b in the ESD protection structure and the body region in the BCD process are formed in the same process.
[0126] Reference Figure 10 , in combination Figure 5 , wherein Figure 10 is an ESD circuit structure schematic diagram of the ESD protection structure of the embodiment of the application.
[0127] Reference Figure 10 , the ESD circuit structure comprises: The first semiconductor transistor 400 comprises the sixth doped layer 206f as a collector region, the seventh doped layer 206g as an emitter region, and the second body region 207b as a base region; and the type of the first semiconductor transistor 400 is an NPN transistor.
[0128] The second semiconductor transistor 401 comprises the first doped layer 206a as an emitter region, the drift region 201 as a base region, and the second body region 207b as a collector region; and the type of the second semiconductor transistor 401 is a PNP transistor.
[0129] The third semiconductor transistor 402 includes: a fourth doped layer 206d as a collector region, a first body region 207a as a base region, and a drift region 201 as an emitter region; the third semiconductor transistor 402 is an NPN transistor.
[0130] The first resistor 404 has one end connected to the emitter region of the third semiconductor transistor 402 and the other end connected to the base region of the second semiconductor transistor 401.
[0131] The second resistor 405 has one end connected to the third doped layer 206c, the other end connected to the base region of the third semiconductor transistor 402, and also connected to the seventh doped layer 206g.
[0132] Will Figure 10 and Figure 1 As can be seen from the comparison, the ESD protection structure of this application embodiment adds the third semiconductor transistor 402, and forms a composite transistor by combining the second semiconductor transistor 401 and the third semiconductor transistor 402, replacing... Figure 1 The second semiconductor device 101 in the composite transistor has a larger current, which allows the first semiconductor transistor 400 to have a shorter charging time, speeds up the conduction process of the ESD protection structure, and reduces the trigger voltage, thereby improving the performance of the ESD protection structure.
[0133] It should be noted that the ESD protection structure is connected to the LDMOS device area and is also connected to the external grounding wire or electrostatic ring. This is used to transmit the ESD generated in the LDMOS device area to the external grounding wire or electrostatic ring through the ESD protection structure, so as to reduce the probability of the LDMOS device in the LDMOS device area being damaged or destroyed.
[0134] This invention also provides an electronic device, including any of the semiconductor devices described above; the electronic device includes, but is not limited to, mobile phones, computers, tablet computers, servers, cloud platforms, etc.
[0135] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.
Claims
1. A method for forming an ESD protection structure, characterized in that, include: Provide a base; A drift region is formed on the substrate; An isolated first doped layer and a second doped layer are formed within the drift region, the first doped layer and the second doped layer having different doping types; A first body region and a second body region are formed within the drift region, wherein the first body region is located on the side of the first doped layer away from the second doped layer, and the second body region is located on the side of the second doped layer away from the first doped layer; A third doped layer, a fourth doped layer, and a fifth doped layer are formed in the first body region, which are isolated from each other. The fourth doped layer is located between the third doped layer and the fifth doped layer, and the fifth doped layer is close to the first doped layer. The doping types of the third doped layer, the fourth doped layer, and the fifth doped layer are alternately arranged, and the doping type of the fourth doped layer is different from that of the first doped layer. An isolated sixth and seventh doped layer are formed within the second body region. The sixth doped layer is close to the second doped layer. The sixth and seventh doped layers have the same doping type, and the fourth doped layer has the same doping type as the sixth doped layer. A first connection line is formed connecting the first doped layer and the sixth doped layer, serving as the anode of the ESD protection structure; A second connection line is formed to connect the second doped layer, the third doped layer, and the fourth doped layer, serving as the cathode of the ESD protection structure; A third connection line is formed connecting the fifth doped layer and the seventh doped layer.
2. The forming method as described in claim 1, characterized in that, After the drift region is formed and before the first doped layer and the second doped layer are formed, a first groove is formed in the drift region; A first isolation layer is formed to fill the first groove, wherein the first doped layer and the second doped layer are located on both sides of the first isolation layer; In the step of forming the first groove, a second groove and a third groove are also formed in the drift region, the second groove being located on one side of the first groove and the third groove being located on the other side of the first groove; In the step of forming a first isolation layer that fills the first groove, a second isolation layer that fills the second groove is also formed, and a third isolation layer that fills the third groove is formed, wherein the first doped layer is located between and in contact with the first and second isolation layers, and the second doped layer is located between and in contact with the first and third isolation layers.
3. The forming method as described in claim 2, characterized in that, After the second isolation layer and the third isolation layer are formed, and before the first doped layer and the second doped layer are formed, a first gate structure and a second gate structure are formed on the drift region. The first gate structure is located on the side of the second isolation layer away from the first isolation layer, and the second gate structure is located on the side of the third isolation layer away from the first isolation layer. A portion of the first body region extends below the first gate structure, such that the first gate structure spans the first body region and the drift region; a portion of the second body region extends below the second gate structure, such that the second gate structure spans the second body region and the drift region.
4. The forming method as described in claim 3, characterized in that, The steps of forming the first gate structure and the second gate structure include: A first gate dielectric layer and a second gate dielectric layer are formed on the drift region; A first gate electrode is formed on the first gate dielectric layer, and a second gate electrode is formed on the second gate dielectric layer; A first gate sidewall is formed covering the first gate electrode, and a second gate sidewall is formed covering the second gate electrode.
5. The forming method as described in claim 1, characterized in that, After the first body region and the second body region are formed, and before the third doped layer, the fourth doped layer and the fifth doped layer that are isolated from each other are formed in the first body region, a fourth groove and a fifth groove are formed in the first body region, and a sixth groove is formed in the second body region. A fourth isolation layer, a fifth isolation layer, and a sixth isolation layer are formed to fill the fourth, fifth, and sixth grooves respectively. The third and fourth doped layers are located on both sides of the fourth isolation layer, the fourth and fifth doped layers are located on both sides of the fifth isolation layer, and the sixth and seventh doped layers are located on both sides of the sixth isolation layer.
6. The forming method as described in claim 2, characterized in that, Also includes: The method for forming the first doped layer further includes: in the step of forming the first groove, forming a seventh groove in the drift region, forming an epitaxial layer in the seventh groove, and stress doping the first doped layer to increase the stress of the first doped layer.
7. The forming method as described in claim 6, characterized in that, The stress-doped doping material includes one or more of germanium, silicon germanide, gallium arsenide, and indium gallium arsenide.
8. An ESD protection structure, characterized in that, include: Base; The drift region is located on the substrate; A first doped layer and a second doped layer isolated within the drift region; The first body region and the second body region are located within the drift region. The first body region is located on the side of the first doped layer away from the second doped layer, and the second body region is located on the side of the second doped layer away from the first doped layer. The third, fourth, and fifth doped layers are isolated from each other and located within the first body region. The fourth doped layer is located between the third and fifth doped layers, and the fifth doped layer is close to the first doped layer. A sixth doped layer and a seventh doped layer are isolated within the second body region, with the sixth doped layer being close to the second doped layer; The first connecting line connects the first doped layer and the sixth doped layer; The second connecting line connects the second doped layer, the third doped layer, and the fifth doped layer; The third connecting line connects the fifth doped layer and the seventh doped layer.
9. The ESD protection structure as described in claim 8, characterized in that, Also includes: A first isolation layer is located within the drift region, and a first doped layer and a second doped layer are located on both sides of the isolation layer; The second and third isolation layers are located within the drift region, the first doped layer is located between and in contact with the first and second isolation layers, and the second doped layer is located between and in contact with the first and third isolation layers; The fourth and fifth isolation layers are located within the first body region; The sixth isolation layer is located within the second body region, the third doped layer and the fourth doped layer are located on both sides of the fourth isolation layer, the fourth doped layer and the fifth doped layer are located on both sides of the fifth isolation layer, and the sixth doped layer and the seventh doped layer are located on both sides of the sixth isolation layer; A first gate structure and a second gate structure are located on the drift region, wherein the first gate structure is located on the side of the second isolation layer away from the first isolation layer, and the second gate structure is located on the side of the third isolation layer away from the first isolation layer; A portion of the first body region extends below the first gate structure, such that the first gate structure spans the first body region and the drift region; a portion of the second body region extends below the second gate structure, such that the second gate structure spans the second body region and the drift region.
10. A semiconductor device, characterized in that, It is manufactured using BCD technology and includes the ESD protection structure as described in claim 8 or 9; The second, fourth, and seventh doped layers in the ESD protection structure are formed by reusing the doping process of the source and drain doped layers in the BCD process. The masks for the second, fourth, and seventh doped layers in the ESD protection structure are formed by adjusting the pattern based on the source / drain doped layer mask in the BCD process. The first body region and the second body region in the ESD protection structure are formed by reusing the body region formation process in the BCD process. The masks for the first and second body regions in the ESD protection structure are formed by adjusting the pattern based on the mask for the body region in the BCD process.