Gallium oxide epitaxial wafers and their preparation methods, solar-blind ultraviolet photodetectors

Abstract

This application relates to a gallium oxide epitaxial wafer and its fabrication method, and a solar-blind ultraviolet photodetector, comprising: providing a growth substrate; continuously supplying an aluminum source and a nitrogen source, and alternately supplying and interrupting a silicon source to alternately grow a silicon-doped first aluminum nitride layer and an undoped second aluminum nitride layer, thereby directly epitaxially growing an aluminum nitride buffer layer on the growth substrate; wherein the thickness of the aluminum nitride buffer layer ranges from 20 nm to 100 nm; and directly epitaxially growing a gallium oxide layer on the aluminum nitride buffer layer. Therefore, while reducing the lattice mismatch between the growth substrate and the gallium oxide layer, controllable stress modulation can be achieved, improving the crystal quality of the gallium oxide layer.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a gallium oxide epitaxial wafer, a preparation method thereof and a solar blind ultraviolet photodetector. BACKGROUND

[0002] Gallium oxide (Ga2O3) has the advantages of super-wide band gap width (about 4.8eV~4.9eV), high breakdown field strength (about 8MV / cm) and higher Baliga figure of merit, and shows significant advantages in the fields of power electronic devices and ultraviolet optoelectronic devices. Moreover, the high voltage resistance and low power consumption characteristics of gallium oxide make it suitable for the preparation of high-temperature, high-frequency and high-power power electronic devices. Among many gallium oxide devices, the solar blind ultraviolet photodetector has the advantages of strong anti-interference ability, high sensitivity and low background noise, and has wide and important application prospects in the fields of environmental monitoring, solar blind imaging, flame detection, missile early warning and safety communication, biomedical applications, etc.

[0003] At present, the main problem restricting the development of gallium oxide devices is the preparation technology of gallium oxide material and the crystal quality of gallium oxide material. Especially for heteroepitaxial growth, lattice mismatch and thermal mismatch will lead to high defect density and poor crystal quality of epitaxially grown gallium oxide. For example, directly epitaxially growing gallium oxide on a silicon substrate, the lattice mismatch degree between silicon and gallium oxide reaches about 24%, and the thermal mismatch degree is as high as about 209%.

[0004] Therefore, how to improve the crystal quality of gallium oxide has become a problem to be solved in the field. SUMMARY

[0005] Therefore, the embodiments of the present application provide a gallium oxide epitaxial wafer, a preparation method thereof and a solar blind ultraviolet photodetector to solve at least one problem in the background art.

[0006] In a first aspect, the embodiments of the present application provide a preparation method of a gallium oxide epitaxial wafer, which comprises:

[0007] providing a growth substrate;

[0008] continuously introducing an aluminum source and a nitrogen source, and alternately introducing and interrupting a silicon source to alternately grow a first silicon-doped aluminum nitride layer and a second non-doped aluminum nitride layer, so as to directly epitaxially grow an aluminum nitride buffer layer on the growth substrate; wherein the thickness of the aluminum nitride buffer layer ranges from 20nm to 100nm;

[0009] directly epitaxially growing a gallium oxide layer on the aluminum nitride buffer layer.

[0010] In conjunction with the first aspect of this application, in an optional embodiment, the duration of a single silicon source supply is greater than the duration of a single silicon source interruption, and less than or equal to twice the duration of a single silicon source interruption.

[0011] In conjunction with the first aspect of this application, in an optional embodiment, the thickness of the first aluminum nitride layer ranges from 2 nm to 5 nm; and the thickness of the second aluminum nitride layer ranges from 1 nm to 3 nm.

[0012] In conjunction with the first aspect of this application, in an optional embodiment, the silicon content in the first aluminum nitride layer ranges from 2% to 10%; and / or,

[0013] In the first aluminum nitride layer, the silicon doping concentration is less than or equal to 9E17cm⁻¹. -3 .

[0014] In conjunction with a first aspect of this application, in an alternative embodiment, the growth temperature remains constant during the alternating growth of a silicon-doped first aluminum nitride layer and an undoped second aluminum nitride layer.

[0015] Secondly, embodiments of this application provide a gallium oxide epitaxial wafer, comprising:

[0016] Growth substrate;

[0017] An aluminum nitride buffer layer is epitaxially grown on the growth substrate and in direct contact with the growth substrate. The aluminum nitride buffer layer includes alternating layers of first aluminum nitride and second aluminum nitride. The first aluminum nitride layer is doped with silicon, and the second aluminum nitride layer is not doped with silicon. The thickness of the aluminum nitride buffer layer ranges from 20 nm to 100 nm.

[0018] A gallium oxide layer is epitaxially grown on the aluminum nitride buffer layer and is in direct contact with the aluminum nitride buffer layer.

[0019] In conjunction with a second aspect of this application, in an optional embodiment, the thickness of the first aluminum nitride layer is greater than the thickness of the second aluminum nitride layer, and less than or equal to twice the thickness of the second aluminum nitride layer.

[0020] In conjunction with the second aspect of this application, in an optional embodiment, the thickness of the first aluminum nitride layer ranges from 2 nm to 5 nm; and the thickness of the second aluminum nitride layer ranges from 1 nm to 3 nm.

[0021] In conjunction with a second aspect of this application, in an optional embodiment, the silicon content in the first aluminum nitride layer ranges from 2% to 10%; and / or,

[0022] In the first aluminum nitride layer, the silicon doping concentration is less than or equal to 9E17cm⁻¹. -3.

[0023] Thirdly, embodiments of this application provide a solar-blind ultraviolet photodetector, comprising a gallium oxide epitaxial wafer prepared by the method for preparing gallium oxide epitaxial wafers as described in any one of the first aspects; or a gallium oxide epitaxial wafer as described in any one of the second aspects.

[0024] The gallium oxide epitaxial wafer and its fabrication method, as well as the solar-blind ultraviolet photodetector provided in this application, alleviate lattice and thermal mismatches between the growth substrate and the gallium oxide layer by introducing an aluminum nitride buffer layer between them. The aluminum nitride buffer layer is directly epitaxially grown on the growth substrate, and the gallium oxide layer is directly epitaxially grown on the aluminum nitride buffer layer, avoiding interference from other structural layers. Alternating silicon-doped first aluminum nitride layers and undoped second aluminum nitride layers release stress layer by layer during epitaxial growth through periodic silicon doping, preventing stress concentration or accumulation from adversely affecting the gallium oxide layer. This also avoids excessive silicon doping damaging the crystal quality of the aluminum nitride buffer layer and degrading its buffering effect. The thickness of the aluminum nitride buffer layer is controlled within the nanometer range of 20nm to 100nm, ensuring sufficient thickness for stress release and lattice transition, while avoiding excessive thickness that could reduce production efficiency, increase costs, or introduce additional defects. Therefore, the crystal quality of the gallium oxide layer is improved.

[0025] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0026] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0027] Figure 1 This is a schematic flowchart illustrating the method for preparing gallium oxide epitaxial wafers according to embodiments of this application.

[0028] Figure 2 This is a schematic cross-sectional view of a gallium oxide epitaxial wafer provided in an embodiment of this application.

[0029] Figure 3 This is a schematic diagram showing the introduction of aluminum, nitrogen, and silicon sources during the epitaxial growth of an aluminum nitride buffer layer.

[0030] Figure 4 This is a SEM image of the gallium oxide layer in the related technology;

[0031] Figure 5 This is a SEM image of the gallium oxide layer in the embodiments of this application;

[0032] Figure 6 AFM image of gallium oxide layer in related technologies;

[0033] Figure 7 This is an AFM image of the gallium oxide layer in an embodiment of this application.

[0034] Explanation of reference numerals in the attached figures:

[0035] 100, Growth substrate; 200, Aluminum nitride buffer layer; 210, First aluminum nitride layer; 220, Second aluminum nitride layer; 300, Gallium oxide layer. Detailed Implementation

[0036] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the disclosure of the present application to those skilled in the art.

[0037] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0038] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0039] When an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. Although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0040] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship of one element or feature shown in the figure to other elements or features. In addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0041] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0042] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0043] This application provides a method for preparing gallium oxide epitaxial wafers. Please refer to the following embodiments. Figure 1 The preparation methods include:

[0044] Step S1: Provide a growth substrate;

[0045] Step S2: Continuously supply aluminum and nitrogen sources, and alternately supply and interrupt silicon sources to alternately grow silicon-doped first aluminum nitride layer and undoped second aluminum nitride layer, so as to directly epitaxially grow aluminum nitride buffer layer on growth substrate; wherein, the thickness of aluminum nitride buffer layer is in the range of 20nm~100nm.

[0046] Step S3: Directly epitaxially grow a gallium oxide layer on the aluminum nitride buffer layer.

[0047] An aluminum nitride (Anitride) buffer layer mitigates lattice and thermal mismatches between the growth substrate and the gallium oxide (GaO) layer. The Anitride buffer layer is directly epitaxially grown on the growth substrate, and the GaO layer is directly epitaxially grown on top of the Anitride buffer layer, avoiding interference from other structural layers with the transition buffering effect of the Anitride buffer layer. Alternating silicon-doped first Anitride layers and undoped second Anitride layers, through periodic silicon doping, releases stress layer by layer during epitaxial growth, preventing stress concentration or accumulation from adversely affecting the GaO layer. Simultaneously, excessive silicon doping avoids damaging the crystal quality of the Anitride buffer layer, thus degrading its transition buffering effect. The thickness of the Anitride buffer layer is controlled within the nanometer range of 20nm to 100nm, ensuring sufficient thickness for stress release and lattice transition, while avoiding excessive thickness that could lead to reduced production efficiency, increased costs, or the introduction of additional defects. This improves the crystal quality of the GaO layer.

[0048] First, step S1 is performed, providing a growth substrate 100.

[0049] In the embodiments of this application, the growth substrate 100 can be any suitable substrate, such as a sapphire substrate, a silicon substrate, a silicon carbide substrate, or a composite substrate made of semiconductor materials.

[0050] Next, please refer to Figure 2 In step S2, aluminum and nitrogen sources are continuously supplied, and silicon sources are alternately supplied and interrupted to alternately grow silicon-doped first aluminum nitride layer 210 and undoped second aluminum nitride layer 220, so as to directly epitaxially grow aluminum nitride buffer layer 200 on growth substrate 100; wherein the thickness of aluminum nitride buffer layer 200 is in the range of 20nm~100nm.

[0051] In some related technologies, an aluminum nitride buffer layer 200 is introduced between the growth substrate 100 and the gallium oxide layer 300 to alleviate the lattice mismatch. However, a large amount of stress accumulates during the epitaxial growth process. This stress is transmitted to the gallium oxide layer 300, forming dislocations and even inducing cracks, thus reducing the crystal quality of the gallium oxide layer 300. In this embodiment, silicon doping is performed during the growth of the aluminum nitride buffer layer 200 to achieve stress release. Specifically, stress is released layer by layer through periodic doping, avoiding stress concentration or accumulation that could adversely affect the gallium oxide layer 300. Simultaneously, excessive doping is avoided to prevent damage to the crystal quality of the aluminum nitride buffer layer 200, thus affecting its effectiveness in alleviating lattice mismatch.

[0052] Understandably, the aluminum nitride buffer layer 200 serves as a transition buffer structure between the growth substrate 100 and the gallium oxide layer 300. Its thickness can achieve the function on the nanometer scale. If the thickness is set on the micrometer scale, the excessive thickness will affect production efficiency and cost, and may even introduce additional defects. Based on this, the thickness of the aluminum nitride buffer layer 200 is set in the range of 20nm to 100nm to ensure that the aluminum nitride buffer layer 200 has sufficient thickness to achieve stress release and lattice transition.

[0053] Furthermore, the thickness of the aluminum nitride buffer layer 200 ranges from 30 nm to 66 nm. Setting the thickness of the aluminum nitride buffer layer 200 within this range allows for a better balance between its functionality and practical production.

[0054] In the actual preparation process, please refer to Figure 3 An aluminum and nitrogen source are continuously supplied, while a silicon source is alternately supplied and interrupted. When the silicon source is supplied, a silicon-doped first aluminum nitride layer 210 is grown; when the silicon source is interrupted, an undoped second aluminum nitride layer 220 is grown. In some embodiments, the duration of a single silicon source supply is greater than the duration of a single silicon source interruption, but less than or equal to twice the duration of a single silicon source interruption. Therefore, the thickness of the first aluminum nitride layer 210 is greater than the thickness of the second aluminum nitride layer 220, but less than or equal to twice the thickness of the second aluminum nitride layer 220. This ensures that the first aluminum nitride layer 210, which has a stress-relieving function, dominates in each "doped-undoped" cycle, effectively relaxing the stress accumulated during aluminum nitride growth while preventing lattice distortion caused by excessive silicon doping and avoiding degradation of the transition buffer function of the aluminum nitride buffer layer 200. This allows for a better balance between stress relief and lattice transition.

[0055] In this embodiment, trimethylaluminum (TMAl) is used as the aluminum source, ammonia (NH3) as the nitrogen source, silane (SiH4) as the silicon source, and high-purity argon (Ar) as the carrier gas. In actual preparation, the growth pressure is controlled within the range of 50 mbar to 100 mbar, the NH3 flow rate is within the range of 0.5 slm to 2 slm, the TMAl flow rate is within the range of 50 sccm to 300 sccm, and the SiH4 flow rate is within the range of 5 sccm to 20 sccm. SiH4 is introduced intermittently, with each introduction lasting 5 to 50 seconds.

[0056] In some embodiments, the thickness of the first aluminum nitride layer 210 ranges from 2 nm to 5 nm; the thickness of the second aluminum nitride layer 220 ranges from 1 nm to 3 nm. Setting the thickness of the silicon-doped first aluminum nitride layer 210 within this range ensures effective stress release; the undoped second aluminum nitride layer 220 has better crystal quality, providing a better growth interface for the next first aluminum nitride layer 210 and avoiding lattice quality degradation that may be caused by continuous doping. Setting its thickness in the range of 1 nm to 3 nm ensures that the second aluminum nitride layer 220 can more effectively repair lattice defects caused by the first aluminum nitride layer 210.

[0057] In some embodiments, the silicon content in the first aluminum nitride layer 210 ranges from 2% to 10%. Limiting the silicon content within this range effectively balances the stress relief effect and the crystal quality of the aluminum nitride buffer layer 200. Further, the silicon content in the first aluminum nitride layer 210 ranges from 3% to 5%.

[0058] In some embodiments, the silicon doping concentration in the first aluminum nitride layer 210 is less than or equal to 9E17cm⁻¹. -3 This avoids excessive silicon doping, which could affect the crystal quality of the aluminum nitride buffer layer 200.

[0059] In some embodiments, within a single growth cycle, a silicon source is first introduced and then interrupted. This causes the first aluminum nitride layer 210 to be located on the side of the second aluminum nitride layer 220 facing the growth substrate 100. Understandably, there is a certain lattice mismatch between the growth substrate 100 and the aluminum nitride; growing the first aluminum nitride layer 210 first can effectively reduce stress and decrease defects and dislocations. Understandably, the growth cycle here refers to one alternation between introducing and interrupting the silicon source; in a single growth cycle, one first aluminum nitride layer 210 and one second aluminum nitride layer 220 are grown.

[0060] In some embodiments, the growth temperature remains constant during the alternating growth of the silicon-doped first aluminum nitride layer 210 and the undoped second aluminum nitride layer 220. Isothermal growth ensures that the aluminum nitride buffer layer 200 is epitaxially grown layer by layer under a consistent thermodynamic environment, avoiding additional thermal stress introduced by temperature cycling.

[0061] Optionally, the growth temperature range is 950℃ to 1050℃. Within this temperature range, sufficient migration ability of aluminum, nitrogen, and silicon atoms is ensured on the growth surface, allowing them to arrange themselves in an orderly manner to form a well-crystallized aluminum nitride lattice, while avoiding the negative effects of excessive heat. Further, the growth temperature is 1000℃.

[0062] In some embodiments, the preparation method may further include performing an annealing process. The annealing process improves the crystal quality of the aluminum nitride buffer layer 200. Specifically, high-purity hydrogen (H2) is used as the annealing gas, the hydrogen flow rate is in the range of 100 slm, and the annealing is carried out at an annealing temperature of 1000°C to 1400°C for 10 min to 30 min.

[0063] Finally, step S3 is performed to directly epitaxially grow a gallium oxide layer 300 on the aluminum nitride buffer layer 200.

[0064] In this embodiment, high-purity oxygen (O2) is used as the oxygen source, triethylgallium (TEGa) or trimethylgallium (TMGa) as the gallium source, and high-purity argon (Ar) as the carrier gas. In actual preparation, the growth pressure is controlled within the range of 50 mbar to 100 mbar, the flow rate of TMGa is controlled within the range of 50 sccm to 500 sccm, the flow rate of O2 is controlled within the range of 50 sccm to 100 sccm, and a gallium oxide layer 300 with a thickness of 500 nm to 2500 nm is grown at a growth temperature of 800 °C to 1200 °C.

[0065] This application also provides a gallium oxide epitaxial wafer; please refer to [reference needed]. Figure 2 Gallium oxide epitaxial wafers include:

[0066] Growth substrate 100;

[0067] An aluminum nitride buffer layer 200 is epitaxially grown on and in direct contact with a growth substrate 100. The aluminum nitride buffer layer 200 includes alternating layers of a first aluminum nitride layer 210 and a second aluminum nitride layer 220. The first aluminum nitride layer 210 is doped with silicon, and the second aluminum nitride layer 220 is not doped with silicon. The thickness of the aluminum nitride buffer layer 200 ranges from 20 nm to 100 nm.

[0068] The gallium oxide layer 300 is epitaxially grown on the aluminum nitride buffer layer 200 and is in direct contact with the aluminum nitride buffer layer 200.

[0069] In some embodiments, the thickness of the first aluminum nitride layer 210 is greater than the thickness of the second aluminum nitride layer 220, and less than or equal to twice the thickness of the second aluminum nitride layer 220.

[0070] In some embodiments, the thickness of the first aluminum nitride layer 210 ranges from 2 nm to 5 nm; the thickness of the second aluminum nitride layer 220 ranges from 1 nm to 3 nm.

[0071] In some embodiments, the silicon content in the first aluminum nitride layer 210 ranges from 2% to 10%; and / or, the silicon doping concentration in the first aluminum nitride layer 210 is less than or equal to 9E17cm⁻¹. -3 .

[0072] refer to Figure 4 and Figure 5 As can be seen from the scanning electron microscope (SEM) images obtained by cathodoluminescence (CL) testing, the defect density of the gallium oxide layer 300 in this embodiment is significantly lower than the curve density of the gallium oxide layer 300 in related technologies. (Reference) Figure 6 and Figure 7 As can be seen from the atomic force microscope (AFM) images, the roughness of the gallium oxide layer 300 in this embodiment is significantly lower than that of the gallium oxide layer 300 in related technologies. Specifically, the surface roughness of the gallium oxide layer 300 in this embodiment is 1.97 nm, while the surface roughness of the gallium oxide layer 300 in related technologies reaches 8.52 nm. Therefore, the crystal quality of the gallium oxide layer 300 in this embodiment is effectively improved.

[0073] Correspondingly, this application also provides a solar-blind ultraviolet photodetector, comprising a gallium oxide epitaxial wafer prepared using the method described in the above embodiments; or, a gallium oxide epitaxial wafer as described in the above embodiments. By improving the crystal quality of the gallium oxide layer 300, the performance of the solar-blind ultraviolet photodetector is further improved.

[0074] The solar-blind ultraviolet photodetector also includes electrodes located on the gallium oxide layer 300. In some examples, the electrodes can be a Ti / Au composite metal thin film structure.

[0075] The technical solution of this application will be further described below with reference to several embodiments and comparative examples.

[0076] Example 1

[0077] Provide sapphire substrates;

[0078] An aluminum source (TMAl) and a nitrogen source (NH3) are continuously introduced, while a silicon source (SiH4) is alternately introduced and interrupted to grow a silicon-doped first aluminum nitride layer and an undoped second aluminum nitride layer, forming an aluminum nitride buffer layer. The growth temperature is maintained at 1000℃, the growth pressure at 50 mbar, the NH3 flow rate at 2 slm, the TMAl flow rate at 200 sccm, the SiH4 implantation flow rate at 15 sccm, the SiH4 introduction time at 30 s, and the SiH4 interruption time at 15 s, to grow a doping concentration of 5E17 cm⁻¹. -3 And a first aluminum nitride layer with a thickness of 4nm and a second aluminum nitride layer with a thickness of 2nm; after 10 cycles, a 60nm aluminum nitride buffer layer is formed;

[0079] Hydrogen gas (H2) is introduced to perform the annealing process. The annealing temperature is 1200℃, the H2 flow rate is 100slm, and the time is 15min.

[0080] Gallium oxide layers were grown by introducing gallium source (TEGa) and oxygen source (O2) at a growth temperature of 1000℃ and a growth pressure of 50mbar. The flow rate of TEGa was 200sccm and the flow rate of O2 was 100sccm, resulting in a gallium oxide layer with a thickness of 1000nm.

[0081] A solar-blind ultraviolet photodetector is formed by depositing Ti / Au / Ti / Au electrodes on a gallium oxide layer.

[0082] Example 2

[0083] Unlike Example 1, the aluminum nitride buffer layer has a thickness of 30 nm.

[0084] Example 3

[0085] Unlike Example 1, the aluminum nitride buffer layer has a thickness of 66 nm.

[0086] Example 4

[0087] Unlike Example 1, the aluminum nitride buffer layer has a thickness of 90 nm.

[0088] Example 5

[0089] Unlike Example 1, the doping concentration of the first aluminum nitride layer is 1E17cm. -3 .

[0090] Comparative Example 1

[0091] Unlike Example 1, the aluminum nitride buffer layer has a thickness of 12 nm.

[0092] Comparative Example 2

[0093] Unlike Example 1, the aluminum nitride buffer layer has a thickness of 18 nm.

[0094] Comparative Example 3

[0095] Unlike Example 1, the thickness of the aluminum nitride buffer layer is 108 nm.

[0096] Comparative Example 4

[0097] Unlike Example 1, the SiH4 was introduced for 15 seconds, and the thickness of the first aluminum nitride layer was 2 nm.

[0098] Comparative Example 5

[0099] Unlike Example 1, the doping concentration of the first aluminum nitride layer is 2E18cm⁻¹. -3 .

[0100] Understandably, the crystal quality of the gallium oxide layer directly affects the dark current of a solar-blind ultraviolet photodetector. Dark current refers to the minute current existing inside the device under conditions of no light illumination, mainly caused by thermally excited charge carriers and material defects (such as dislocations and point defects) acting as recombination centers or tunneling channels. When the crystal quality of the gallium oxide layer is high and the defect density is low, the number of defect centers inside the material available for non-radiative recombination or tunneling of charge carriers is significantly reduced, thereby significantly suppressing the generation of dark current. Lower dark current means higher sensitivity and better detectivity of the solar-blind ultraviolet photodetector in practical applications. Correspondingly, the lower the dark current, the better the crystal quality of the gallium oxide layer.

[0101] Dark current tests were performed on the solar-blind ultraviolet photodetectors fabricated in the above embodiments and comparative examples, and the results are shown in Table 1.

[0102]

[0103] In conjunction with Examples 1 to 4 and Comparative Examples 1 to 3, as the thickness of the aluminum nitride buffer layer increased from 12 nm to 108 nm, the dark current increased from 6.51 × 10⁻⁶. -11 The relatively large value of A gradually decreased to 1.56 × 10 -13 The minimum value of A is gradually increased to 1.93 × 10. -10 This maximum value (A) indicates that within the aluminum nitride buffer layer thickness range of 20nm to 100nm, the dark current first decreases and then increases with increasing thickness, reaching a minimum in the 30nm to 66nm range, where device performance is optimal. Furthermore, controlling the aluminum nitride buffer layer thickness within the 20nm to 100nm range ensures a dark current below 10... -10 A; Furthermore, controlling the thickness within the range of 30nm~66nm can ensure a dark current of 10. -13With the improvement in device performance by orders of magnitude, the crystal quality of the gallium oxide layer is correspondingly improved.

[0104] Combining Example 1 and Comparative Example 4, the SiH4 introduction time was reduced from 30s to 15s, causing the ratio of the SiH4 introduction time to the SiH4 interruption time (or the ratio of the thickness of the first aluminum nitride layer to the thickness of the second aluminum nitride layer) to decrease from 2:1 to 1:1, and the dark current to decrease from 1.56×10 -13 A rose to 6.13×10 -12 A. Device performance degrades, and the crystal quality of the gallium oxide layer decreases. It is evident that setting the ratio of the time SiH4 is introduced to the time SiH4 is interrupted (or the ratio of the thickness of the first aluminum nitride layer to the thickness of the second aluminum nitride layer) to be greater than 1:1 can effectively improve the crystal quality of the gallium oxide layer.

[0105] Combining Examples 1, 5, and Comparative Example 5, when the doping concentration of the first aluminum nitride layer is 1E17cm -3 At that time, the dark current was 1.17 × 10⁻⁶. -12 A, when the doping concentration of the first aluminum nitride layer is 5E17cm -3 At that time, the dark current was 1.56 × 10⁻⁶. -13 A, all below 10 -10 A. The device performance is good, and the crystal quality of the gallium oxide layer is high. Furthermore, when the doping concentration of the first aluminum nitride layer is 2E18cm⁻¹ -3 At that time, the dark current was 5.81 × 10⁻⁶. -10 A, greater than 10 -10 A. It can be seen that controlling the doping concentration of the first aluminum nitride layer to be less than or equal to 9E17cm -3 This can effectively improve the crystal quality of gallium oxide layers.

[0106] It should be noted that the gallium oxide epitaxial wafer embodiments provided in this application and the gallium oxide epitaxial wafer preparation method embodiments belong to the same concept; the technical features in the technical solutions described in each embodiment can be arbitrarily combined without conflict. However, it should be further noted that the combination of technical features of the gallium oxide epitaxial wafer provided in the embodiments of this application can already solve the technical problems to be solved by this application; therefore, the gallium oxide epitaxial wafer provided in the embodiments of this application is not limited to the gallium oxide epitaxial wafer preparation method provided in the embodiments of this application, and any gallium oxide epitaxial wafer that can form the gallium oxide epitaxial wafer preparation method provided in the embodiments of this application is within the scope of protection of this application.

[0107] It should be understood that the above embodiments are exemplary and not intended to encompass all possible implementations. Various modifications and changes can be made to the above embodiments without departing from the scope of this disclosure. Similarly, the various technical features of the above embodiments can be arbitrarily combined to form other embodiments of this application that may not be explicitly described. Therefore, the above embodiments only illustrate several implementations of this application and do not limit the scope of protection of this patent application.

Claims

1. A method for preparing a gallium oxide epitaxial wafer, characterized in that, The method includes: Provide growth substrate; An aluminum source and a nitrogen source are continuously supplied, and a silicon source is alternately supplied and interrupted to alternately grow a silicon-doped first aluminum nitride layer and an undoped second aluminum nitride layer, so as to directly epitaxially grow an aluminum nitride buffer layer on the growth substrate; wherein the thickness of the aluminum nitride buffer layer is in the range of 20nm~100nm. A gallium oxide layer is directly epitaxially grown on the aluminum nitride buffer layer.

2. The method for preparing gallium oxide epitaxial wafers according to claim 1, characterized in that, The duration of a single silicon source supply is greater than the duration of a single silicon source interruption, and less than or equal to twice the duration of a single silicon source interruption.

3. The method for preparing gallium oxide epitaxial wafers according to claim 1 or 2, characterized in that, The thickness of the first aluminum nitride layer ranges from 2 nm to 5 nm; The thickness of the second aluminum nitride layer ranges from 1 nm to 3 nm.

4. The method for preparing gallium oxide epitaxial wafers according to claim 1, characterized in that, In the first aluminum nitride layer, the silicon content ranges from 2% to 10%; and / or, In the first aluminum nitride layer, the silicon doping concentration is less than or equal to 9E17cm⁻¹. -3 .

5. The method for preparing gallium oxide epitaxial wafers according to claim 1, characterized in that, During the alternating growth of the silicon-doped first aluminum nitride layer and the undoped second aluminum nitride layer, the growth temperature remains constant.

6. A gallium oxide epitaxial wafer, characterized in that, include: Growth substrate; An aluminum nitride buffer layer is epitaxially grown on the growth substrate and in direct contact with the growth substrate. The aluminum nitride buffer layer includes alternating layers of first aluminum nitride and second aluminum nitride. The first aluminum nitride layer is doped with silicon, and the second aluminum nitride layer is not doped with silicon. The thickness of the aluminum nitride buffer layer ranges from 20 nm to 100 nm. A gallium oxide layer is epitaxially grown on the aluminum nitride buffer layer and is in direct contact with the aluminum nitride buffer layer.

7. The gallium oxide epitaxial wafer according to claim 6, characterized in that, The thickness of the first aluminum nitride layer is greater than the thickness of the second aluminum nitride layer, and less than or equal to twice the thickness of the second aluminum nitride layer.

8. The gallium oxide epitaxial wafer according to claim 6 or 7, characterized in that, The thickness of the first aluminum nitride layer ranges from 2 nm to 5 nm; The thickness of the second aluminum nitride layer ranges from 1 nm to 3 nm.

9. The gallium oxide epitaxial wafer according to claim 6, characterized in that, In the first aluminum nitride layer, the silicon content ranges from 2% to 10%; and / or, In the first aluminum nitride layer, the silicon doping concentration is less than or equal to 9E17cm⁻¹. -3 .

10. A solar-blind ultraviolet photodetector, characterized in that, This includes gallium oxide epitaxial wafers prepared using the method for preparing gallium oxide epitaxial wafers as described in any one of claims 1 to 5; or gallium oxide epitaxial wafers as described in any one of claims 6 to 9.

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