High radio frequency signal Fan-out packaging structure and process

Abstract

The invention discloses a high radio frequency signal Fan-out packaging structure and process, and belongs to the technical field of semiconductor packaging, the packaging structure comprises a packaging substrate, at least one chip, an insulating layer, an interconnection structure, a solder mask layer and a solder ball, the interconnection structure adopts a repeated stacking design, the signal spacing between lines is accurately controlled by using the height of a second connecting column, and the high radio frequency signal Fan-out packaging process is realized. According to the packaging technology, a glass substrate serves as a temporary bearing platform, and the packaging technology is completed through the steps of chip mounting, plastic packaging and grinding, temporary substrate attaching and stripping, insulating layer preparing, stacking sub-step repeated execution, first connecting column preparing, bump lower metallization layer and solder mask layer preparing, ball planting and cutting and the like in sequence. According to the invention, the frequency limitation of traditional packaging of 10GHz is broken through, transmission of ultrahigh frequency signals of more than 40GHz and multi-chip integration are supported, the interconnection reliability is high, the process compatibility is strong, the scene adaptation is flexible, and the method is suitable for semiconductor devices such as 5G millimeter waves, high-speed optical communication, computing chips and the like.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging technology, specifically relating to a high-frequency signal fan-out packaging structure and process. Background Technology

[0002] As semiconductor technology develops towards high density, ultra-high frequency, and multi-chip integration, chip packaging not only needs to protect and electrically expose the chip, but also needs to overcome core technical bottlenecks such as high-frequency signal transmission loss and multi-chip collaborative interconnection. High frequency refers to 10 GHz and above.

[0003] Traditional Fan-out Packages (FOWLP) achieve pin fan-out through a redistribution layer, but they have the following key drawbacks in ultra-high frequency and multi-chip integration scenarios: 1. Low high-frequency signal transmission limit: The signal transmission path of traditional FOWLP relies on a single or simple conductive structure. The uniformity of the insulating material coating is difficult to control precisely, resulting in strong electromagnetic coupling effect between conductive areas. The high-frequency signal transmission limit is usually only below 10GHz, which cannot meet the low-loss transmission requirements of ultra-high frequency signals above 40GHz. The signal attenuation and reflection are serious, which restricts the improvement of chip performance. 2. Insufficient interconnect reliability: The connection design between the conductive structure and the redistribution layer of the existing package is unreasonable and lacks an effective transition and protection mechanism. Under long-term working environment (such as high and low temperature cycle, humidity change), problems such as metal atom interdiffusion and interface peeling are prone to occur, resulting in connection failure and shortening the service life of the package. 3. Lack of multi-chip integration capability: The interconnect architecture design of traditional fan-out packaging is limited, making it difficult to achieve efficient collaborative interconnection of multiple chips. Moreover, after multi-chip integration, problems such as signal interference and unstable power supply are prone to occur, which cannot meet the multi-chip integration requirements of high-end devices. Summary of the Invention

[0004] To address the problems mentioned in the background art, the present invention provides a high-frequency signal fan-out packaging structure and process to solve the problems of low high-frequency signal transmission limit, insufficient interconnect reliability, and lack of multi-chip integration capability in existing packages.

[0005] To achieve the above objectives, the present invention provides the following technical solution: A high-frequency signal fan-out packaging structure, comprising: Encapsulation substrate; the top surface of the encapsulation substrate is provided with a solder resist layer; Chip; The chip is disposed inside the bottom of the package substrate, and the chip has at least one pad, with the side of the chip with the pad facing the top surface of the package substrate; At least one set of interconnect structures; the top of the interconnect structure is disposed outside the solder mask layer, and the bottom of the set of interconnect structures passes through the solder mask layer, is inserted into the package substrate, and is connected to a pad; A set of interconnect structures includes: A first connecting post, a redistribution layer and its spacing control structure are disposed in the encapsulation substrate; the bottom surface of the redistribution layer and its spacing control structure is connected to the top surface of the pad, and the top surface of the redistribution layer and its spacing control structure is connected to the bottom end of the first connecting post. A metallization layer under the bump is disposed in the solder mask layer; the bottom surface of the metallization layer under the bump is connected to the top surface of the package substrate, and the top surface of the first connecting post is connected to the bottom surface of the metallization layer under the bump. Solder ball; The solder ball is embedded in the top surface of the solder resist layer, and the bottom end of the solder ball is connected to the top surface of the metallization layer under the bump; The redistribution layer and its spacing control structure are a stacked overall structure of multiple signal transmission layers, used to realize the high-frequency signal output and horizontal wiring transmission of the chip, as well as the limitation of the vertical spacing between adjacent signal transmission layers. By controlling the vertical spacing, inter-layer electromagnetic coupling interference is suppressed, and the transmission loss and reflection loss of high-frequency signals are reduced.

[0006] Preferably, the redistribution layer and its spacing control structure include: at least two second connecting pillars and a corresponding number of redistribution layers, the top of one second connecting pillar is connected to the bottom surface of one redistribution layer to form a unit, all units are stacked and connected, the bottom surface of the second connecting pillar of one unit is connected to the top surface of the pad or the top surface of the redistribution layer of another unit, and the top surface of the redistribution layer of one unit is connected to the bottom end of the first connecting pillar or the second connecting pillar.

[0007] Preferably, the top surface of the chip is provided with a PI layer, the PI layer is provided with a plurality of interconnect vias, the pads are disposed in the PI layer, and a second connecting post passes through an interconnect via and is connected to a pad.

[0008] Preferably, the PI layer is made of polyimide.

[0009] Preferably, both the first connecting post and the second connecting post are copper posts.

[0010] Preferably, the encapsulation substrate is made of epoxy resin molding compound.

[0011] A high-frequency signal fan-out packaging process includes the following steps: S1: A first temporary support substrate is provided, and a release layer and an adhesive layer are sequentially formed on the top surface of the first temporary support substrate; S2: The chip is flip-mounted with the side with the pads facing the first temporary substrate; S3: The mounted chip is encapsulated using a packaging substrate material to form a packaging substrate prototype. The top surface of the packaging substrate prototype is then ground until it is smooth. S4: Provide a second temporary carrier substrate, and attach and fix the top surface of the encapsulation substrate prototype to the second temporary carrier substrate with a temporary adhesive; S5: Utilizing the release properties of the release layer, separate the first temporary carrier substrate from the adhesive layer, then remove the adhesive layer to fully expose the side of the chip with the pads, and invert the package substrate prototype so that the exposed pad surface is the top surface; S6: Prepare a PI layer on the surface of the pads and the top surface of the package substrate prototype. Through exposure and development processes, open interconnect vias at the positions of the pads in the PI layer so that the pads are exposed through the interconnect vias. S7: Perform a preset number of stacking sub-steps to prepare a stacked redistribution layer and its spacing control structure, wherein the preset number of times is ≥2, and the stacking sub-steps include: S71: A second connection post is deposited on the current surface to be connected using a sputtering process. The bottom end of the second connection post is electrically connected to the conductive area of ​​the current surface to be connected. The current surface to be connected is initially a pad exposure surface and subsequently the redistribution layer surface formed in the previous stacking sub-step. S72: Use a packaging substrate material to encapsulate the second connecting post and the current surface to be connected, and grind the encapsulated surface to expose the top of the second connecting post; S73: Prepare a redistribution layer wiring pattern window on the polished plastic encapsulation surface, and then deposit copper to form a redistribution layer through an electroplating process. Its bottom surface is electrically connected to the top of the second connecting post, completing one stacking sub-step. By repeating S71-S73 multiple times, the structures formed by adjacent stacking sub-steps are electrically connected in sequence, and the vertical spacing between adjacent redistribution layers is limited by the height of the second connecting pillar. S8: Deposit a first connecting post on the top surface of the redistribution layer formed in the last stacking sub-step, with its bottom end electrically connected to the top surface of the redistribution layer; S9: The first connecting post and its connected redistribution layer are encapsulated using an encapsulation substrate material to complete the preparation of the encapsulation substrate. The top surface of the encapsulation substrate is ground to expose the top of the first connecting post. S10: A metallization layer under the bump and a solder mask layer are sequentially prepared on the top surface of the packaging substrate. The metallization layer under the bump is electrically connected to the top of the first connecting post. A window is opened in the solder mask layer at the position corresponding to the metallization layer under the bump. S11: Peel off the second temporary carrier substrate, solder the solder balls inside the solder mask window, and connect the solder balls to the metallization layer under the bump to complete the encapsulation.

[0012] Preferably, in S7, when the preset number of times is 2, the current surface to be connected in the first stacking sub-step is the exposed surface of the pad, and the bottom end of the second connecting post in the first stacking sub-step is electrically connected to the chip pad; the current surface to be connected in the second stacking sub-step is the surface of the redistribution layer formed in the first stacking sub-step, and the bottom end of the second connecting post in the second stacking sub-step is electrically connected to the top surface of the redistribution layer.

[0013] Preferably, in S6, the PI layer is prepared sequentially through coating, pre-baking, exposure, development, and curing processes.

[0014] Preferably, the vertical spacing between adjacent redistribution layers is set to 30-80 μm.

[0015] Compared with the prior art, the beneficial effects of the present invention are: 1. This application optimizes the electromagnetic environment between conductive areas by controlling the signal spacing between lines, effectively suppressing electromagnetic coupling interference, and increasing the signal transmission limit from 10GHz in traditional packaging to over 40GHz, achieving low-loss and high-stability transmission of ultra-high frequency signals, meeting the needs of scenarios such as 5G millimeter wave and high-speed optical communication; 2. This application optimizes the packaging architecture and interconnect design to support the collaborative integration and efficient interconnection of multiple chips, solving the problems of difficult multi-chip integration and severe signal interference in traditional packaging, and is suitable for multi-chip collaborative working scenarios such as computing power chips; 3. This application adopts a stacked overall structure of multi-layer signal transmission layers and a plastic encapsulation protection design with epoxy resin molding compound throughout, which strengthens the interface connection strength between the conductive structure and the redistribution layer, suppresses the interdiffusion of metal atoms, avoids interface peeling and connection failure, and significantly extends the service life of the package. 4. The process flow of this application is highly compatible with existing Fan-out packaging production lines, requires no special customized equipment, has strong repeatability, and reduces mass production costs. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the high-frequency signal Fan-out package structure; The diagram is marked as follows: 1-Packaging substrate; 2-Chip; 3-Pad; 4-PI layer; 5-Second connecting post; 6-Redistribution layer; 7-First connecting post; 8-Solder resist layer; 9-Solder ball; 10-Under-bump metallization layer. Detailed Implementation

[0017] To facilitate understanding of the technical content of this invention by those skilled in the art, the invention will be further described in detail below with reference to the accompanying drawings and specific examples. It should be understood that the specific examples described herein are merely illustrative and not intended to limit the scope of the invention.

[0018] like Figure 1 As shown, a high-frequency signal fan-out packaging structure includes: Encapsulation substrate 1; The top surface of the encapsulation substrate 1 is provided with a solder resist layer 8, which is an insulating coating, and the material of the encapsulation substrate 1 is epoxy resin molding compound. Two chips 2; the chips 2 are disposed inside the bottom of the package substrate 1, each chip 2 has two pads 3, and the side of the chip 2 with the pads 3 faces the top surface of the package substrate 1. Four interconnect structures; each pair of interconnect structures is set on a chip 2, the top of the interconnect structure is set outside the solder mask layer 8, and the bottom of one interconnect structure passes through the solder mask layer 8, is inserted into the package substrate 1 and connected to a pad 3. A set of interconnect structures includes: The first connecting post 7, the redistribution layer and its spacing control structure are disposed in the encapsulation substrate 1; the bottom surface of the redistribution layer and its spacing control structure is connected to the top surface of a pad 3, and the top surface of the redistribution layer and its spacing control structure is connected to the bottom end of the first connecting post 7. A metallization layer 10 under the bump is disposed in the solder mask layer 8; the metallization layer 10 under the bump is a multilayer metal thin film structure, the bottom surface of the metallization layer 10 under the bump is connected to the top surface of the encapsulation substrate 1, and the top end of the first connecting post 7 is connected to the bottom surface of the metallization layer 10 under the bump. Solder ball 9; Solder ball 9 is made of lead-free solder ball, and solder ball 9 is embedded in the top surface of solder resist layer 8. The bottom end of solder ball 9 is connected to the top surface of metallization layer 10 under bump. The redistribution layer and its spacing control structure are a stacked overall structure of multiple signal transmission layers, used to realize the high-frequency signal output and horizontal wiring transmission of chip 2, as well as the limitation of the vertical spacing between adjacent signal transmission layers. By controlling the vertical spacing, inter-layer electromagnetic coupling interference is suppressed, and the transmission loss and reflection loss of high-frequency signals are reduced.

[0019] A redistribution layer and its spacing control structure include: two second connecting posts 5 and two redistribution layers 6. The top of one second connecting post 5 is connected to the bottom surface of one redistribution layer 6 to form a unit. All units are stacked and connected. The bottom surface of the second connecting post 5 of one unit is connected to the top surface of the pad 3 or the top surface of the redistribution layer 6 of another unit. The top surface of the redistribution layer 6 of one unit is connected to the bottom end of the first connecting post 7 or the second connecting post 5. The top surface of chip 2 is provided with a PI layer 4, and the PI layer 4 is provided with interconnect vias in the same number as the pads 3. The pads 3 are disposed in the PI layer 4. A second connecting post 5 passes through an interconnect via and is connected to a pad 3. The material of the PI layer 4 is polyimide, and the first connecting post 7 and the second connecting post 5 are both copper posts.

[0020] A high-frequency signal fan-out packaging process includes the following steps: S1: A first temporary support substrate is provided. The first temporary support substrate is a glass substrate. A release layer and an adhesive layer are sequentially formed on the top surface of the first temporary support substrate. S2: The chip 2 is flip-mounted with the side with the pads 3 facing the first temporary substrate; S3: The mounted chip 2 is encapsulated using the encapsulation substrate 1 material to form an encapsulation substrate prototype. The top surface of the encapsulation substrate prototype is then ground until it is flat. S4: Provide a second temporary support substrate, which is a glass substrate, and attach and fix the top surface of the encapsulation substrate prototype to the second temporary support substrate with a temporary adhesive; S5: Utilizing the release properties of the release layer, separate the first temporary carrier substrate from the adhesive layer, then remove the adhesive layer to fully expose the side of the chip 2 with the pad 3, and invert the package substrate prototype so that the exposed surface of the pad 3 is the top surface; S6: Prepare PI layer 4 on the surface of pad 3 and the top surface of the package substrate prototype. PI layer 4 is prepared by coating, pre-baking, exposure, development and curing in sequence. Interconnect vias are opened in the PI layer 4 at the position corresponding to pad 3 through exposure and development processes, so that pad 3 is exposed through interconnect vias. S7: Perform a stacking sub-step a preset number of times to prepare a stacked redistribution layer and its spacing control structure. The preset number of times is 2. The stacking sub-step includes: S71: A second connecting post 5 is deposited on the current surface to be connected using a sputtering process. The bottom end of the second connecting post 5 is electrically connected to the conductive area of ​​the current surface to be connected. The current surface to be connected is initially the exposed surface of the pad 3, and subsequently the surface of the redistribution layer 6 formed in the previous stacking sub-step. S72: The second connecting post 5 and the current surface to be connected are encapsulated using the encapsulation substrate 1 material, and the encapsulated surface is ground to expose the top of the second connecting post 5. S73: Prepare a wiring pattern window of redistribution layer 6 on the polished plastic encapsulation surface, and then deposit copper to form redistribution layer 6 through electroplating process. Its bottom surface is electrically connected to the top of the second connecting post 5, completing one stacking sub-step. By repeating S71-S73 multiple times, the "redistribution layer 6 + second connecting post 5" structure of adjacent stacking sub-steps is electrically connected in sequence, and the vertical spacing between adjacent redistribution layers 6 is limited by the height of the second connecting post 5, and the vertical spacing between adjacent redistribution layers 6 is set to 30μm. When the preset number of times is 2, the current surface to be connected in the first stacking sub-step is the exposed surface of the pad 3, and the bottom end of the second connecting post 5 in the first stacking sub-step is electrically connected to the pad 3; the current surface to be connected in the second stacking sub-step is the surface of the redistribution layer 6 formed in the first stacking sub-step, and the bottom end of the second connecting post 5 in the second stacking sub-step is electrically connected to the top surface of the redistribution layer 6. S8: A first connecting post 7 is deposited on the top surface of the redistribution layer 6 formed in the last stacking sub-step, and its bottom end is electrically connected to the top surface of the redistribution layer 6. S9: The first connecting post 7 and its connected redistribution layer 6 are encapsulated using the encapsulation substrate 1 material to complete the preparation of the encapsulation substrate 1. The top surface of the encapsulation substrate 1 is ground to expose the top of the first connecting post 7. S10: A bump under-metallization layer 10 and a solder mask layer 8 are sequentially prepared on the top surface of the packaging substrate 1. The bump under-metallization layer 10 is electrically connected to the top of the first connecting post 7. The solder mask layer 8 has an opening at the position corresponding to the bump under-metallization layer 10. S11: Peel off the second temporary carrier substrate, solder ball 9 is soldered in the window of solder mask layer 8, solder ball 9 is connected to the metallization layer under bump 10, and the encapsulation is completed.

[0021] This application sets up a repeating stacked structure, uses the height of the second connecting post 5 to accurately define the signal spacing between lines, optimizes the electromagnetic distribution between conductive areas, weakens electromagnetic coupling interference, and increases the signal transmission limit from 10GHz in traditional packaging to over 40GHz, achieving low-loss and high-stability transmission of high-frequency signals and breaking through the high-frequency transmission bottleneck of traditional packaging.

[0022] This application also includes adjustable stacking sub-steps. By flexibly adjusting the preset number of stacking sub-steps and the height of the second connecting post 5, it can adapt to different high-frequency signal requirements and chip integration numbers. For example, when multiple chips are integrated in a package substrate 1, different spacing of the redistribution layer 6 can be set according to the situation of each chip to avoid mutual interference. This application can be compatible with different frequency band signal transmission and multi-chip integration requirements without redesigning the process flow, breaking through the limitations of insufficient flexibility in traditional packaging scenarios and reducing the cost of multi-scenario adaptation.

[0023] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A high-frequency signal fan-out packaging structure, characterized in that, include: Encapsulation substrate (1); The top surface of the encapsulation substrate (1) is provided with a solder resist layer (8); Chip (2); Chip (2) is disposed inside the bottom end of the packaging substrate (1), and at least one pad (3) is provided on the chip (2), with the side of the chip (2) having the pad (3) facing the top surface of the packaging substrate (1); At least one set of interconnect structures; the top of the interconnect structure is disposed outside the solder mask layer (8), and the bottom of the set of interconnect structures passes through the solder mask layer (8), is inserted into the package substrate (1), and is connected to a pad (3); A set of interconnect structures includes: The first connecting post (7), the redistribution layer and its spacing control structure are set in the encapsulation substrate (1); The bottom surface of the redistribution layer and its spacing control structure is connected to the top surface of the pad (3), and the top surface of the redistribution layer and its spacing control structure is connected to the bottom end of the first connecting post (7); A bump under-metallization layer (10) is provided in the solder mask layer (8); the bottom surface of the bump under-metallization layer (10) is connected to the top surface of the encapsulation substrate (1), and the top end of the first connecting post (7) is connected to the bottom surface of the bump under-metallization layer (10). Solder ball (9); The solder ball (9) is embedded in the top surface of the solder resist layer (8), and the bottom end of the solder ball (9) is connected to the top surface of the metallization layer (10) under the bump; The redistribution layer and its spacing control structure are a stacked overall structure of multiple signal transmission layers, used to realize the high-frequency signal output and horizontal wiring transmission of the chip (2), as well as the limitation of the vertical spacing between adjacent signal transmission layers. The vertical spacing control suppresses interlayer electromagnetic coupling interference and reduces the transmission loss and reflection loss of high-frequency signals.

2. The high-frequency signal fan-out packaging structure according to claim 1, characterized in that, The redistribution layer and its spacing control structure include: at least two second connecting pillars (5) and a corresponding number of redistribution layers (6), the top of one second connecting pillar (5) is connected to the bottom surface of one redistribution layer (6) to form a unit, all units are stacked and connected, the bottom surface of the second connecting pillar (5) of one unit is connected to the top surface of the pad (3) or the top surface of the redistribution layer (6) of another unit, and the top surface of the redistribution layer (6) of one unit is connected to the bottom end of the first connecting pillar (7) or the second connecting pillar (5).

3. The high-frequency signal fan-out packaging structure according to claim 2, characterized in that, The chip (2) has a PI layer (4) on its top surface. The PI layer (4) has multiple interconnect vias. The pad (3) is located in the PI layer (4). A second connecting post (5) passes through an interconnect via and is connected to a pad (3).

4. The high-frequency signal fan-out packaging structure according to claim 3, characterized in that, The PI layer (4) is made of polyimide.

5. The high-frequency signal fan-out packaging structure according to claim 2, characterized in that, Both the first connecting post (7) and the second connecting post (5) are copper posts.

6. The high-frequency signal fan-out packaging structure according to claim 1, characterized in that, The encapsulation substrate (1) is made of epoxy resin molding compound.

7. A high-RF signal Fan-out packaging process, applied to a high-RF signal Fan-out packaging structure as described in any one of claims 1-6, characterized in that, Includes the following steps: S1: A first temporary support substrate is provided, and a release layer and an adhesive layer are sequentially formed on the top surface of the first temporary support substrate; S2: The chip (2) is flip-mounted with the side with the pads (3) facing the first temporary substrate; S3: The chip (2) after mounting is encapsulated using the encapsulation substrate (1) material to form an encapsulation substrate prototype. The top surface of the encapsulation substrate prototype is ground until the surface is flat. S4: Provide a second temporary carrier substrate, and attach and fix the top surface of the encapsulation substrate prototype to the second temporary carrier substrate with a temporary adhesive; S5: Utilize the release properties of the release layer to separate the first temporary carrier substrate from the adhesive layer, and then remove the adhesive layer to fully expose the side of the chip (2) with the pad (3), and invert the packaging substrate prototype so that the exposed surface of the pad (3) is the top surface; S6: Prepare a PI layer (4) on the surface of the pad (3) and the top surface of the package substrate prototype. Through exposure and development process, open interconnect vias at the positions of the PI layer (4) corresponding to the pad (3) so that the pad (3) is exposed through the interconnect vias. S7: Perform a preset number of stacking sub-steps to prepare a stacked redistribution layer and its spacing control structure, wherein the preset number of times is ≥2, and the stacking sub-steps include: S71: A second connecting post (5) is deposited on the current surface to be connected using a sputtering process. The bottom end of the second connecting post (5) is electrically connected to the conductive area of ​​the current surface to be connected. The current surface to be connected is initially the exposed surface of the pad (3) and subsequently the surface of the redistribution layer (6) formed in the previous stacking sub-step. S72: Use the encapsulation substrate (1) material to encapsulate the second connecting post (5) and the current surface to be connected, and grind the encapsulated surface to expose the top of the second connecting post (5); S73: Prepare a redistribution layer (6) wiring pattern window on the polished plastic encapsulation surface, and then deposit copper through electroplating process to form a redistribution layer (6). Its bottom surface is electrically connected to the top of the second connecting post (5) to complete one stacking sub-step. By repeating S71-S73 multiple times, the structures formed by adjacent stacking sub-steps are electrically connected in sequence, and the vertical spacing of adjacent redistribution layers (6) is limited by the height of the second connecting post (5). S8: Deposit a first connecting post (7) on the top surface of the redistribution layer (6) formed in the last stacking sub-step, with its bottom end electrically connected to the top surface of the redistribution layer (6); S9: The first connecting post (7) and its connected redistribution layer (6) are encapsulated using the encapsulation substrate (1) material to complete the preparation of the encapsulation substrate (1). The top surface of the encapsulation substrate (1) is ground to expose the top of the first connecting post (7). S10: A bump under-metallization layer (10) and a solder mask layer (8) are sequentially prepared on the top surface of the encapsulation substrate (1). The bump under-metallization layer (10) is electrically connected to the top of the first connecting post (7). The solder mask layer (8) has an opening at the position corresponding to the bump under-metallization layer (10). S11: Peel off the second temporary carrier substrate, solder balls (9) are soldered in the window of the solder mask layer (8), and the solder balls (9) are connected to the metallization layer under the bump (10) to complete the encapsulation.

8. The high-frequency signal fan-out packaging process according to claim 7, characterized in that, In S7, when the preset number of times is 2, the current surface to be connected in the first stacking sub-step is the exposed surface of the pad (3), and the bottom end of the second connecting post (5) in the first stacking sub-step is electrically connected to the pad (3); the current surface to be connected in the second stacking sub-step is the surface of the redistribution layer (6) formed in the first stacking sub-step, and the bottom end of the second connecting post (5) in the second stacking sub-step is electrically connected to the top surface of the redistribution layer (6).

9. The high-frequency signal fan-out packaging process according to claim 7, characterized in that, In S6, the PI layer (4) is prepared sequentially through coating, pre-baking, exposure, development and curing processes.

10. The high-frequency signal fan-out packaging process according to claim 7, characterized in that, The vertical spacing between adjacent redistribution layers (6) is set to 30-80 μm.

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