Semiconductor device and manufacturing method thereof

Abstract

The embodiment of the invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a first chip and a second chip which are stacked along a first direction, wherein the first chip comprises a modulator structure and a modulator driving circuit; the second chip comprises a detector structure and a transimpedance amplification circuit; and the first chip is in bonding connection with the second chip.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, a semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] Optical engine (OE) chip is a core integrated device for realizing photoelectric signal conversion, and is a key to break through the bottleneck of electrical interconnection and build the next generation of high-performance information systems. With the rapid development of digitalization, intelligentization and cloud computing technology, data traffic is surging, and higher requirements are put forward for the bandwidth, energy efficiency and delay of data transmission. Optical interconnection technology is developing towards shorter distance and higher integration, and evolving from device level to board level and chip level. Silicon-based optoelectronic technology provides a platform for realizing large-scale photon integration, and co-packaged optics represents the forefront paradigm of photoelectric collaborative design. The technical progress of optical engine chip directly supports the energy efficiency and scale expansion of computing infrastructure, and has become a strategic hardware foundation for enabling digital economy and the intelligent era. SUMMARY

[0003] The present disclosure provides a semiconductor device and a manufacturing method thereof.

[0004] The present disclosure provides a semiconductor device, comprising: a first chip and a second chip stacked along a first direction; wherein the first chip comprises a modulator structure and a modulator driving circuit; the second chip comprises a detector structure and a transimpedance amplification circuit; the first chip and the second chip are bonded and connected.

[0005] The present disclosure provides a manufacturing method of a semiconductor device, comprising: respectively forming a first chip and a second chip; the first chip comprises a modulator structure and a modulator driving circuit; the second chip comprises a detector structure and a transimpedance amplification circuit; stacking the first chip and the second chip along a first direction.

[0006] In the embodiment of the present disclosure, the semiconductor device includes a first chip and a second chip stacked along a first direction, the first chip includes a modulator structure and a modulator driving circuit, the second chip includes a detector structure and a transimpedance amplification circuit, and the first chip and the second chip are bonded and connected. In a first aspect, the modulator structure and the detector structure in the embodiment of the present disclosure are respectively located in two chips, which can reduce the waveguide density, reduce the overall internal stress of the semiconductor device, and thus improve the reliability of the semiconductor device. In a second aspect, the first chip including the modulator structure and the modulator driving circuit and the second chip including the detector structure and the transimpedance amplification circuit are stacked along the first direction, so that the area occupied by the semiconductor device can be reduced. In a third aspect, the modulator structure and the detector structure are respectively located in two chips, and the first chip and the second chip can be formed respectively, that is, the modulator structure and the detector structure can be formed synchronously in different chips, so that the modulator and the detector can be flexibly compatible with material systems with better optical performance such as III-V compound and lithium niobate, and can be compatible with modulators and detectors prepared by different epitaxial materials. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 Structure diagram of a semiconductor device provided in an embodiment of the present disclosure Figure 1 ; Figure 2 Structure diagram of a semiconductor device provided in an embodiment of the present disclosure Figure 2 ; Figure 3 Structure diagram of a first chip provided in an embodiment of the present disclosure Figure 1 ; Figure 4 Structure diagram of a second chip provided in an embodiment of the present disclosure Figure 1 ; Figure 5 Structure diagram of a first chip provided in an embodiment of the present disclosure Figure 2 ; Figure 6 Structure diagram of a second chip provided in an embodiment of the present disclosure Figure 2 ; Figure 7 Structure diagram of a semiconductor device provided in an embodiment of the present disclosure Figure 3 ; Figure 8 Structure diagram of a semiconductor device provided in an embodiment of the present disclosure Figure 4 ; Figure 9 Structure diagram of a semiconductor device provided in an embodiment of the present disclosure Figure 5 ; Figure 10A flowchart of a method for forming a semiconductor device is provided for an embodiment of the present disclosure. Figure 11 A structural diagram of a forming process of a semiconductor structure is provided for an embodiment of the present disclosure Figure 1 ; Figure 12 A structural diagram of a forming process of a semiconductor structure is provided for an embodiment of the present disclosure Figure 2 ; Figure 13 A structural diagram of a forming process of a semiconductor structure is provided for an embodiment of the present disclosure Figure 3 ; Figure 14 A structural diagram of a forming process of a semiconductor structure is provided for an embodiment of the present disclosure Figure 4 . DETAILED DESCRIPTION

[0008] Exemplary embodiments of the present disclosure will be described herein below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be embodied in various forms without being limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0009] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure can be practiced without one or more of these specific details. In other instances, well-known features are not described in detail in order to avoid obscuring aspects of the present disclosure. In the interest of clarity, not all of the included components of the systems are shown and described. It can be appreciated that in the development of any such actual implementation, numerous implementation-specific decisions can be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill in the art having the benefit of this disclosure.

[0010] In the drawings, the size of layers, regions, elements, and the relative sizes of the same can be exaggerated for clarity. Like reference numbers in different drawings can represent similar elements.

[0011] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.

[0012] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0013] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0014] In order to enable a more detailed understanding of the features and technical content of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure is described in detail below with reference to the drawings, which are only used for reference and do not limit the embodiments of the present disclosure.

[0015] As the core device of optical interconnection system, the light engine chip usually adopts the way of co-packaging of photonic integrated circuit (PIC) and electronic integrated circuit (EIC) to realize photoelectric collaborative processing. However, the current silicon optical chip generally integrates input and output modules such as modulator and detector in the same chip, resulting in larger chip area, higher waveguide density, and significantly increased stress in the chip, which affects the long-term reliability of the device. At the same time, the modulator has strict requirements on temperature stability, and often needs to integrate a thermal management module inside the chip, further increasing the complexity of power consumption and heat dissipation design. In addition, the integrated architecture limits the modulator and detector to the silicon-based material platform, making it difficult to flexibly compatible with material systems such as III-V compounds and lithium niobate, which have better optical performance, limiting the further improvement and functional expansion of device performance.

[0016] Embodiments of the present disclosure provide a semiconductor device, such as Figure 1 As shown in the figure, the semiconductor device includes: a first chip 101 and a second chip 102 stacked along a first direction; wherein the first chip 101 includes a modulator structure 103 and a modulator driving circuit 104; the second chip 102 includes a detector structure 105 and a transimpedance amplification circuit 106; the first chip 101 and the second chip 102 are bonded and connected.

[0017] Here, the modulator driving circuit 104 is used to drive the modulator structure 103, and the transimpedance amplification circuit 106 can amplify weak optical signals.

[0018] The first direction in the embodiments of the present disclosure can be understood as the Z-axis direction in the figure, and the second direction in the following text can be understood as the X-axis direction in the figure.

[0019] In the embodiment of the present disclosure, the semiconductor device includes a first chip 101 and a second chip 102 stacked along a first direction, the first chip 101 includes a modulator structure 103 and a modulator driving circuit 104, the second chip 102 includes a detector structure 105 and a transimpedance amplification circuit 106, and the first chip 101 and the second chip 102 are bonded and connected. In a first aspect, the modulator structure 103 and the detector structure 105 in the embodiment of the present disclosure are respectively located in two chips, which can reduce the waveguide density, reduce the overall internal stress of the semiconductor device, and thus improve the reliability of the semiconductor device; in a second aspect, the first chip 101 including the modulator structure 103 and the modulator driving circuit 104 and the second chip 102 including the detector structure 105 and the transimpedance amplification circuit 106 are stacked along the first direction, so that the area occupied by the semiconductor device can be reduced; in a third aspect, the modulator structure 103 and the detector structure 105 are respectively located in two chips, and the first chip 101 and the second chip 102 can be formed respectively, that is, the modulator structure 103 and the detector structure 105 can be synchronously formed in different chips, so that the modulator and the detector can be flexibly compatible with material systems with better optical performance such as III-V compound and lithium niobate, and can be compatible with modulators and detectors prepared by different epitaxial materials.

[0020] In some embodiments, with reference to Figure 1 , Figure 2 and Figure 3 , the first chip 101 includes a first semiconductor structure 107, a first hybrid bonding layer 108 and a second semiconductor structure 109 stacked in sequence along the first direction; the first semiconductor structure 107 includes the modulator structure 103, and the second semiconductor structure 109 includes the modulator driving circuit 104; the first hybrid bonding layer 108 includes a first bonding structure 110; and the modulator structure 103 and the modulator driving circuit 104 are connected through the first bonding structure 110.

[0021] In the embodiment of the present disclosure, the modulator structure 103 and the modulator driving circuit 104 are stacked along the Z-axis direction, which can shorten the interconnection distance, reduce transmission delay, parasitic capacitance and inductance, and reduce signal loss and crosstalk; on the other hand, it can improve the integration density and miniaturization, and realize more compact packaging; on the other hand, the first semiconductor structure 107 and the second semiconductor structure 109 are bonded and connected through the first hybrid bonding layer 108, and the first semiconductor structure 107 and the second semiconductor structure 109 are heterogeneously integrated, which can solve the problem of mismatch between the material systems of the first semiconductor structure 107 and the second semiconductor structure 109 and process temperature conflict, so that both the first semiconductor structure 107 and the second semiconductor structure 109 can achieve their own optimal performance.

[0022] In some embodiments, with reference to Figure 1 ,Figure 2 and Figure 4 The second chip 102 comprises a third semiconductor structure 111, a second hybrid bonding layer 112, and a fourth semiconductor structure 113 stacked in sequence along the first direction; the third semiconductor structure 111 comprises the detector structure 105, and the fourth semiconductor structure 113 comprises the transimpedance amplification circuit 106; the first semiconductor structure 107 and the third semiconductor structure 111 are both located between the second hybrid bonding layer 112 and the first hybrid bonding layer 108; the second hybrid bonding layer 112 comprises a second bonding structure 114; the detector structure 105 and the transimpedance amplification circuit 106 are connected through the second bonding structure 114.

[0023] In the embodiments of the present disclosure, the detector structure 105 and the transimpedance amplification circuit 106 are stacked along the Z-axis direction, which can shorten the interconnection distance, reduce transmission delay, parasitic capacitance and inductance, and reduce signal loss and crosstalk; on the other hand, it can improve the integration density and miniaturization, and realize more compact packaging; on the other hand, the third semiconductor structure 111 and the fourth semiconductor structure 113 are bonded and connected through the second hybrid bonding layer 112, and the third semiconductor structure 111 and the fourth semiconductor structure 113 are heterogeneously integrated, which can solve the problem of material system mismatch and process temperature conflict of the third semiconductor structure 111 and the fourth semiconductor structure 113, and make both the third semiconductor structure 111 and the fourth semiconductor structure 113 achieve their own optimal performance.

[0024] In some embodiments, the first chip 101 and the second chip 102 can be one of which is heterogeneously integrated, or both of which are heterogeneously integrated. In other embodiments, neither the first chip 101 nor the second chip 102 is heterogeneously integrated, and the first semiconductor structure 107 and the second semiconductor structure 109 in the first chip 101 are formed on the same wafer, and the third semiconductor structure 111 and the fourth semiconductor structure 113 in the second chip 102 are formed on the same wafer.

[0025] In some embodiments, as shown in Figure 2 and Figure 3 The first semiconductor structure 107 further comprises a first waveguide layer 115, a first substrate 116, and a first interconnection layer 117 stacked in sequence along the first direction; the first interconnection layer 117 is located between the first hybrid bonding layer 108 and the first substrate 116; the modulator structure 103 comprises a modulator and a first waveguide structure 118; the first waveguide structure 118 is located in the first waveguide layer 115, and the modulator is located in the first substrate 116 and between the first substrate 116 and the first interconnection layer 117.

[0026] Here, the first substrate 116 can be a semiconductor substrate, including but not limited to a single-element semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a compound semiconductor material substrate (e.g., a silicon-germanium (SiGe) substrate, etc.), at least one III-V compound semiconductor material (e.g., a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc.

[0027] Here, the first waveguide layer 115 includes a first dielectric layer and a first waveguide structure 118 in the first dielectric layer. The material of the first dielectric layer includes but is not limited to silicon oxide, and the material of the first waveguide structure 118 includes but is not limited to silicon or silicon nitride. As shown in FIG. 1, the first waveguide structure 118 includes a first waveguide core 119 and a first waveguide cladding 120 surrounding the first waveguide core 119. Figure 3 As shown in FIG. 1, the first interconnection layer 117 includes a second dielectric layer and a first interconnection structure 142 in the second dielectric layer, and the material of the second dielectric layer includes but is not limited to silicon oxide. The material of the first interconnection structure 142 includes but is not limited to at least one of a conductive material, e.g., a doped semiconductor material (e.g., doped silicon, doped germanium, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), a metal material (e.g., aluminum, copper, tungsten, titanium, tantalum, etc.), and a metal-semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0028] In some embodiments, the modulator structure 103 includes a thin-film lithium niobate modulator.

[0029] In some specific examples, the first substrate 116 is a silicon-on-insulator substrate, and the first substrate 116 includes a front side and a back side. Here, the front side can be understood as a side of the substrate on which a corresponding device is formed, and the back side and the front side are two sides of the substrate opposite to each other along the thickness direction of the substrate. The modulator is formed on the front side of the first substrate 116, as shown in FIG. 1. Figure 5 As shown in FIG. 1, the modulator includes a thin-film lithium niobate layer 150 and a silicon nitride waveguide 151 in the first substrate 116. As shown in FIG. 1, the modulator includes a first electrode 153 on the thin-film lithium niobate layer 150. Figure 5 As shown in FIG. 1, the first substrate 116 includes an insulating silicon dioxide intermediate layer 152, also known as a buried oxide (BOX). The modulator further includes a first electrode 153 on the thin-film lithium niobate layer 150. The first electrode 153 can be connected with the first interconnection structure 142 in the first interconnection layer 117.

[0030] In some specific examples, as shown in FIG. 1, the modulator structure 103 further includes a second interconnection layer 121, a second waveguide layer 122, and a second substrate 123. Figure 3As shown, the first hybrid bonding layer 108 includes a third dielectric layer and a first bonding structure 110 located within the third dielectric layer. The material of the third dielectric layer includes, but is not limited to, silicon nitride and silicon oxide, and the material of the first bonding structure 110 includes a conductive material, including, but not limited to, tungsten, copper, and aluminum. The third dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer stacked along a first direction, and the first bonding structure 110 includes a first sub-bonding structure 110-1 and a second sub-bonding structure 110-2 stacked along the first direction.

[0031] In some specific examples, such as Figure 3 As shown, the first interconnect structure 142 is connected to the first bonding structure 110 in the first hybrid bonding layer 108 and is also connected to the modulator.

[0032] In some embodiments, such as Figure 2 As shown, the second semiconductor structure 109 further includes a second substrate 119 and a second interconnect layer 120 stacked sequentially along a first direction, the second interconnect layer 120 being located between the second substrate 119 and the first hybrid bonding layer 108; the modulator driving circuit 104 is located in the second substrate 119 and between the second substrate 119 and the second interconnect layer 120.

[0033] In some specific examples, the second substrate 119 includes, but is not limited to, a single-element semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., a germanium-silicon (SiGe) substrate, etc.), at least one III-V compound semiconductor material (e.g., a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc.

[0034] In some specific examples, the modulator drive circuit 104 is formed on the front side of the second substrate 119, such as... Figure 3 As shown, the second interconnect layer 120 includes a fourth dielectric layer and a second interconnect structure 143 located in the fourth dielectric layer. The second interconnect structure 143 connects the modulator drive circuit 104 to the first bonding structure 110.

[0035] In some embodiments, such as Figure 4 As shown, the third semiconductor structure 111 further includes a third interconnect layer 121, a third substrate 122, and a second waveguide layer 123 stacked sequentially along a first direction; the third interconnect layer 121 is located between the second hybrid bonding layer 112 and the third substrate 122; the detector structure 105 includes a detector and a second waveguide structure 124; the second waveguide structure 124 is located in the second waveguide layer 123, and the detector is located in the third substrate 122 and between the third substrate 122 and the third interconnect layer 121.

[0036] Here, the third substrate 122 can be a semiconductor substrate, including but not limited to a single semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., a germanium-silicon (SiGe) substrate, etc.), at least one III-V compound semiconductor material (e.g., a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc.

[0037] The second waveguide layer 123 includes a fifth dielectric layer and a second waveguide structure 124 located within the fifth dielectric layer. The material of the fifth dielectric layer includes, but is not limited to, silicon oxide, and the material of the second waveguide structure 124 includes, but is not limited to, silicon or silicon nitride. The third interconnect layer 121 includes a sixth dielectric layer and a third interconnect structure 144 located within the sixth dielectric layer. The material of the sixth dielectric layer includes, but is not limited to, silicon oxide. The material of the third interconnect structure 144 includes a conductive material.

[0038] In some embodiments, the detector structure 105 includes an InGaAs detector.

[0039] In some specific examples, the third substrate 122 is an indium phosphide (InP) substrate, and the third substrate 122 includes a front side and a back side, with the detector formed on the front side of the third substrate 122. For example... Figure 6 As shown, the detector may include an indium phosphide substrate 154, an indium phosphide buffer layer 155, an indium phosphide absorber layer 156, an indium phosphide cap layer 157, and a second electrode 158. The indium phosphide substrate 154, the indium phosphide buffer layer 155, the indium phosphide absorber layer 156, and the indium phosphide cap layer 157 are all, for example, N-type doped. A P-type doped region 159 is formed in the indium phosphide cap layer 157, and the P-type doped region 159 in the indium phosphide cap layer 157 is connected to the second electrode 158.

[0040] In some specific examples, such as Figure 6 As shown, the second hybrid bonding layer 112 includes a seventh dielectric layer and a second bonding structure 114 located within the seventh dielectric layer. The material of the seventh dielectric layer includes, but is not limited to, silicon nitride and silicon oxide. The material of the second bonding structure 114 includes conductive materials, including, but not limited to, tungsten, copper, and aluminum. The seventh dielectric layer includes a third sub-dielectric layer and a fourth sub-dielectric layer stacked along a first direction. The second bonding structure 114 includes a third sub-bonding structure 114-1 and a fourth sub-bonding structure 114-2 stacked along the first direction.

[0041] In some specific examples, such as Figure 4 As shown, the third interconnect structure 144 is connected to the second bonding structure 114 in the second hybrid bonding layer 112 and is also connected to the detector.

[0042] In some embodiments, as shown in FIG. 1A, the semiconductor device further includes a sixth interconnection layer 128; the sixth interconnection layer 128 includes a fifth substrate 131 and a first conductive via structure 132 passing through the fifth substrate 131; the sixth interconnection layer 128 is bonded to the second chip 102 on a side of the second chip 102 away from the fifth interconnection layer 127. Figure 4 As shown in FIG. 1A, the fourth semiconductor structure 113 further includes a fourth substrate 125 and a fourth interconnection layer 126 stacked in sequence along the first direction; the fourth interconnection layer 126 is located between the fourth substrate 125 and the second hybrid bonding layer 112; the transimpedance amplification circuit 106 is located in the fourth substrate 125 and between the fourth substrate 125 and the fourth interconnection layer 126.

[0043] In some specific examples, the fourth substrate 125 includes, but is not limited to, a single-element semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., a silicon-germanium (SiGe) substrate, etc.), at least one III-V compound semiconductor material (e.g., a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc.

[0044] In some specific examples, the transimpedance amplification circuit 106 is formed on the front side of the fourth substrate 125; the fourth interconnection layer 126 includes an eighth dielectric layer and fourth interconnection structures 145 located in the eighth dielectric layer. The fourth interconnection structures 145 are connected to the second bonding structures 114.

[0045] In some embodiments, as shown in FIG. 1A, the semiconductor device further includes a sixth interconnection layer 128; the sixth interconnection layer 128 includes a fifth substrate 131 and a first conductive via structure 132 passing through the fifth substrate 131; the sixth interconnection layer 128 is bonded to the second chip 102 on a side of the second chip 102 away from the fifth interconnection layer 127. Figure 2 As shown in FIG. 1A, the semiconductor device further includes a sixth interconnection layer 128; the sixth interconnection layer 128 includes a fifth substrate 131 and a first conductive via structure 132 passing through the fifth substrate 131; the sixth interconnection layer 128 is bonded to the second chip 102 on a side of the second chip 102 away from the fifth interconnection layer 127.

[0046] In some embodiments, the sixth interconnection layer 128 is bonded to the first chip 101 on a side of the first chip 101 away from the fifth interconnection layer 127.

[0047] In some embodiments, as shown in FIG. 1A, the semiconductor device further includes a sixth interconnection layer 128; the sixth interconnection layer 128 includes a fifth substrate 131 and a first conductive via structure 132 passing through the fifth substrate 131; the sixth interconnection layer 128 is bonded to the second chip 102 on a side of the second chip 102 away from the fifth interconnection layer 127. Figure 2 As shown in FIG. 1A, the sixth interconnection layer 128 can further include corresponding interconnection structures composed of metal wires and contact structures between the second chip 102 and the first conductive via structure 132, first micro-bumps 160; the sixth interconnection layer 128 can further include corresponding interconnection structures on a side of the first conductive via structure 132 away from the second chip 102 and second micro-bumps 161.

[0048] In the embodiments of the present disclosure, the first chip 101 can be on the top, or the second chip 102 can be on the top. When the first chip 101 is on the top and the second chip 102 is on the bottom, the sixth interconnection layer 128 is located on the side away from the fifth interconnection layer 127 among the two sides opposite to each other along the first direction of the second chip 102, and is bonded to the second chip 102. When the first chip 101 is on the bottom and the second chip 102 is on the top, the sixth interconnection layer 128 is located on the side away from the fifth interconnection layer 127 among the two sides opposite to each other along the first direction of the first chip 101, and is bonded to the first chip 101. The bonding mode of the sixth interconnection layer 128 to the first chip 101 / second chip 102 can be micro-bump bonding, or hybrid bonding, or other bonding modes, which are not limited in the present disclosure. When the sixth interconnection layer 128 is bonded to the first chip 101, the sixth interconnection layer 128 can be bonded to the back surface of the second substrate 119 of the first chip 101; when the sixth interconnection layer 128 is bonded to the second chip 102, the sixth interconnection layer 128 can be bonded to the back surface of the fourth substrate 125 of the second chip 102.

[0049] In the embodiments of the present disclosure, the first chip 101 and the second chip 102 are bonded, and the first chip 101 and the second chip 102 can be directly bonded, or indirectly bonded through other layers.

[0050] The following first describes the direct bonding of the first chip 101 and the second chip 102, with the first chip 101 on the top and the second chip 102 on the bottom.

[0051] As shown in FIG. 1, the first chip 101 and the second chip 102 are directly bonded. Figure 7As shown, the first semiconductor structure 107 further includes a second conductive via structure 133 and a fifth sub-bonding layer 146; the fifth sub-bonding layer 146 includes a fifth sub-bonding structure 147 in a corresponding dielectric layer, the second conductive via structure 133 passes through the first waveguide layer 115 and the first substrate 116 in the first direction, one end of the second conductive via structure 133 in the first direction is connected with the first interconnection structure 142 in the first interconnection layer 117, and the other end is connected with the fifth sub-bonding structure 147. The third semiconductor structure 111 further includes a sixth sub-bonding layer 148, the sixth sub-bonding layer 148 includes a sixth sub-bonding structure 149 in a corresponding dielectric layer, the fifth sub-bonding structure 147 is connected with the sixth sub-bonding structure 149, and the third bonding structure includes the fifth sub-bonding structure 147 and the sixth sub-bonding structure 149. The second chip 102 further includes a fourth conductive via structure 135 passing through the second waveguide layer 123, the third substrate 122 and the third interconnection layer 121 in the first direction, one end of the fourth conductive via structure 135 in the first direction is connected with the sixth sub-bonding structure 149, and the other end is connected with the third interconnection structure 144 in the third interconnection layer 121. The fourth semiconductor structure 113 further includes a third conductive via structure 134; the third conductive via structure 134 passes through the fourth substrate 125 in the first direction, and one end of the third conductive via structure 134 in the first direction is connected with the fourth interconnection structure 145 in the fourth interconnection layer 126.

[0052] It can be understood that, in the case that the first chip 101 and the second chip 102 are directly bonded and connected, and the first chip 101 is above and the second chip 102 is below, the regulator structure and the regulator driving circuit in the first chip 101 are connected with, for example, the first conductive via structure 132 in the sixth interconnection layer 128 of the semiconductor device through the first interconnection structure 142, the second interconnection structure 143, the first bonding structure 110, the second conductive via structure 133, the third bonding structure, the fourth conductive via structure 135, the third interconnection structure 144, the second bonding structure 114, the fourth interconnection structure 145, and the third conductive via structure 134.

[0053] Next, further description is made in the case that the first chip 101 is above, the second chip 102 is below, and the first chip 101 and the second chip 102 are connected through other interlayer indirect bonding.

[0054] In some embodiments, as Figure 2 As shown, the semiconductor device further includes a fifth interconnection layer 127; the fifth interconnection layer 127 is located between the first chip 101 and the second chip 102 and is bonded and connected with both the first chip 101 and the second chip 102; the fifth interconnection layer 127 includes a fifth interconnection structure 129 and a third waveguide structure 130.

[0055] In some embodiments, the fifth interconnection layer 127 is bonded to the first waveguide layer 115 on one side and to the second waveguide layer 123 on the other side along the first direction, so that the first chip 101 and the second chip 102 are indirectly bonded by the fifth interconnection layer 127. The fifth interconnection layer 127 is bonded to the first chip 101 / second chip 102 by, for example, hybrid bonding or fusion bonding. The fifth interconnection structure 129 in the fifth interconnection layer 127 can be used for power supply / data transmission of the upper first chip 101, and the third waveguide structure 130 can be used for optical interaction between the first chip 101 and the second chip 102 and the external optical fiber.

[0056] In the embodiments of the present disclosure, the first waveguide layer 115 with the first waveguide structure 118 is arranged on the back of the first substrate 116, and the second waveguide layer 123 with the second waveguide structure 124 is arranged on the back of the third substrate 122, for optical interconnection; electrical interconnection is realized by the fifth interconnection structure 129 in the fifth interconnection layer 127; and optical transmission with the optical fiber array 140 and the laser 141 mentioned later is realized by the third waveguide structure 130 in the fifth interconnection layer 127.

[0057] In some embodiments, as shown in Figure 2 、 Figure 3 and Figure 4 , the sixth interconnection layer 128 is bonded to the second chip 102 on the side away from the fifth interconnection layer 127 along the first direction; the first semiconductor structure 107 further includes a second conductive via structure 133; the second conductive via structure 133 passes through the first waveguide layer 115 and the first substrate 116 along the first direction, and one end of the second conductive via structure 133 along the first direction is connected to the first interconnection structure 142 in the first interconnection layer 117, and the other end is connected to the fifth interconnection structure 129; the fourth semiconductor structure 113 further includes a third conductive via structure 134; the third conductive via structure 134 passes through the fourth substrate 125 along the first direction, and one end of the third conductive via structure 134 along the first direction is connected to the fourth interconnection structure 145 in the fourth interconnection layer 126, and the other end is connected to the first conductive via structure 132.

[0058] It can be understood that, as shown in Figure 2 、 Figure 3 and Figure 4 , in the case where the first chip 101 is on top and the second chip 102 is on the bottom, and the first chip 101 and the second chip 102 are indirectly bonded by the fifth interconnection layer 127, the first chip 101 realizes power supply / data transmission by the second conductive via structure 133 and the fifth interconnection structure 129, and the second chip 102 realizes power supply / data transmission by the third conductive via structure 134.

[0059] In some embodiments, as shown in FIG. 1A, the second chip 102 further includes a fourth conductive via structure 135 passing through the second waveguide layer 123, the third substrate 122, and the third interconnection layer 121 along the first direction; one end of the fourth conductive via structure 135 is connected with the fifth interconnection structure 129, and the other end is connected with the third interconnection structure 144. Figure 8

[0060] It can be understood that the fifth interconnection structure 129 in the fifth interconnection layer 127 can be connected with the first conductive via structure 132 in the sixth interconnection layer 128 through the fourth conductive via structure 135, the third interconnection structure 144, the second bonding structure 114, the fourth interconnection structure 145, and the third conductive via structure 134 in the second chip 102.

[0061] In some embodiments, as shown in FIG. 1A, the second chip 102 further includes a fourth conductive via structure 135 passing through the second waveguide layer 123, the third substrate 122, and the third interconnection layer 121 along the first direction; one end of the fourth conductive via structure 135 is connected with the fifth interconnection structure 129, and the other end is connected with the third interconnection structure 144. Figure 2

[0062] It can be understood that the second chip 102 can include two independent sub-chips, which are separated by a medium layer, and the fifth interconnection structure 129 in the fifth interconnection layer 127 can be connected with the first conductive via structure 132 in the sixth interconnection layer 128 through the fifth conductive via structure 139 in the second sub-chip 137.

[0063] The second sub-chip 137 in the above embodiments functions to provide a metal path for the upper chip (the first chip 101) to interact with the outside world. Optionally, if the lower chip (the first sub-chip 136) allows to make a sufficient number of fourth conductive via structures, which can be used by the upper chip (the first chip 101), the second sub-chip 137 can be removed; if the lower chip (the first sub-chip 136) makes too many conductive via structures, which leads to performance degradation, the second sub-chip 137 can be used.

[0064] In some embodiments, as shown in FIG. 1A, the second chip 102 further includes a fourth conductive via structure 135 passing through the second waveguide layer 123, the third substrate 122, and the third interconnection layer 121 along the first direction; one end of the fourth conductive via structure 135 is connected with the fifth interconnection structure 129, and the other end is connected with the third interconnection structure 144. Figure 2

[0065] ​​​In some embodiments, the fiber optic array 140 is located in the first semiconductor structure 107; or, the fiber optic array 140 and the first chip 101 are located on the same side of two opposing sides of the fifth interconnect layer 127 along a first direction, and the fiber optic array 140 and the first chip 101 are arranged side by side along a second direction; or, the fiber optic array 140 and the second chip 102 are located on the same side of two opposing sides of the fifth interconnect layer 127 along a first direction, and the fiber optic array 140 and the second chip 102 are arranged side by side along a second direction; the first direction is perpendicular to the second direction.

[0066] In this embodiment of the disclosure, the fiber optic array 140 can also be integrated into the semiconductor device. Regarding the location of the fiber optic array 140, such as... Figure 2 As shown, the fiber optic array 140 and the first chip 101 can be located on the same side of the fifth interconnect layer 127 opposite each other along the first direction, and the fiber optic array 140 and the first chip 101 can be arranged side by side along the second direction. The fiber optic array 140 can also be integrated into the same chip as the regulator structure, for example, located on the side of the regulator structure in the first semiconductor structure 107. The fiber optic array 140 can also be located on the same side of the fifth interconnect layer 127 opposite each other along the first direction, and the fiber optic array 140 and the second chip 102 can be arranged side by side along the second direction. This embodiment does not limit the position of the fiber optic array 140. The fiber optic array 140 can be mounted to the surface of the fifth interconnect layer 127 using optically transparent adhesive.

[0067] In some embodiments, such as Figure 9 As shown, the semiconductor device also includes a laser 141.

[0068] In some embodiments, the laser 141 and the first chip 101 are located on the same side of the fifth interconnect layer 127 opposite to each other along the first direction, and the laser 141 and the first chip 101 are arranged side by side along the second direction; or, the laser 141 and the second chip 102 are located on the same side of the fifth interconnect layer 127 opposite to each other along the first direction, and the laser 141 and the second chip 102 are arranged side by side along the second direction; the first direction is perpendicular to the second direction.

[0069] In this embodiment of the disclosure, the laser 141 can also be integrated into the semiconductor device. Regarding the location of the laser 141, such as... Figure 9 As shown, laser 141 and first chip 101 can be located on the same side of the fifth interconnect layer 127 opposite each other along the first direction, and laser 141 and first chip 101 can be arranged side-by-side along the second direction. Laser 141 can also be located on the same side of the fifth interconnect layer 127 opposite each other along the first direction, and laser 141 and second chip 102 can be arranged side-by-side along the second direction. Laser 141 and fiber array 140 can be... Figure 9As shown, the laser 141 and the fiber array 140 are located on the same side of the fifth interconnection layer 127 along the opposite sides of the first direction. The laser 141 and the fiber array 140 can also be located on different sides of the fifth interconnection layer 127 along the opposite sides of the first direction, respectively. The laser 141 can perform optical signal transmission through the third waveguide structure 130 in the fifth interconnection layer 127, and the laser 141 is connected with the fifth interconnection structure 129 in the fifth interconnection layer 127. The laser 141 can be bonded to the fifth interconnection layer 127, and the bonding mode includes but is not limited to hybrid bonding.

[0070] Based on the above semiconductor device, the embodiment of the present disclosure further provides a manufacturing method of a semiconductor device, such as Figure 10 As shown, the manufacturing method of the semiconductor device includes the following steps: step S1001: forming a first chip 101 and a second chip 102, respectively; the first chip 101 includes a modulator structure 103 and a modulator driving circuit 104; the second chip 102 includes a detector structure 105 and a transimpedance amplification circuit 106; step S1002: stacking the first chip 101 and the second chip 102 along a first direction.

[0071] In the embodiment of the present disclosure, the first chip 101 including the modulator structure 103 and the modulator driving circuit 104 and the second chip 102 including the detector structure 105 and the transimpedance amplification circuit 106 are formed respectively, and then the first chip 101 and the second chip 102 are stacked along the first direction, that is, the modulator structure 103 and the detector structure 105 are formed in different chips, so that the modulator and the detector can be flexibly compatible with the material system with better optical performance such as III-V compound and lithium niobate, and can be compatible with modulators and detectors prepared by different epitaxial materials.

[0072] Figures 11 to 14 The process schematic diagram of the manufacturing method of the semiconductor device provided by an embodiment of the present disclosure is shown in FIG. 10. The following will be further introduced in combination with Figures 10 to 14 The manufacturing method of the semiconductor device is further introduced.

[0073] Step S1001 is mainly to form the first chip 101 and the second chip 102, respectively.

[0074] In some embodiments, the first chip 101 and the second chip 102 can be formed synchronously.

[0075] In some embodiments, as shown in FIG. 11, the first chip 101 and the second chip 102 can be formed asynchronously. Figure 11As shown, forming the first chip 101 comprises: forming the first semiconductor structure 107 and the first sub hybrid bonding layer 162; the first semiconductor structure 107 comprises the modulator structure; forming the second semiconductor structure 109 and the second sub hybrid bonding layer 163; the second semiconductor structure 109 comprises the modulator driving circuit; bonding the first sub hybrid bonding layer 162 and the second sub hybrid bonding layer 163, so that the modulator structure and the modulator driving circuit are connected through the first bonding structure in the first hybrid bonding layer 108 composed of the first sub hybrid bonding layer 162 and the second sub hybrid bonding layer 163.

[0076] In some specific examples, the forming of the first semiconductor structure 107 and the first sub hybrid bonding layer 162 and the forming of the second semiconductor structure 109 and the second sub hybrid bonding layer 163 can be performed synchronously.

[0077] In some embodiments, forming the first semiconductor structure 107 comprises: providing the first substrate 116; sequentially forming the modulator of the modulator structure, the first interconnection layer 117 from the front surface of the first substrate 116; forming the first waveguide layer 115 from the back surface of the first substrate 116, the first waveguide layer 115 comprising the first waveguide structure 118 of the modulator structure 103; the first sub hybrid bonding layer 162 is formed on the first interconnection layer 117 of the front surface of the first substrate 116.

[0078] In some embodiments, forming the second semiconductor structure 109 comprises: providing the second substrate 119; sequentially forming the modulator driving circuit, the second interconnection layer 120 from the front surface of the second substrate 119; the second sub hybrid bonding layer 163 is formed on the second interconnection layer 120 of the front surface of the second substrate 119.

[0079] In some embodiments, as Figure 12 As shown, forming the second chip 102 comprises: forming the third semiconductor structure 111 and the third sub hybrid bonding layer 164; the third semiconductor structure 111 comprises the detector structure; forming the fourth semiconductor structure 113 and the fourth sub hybrid bonding layer 165; the fourth semiconductor structure 113 comprises the transimpedance amplification circuit; bonding the third sub hybrid bonding layer 164 and the fourth sub hybrid bonding layer 165, so that the detector structure and the transimpedance amplification circuit are connected through the second bonding structure of the second hybrid bonding layer 112 composed of the third sub hybrid bonding layer 164 and the fourth sub hybrid bonding layer 165.

[0080] In some specific examples, the forming of the third semiconductor structure 111 and the third sub hybrid bonding layer 164 and the forming of the fourth semiconductor structure 113 and the fourth sub hybrid bonding layer 165 can be performed synchronously.

[0081] In some embodiments, forming the third semiconductor structure 111 comprises: providing the third substrate 122; sequentially forming a detector of the detector structure, the third interconnection layer 121 from the front surface of the third substrate 122; forming the second waveguide layer 123 from the back surface of the second substrate 119, the second waveguide layer 123 comprising a second waveguide structure 124 of the detector structure; the third sub-hybrid bonding layer 164 is formed on the third interconnection layer 121 of the front surface of the third substrate 122.

[0082] In some embodiments, forming the fourth semiconductor structure 113 comprises: providing the fourth substrate 125; sequentially forming a transimpedance amplification circuit, the fourth interconnection layer 126 from the front surface of the fourth substrate 125; the fourth sub-hybrid bonding layer 165 is formed on the fourth interconnection layer 126 of the front surface of the fourth substrate 125.

[0083] The step S1002 is mainly to stack the first chip 101 and the second chip 102 along the first direction.

[0084] It can be understood that, in the embodiments of the present disclosure, the first chip 101 and the second chip 102 are bonded and connected, which can be directly bonding the first chip and the second chip, for example, hybrid bonding; the first chip and the second chip can also be indirectly bonded and connected through other layers, so as to stack the first chip 101 and the second chip 102 along the first direction.

[0085] The following will be further described by taking the example that the first chip and the second chip are indirectly bonded and connected through the fifth interconnection layer.

[0086] In combination Figure 13 In some embodiments, the manufacturing method further comprises: providing a seventh substrate; forming the fifth interconnection layer 127 on the seventh substrate; the fifth interconnection layer 127 comprises the fifth interconnection structure 129 and the third waveguide structure 130; and stacking the first chip 101 and the second chip 102 along the first direction, comprising: bonding one of the first chip 101 and the second chip 102 on the first surface of the fifth interconnection layer 127; removing the seventh substrate, and bonding the other of the first chip 101 and the second chip 102 on the second surface of the fifth interconnection layer 127.

[0087] Here, the first surface and the second surface are two surfaces of the fifth interconnection layer 127 opposite along the first direction, and the seventh substrate is on the second surface of the fifth interconnection layer 127. After removing the seventh substrate, the second surface of the fifth interconnection layer 127 is exposed.

[0088] In some embodiments, in combination Figure 11 and Figure 13, the second chip 102 is located between the fifth substrate 131 and the fifth interconnection layer 127; forming the first semiconductor structure 107 further includes: forming a second conductive via structure 133 passing through the first waveguide layer 115 and the first substrate 116 in the first direction; one end of the second conductive via structure 133 in the first direction is connected with the first interconnection structure 142 in the first interconnection layer 117, and the other end is connected with the fifth interconnection structure 129; combining Figure 12 and Figure 13 , forming the fourth semiconductor structure 113 further includes: forming a third conductive via structure 134 passing through the fourth substrate 125 in the first direction; one end of the third conductive via structure 134 in the first direction is connected with the fourth interconnection structure 145 in the fourth interconnection layer 126, and the other end is connected with the first conductive via structure 132.

[0089] In some embodiments, the manufacturing method further includes: as shown in Figure 13 , forming a sixth interconnection layer 128; bonding one side of the first chip 101 or the second chip 102, which is away from the fifth interconnection layer 127, to the sixth interconnection layer 128 in the first direction; forming the sixth interconnection layer 128 includes: providing the fifth substrate 131; forming the first conductive via structure 132 passing through the fifth substrate 131.

[0090] In some embodiments, forming the second chip 102 includes: combining Figure 13 , respectively forming a first sub-chip 136 and a second sub-chip 137; the first sub-chip 136 includes the third semiconductor structure 111, the second hybrid bonding layer 112, and the fourth semiconductor structure 113; the second sub-chip 137 includes the sixth substrate 138 and the fifth conductive via structure 139 passing through the sixth substrate 138 in the first direction; bonding the first sub-chip 136 and the second sub-chip 137 to the fifth interconnection layer 127; one end of the fifth conductive via structure 139 in the first direction is connected with the fifth interconnection structure 129, and the other end is connected with the first conductive via structure 132.

[0091] In some embodiments, forming the second chip 102 further includes: forming a fourth conductive via structure passing through the second waveguide layer 123, the third substrate 122, and the third interconnection layer 121 in the first direction; one end of the fourth conductive via structure in the first direction is connected with the fifth interconnection structure 129, and the other end is connected with the third interconnection structure 144 in the third interconnection layer 121.

[0092] It can be understood that in the case that a sufficient number of fourth conductive via structures can be formed in the second sub-chip, the first sub-chip can not be provided.

[0093] In some embodiments, the manufacturing method further includes: as shown in Figure 14As shown, the optical fiber array 140 is formed; the optical fiber array 140 is attached to one side of the fifth interconnection layer 127 along the first direction opposite sides; and / or the manufacturing method further comprises: forming a laser 141; the laser 141 is bonded on one side of the fifth interconnection layer 127 along the first direction opposite sides.

[0094] Taking the first chip 101 on top, the second chip 102 on the bottom, and the second chip 102 including the first sub-chip 136 and the second sub-chip 137 as an example, the process of forming the above semiconductor device includes: one, respectively forming the first semiconductor structure 107, the second semiconductor structure 109, the third semiconductor structure 111, and the fourth semiconductor structure 113, and mixedly bonding the first semiconductor structure 107 and the second semiconductor structure 109 to form the first chip 101, and mixedly bonding the third semiconductor structure 111 and the fourth semiconductor structure 113 to form the first sub-chip 136; two, reconstituting the second sub-chip 137 and the first sub-chip 136 into a wafer, and then performing wafer-to-wafer (W2W) level bonding with the fifth interconnection layer 127, for example, the bonding mode can be mixed bonding; three, performing die-to-wafer (D2W) level bonding of the upper layer first chip 101 and the fifth interconnection layer 127 to the upper surface of the fifth interconnection layer 127, for example, the bonding mode can be mixed bonding; four, bonding the composite die including the first sub-chip, the second sub-chip, the fifth interconnection layer, and the first chip to the sixth interconnection layer 128, for example, at the wafer-to-wafer (W2W) level or the die-to-wafer (D2W) level or the die-to-die (D2D) level, and the bonding mode is, for example, micro-bump bonding or mixed bonding; five, attaching the optical fiber array 140 to the upper surface using an optically transparent adhesive.

[0095] In the case where the first chip 101 is on top, the second chip 102 is on the bottom, the semiconductor device does not include the fifth interconnection layer 127, and the second chip 102 does not include the second sub-chip 137, after the first chip 101 and the second chip 102 are formed, the first chip 101 and the second chip 102 can be bonded at the die-to-die (D2D) level or the wafer-to-wafer (W2W) level or the die-to-wafer (D2W) level, for example, the bonding mode is mixed bonding; then, the composite die containing the first chip 101 and the second chip 102 is bonded to the sixth interconnection layer 128 at the die-to-die (D2D) level or the die-to-wafer (D2W) level, for example, the bonding mode is mixed bonding or micro-bump bonding.

[0096] It should be understood that any reference to an "embodiment" or "one embodiment" or "an embodiment" or "one implementation" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation of the disclosure. The appearance of the phrase in various places in the specification are not necessarily all referring to the same embodiment. Further, the particular features, structures, or characteristics can be combined in any suitable manner in one or more implementations. It will be appreciated that the sizes of the various processes in the preceding description are not necessarily the sizes of processes in any particular implementation. Rather, the sizes are intended to convey the relative significance of the processes to the disclosure. The sizes can be defined in various ways to indicate different levels of significance.

[0097] The methods disclosed in the several method embodiments provided by the disclosure can be combined in any suitable manner without conflict, to obtain new method embodiments.

[0098] The above description is merely illustrative of the disclosure, and the protection scope of the disclosure is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the disclosure, and all these changes and replacements should be encompassed in the protection scope of the disclosure.

Claims

1. A semiconductor device, characterized in that, include: A first chip and a second chip are stacked along a first direction; wherein, The first chip includes a modulator structure and a modulator driving circuit. The second chip includes a detector structure and a transimpedance amplifier circuit; the first chip and the second chip are bonded together.

2. The semiconductor device according to claim 1, characterized in that, The first chip includes a first semiconductor structure, a first hybrid bonding layer, and a second semiconductor structure stacked sequentially along the first direction; the first semiconductor structure includes the modulator structure, and the second semiconductor structure includes the modulator driving circuit. The first hybrid bonding layer includes a first bonding structure; the modulator structure and the modulator driving circuit are connected through the first bonding structure; The second chip includes a third semiconductor structure, a second hybrid bonding layer, and a fourth semiconductor structure stacked sequentially along the first direction; the third semiconductor structure includes the detector structure, and the fourth semiconductor structure includes the transimpedance amplifier circuit. Both the first semiconductor structure and the third semiconductor structure are located between the second hybrid bonding layer and the first hybrid bonding layer; the second hybrid bonding layer includes a second bonding structure; the detector structure and the transimpedance amplifier circuit are connected through the second bonding structure.

3. The semiconductor device according to claim 2, characterized in that, The first semiconductor structure further includes a first waveguide layer, a first substrate, and a first interconnect layer stacked sequentially along the first direction; the first interconnect layer is located between the first hybrid bonding layer and the first substrate; the modulator structure includes a modulator and a first waveguide structure; the first waveguide structure is located in the first waveguide layer, and the modulator is located in the first substrate and between the first substrate and the first interconnect layer; The second semiconductor structure further includes a second substrate and a second interconnect layer stacked sequentially along the first direction, the second interconnect layer being located between the second substrate and the first hybrid bonding layer; the modulator driving circuit is located in the second substrate and between the second substrate and the second interconnect layer.

4. The semiconductor device according to claim 3, characterized in that, The third semiconductor structure further includes a third interconnect layer, a third substrate, and a second waveguide layer stacked sequentially along the first direction; the third interconnect layer is located between the second hybrid bonding layer and the third substrate; the detector structure includes a detector and a second waveguide structure; the second waveguide structure is located in the second waveguide layer, and the detector is located in the third substrate and between the third substrate and the third interconnect layer; The fourth semiconductor structure further includes a fourth substrate and a fourth interconnect layer stacked sequentially along the first direction, the fourth interconnect layer being located between the fourth substrate and the second hybrid bonding layer; the transimpedance amplifier circuit is located in the fourth substrate and between the fourth substrate and the fourth interconnect layer.

5. The semiconductor device according to claim 4, characterized in that, The semiconductor device further includes a fifth interconnect layer and a sixth interconnect layer; wherein... The fifth interconnect layer is located between the first chip and the second chip, and is bonded to both the first chip and the second chip; the fifth interconnect layer includes a fifth interconnect structure and a third waveguide structure; The sixth interconnect layer includes a fifth substrate and a first conductive via structure passing through the fifth substrate; the sixth interconnect layer is located on one side of the first chip opposite to each other along the first direction, away from the fifth interconnect layer, and is bonded to the first chip; or, the sixth interconnect layer is located on one side of the second chip opposite to each other along the first direction, away from the fifth interconnect layer, and is bonded to the second chip.

6. The semiconductor device according to claim 5, characterized in that, The sixth interconnect layer is located on the side of the second chip that is away from the fifth interconnect layer on both sides opposite to each other along the first direction, and is bonded to the second chip; The first semiconductor structure further includes a second conductive via structure; the second conductive via structure passes through the first waveguide layer and the first substrate along the first direction, and one end of the second conductive via structure along the first direction is connected to the first interconnect structure in the first interconnect layer, and the other end is connected to the fifth interconnect structure. The fourth semiconductor structure further includes a third conductive via structure; the third conductive via structure passes through the fourth substrate along the first direction, one end of the third conductive via structure along the first direction is connected to the fourth interconnect structure in the fourth interconnect layer, and the other end is connected to the first conductive via structure.

7. The semiconductor device according to claim 6, characterized in that, The second chip further includes a fourth conductive via structure passing through the second waveguide layer, the third substrate, and the third interconnect layer along the first direction; one end of the fourth conductive via structure is connected to the fifth interconnect structure at opposite ends along the first direction, and the other end is connected to the third interconnect structure in the third interconnect layer; or, The second chip includes a first sub-chip and a second sub-chip arranged side by side along a second direction; the first sub-chip includes the third semiconductor structure, the second hybrid bonding layer, and the fourth semiconductor structure; the second chip includes a sixth substrate and a fifth conductive via structure passing through the sixth substrate along the first direction; One end of the fifth conductive via structure is connected to the fifth interconnect structure at its two opposite ends along the first direction, and the other end is connected to the first conductive via structure; the first direction is perpendicular to the second direction.

8. The semiconductor device according to claim 5, characterized in that, The semiconductor device further includes an optical fiber array; the optical fiber array is located in the first semiconductor structure; or, the optical fiber array and the first chip are located on the same side of two opposite sides of the fifth interconnect layer along the first direction, and the optical fiber array and the first chip are arranged side by side along the second direction; or, the optical fiber array and the second chip are located on the same side of two opposite sides of the fifth interconnect layer along the first direction, and the optical fiber array and the second chip are arranged side by side along the second direction; the first direction is perpendicular to the second direction.

9. The semiconductor device according to claim 5, characterized in that, The semiconductor device further includes a laser; the laser and the first chip are located on the same side of opposite sides of the fifth interconnect layer along the first direction, and the laser and the first chip are arranged side by side along the second direction; or, the laser and the second chip are located on the same side of opposite sides of the fifth interconnect layer along the first direction, and the laser and the second chip are arranged side by side along the second direction; the first direction is perpendicular to the second direction.

10. The semiconductor device according to claim 1, characterized in that, The modulator structure includes a thin-film lithium niobate modulator, and the detector structure includes an InGaAs detector.

11. A method for fabricating a semiconductor device, characterized in that, include: A first chip and a second chip are formed respectively; the first chip includes a modulator structure and a modulator driving circuit; the second chip includes a detector structure and a transimpedance amplifier circuit. The first chip and the second chip are stacked along the first direction.

12. The method for fabricating a semiconductor device according to claim 11, characterized in that, The formation of the first chip includes: A first semiconductor structure and a first sub-hybrid bonding layer are formed; the first semiconductor structure includes the modulator structure. A second semiconductor structure and a second sub-hybrid bonding layer are formed; the second semiconductor structure includes the modulator driving circuit. The first sub-hybrid bonding layer is bonded to the second sub-hybrid bonding layer, such that the modulator structure and the modulator driving circuit are connected through the first bonding structure of the first hybrid bonding layer composed of the first sub-hybrid bonding layer and the second sub-hybrid bonding layer; Forming the second chip includes: A third semiconductor structure and a third sub-hybrid bonding layer are formed; the third semiconductor structure includes the detector structure. A fourth semiconductor structure and a fourth sub-hybrid bonding layer are formed; the fourth semiconductor structure includes the transimpedance amplifier circuit. The third sub-hybrid bonding layer is bonded to the fourth sub-hybrid bonding layer, such that the detector structure and the transimpedance amplifier circuit are connected through a second bonding structure of a second hybrid bonding layer composed of the third sub-hybrid bonding layer and the fourth sub-hybrid bonding layer.

13. The method for fabricating a semiconductor device according to claim 12, characterized in that, Forming the first semiconductor structure includes: providing a first substrate; sequentially forming a modulator of the modulator structure and a first interconnect layer from the front side of the first substrate; forming a first waveguide layer from the back side of the first substrate, the first waveguide layer including the first waveguide structure of the modulator structure; and forming a first sub-hybrid bonding layer on the first interconnect layer on the front side of the first substrate. Forming the second semiconductor structure includes: providing a second substrate; sequentially forming the modulator driving circuit and the second interconnect layer from the front side of the second substrate; and forming the second sub-hybrid bonding layer on the second interconnect layer on the front side of the second substrate. Forming the third semiconductor structure includes: providing a third substrate; sequentially forming a detector of the detector structure and a third interconnect layer from the front side of the third substrate; forming a second waveguide layer from the back side of the second substrate, the second waveguide layer including the second waveguide structure of the detector structure; and forming a third sub-hybrid bonding layer on the third interconnect layer on the front side of the third substrate. Forming the fourth semiconductor structure includes: providing a fourth substrate; sequentially forming the transimpedance amplifier circuit and the fourth interconnect layer from the front side of the fourth substrate; and forming the fourth sub-hybrid bonding layer on the fourth interconnect layer on the front side of the fourth substrate.

14. The method for fabricating a semiconductor device according to claim 13, characterized in that, The manufacturing method further includes: A seventh substrate is provided; a fifth interconnect layer is formed on the seventh substrate; the fifth interconnect layer includes a fifth interconnect structure and a third waveguide structure; Stacking the first chip and the second chip along a first direction includes: bonding one of the first chip and the second chip to a first side of the fifth interconnect layer; removing the seventh substrate and bonding the other of the first chip and the second chip to a second side of the fifth interconnect layer; The fabrication method further includes: forming a sixth interconnect layer; bonding one side of the first chip or the second chip away from the fifth interconnect layer from two opposite sides along the first direction to the sixth interconnect layer; forming the sixth interconnect layer includes: providing a fifth substrate; forming a first conductive via structure through the fifth substrate.

15. The method for fabricating a semiconductor device according to claim 14, characterized in that, The second chip is located between the fifth substrate and the fifth interconnect layer; The formation of the first semiconductor structure further includes: forming a second conductive via structure that passes through the first waveguide layer and the first substrate along the first direction; one end of the second conductive via structure along the first direction is connected to a first interconnect structure in the first interconnect layer, and the other end is connected to the fifth interconnect structure. The formation of the fourth semiconductor structure further includes: forming a third conductive via structure that passes through the fourth substrate along the first direction; one end of the third conductive via structure along the first direction is connected to the fourth interconnect structure in the fourth interconnect layer, and the other end is connected to the first conductive via structure.

16. The method for fabricating a semiconductor device according to claim 15, characterized in that, Forming the second chip further includes: forming a fourth conductive via structure that passes through the second waveguide layer, the third substrate, and the third interconnect layer along the first direction; one end of the fourth conductive via structure is connected to the fifth interconnect structure at opposite ends along the first direction, and the other end is connected to the third interconnect structure in the third interconnect layer; or, Forming the second chip includes: forming a first sub-chip and a second sub-chip respectively; the first sub-chip includes the third semiconductor structure, the second hybrid bonding layer and the fourth semiconductor structure; the second sub-chip includes a sixth substrate and a fifth conductive via structure passing through the sixth substrate along the first direction; bonding the first sub-chip and the second sub-chip to the fifth interconnect layer; one end of the fifth conductive via structure is connected to the fifth interconnect structure at opposite ends along the first direction, and the other end is connected to the first conductive via structure.

17. The method for fabricating a semiconductor device according to claim 14, characterized in that, The manufacturing method further includes: forming an optical fiber array; attaching the optical fiber array to one of the two opposite sides of the fifth interconnect layer along the first direction; And / or, The fabrication method further includes: forming a laser; and bonding the laser to one side of the two opposite sides of the fifth interconnect layer along the first direction.

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