Multi-device training flow to reduce process recipe time for computationally guided inspection

Abstract

A method of training a computational defect probability model to guide an inspection using an inspection tool is disclosed. More specifically, a method of combining input data from a plurality of devices, correlating metrology data with defect data from devices processed according to the same device manufacturing technology to train a computational defect probability, and applying the trained computational defect probability model to a guided inspection is disclosed. A computational defect probability prediction model is disclosed for generating defective die probability estimates in a shorter time with improved accuracy and versatility to guide inspection.

Description

Cross Reference to Related Applications

[0001] This application claims priority to U.S. Application 63 / 528,624, filed July 24, 2023, which is incorporated by reference in its entirety. TECHNICAL FIELD

[0002] Embodiments provided herein relate to training a computational defect probability model, and more specifically to methods of training a computational defect probability model using correlated defect metrology information input data from multiple devices and using the trained computational defect probability model to generate a sampling plan for device inspection to train a computational guided inspection model and improve model performance. BACKGROUND

[0003] In the manufacturing process of integrated circuits (ICs), unfinished or finished circuit components are inspected to ensure that they are manufactured according to the design and are free of defects. Inspection systems utilizing optical microscopes or charged particle (e.g., electron) beam microscopes, such as scanning electron microscopes (SEMs), can be employed. As the physical size of IC components continues to shrink, the accuracy of defect detection and yield become more important. Various metrology tools are developed and used to check whether an IC is manufactured correctly. To improve defect inspection performance, a computational guided inspection (CGI) machine learning model can be used to assist tools by indicating regions of a wafer to be inspected. SUMMARY

[0004] Embodiments provided herein disclose a method of training a computational defect probability model, and more specifically a method of correlating data from multiple devices manufactured from the same device manufacturing technology to train a computational defect probability model for improved defect die probability modeling.

[0005] Some embodiments provide an apparatus for training a computational defect probability model to guide device inspection. The apparatus comprises a memory storing a set of instructions; and at least one processor configured to execute the set of instructions to cause the apparatus to perform operations. The operations comprise obtaining input data for a plurality of devices manufactured according to a same device manufacturing technology; correlating the input data for the plurality of devices; training a computational defect probability model based on the correlation; and generating a sampling plan to guide inspection of the plurality of devices.

[0006] Other advantages of the present disclosure will become apparent from the following description taken in conjunction with the accompanying drawings which illustrate, by way of example, certain embodiments of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0007] The above and other aspects of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which: BEST MODE FOR CARRYING OUT THE INVENTION

[0008] Figure 1 is a schematic diagram illustrating an example charged particle beam inspection system according to embodiments of the present disclosure.

[0009] Figure 2 is a schematic diagram illustrating an example multi-beam tool that can be part of an example charged particle beam inspection system according to embodiments of the present disclosure. Figure 1

[0010] Figure 3 is a schematic block diagram illustrating an example throughput of generating input data according to embodiments of the present disclosure.

[0011] Figure 4 is an example block diagram illustrating training of a CGI model using an initial training data set.

[0012] Figure 5A is a diagram illustrating example components in time of generating a sampling plan for guided wafer inspection using a CGI model.

[0013] Figure 5B is an illustration of a conventional data collection workflow.

[0014] Figure 5C is an illustration of an example data collection workflow according to embodiments of the present disclosure to train a computational model using a plurality of devices manufactured by the same device manufacturing technology.

[0015] Figure 6 is a block diagram illustrating an example system for training a computational model according to embodiments of the present disclosure.

[0016] Figure 7 is a block diagram illustrating an example system of applying a trained computational model to guide inspection of a device according to embodiments of the present disclosure.

[0017] Figure 8 is a flowchart diagram illustrating an example method of training a computational model using correlated defect metrology information input data and generating a sampling plan for device inspection using a trained computational defect probability model according to embodiments of the present disclosure. DETAILED DESCRIPTION

[0018] ​Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings in which the same numbers represent the same or similar elements unless the context clearly dictates otherwise. The implementations set forth in the following description of exemplary embodiments are not meant to be all-inclusive or mutually exclusive. Instead, they are merely illustrative aspects that are consistent with the disclosed embodiments as recited in the appended claims. For example, although some embodiments are described in the context of an electron beam, the present disclosure is not limited thereto. Other types of charged particle beams (e.g., including protons, ions, muons, or any other particle that carries a charge) can be similarly applied. Further, other imaging systems can be used, such as optical imaging, photon detection, x-ray detection, ion detection, etc.

[0019] Electronic devices are constructed from circuits formed on a piece of semiconductor material known as a substrate. The semiconductor material can include, for example, silicon, gallium arsenide, indium phosphide, or silicon germanium, among others. Many circuits can be formed together on the same piece of silicon and are referred to as integrated circuits or ICs. The size of these circuits has been significantly reduced so that many of them can be packed on a substrate. Enhanced computing power of electronic devices can be achieved by significantly increasing the packing density of circuit components such as transistors, capacitors, diodes, and the like on an IC chip, while reducing the physical size of the device. For example, an IC chip of a smart phone the size of a fingernail can include over 2 billion transistors, each transistor smaller than 1 / 1000th of a human hair.

[0020] ICs can be manufactured using photolithography, which is a manufacturing process that involves drawing a complex circuit pattern on a mask deposited onto a substrate. Photolithography can be performed by a lithography apparatus, which is a machine that applies a source of radiation (e.g., light or X-rays) onto a target portion of a substrate to form a desired pattern. The target portion of the substrate can be covered with a patterning device (e.g., a mask), which can be eliminated or developed after exposure to the source of radiation. This process of transferring a desired pattern onto a substrate is referred to as a patterning process. The patterning process can include a patterning step of transferring a pattern from a patterning device (e.g., a mask) to a substrate. There can also be one or more related pattern processing steps, such as mask development by a developing device, baking the substrate using a baking tool, etching the pattern onto the substrate using an etching device, or other chemical and physical processing steps involved in fabricating a pattern on a substrate. Variations in experimental parameters (e.g., random variations, errors, or noise caused by inspection tools or pattern processing tools) can potentially limit photolithographic implementation of ICs in high volume manufacturing (HVM) or process yield and introduce defects into the IC structure.

[0021] In the manufacture of ICs using a lithographic apparatus, a number of lithographic patterning steps are typically performed, forming functional features in successive layers on a substrate. A key aspect of the performance of a lithographic apparatus is therefore the ability to place the applied pattern correctly and accurately with respect to features laid down in previous layers. To this end, the substrate is provided with one or more sets of alignment marks. Each mark is a structure having a position that can be subsequently measured using, for example, an electron beam inspection tool. Defects can occur when the applied pattern structure or pattern layer is incorrectly placed with respect to the reference marks, or when the manufacturing conditions are not optimal. The reference marks or layout define the desired structure, structure dimensions, and distances between IC structures, such as gates, capacitors, etc., or interconnect lines. This can ensure that the IC devices or lines do not interact with each other in an undesirable way. The structure limits provided by the reference layout are often referred to as critical dimensions. A critical dimension of a circuit can be defined as the minimum width of a line or hole, or the minimum spacing between two lines or holes. The critical dimensions therefore determine the overall size and packing density of the designed IC. The goal of IC manufacturing is to faithfully reproduce the original IC design on the substrate. If errors occur during manufacturing, causing the IC design pattern produced to not match the reference design, this can result in defects in the IC structure and render the IC inoperable.

[0022] Manufacturing these ICs with extremely small structures or components is a complex, time-consuming and expensive process, often involving hundreds of individual steps. Even an error in one step can have the potential to significantly affect the functionality of the final product. Even one "killer defect" can cause a device to fail. The goal of the manufacturing process is to improve the overall yield of the process. For example, to achieve a 75% yield for a 50-step process, each individual step must have a yield greater than 99.4%, and if the individual step yield is 95%, the overall process yield drops to 7%.

[0023] While high process yields are desired in IC chip manufacturing facilities, it is also necessary to maintain high wafer throughput, defined as the number of wafers processed per hour. High process yields and high wafer throughput can be impacted by the presence of defects, particularly if operator intervention is required to inspect the defects. Therefore, high throughput detection and identification of micron and nanometer scale defects is desired. One component of improving process yields and wafer throughput can be monitoring the IC manufacturing process to ensure that a desired number of defect-free ICs are produced. One way to monitor the manufacturing process is to inspect the chip circuit structures at various stages of the manufacturing. Inspection using tools such as charged particle beam inspection tools can be used to this effect to maintain high process yields and high wafer throughput. Inspecting a wafer using an electron beam inspection tool can generate an image of the wafer to measure the IC structure dimensions. The measured dimensions can be compared to a reference structure that is free of any defects to determine the presence of defects in the imaged structure. If the structure has defects, the manufacturing process can be adjusted so that defects are less likely to occur again. However, since a wafer can contain up to 1 billion IC structures, inspecting the ICs for defect detection is often a time consuming process and can not be able to inspect the wafer at the right location to identify defects.

[0024] A compute guided inspection (CGI) process guides an inspection tool to locations on a wafer where there is a higher probability of defects. A CGI machine learning model receives inputs from various data sources, such as wafer characteristic data, which can include scanner data, metrology data, and manufacturing process data, to train the model with inspection results. The CGI machine learning model can be built and used to output a sampling plan that indicates locations on the wafer where defects are likely to form after a wafer processing step, so that the inspection tool will reach the sampling locations to perform inspection with higher efficiency than inspecting wafer locations based on experience, e.g., history of previous defects detected during scanning. The CGI process occurs online with wafer manufacturing and improves inspection tool efficiency by increasing the accuracy of finding defects on the wafer at a higher than baseline value of the capture rate of finding defects. The inspection results can be used to confirm that a satisfactory wafer yield is maintained throughout the manufacturing process and to project the failure rate or die loss per wafer at the end of production. The projected failure rate can be compared to the results of wafer probe testing, which determines the failure rate of each die manufactured on the wafer. The final metric for the CGI model use case can be the R 2 elation score between the estimated and measured die defects for a wafer.

[0025] The CGI model can be applied to the lot data to estimate the probability of defects for each die on the wafer. A sampling plan optimizer or generator then aggregates the estimated probability of defective dies for each die on the wafer to generate a probability of defective die map or sampling plan. The sampling plan can be generated according to input information that defines the predetermined wafer area definition and sampling budget for each wafer area. The sampling plan can then be used to direct an inspection tool (e.g., a scanning electron microscope (SEM) or optical tool) to areas on the wafer where the sampling plan has a set number of dies to inspect (e.g., the sampling budget). The inspection results obtained via the sampling plan indicate the number of actual defective dies that are present, and the inspection results can then be used to project the estimated die yield for the wafer. Thus, the CGI-generated sampling plan used to direct the inspection can be referred to as a "validated sampling plan." The R 2 score of the CGI model sampling plan can be determined by collecting "ground truth" results for the wafer. The "ground truth" results indicate the actual defective die results for the wafer at the end of production, and correspond to the probe test results for the fully completed wafer. Thus, the probe test results provide accurate identification of defects for each die on the wafer. The final measure of the CGI model can be the correlation R 2 score between the projected estimated die yield determined by the CGI model and the actual die yield determined by the probe test results.

[0026] To generate a sampling plan, input data must be supplied to train a CGI model. Typically, in current CGI model setup procedures, the input data includes input metrology data and probe data from a single device. Once a CGI model is available (e.g., trained), the trained CGI model is applied to generate a dynamic sampling plan for an incoming wafer with the same device manufactured on top of the wafer. However, to manufacture a new device in HVM, where the manufacturing tools have not fully ramped up after going on line, the run rate (e.g., wafer manufacturing rate) is typically lower. Therefore, it takes a longer time to collect a sufficient amount of input data to train a CGI model to guide inspection of the new device manufactured on the wafer. This can increase the time to generate a working CGI model, thereby reducing throughput during HVM. Additionally, if the device manufactured onto a wafer in HVM does not have an existing trained CGI model, a new CGI model needs to be trained based on input data from the same device manufactured on other wafers. This can occur in HVM use cases where multiple manufacturing tools can be running simultaneously to manufacture different devices on different wafers, and ramping up production at different rates. Therefore, wafers can be manufactured and available to train a CGI model at different times, and thus multiple CGI models can need to be trained to account for multiple devices. As a result, current CGI model setup procedures can take an undesirably long time to establish a working CGI model, and thus adversely affect wafer inspection throughput during HVM. It should be appreciated that a device can be an electronic device manufactured on top of a wafer substrate. Example devices include, but are not limited to, DRAM, 3D-NAND, FinFET, MOSFET, and other memory, logic, or flash memory devices.

[0027] Embodiments of the present disclosure can provide a method of training and generating a computational defect probability model using input data from multiple devices manufactured on multiple wafers. In some embodiments, the present disclosure can provide a method of reducing the time for training a computational defect probability model and generating a sampling plan to guide device inspection. In some embodiments, the "process recipe time" for computing a defect probability model is reduced. In some embodiments, a multi-device model training workflow is used to combine input data for multiple devices sharing the same device manufacturing technology. In some embodiments, the multi-device model training workflow can be applied simultaneously to a first plurality of devices manufactured according to a first device manufacturing technology and a second plurality of devices manufactured according to a second device manufacturing technology. In some embodiments, a trained computational model is provided that can maintain the expected die yield and R 2Accuracy of correlation scores. Some embodiments of the present disclosure can provide a method of improving CGI model performance and versatility to guide wafer inspection. Some embodiments of the present disclosure can provide a method of maintaining defect inspection accuracy and yield of defect-free wafers throughout HVM.

[0028] For clarity, relative dimensions of the components in the drawings can be exaggerated. In the following description of the drawings, like or similar components are referred to with like or similar reference numerals, and differences with respect to the various embodiments are only described with respect to the differences. As used herein, the term “or” encompasses all possible combinations, unless otherwise specifically stated, unless otherwise specifically stated or impractical. For example, if a component is stated to include A or B, then, unless specifically stated otherwise or impractical, the component can include A, or B, or A and B. As a second example, if a component is stated to include A, B, or C, then, unless specifically stated otherwise or impractical, the component can include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.

[0029] Figure 1 An example electron beam inspection (EBI) system 100 according to embodiments of the present disclosure is illustrated. The EBI system 100 can be used for imaging. As shown in Figure 1 The EBI system 100 includes a main chamber 101, a load / lock chamber 102, a beam tool 104, and an equipment front end module (EFEM) 106. The beam tool 104 is located within the main chamber 101. The EFEM 106 includes a first load port 106a and a second load port 106b. The EFEM 106 can include additional load port(s). The first load port 106a and the second load port 106b receive wafer front opening unified pods (FOUPs) containing wafers (e.g., semiconductor wafers or wafers made of other material(s)) or samples to be inspected (wafers and samples can be used interchangeably). A “lot” is a plurality of wafers that can be loaded as a batch for wafer processing.

[0030] One or more robotic arms (not shown) in the EFEM 106 can transport the wafers to the load / lock chamber 102. The load / lock chamber 102 is connected to a load / lock vacuum pump system (not shown) that removes gas molecules in the load / lock chamber 102 to reach a first pressure that is lower than atmospheric pressure. After reaching the first pressure, one or more robotic arms (not shown) can transport the wafers from the load / lock chamber 102 to the main chamber 101. The main chamber 101 is connected to a main chamber vacuum pump system (not shown) that removes gas molecules in the main chamber 101 to reach a second pressure that is lower than the first pressure. After reaching the second pressure, the wafers are subjected to inspection by the beam tool 104. The beam tool 104 can be a single-beam system or a multi-beam system.

[0031] Controller 109 is electrically connected to beam tool 104. Controller 109 can be a computer configured to perform various controls of EBI system 100. Although controller 109 is shown in FIG. 1 as being external to the structure including main chamber 101, load / lock chamber 102, and EFEM 106, it should be appreciated that controller 109 can be part of the structure. Figure 1

[0032] In some embodiments, controller 109 can include one or more processors (not shown). A processor can be a general or special purpose electronic device capable of manipulating or processing information. For example, a processor can include any combination of any number of central processing units (or “CPUs”), graphics processing units (or “GPUs”), light processors, programmable logic controllers, microcontrollers, microprocessors, digital signal processors, intellectual property (IP) cores, programmable logic arrays (PLAs), programmable array logic (PALs), generic array logic (GALs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), systems on a chip (SoCs), application-specific integrated circuits (ASICs), and any type of circuit capable of data processing. A processor can also be a virtual processor that includes one or more processors distributed across multiple machines or devices coupled via a network.

[0033] In some embodiments, controller 109 can also include one or more memories (not shown). A memory can be a general or special purpose electronic device capable of storing code and data that can be accessed by a processor (e.g., via a bus). For example, a memory can include any combination of any number of random access memories (RAMs), read only memories (ROMs), optical discs, magnetic discs, hard disc drives, solid state drives, flash drives, secure digital (SD) cards, memory sticks, compact flash (CF) cards, or any type of storage device. Code and data can include an operating system (OS) and one or more application programs (or “apps”) for specific tasks. A memory can also be a virtual memory that includes one or more memories distributed across multiple machines or devices coupled via a network.

[0034] Figure 2 FIG. 1 illustrates a schematic diagram of an example multi-beam tool 104 (also referred to herein as apparatus 104) and an image processing system 290 that can be configured for use in EBI system 100 in accordance with embodiments of the present disclosure. Figure 1

[0035] ​​Beam tool 104 includes a charged particle source 202, a gun aperture 204, a condenser lens 206, a primary charged particle beam 210 emitted from charged particle source 202, a source conversion unit 212, a plurality of sub-beams 214, 216, and 218 of primary charged particle beam 210, a primary projection optics system 220, an actuated wafer stage 280, a wafer holder 282, a plurality of secondary charged particle beams 236, 238, and 240, a secondary optics system 242, and a charged particle detection apparatus 244. Primary projection optics system 220 can include a beam separator 222, a deflection scanning unit 226, and an objective lens 228. Charged particle detection apparatus 244 can include probe sub-areas 246, 248, and 250.

[0036] Charged particle source 202, gun aperture 204, condenser lens 206, source conversion unit 212, beam separator 222, deflection scanning unit 226, and objective lens 228 can be aligned with a primary optical axis 260 of apparatus 104. Secondary optics system 242 and charged particle detection apparatus 244 can be aligned with a secondary optical axis 252 of apparatus 104.

[0037] Charged particle source 202 can emit one or more charged particles, such as electrons, protons, ions, muons, or any other particle that carries an electric charge. In some embodiments, charged particle source 202 can be an electron source. For example, charged particle source 202 can include a cathode, an extractor, or an anode, where primary electrons can be emitted from the cathode and extracted or accelerated to form primary charged particle beam 210 (in this case, a primary electron beam) with a crossover 208 (virtual or real). For ease of explanation without causing ambiguity, electrons are used as an example in some descriptions herein. However, it should be noted that any charged particle can be used in any embodiment of the present disclosure without being limited to electrons. Primary charged particle beam 210 can be visualized as being emitted from crossover 208. Gun aperture 204 can block peripheral charged particles of primary charged particle beam 210 to reduce a Coulomb effect. The Coulomb effect can cause an increase in a probe spot size.

[0038] Source conversion unit 212 can include an imaging element array and a limiting aperture array. The imaging element array can include a micro-deflector or a micro-lens array. The imaging element array can form a plurality of parallel images (virtual or real) of crossover 208 with a plurality of sub-beams 214, 216, and 218 of primary charged particle beam 210. The limiting aperture array can limit the plurality of sub-beams 214, 216, and 218. Although in the example of FIG. 1, the imaging element array and the limiting aperture array are shown as being separate components, in other embodiments, the imaging element array and the limiting aperture array can be combined into a single component. Figure 2Three sub-beams 214, 216, and 218 are shown in FIG. 2, but embodiments of the present disclosure are not limited thereto. For example, in some embodiments, the apparatus 104 can be configured to generate a first number of sub-beams. In some embodiments, the first number of sub-beams can be in a range from 1 to 1000. In some embodiments, the first number of sub-beams can be in a range from 200-500. In an exemplary embodiment, the apparatus 104 can generate 400 sub-beams.

[0039] The condenser lens 206 can focus the primary charged particle beam 210. The current of the sub-beams 214, 216, and 218 downstream of the source conversion unit 212 can be changed by adjusting the focusing power of the condenser lens 206 or by changing the radial size of the corresponding limiting aperture within the limiting aperture array. The objective lens 228 can focus the sub-beams 214, 216, and 218 onto the wafer 230 for imaging and can form a plurality of probe spots 270, 272, and 274 on the surface of the wafer 230.

[0040] The beam separator 222 can be a Wien filter type of beam separator that generates an electrostatic dipole field and a magnetic dipole field. In some embodiments, the force exerted by the electrostatic dipole field on the charged particles (e.g., electrons) of the sub-beams 214, 216, and 218, if they are applied, can be substantially equal in magnitude and opposite in direction to the force exerted by the magnetic dipole field on the charged particles. Thus, the sub-beams 214, 216, and 218 can pass directly through the beam separator 222 with a zero deflection angle. However, the total dispersion of the sub-beams 214, 216, and 218 generated by the beam separator 222 can also be non-zero. The beam separator 222 can separate the secondary charged particle beams 236, 238, and 240 from the sub-beams 214, 216, and 218 and direct the secondary charged particle beams 236, 238, and 240 toward the secondary optical system 242.

[0041] The deflection scanning unit 226 can deflect the beamlets 214, 216, and 218 to scan the probe points 270, 272, and 274 over a surface region of the wafer 230. In response to the incidence of the beamlets 214, 216, and 218 at the probe points 270, 272, and 274, secondary charged particle beams 236, 238, and 240 can be emitted from the wafer 230. The secondary charged particle beams 236, 238, and 240 can include charged particles (e.g., electrons) having an energy distribution. For example, the secondary charged particle beams 236, 238, and 240 can be secondary electron beams including secondary electrons (energy < 50 eV) and backscattered electrons (energy between 50 eV and the landing energy of the beamlets 214, 216, and 218). The secondary optics system 242 can focus the secondary charged particle beams 236, 238, and 240 onto detection sub-areas 246, 248, and 250 of a charged particle detection device 244. The detection sub-areas 246, 248, and 250 can be configured to detect the corresponding secondary charged particle beams 236, 238, and 240 and generate corresponding signals (e.g., voltage, current, etc.) that are used to reconstruct an SCPM image of the structure above or below the surface region of the wafer 230.

[0042] The generated signals can represent the intensities of the secondary charged particle beams 236, 238, and 240 and can be provided to an image processing system 290 that is in communication with the charged particle detection device 244, the primary projection optics system 220, and the actuated wafer stage 280. The movement speed of the actuated wafer stage 280 can be synchronized and coordinated with the beam deflection controlled by the deflection scanning unit 226 such that the movement of the scanned probe points (e.g., the scanned probe points 270, 272, and 274) can orderly cover the region of interest on the wafer 230. The parameters of this synchronization and coordination can be adjusted to accommodate different materials of the wafer 230. For example, different materials of the wafer 230 can have different resistance-capacitance characteristics, which can cause different signal sensitivities to the movement of the scanned probe points.

[0043] The intensities of the secondary charged particle beams 236, 238, and 240 can vary depending on the external or internal structure of the wafer 230 and, thus, can indicate whether the wafer 230 includes a defect. Moreover, as discussed above, the beamlets 214, 216, and 218 can be projected onto different locations of the top surface of the wafer 230 or onto different sides of the local structure of the wafer 230 to generate the secondary charged particle beams 236, 238, and 240 that can have different intensities. Thus, by mapping the intensities of the secondary charged particle beams 236, 238, and 240 to the regions of the wafer 230, the image processing system 290 can reconstruct an image that reflects the characteristics of the internal or external structure of the wafer 230.

[0044] In some embodiments, the image processing system 290 can include an image acquirer 292, a storage 294, and a controller 296. The image acquirer 292 can include one or more processors. For example, the image acquirer 292 can include a computer, a server, a mainframe, a terminal, a personal computer, any type of mobile computing device, or the like, or a combination thereof. The image acquirer 292 can be communicatively coupled to the charged particle detection device 244 of the beam tool 104 through a medium such as an electrical conductor, a fiber optic cable, a portable storage medium, IR, Bluetooth, the Internet, a wireless network, a radio, or a combination thereof. In some embodiments, the image acquirer 292 can receive signals from the charged particle detection device 244 and can construct images. Thus, the image acquirer 292 can acquire SCPM images of the wafer 230. The image acquirer 292 can also perform various post-processing functions such as generating contours, superimposing indicators on the acquired images, and the like. The image acquirer 292 can be configured to perform adjustments of brightness and contrast of the acquired images. In some embodiments, the storage 294 can be a storage medium such as a hard disk, a flash drive, a cloud memory device, a random access memory (RAM), other types of computer readable memory, or the like. The storage 294 can be coupled to the image acquirer 292 and can be used to save the scanned raw image data as raw images, as well as post-processed images. The image acquirer 292 and the storage 294 can be connected to the controller 296. In some embodiments, the image acquirer 292, the storage 294, and the controller 296 can be integrated together as one control unit.

[0045] In some embodiments, the image acquirer 292 can acquire one or more SCPM images of the wafer based on the imaging signals received from the charged particle detection device 244. The imaging signals can correspond to a scanning operation for constructing charged particle images. The acquired images can be a single image that includes a plurality of imaging regions. The single image can be stored in the storage 294. The single image can be a raw image that can be divided into a plurality of regions. Each region can include an imaging region that contains a feature of the wafer 230. The acquired images can include a plurality of images of a single imaging interval of the wafer 230 that are sampled a plurality of times over a time sequence. The plurality of images can be stored in the storage 294. In some embodiments, the image processing system 290 can be configured to perform image processing steps with a plurality of images of the same location of the wafer 230.

[0046] In some embodiments, the image processing system 290 can include a measurement circuit (e.g., an analog-to-digital converter) to obtain a distribution of detected secondary charged particles (e.g., secondary electrons). The charged particle distribution data collected during the detection time window, in conjunction with the corresponding scan path data of the beamlets 214, 216, and 218 incident on the wafer surface, can be used to reconstruct an image of the wafer structure under inspection. The reconstructed image can be used to reveal various features of the internal or external structure of the wafer 230, which can be used to reveal any defects that can exist in the wafer.

[0047] In some embodiments, the charged particles can be electrons. When the electrons of the primary charged particle beam 210 are projected onto the surface of the wafer 230 (e.g., the probe points 270, 272, and 274), the electrons of the primary charged particle beam 210 can penetrate a certain depth of the surface of the wafer 230, interact with the particles of the wafer 230. Some of the electrons of the primary charged particle beam 210 can interact elastically with the material of the wafer 230 (e.g., in the form of elastic scattering or collision), and can be reflected or backscattered out of the surface of the wafer 230. Elastic interaction conserves the total kinetic energy of the interacting body (e.g., the electron of the primary charged particle beam 210), where the kinetic energy of the interacting body is not converted into other forms of energy (e.g., thermal energy, electromagnetic energy, etc.). Such reflected electrons generated by elastic interaction can be referred to as backscattered electrons (BSEs). Some of the electrons of the primary charged particle beam 210 can interact inelastically with the material of the wafer 230 (e.g., in the form of inelastic scattering or collision). Inelastic interaction does not conserve the total kinetic energy of the interacting body, where some or all of the kinetic energy of the interacting body is converted into other forms of energy. For example, through inelastic interaction, the kinetic energy of some of the electrons of the primary charged particle beam 210 can cause electron excitation and transition of material atoms. Such inelastic interaction can also generate electrons that exit the surface of the wafer 230, which can be referred to as secondary electrons (SEs). The yield or emission rate of BSEs and SEs depends on, for example, the material being inspected and the landing energy of the electrons of the primary charged particle beam 210 landing on the surface of the material, etc. The electron energy of the primary charged particle beam 210 can be imparted in part by its acceleration voltage (e.g., the acceleration voltage between the anode and the cathode of the charged particle source 202 in FIG. 1A). Figure 2 The amount of BSEs and SEs can be more or less (or even the same) than the number of injected electrons of the primary charged particle beam 210.

[0048] Images generated by the SCPM can be used for defect inspection. For example, a generated image capturing a test device region of a wafer can be compared to a reference image capturing the same test device region. The reference image can be predetermined (e.g., by simulation) and does not include known defects. If a difference between the generated image and the reference image exceeds a tolerance level, a potential defect can be identified. For another example, the SCPM can scan multiple regions of a wafer, each region including a test device region designed to be the same, and generate multiple images capturing those test device regions as manufactured. The multiple images can be compared to each other. If a difference between the multiple images exceeds a tolerance level, a potential defect can be identified.

[0049] Although reference can be made in this disclosure to ICs, it should be appreciated that the disclosure can be applicable to other possible applications or designs. For example, the disclosure can be applied to integrated optical systems, magnetic domain memory, liquid crystal display panels, thin-film magnetic heads, and other nano-scale structures. It should also be appreciated that the terms “die,” “structure,” and “IC structure” are used interchangeably in this disclosure.

[0050] Reference is now made to Figure 3 FIG. 1 is a block diagram of an example system for generating input data according to embodiments of the disclosure. The system can be used to generate input data for a model that predicts a manufacturing condition of a lithographic projection apparatus. The system can include a lithographic projection apparatus 101, an inspection tool 102, and a processor 103 with memory. Figure 3 The lithographic projection apparatus 101 can be used to manufacture a wafer under constant manufacturing conditions (e.g., focus of a radiation source and dose). The inspection tool 102 (e.g., the EBI system 100 in Figure 3 or the multi-beam tool 104 in Figure 1 ) can be used to measure metrology information of structures formed on the wafer generated by the lithographic projection apparatus 101. The metrology information can include, but is not limited to, necking, line pullback, line thinning, critical dimension, edge placement, overlay, resist top loss, resist undercut, missing defects, and bridging defects of IC structures on the wafer. The processor 103 with memory can be communicatively connected to the inspection tool 102 to store the measured metrology information. Figure 2 Figure 1

[0051] ​​Images generated by the inspection tool 302 can be used for wafer inspection. For example, a generated image that captures a test device region of a wafer can be compared to a reference image that captures the same test device region. The reference image can be predetermined (e.g., by simulation) and does not include known defects. If a difference between the generated image and the reference image exceeds a tolerance level, a potential defect can be identified. For another example, the inspection tool 302 can scan multiple regions of a wafer, each region including a test device region designed to be the same, and generate multiple images that capture those test device regions as manufactured. The multiple images can be compared to each other. If a difference between the multiple images exceeds a tolerance level, a potential defect can be identified.

[0052] In some embodiments, the processor 303 can be a general or special purpose electronic device capable of manipulating or processing information. For example, the processor 303 can include any combination of any number of central processing units (or “CPUs”), graphics processing units (or “GPUs”), optical processors, programmable logic controllers, microcontrollers, microprocessors, digital signal processors, intellectual property (IP) cores, programmable logic arrays (PLAs), programmable array logic (PALs), generic array logic (GALs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), systems on a chip (SoCs), application-specific integrated circuits (ASICs), and any type of circuit capable of data processing. The processor 303 can also be a virtual processor that includes one or more processors distributed across multiple machines or devices coupled via a network.

[0053] In some embodiments, the processor 303 can further include one or more memories (not shown). The memory can be a general or special purpose electronic device capable of storing code and data that can be accessed by the processor (e.g., via a bus). For example, the memory can include any combination of any number of random access memories (RAMs), read only memories (ROMs), optical discs, magnetic discs, hard disc drives, solid-state drives, flash drives, secure digital (SD) cards, memory sticks, compact flash (CF) cards, or any type of memory device. The code and data can include an operating system (OS) and one or more application programs (or “apps”) for particular tasks. The memory can also be a virtual memory that includes one or more memories distributed across multiple machines or devices coupled via a network.

[0054] A conventional compute guided inspection (CGI) process directs an inspection tool to locations on a wafer where there is a higher probability of defects. As described above, a machine learning based CGI model receives input from various data sources, including wafer characteristic data such as scanner data, metrology data, and manufacturing process data, to train the model with inspection results. A CGI machine learning model can be built and used to output sampling locations on a wafer, so that the inspection tool will go to the sampling locations to perform inspection with higher efficiency than inspecting wafer locations based on experience (e.g., history of previous defects in a given location detected during scanning). Thus, the CGI model can use input data from a reference wafer (e.g., reference patterns according to manufacturing or wafer processing steps, metrology information, etc.) to guide future inspection of wafers processed during HVM. The CGI model improves inspection tool efficiency by improving the accuracy of finding defects on a wafer with a higher than baseline rate of capture of finding defects. However, for effective and accurate defect prediction capability, the CGI model needs a full set of input data for a wafer. This can include metrology information after each processing step for the wafer. As described above, conventional down-sampling of wafers at a lot / wafer level can result in an insufficient amount of metrology data collected for a wafer to be supplied to and train the CGI model.

[0055] Figure 4 is an example block diagram illustrating training of a CGI model 401 using an initial training data set according to various embodiments of the present disclosure. The CGI model 401 can be trained using an initial training data set 405 before it can be used to generate predictions for a wafer. The initial training data set 405 can be a labeled data set that includes process related data 410a-410n and inspection results 415a-415n for “n” substrates. For example, for wafer “A”, the initial training data set 405 can include process related data 410a and inspection results 415a associated with substrate “A”. The process related data 410a can include metrology data such as described above, or other such data that can result in defects. The inspection results 415a can include images of the inspected locations (e.g., SEM images), location information of the inspected locations (e.g., (x, y) coordinates), and whether the location was found to be defective or non-defective. The labeled data set can be obtained from various sources, including Figure 3 a lithographic projection apparatus 301 and an inspection tool 302.

[0056] The CGI model 401 can include a location prediction model 450 and a confidence model 455, both of which can be machine learning models. Training of the CGI model 401 can be an iterative process, where each iteration can involve analyzing process-related data 410 associated with a wafer, determining a cost function, and updating a configuration of the CGI model 401 based on the cost function. The CGI model 401 can be trained in a “batch” manner rather than an iterative process. For example, a training dataset 405 can be collectively inputted with process-related data 410a-410n and inspection results 415a-415n for “n” substrates. After inputting the process-related data 410a and the inspection results 415a, the location prediction model 450 generates predictions 425al-425ax for “x” locations on wafer “A,” and the confidence model 455 assigns confidence scores 430al-430ax for the predictions 425al-425ax, respectively. The CGI model 401 then compares the prediction results with the inspection results 415a to determine a cost function 460 of the CGI model 401, which can indicate a deviation between the prediction results 425al-425ax and the actual inspection results 415a. The CGI model 401 can update its configuration (e.g., weights, biases, or other parameters of the location prediction model 450 or the confidence model 455) based on the cost function 460 or other reference feedback information (e.g., user indications of accuracy, reference labels, or other information) to minimize the cost function 460. The above process is iteratively repeated with process-related data and inspection results associated with different substrates in each iteration until a termination condition is satisfied. The termination condition can include a predetermined number of iterations, the cost function satisfying a specified threshold, or other such conditions. After the termination condition is satisfied, the CGI model 401 can be considered “trained” and can be used to identify or predict defect locations in new wafers (e.g., wafers that have not been analyzed using the CGI model 401).

[0057] As described above with respect to Figure 4 Input data is used to train the CGI model. Reference is now made to FIG. 5, Figure 5A is an example diagram illustrating the time from data collection to generating a sampling plan for a pilot wafer inspection, according to embodiments of the present disclosure. Figure 5A The time 501 to generate a sampling plan for a pilot wafer inspection includes many components, the first of which is the time for data collection 502. The time for data collection 502 is the longest time component, which includes the time to generate a sampling plan for a pilot device inspection 501, also referred to as “process recipe time” (e.g., the time for data collection 502 is the largest contributor), and is in Figure 5AThe time 502 for data collection can be the time for collecting input data (e.g., measurement data for the device after a wafer processing step). The input data can be probe test data for a fully fabricated device on the wafer. In some embodiments, the time 502 for data collection can be the time for collecting input data for three fully fabricated devices on three wafers, respectively. When probe test data is available for fully fabricated devices, the time for data collection 502 and the time for fully fabricating the device on the wafer can be 10 weeks. The time 502 for data collection is described in further detail below. After the time 502 for data collection, the next component in the “process recipe time” can be the time 503 for data ingestion, where the input data acquired during the time 502 for data collection is ingested into a database for building a machine learning model. The time 504 for model training can be the time for training as described above for… Figure 4 The time for the described computational model, and then the time for generating the sampling plan 505, can be the time for generating the sampling plan for bootstrapping device checks. It should be understood that... Figure 5A The diagram illustrates the relative time amount for each time component (e.g., time 502 for data collection, time 503 for data ingestion, etc.). The time amount for each time component of "process formulation time" can be variable, but time 502 for data collection is likely the largest component.

[0058] Now to Figure 5B For reference, Figure 5B This is an example diagram of a typical data collection workflow. Figure 5B The diagram illustrates when input data for devices fabricated on the wafer as of time 501 is available during wafer processing. Specifically, Figure 5B The diagram illustrates the workflow of manufacturing tools 506 for the first device 506, 507 for the second device 507, 508 for the third device, and 509 for the fourth device. Each device 506-509 can be a different device or device ID (e.g., device 506 can be a DRAM device, device 507 can be a 3D-NAND device, etc.). Each device 506-509 can be manufactured onto wafer 50#_# using the same wafer manufacturing tools (e.g., manufacturing device 506 onto wafer 506_1). Each device 506-509 can be manufactured onto wafer 50#_# using multiple wafer manufacturing tools. Each device 506-509 can be manufactured onto the wafer at different operating rates. Figure 5B The operating rate is illustrated as the space between devices manufactured on a wafer with available input data (e.g., the space between wafer 506_1 and wafer 506_2). The operating rate can be variable between identical devices manufactured using the same wafer fabrication tools, and between different devices. It should be understood that...Figure 5B is an example illustration of the run rate of the devices 506-509, and embodiments of the present disclosure are not limited thereto. The input data for the devices can be metrology data and probe test data after wafer processing steps (e.g., when the devices are fully fabricated onto a wafer). It should be appreciated that, Figure 5B The wafers illustrated in FIG. 6 (e.g., wafers 506_1, 507_2, 509_2, etc.) represent when metrology data and probe test data are available for fully fabricated devices, and thus can be supplied to the computational model. According to conventional methods and systems, the input data needed to collect and be used to train the computational model for each device 506-509 is represented by the dashed rectangles. Thus, data collection can take different amounts of time to complete training of the computational model for each device 506-509. It should be appreciated that device 508 can be fabricated onto wafers 508_1-508_3 at a uniform run rate, and it can take 10 weeks to generate input data to fully train the computational CGI model (e.g., obtain metrology data after each wafer processing step and probe test results for fully fabricated devices). Because devices 506, 507, and 509 have non-uniform fabrication rates, it can take longer than 10 weeks to complete the data collection step to generate computational CGI models for those devices. In addition, input data from one device is not used as input data for another device. For example, the input data used to train the computational model for device 508 is not used to generate a computational model for device 509 after data collection for device 508 is complete. Rather, the computational model can only be applied to the same device (e.g., device 508). In conventional systems, once fabrication is underway for device 509, it must collect input data after each wafer processing step for device 509, which can take 10 weeks or more depending on the run rate of device fabrication for device 509 onto a wafer (e.g., wafer 509_1). Thus, according to conventional methods, data collection is performed repeatedly for each device to train the computational model. This can be cumbersome and time consuming for HVM use cases, as data collection for each device can take 10 weeks or more as described above.

[0059] Embodiments of the present disclosure can provide a method of training and generating a computational defect probability model for multiple devices. As Figure 5BAs illustrated, data collection according to conventional methods is repeatedly performed for each device to train a computational model for a single device (e.g., device 506). Embodiments of this disclosure can utilize input data from multiple devices to reduce the data collection time required to train a computational model that can be applied to multiple devices. In some embodiments, this disclosure can utilize input data from multiple devices manufactured according to the same device fabrication technology or technology node. Device fabrication technology can refer to a device manufacturing process used to manufacture devices with a specific feature size (e.g., transistor). Device fabrication technology can also be considered as a technology node (or process node, process technology, or node) and indicates the specific device fabrication process and design rules for the device manufactured onto a wafer. Device fabrication technology can be represented as a number followed by an abbreviation for nanometer (e.g., 22 nm, 14 nm, etc.). Smaller device fabrication technology may mean a more advanced generation of device fabrication process used to manufacture smaller IC structures. Devices manufactured according to smaller device fabrication technologies (e.g., 3 nm or 2 nm) produce smaller and more transistors on the IC chip, thus resulting in faster speeds and higher energy efficiency. Device fabrication technology can be considered as a CD indicating the features on an IC. However, more recent advanced device fabrication technologies, such as 3 nm or 2 nm, may not necessarily mean that CD is 3 nm and 2 nm respectively. Instead, smaller device fabrication technologies (e.g., 3 nm or 2 nm) may indicate a newer generation of device fabrication processes or tools that can fabricate devices with smaller features (e.g., transistors). Devices fabricated using the same device fabrication technology are also fabricated using the same wafer processing flow, which includes wafer processing steps such as, but not limited to, oxidation, photolithography, etching, implantation, metal deposition, polishing, dicing, die attachment, wire bonding, packaging, and testing. For devices fabricated using the same device fabrication technology, key differences may be die layout or die size on the wafer and measurement sampling locations. However, if there is a correlation or link between input data (e.g., measurement data and probe data) and the formation of defects of interest, the defects will remain the same for different devices fabricated using the same device fabrication technology.

[0060] Now to Figure 5C For reference, Figure 5C This is an example illustration of a data collection workflow for training a defect probability model using multiple devices manufactured using the same device fabrication technology, according to embodiments of this disclosure. Instead of waiting to collect data for three identical devices (e.g., fabricated on a wafer)... Figure 5B Instead of using input data from chips 506_1, 506_2, and 506_3 in order to train a computational model for a device (e.g., device 506), input data from multiple device IDs can be combined. Figure 5CThe multi-device input data collection workflow is illustrated by dashed rectangle 510, in which input data is collected on wafers 506_1, 507_1, and 508_1 on which devices 506, 507, and 508, respectively, are fully fabricated. The collected input data can be used to train a computational model for devices 506-508. As described above, the input data can be metrology data after wafer processing steps and probe test results for fully fabricated devices. Figure 5C The dashed rectangle 510 illustrates that the time required to collect input data for multiple wafer devices (e.g., devices 506-508) can be reduced. Compared to the dashed rectangles in Figure 5B The dashed rectangle 510 illustrates that the time required to collect input data for multiple wafer devices (e.g., devices 506-508) can be reduced. Compared to the dashed rectangles in Figure 5C The dashed rectangle 510 illustrates that the time required to collect input data for multiple wafer devices (e.g., devices 506-508) can be reduced. Compared to the dashed rectangles in Figure 5B The dashed rectangle in represents data collection for the above-described conventional approach. It should be appreciated that Figure 5C The dashed rectangle 510 illustrates a non-uniform fabrication rate for devices 506 to 508, but the present disclosure can include a uniform fabrication rate. In some embodiments, Figure 5C The multi-device flow illustrated in can reduce the data collection time to 1 / M, where M is the number of devices, and wafers are fabricated using the same wafer fabrication technology.

[0061] After training the computational defect probability model by the input data collected for wafers 506_1, 507_1, and 508_1, the trained computational defect probability model can be directly applied to subsequent wafers to generate a sampling plan once input data is available for devices on the subsequent wafers. The subsequent wafers can be wafers 506_2, 507_2, or 508_2, which contain the same devices used in training the computational defect probability model. In addition, the subsequent wafers can be wafer 509_1 on which device 509 is fabricated, and device 509 is not used to train the computational defect probability model. Since devices 506-509 are all fabricated according to the same device fabrication technology (e.g., technology node), the correlation between input data and the detection of interest can be equal for all devices 506-509. Therefore, the data collection time to train the computational defect probability model is reduced. In addition, no data collection is needed to train a computational defect probability model for a new device that is not used to train the computational model processed by the new wafer to fabricate a device (e.g., device 509 on wafer 509_1). The conventional approach and system as described above would train a new computational defect probability model for device 509, and thus can further increase the data collection time and reduce wafer inspection throughput during HVM.

[0062] After data collection is completed according to the multi-device model setup, Figure 5A and Figure 4The computational model is trained in the process. Then, when the measurement data is available for subsequent devices, the trained computational model can be directly applied to the subsequent devices manufactured on the wafer. Figure 5C The illustration shows a device on a subsequent wafer where a trained computational model can be directly applied, having the same device ID as the device manufactured on the wafer used to train the computational model (e.g., wafers 506_2, 507_2, and 508_2). Alternatively, if the subsequent device is manufactured using the same device fabrication technology (e.g., technology node), the trained computational model can be directly applied to the subsequent device manufactured on that wafer, where the device was not used to train the computational model. In other words, redundant data collection is unnecessary. Therefore, the data collection time for generating a sampling schedule for subsequent devices can be virtually zero, as the previously trained computational model can be directly applied to generate the sampling schedule once measurement data for the subsequent device is available. This can significantly reduce the “process recipe time” used to guide wafer inspection throughout HVM using the computational model.

[0063] It should be understood that Figure 5C The embodiments illustrated herein can be applied to multiple devices processed by multiple device manufacturing tools using a shared device manufacturing technology. As discussed above, devices 506-509 can each be manufactured according to the same device manufacturing technology. In HVM, different device manufacturing technologies (e.g., technology nodes) can be employed in parallel to manufacture devices on a wafer. For example, first and second devices can be manufactured onto first and second wafers respectively according to a first device manufacturing technology. Third and fourth devices can be manufactured onto third and fourth wafers respectively according to a second device manufacturing technology. Input data (e.g., measurement data and probe test data) for manufacturing the first, second, third, and fourth devices onto the wafer can be obtained and used to train computational models for devices manufactured according to the first device manufacturing technology (e.g., the first and second devices) and devices manufactured according to the second device manufacturing technology (e.g., the third and fourth devices). In some embodiments, data collection and computational defect model training can occur simultaneously for devices processed by the first device manufacturing technology and devices processed by the second device manufacturing technology.

[0064] Now to Figure 6 For reference, Figure 6 This is an example block diagram illustrating a system 600 with various modules according to an embodiment of the present disclosure. The system 600 can use input data from multiple devices to train a computational defect probability model and can generate a computational model database associated with device manufacturing technology. Figure 6 The modules in system 600 can be accessed via Figure 1 Controller 109 in Figure 2 Controller 290 orFigure 3 The processor 303 in the system is used. A database of computational models associated with device manufacturing technologies can store computational models associated with device manufacturing technologies (e.g., technology nodes) used to manufacture devices on the wafer during HVM. Figure 6 The illustrated database of computational models can also be referred to as a computational model library. The computational models can be CGI models.

[0065] Input data can be obtained for the manufactured device and supplied to the CGI model. The input data can be input measurement information 601 obtained from a measurement tool. Input measurement information 601 can be obtained from different types of measurement tools. Example measurement tools may include, but are not limited to, scattering measurement tools or inspection tools (e.g., Figure 1 The bundle tool 104 or Figure 3 (Inspection tool 302 in the process). Input measurement information 601 may be an image collected for a device or a batch of devices processed according to a wafer processing step (e.g., a wafer processing step in the wafer workflow described above). The image may be included in measurement information that can be used for the device after the wafer processing step. Input data may also be probe test information 602 for a fully manufactured device or a fully manufactured batch of devices.

[0066] Linker 603 can correlate input measurement information 601 with input probe test information 602 for a single device or a batch of devices manufactured. As described above, the basic assumption of embodiments of this disclosure is that when different devices are manufactured using the same device manufacturing technology, the correlation between input measurement data and probe test data should be the same for different devices (e.g., device ID). For example, linker 603 can identify a result from measurement data 601 that directly leads to a result in input probe test information 602. The result could be a defect in the device (e.g., a physical defect or pattern defect). Therefore, linker 603 outputs the correlation between input probe test information 602 and measurement or inspection results in input measurement information 601. Linker 603 can output the correlation for each type of measurement information (e.g., etching, CD, overlay, etc.) that can be used on the wafer after wafer processing steps. Correlation can be generated for each type of measurement information that can be used on a batch of wafers processed according to wafer processing to generate a correlation library that links specific measurement results to wafer processing steps during HVM.

[0067] Then, linker 603 supplies the relevant dataset of the device to the defect probability calculation model 604. The relevant dataset supplied by linker 603 can be used to train the defect probability calculation model 604. Therefore, the relevant dataset can be referred to as the training dataset. Training the defect probability calculation model 604 can be performed as described above. Figure 4As described, a trained computational defect probability model 604 can be added to a computational defect probability model library 605, which can contain multiple trained computational defect probability models that can be associated with multiple contextual measurement correlations.

[0068] Now to Figure 7 For reference, Figure 7 This is an example block diagram illustrating a system 700 according to an embodiment of the present disclosure, which applies a trained computational model to generate a sampling plan for subsequent devices on a subsequent wafer to guide wafer inspection. Figure 7 As illustrated, subsequent device input information, such as subsequent device measurement information 701 and subsequent probe test information 702, can be supplied to the linker 603.

[0069] Subsequent device measurement information 701 may include Figure 6 The training dataset contains measurement information of unused devices. As described above, linker 603 can identify defect measurement correlations between subsequent device measurement information 701 and subsequent probe test information 702. Additionally, linker 603 can identify whether the defect measurement correlation is associated with a trained computational model available in the computational defect probability model library 605. If the trained computational defect probability model 703 associated with the defect measurement correlation is unavailable, this can indicate that subsequent devices should be manufactured according to a second device manufacturing technique. System 700 can then perform data collection 706 for additional subsequent devices (e.g., devices processed by the same device manufacturing technique as the subsequent devices) and train computational defect probability models to add to the computational defect probability model library (e.g., ...). Figure 6 The computational defect probability model library 605 is used. If a trained computational defect probability model 703 is available, the trained computational defect probability model 703 can be applied to subsequent device measurement information 701 and can determine the defective die probability of at least one die of the subsequent device. A sampling plan 704 can then be generated and supplied to the inspection tool 705 (e.g., Figure 1 EBI system in China Figure 2 Multi-beam tool 104 or Figure 3 The inspection tool 302 in the middle guides the inspection of subsequent devices.

[0070] Now to Figure 8 For reference, Figure 8 This is an example flowchart illustrating a method 800 according to an embodiment of the present disclosure for training a computational defect probability model using relevant defect measurement information as input data and using the trained computational defect probability model to generate a sampling plan for device inspection. The steps of method 800 may include, for example... Figure 1 Controller 109Figure 2 Controller 290 or Figure 3 The processor 303 is used to execute the computational device. It should be understood that the illustrated method 800 can be modified to change the order of the steps and include additional steps.

[0071] Steps 801 to 804 of method 800 can be considered as setup phase 800_1, and steps 805 to 809 of method 800 can be considered as application phase 800_2. Setup phase 800_1 can be... Figure 6 System 600 executes the process, while application phase 800_2 can be handled by... Figure 7 The system 700 is executed. In some embodiments, the same system may execute setup phase 800_1 and application phase 800_2.

[0072] In step 801, input data is acquired and fed into the defect probability calculation model (e.g., Figure 4 The input data can be measurement information available for a batch of devices processed using the same device manufacturing technology, measured after the wafer processing step. The input data can also be probe test data for each device in the batch (e.g., ...). Figure 6 Input probe test information 602).

[0073] In step 802, a relationship is calculated to link the input data. This relationship can be the correlation between probe test information and device measurement information, linking results from the measurement data that directly lead to the results in the probe test information. The results can be device defects (e.g., physical or pattern defects). When devices are manufactured using the same device fabrication technology, the correlation between the input measurement data and the probe test data should be the same across the batch of devices.

[0074] In step 803, the linked input data is used to train a model for calculating the defect probability. Training the model for calculating the defect probability can be done as described above. Figure 4 As described, the trained computational defect probability model can be correlated with linked probe test information and measurement information (e.g., outcome measurement correlation).

[0075] In step 804, a library of computational defect probability models is generated by repeating steps 801-803 for input data for devices processed according to different device manufacturing technologies (e.g., technology nodes). In HVM, different device manufacturing technologies (e.g., technology nodes) can be employed in parallel to fabricate devices on a wafer, where a first batch of devices corresponds to a first device manufacturing technology and a second batch of devices corresponds to a second device manufacturing technology. The library of computational defect probability models can include trained computational defect probability models that can be associated with multiple devices and multiple device manufacturing technologies.

[0076] In application phase 800_2, at step 805, input data for a subsequent device is acquired and supplied to the computational defect probability model. The input data for the subsequent device can include metrology information that was not used in training the computational defect probability models in the library of computational defect probability models. The input data can be for the same device manufacturing technology that was used to fabricate one device or a batch of devices used to train the computational defect probability models.

[0077] In step 806, the device manufacturing technology information for the subsequent device is searched in the library of computational defect probability models.

[0078] In step 807, the trained computational defect probability model associated with the device manufacturing technology of the subsequent device is applied to the subsequent device metrology information to determine a defective die probability for at least one die of the subsequent device.

[0079] In step 808, a sampling plan is generated using the defective die probability for at least one die computed in step 807. In step 809, the generated sampling plan is used to guide inspection of the subsequent device, and die yield is projected from the inspection results.

[0080] A benefit provided by embodiments of the present disclosure can be a reduction in time to train computational defect probability models and generate sampling plans for guiding device inspection. In some embodiments, “recipe time” for computing defect probability models is reduced. In some embodiments, a multi-device model training workflow is used to combine input data for multiple devices processed by the same device manufacturing technology. In some embodiments, the multi-device model training workflow can be applied simultaneously to a first plurality of devices sharing a first device manufacturing technology and a second plurality of devices sharing a second device manufacturing technology. In some embodiments, a multi-device model setup can improve interpolation of missing metrology information for devices or wafers fabricated by a fabrication tool by combining wafers with different fabrication devices processed by the same fabrication tool. In some embodiments, trained computational models are provided that can maintain CGI generated projected die yield and R 2Accuracy of correlation scores. Some embodiments of the present disclosure can provide a method to improve CGI model performance and generality to guide device inspection. Some embodiments of the present disclosure can provide a method to maintain defect inspection accuracy and yield of defect-free devices throughout HVM.

[0081] A non-transitory computer readable medium can be provided that can store instructions for a processor of a controller (e.g., controller 109 of Figure 1 ) to, among other things, perform image inspection, image acquisition, stage positioning, beam focusing, electric field adjustment, beam bending, condenser lens adjustment, activating a charged particle source, beam deflection, store instructions for a processor of a lithography projection device (e.g., lithography projection apparatus 301 of Figure 3 ) and an inspection tool (e.g., inspection tool 302 of Figure 3 ) to determine input data of a specimen, perform Figure 8 method 800 and other executable functions related to identifying locations on a wafer for inspection during HVM. Common forms of non-transitory media that can be used to provide instructions include, for example, a floppy disk, flexible disk, hard disk, solid-state drive, magnetic tape, or any other magnetic data storage medium, a Compact Disc Read Only Memory (CD-ROM), any other optical data storage medium, any physical medium with patterns of holes, a Random Access Memory (RAM), a Programmable Read-Only Memory (PROM), and Erasable Programmable Read-Only Memory (EPROM), a FLASH- EPROM or any other flash memory, Non-Volatile Random Access Memory (NVRAM), a cache, a register, any other memory chip or cartridge, and a networked version of any of the foregoing.

[0082] These embodiments can be further described using the following clauses:

[0083] 1. A method of training a computational defect probability model to guide device inspection, the method comprising:

[0084] obtaining input data for a plurality of devices manufactured according to a same device manufacturing technology;

[0085] correlating the input data for the plurality of devices;

[0086] training a computational defect probability model based on the correlation; and

[0087] generating a sampling plan to guide inspection of the plurality of devices.

[0088] 2. The method of clause 1, wherein the input data are metrology or inspection results.

[0089] 3. The method of clause 2, wherein the metrology or inspection results are collected at different locations on a device of the plurality of devices.

[0090] 4. The method of clause 1, wherein the input data is probe test information.

[0091] 5. The method of any of clauses 1-4, wherein the plurality of devices share a correlation between the input data and defects present on devices of the plurality of devices.

[0092] 6. The method of clause 5, wherein correlating input data of the plurality of devices with defects present on devices of the plurality of devices facilitates determining a link between the input data and the defects.

[0093] 7. The method of clause 5 or 6, wherein the defects are physical defects.

[0094] 8. The method of clause 5 or 6, wherein the defects are pattern defects.

[0095] 9. The method of any of clauses 1-8, wherein the plurality of devices includes devices having different die layouts.

[0096] 10. The method of any of clauses 1-8, wherein the plurality of devices includes devices having different die sizes.

[0097] 11. The method of clause 1, further comprising:

[0098] applying the trained computational defect probability model to a subsequent device; and

[0099] generating a sampling plan to guide inspection of the subsequent device.

[0100] 12. The method of clause 11, wherein the subsequent device was not used to train the computational defect probability model.

[0101] 13. The method of clause 11, wherein the computational defect probability model trained after obtaining input data for the subsequent device is applied to the subsequent device.

[0102] 14. The method of clause 13, wherein the input data for the subsequent device is metrology or inspection results.

[0103] 15. The method of clause 13, wherein the input data for the subsequent device is contextual information.

[0104] 16. The method of any of clauses 1-15, wherein the plurality of devices and the subsequent device are manufactured according to the same device manufacturing technology.

[0105] 17. The method of any of Clauses 1-16, wherein the computed defect probability model is a computed guided inspection model.

[0106] 18. The method of any of Clauses 1-17, wherein a first computed defect probability model for guiding inspection of devices is trained on a first plurality of devices manufactured according to a first device manufacturing technology, and simultaneously a second computed defect probability model for guiding inspection of devices is trained on a second plurality of devices manufactured according to a second device manufacturing technology.

[0107] 19. An apparatus for training a computed defect probability model to guide inspection of devices, comprising:

[0108] a memory storing a set of instructions; and

[0109] at least one processor configured to execute the set of instructions to cause the apparatus to perform operations comprising:

[0110] obtaining input data for a plurality of devices manufactured according to a same device manufacturing technology;

[0111] correlating the input data for the plurality of devices;

[0112] training a computed defect probability model based on the correlation; and

[0113] generating a sampling plan to guide inspection of the plurality of devices.

[0114] 20. The apparatus of Clause 19, wherein the input data is metrology or inspection results.

[0115] 21. The apparatus of Clause 20, wherein the metrology or inspection results are collected at different locations on devices in the plurality of devices.

[0116] 22. The apparatus of Clause 19, wherein the input data is probe test information.

[0117] 23. The apparatus of any of Clauses 19-22, wherein the plurality of devices share a similar correlation between the input data and defects present on devices in the plurality of devices.

[0118] 24. The apparatus of Clause 23, wherein the operation of correlating the input data for the plurality of devices and defects present on devices in the plurality of devices facilitates determining a link between the input data and the defects.

[0119] 25. The apparatus of Clause 23 or 24, wherein the defects are physical defects.

[0120] 26. The apparatus of clause 23 or 24, wherein the defects are pattern defects.

[0121] 27. The apparatus of any of clauses 19-26, wherein the plurality of devices includes devices having different die layouts.

[0122] 28. The apparatus of any of clauses 19-26, wherein the plurality of devices includes devices having different die sizes.

[0123] 29. The apparatus of clause 19, wherein the operations further comprise:

[0124] applying the trained computational defect probability model to a subsequent device; and

[0125] generating a sampling plan to guide inspection of the subsequent device.

[0126] 30. The apparatus of clause 29, wherein the subsequent device was not used to train the computational defect probability model.

[0127] 31. The apparatus of clause 29, wherein the computational defect probability model trained after obtaining input data for the subsequent device is applied to the subsequent device.

[0128] 32. The apparatus of clause 31, wherein the input data for the subsequent device is metrology or inspection results.

[0129] 33. The apparatus of clause 31, wherein the input data for the subsequent device is probe test information.

[0130] 34. The apparatus of any of clauses 29-33, wherein the plurality of devices and the subsequent device are manufactured according to the same device manufacturing technology.

[0131] 35. The apparatus of any of clauses 19-34, wherein the computational defect probability model is a computational guided inspection model.

[0132] 36. The apparatus of any of clauses 19-35, wherein a first computational defect probability model for guiding device inspection is trained for a first plurality of devices manufactured according to a first device manufacturing technology, and simultaneously a second computational defect probability model for guiding device inspection is trained for a second plurality of devices manufactured according to a second device manufacturing technology.

[0133] 37. A non-transitory computer-readable medium comprising a set of instructions executable by one or more processors of a computing device to cause the computing device to perform operations for training a computational defect probability model to guide inspection, the operations comprising:

[0134] obtaining input data for a plurality of devices manufactured by a same device manufacturing technology;

[0135] correlating the input data for the plurality of devices;

[0136] training a computational defect probability model based on the correlation; and

[0137] generating a sampling plan to guide inspection of the plurality of devices.

[0138] 38. The non-transitory computer-readable medium of clause 37, wherein the input data is metrology or inspection results.

[0139] 39. The non-transitory computer-readable medium of clause 38, wherein the metrology or inspection results are collected at different locations on devices in the plurality of devices.

[0140] 40. The non-transitory computer-readable medium of clause 37, wherein the input data is probe test information.

[0141] 41. The non-transitory computer-readable medium of any of clauses 37-40, wherein the plurality of devices share a similar correlation between the input data and defects present on devices in the plurality of devices.

[0142] 42. The non-transitory computer-readable medium of clause 41, wherein correlating the input data for the plurality of devices and defects present on devices in the plurality of devices facilitates determining a link between the input data and the defects.

[0143] 43. The non-transitory computer-readable medium of clause 41 or 42, wherein the defects are physical defects.

[0144] 44. The non-transitory computer-readable medium of clause 41 or 42, wherein the defects are pattern defects.

[0145] 45. The non-transitory computer-readable medium of any of clauses 37-44, wherein the plurality of devices comprises devices having different die layouts.

[0146] 46. The non-transitory computer-readable medium of any of clauses 37-44, wherein the plurality of devices comprises devices having different die sizes.

[0147] 47. The non-transitory computer-readable medium of clause 37, wherein the operations further comprise:

[0148] applying the trained computational defect probability model to a subsequent device; and

[0149] generating a sampling plan to guide inspection of the subsequent device.

[0150] 48. The non-transitory computer-readable medium of clause 47, wherein the subsequent device was not used to train the computational defect probability model.

[0151] 49. The non-transitory computer-readable medium of clause 47, wherein the computational defect probability model trained after obtaining input data for the subsequent device is to be used for the subsequent device.

[0152] 50. The non-transitory computer-readable medium of clause 49, wherein the input data for the subsequent device is metrology or inspection results.

[0153] 51. The non-transitory computer-readable medium of clause 49, wherein the input data for the subsequent device is probe test information.

[0154] 52. The non-transitory computer-readable medium of any of clauses 47-51, wherein the plurality of devices and the subsequent device are manufactured according to the same device manufacturing technology.

[0155] 53. The non-transitory computer-readable medium of any of clauses 37-52, wherein the computational defect probability model is a computational guided inspection model.

[0156] 54. The non-transitory computer-readable medium of any of clauses 37-53, wherein a first computational defect probability model for guiding device inspection is trained for a first plurality of devices manufactured according to a first device manufacturing technology and simultaneously a second computational defect probability model for guiding device inspection is trained for a second plurality of devices manufactured according to a second device manufacturing technology.

[0157] 55. A method of training a computational defect probability model to guide device inspection, the method comprising:

[0158] obtaining input data for a first plurality of devices manufactured according to a first device manufacturing technology and input data for a second plurality of devices manufactured according to a second device manufacturing technology;

[0159] correlating the input data for the first plurality of devices with the input data for the second plurality of devices;

[0160] training a first computational defect probability model based on the correlation of the input data for the first plurality of devices and training a second computational defect probability model based on the correlation of the input data for the second plurality of devices; and

[0161] generating a first sampling plan based on the first computational defect probability model to guide inspection of the first plurality of devices and generating a second sampling plan based on the second computational defect probability model to guide inspection of the second plurality of devices.

[0162] 56. The method of clause 55, wherein the input data for the first plurality of devices is metrology or inspection results.

[0163] 57. The method of clause 55, wherein the input data for the first plurality of devices is probe test information.

[0164] 58. The method of clause 55, wherein the input data for the second plurality of devices is metrology or inspection results.

[0165] 59. The method of clause 55, wherein the input data for the second plurality of devices is probe test information.

[0166] 60. The method of any one of clauses 55-59, wherein the first plurality of devices share a correlation between input data for the first plurality of devices and defects present on devices in the first plurality of devices, and wherein the second plurality of devices share a correlation between input data for the second plurality of devices and defects present on devices in the second plurality of devices.

[0167] 61. The method of clause 60, wherein correlating input for the first plurality of devices with defects present on devices in the first plurality of devices facilitates determining a link between input data for the first plurality of devices and the defects.

[0168] 62. The method of clause 60, wherein correlating input for the second plurality of devices with defects present on devices in the second plurality of devices facilitates determining a link between input data for the second plurality of devices and the defects.

[0169] 63. The method of clause 55, further comprising:

[0170] applying the first trained computational defect probability model to a first subsequent device;

[0171] applying a second trained computational defect probability model to a second subsequent device;

[0172] generating a sampling plan to guide inspection of the first subsequent device; and

[0173] generating a sampling plan to guide inspection of the second subsequent device.

[0174] 64. The method of clause 63, wherein the first subsequent device was not used to train the first computational defect probability model.

[0175] 65. The method of clause 63, wherein the second subsequent device was not used to train the second computational defect probability model.

[0176] 66. The method of clause 63, wherein the first trained computational defect probability model is applied to the first subsequent device after obtaining input data for the first subsequent device, and wherein the second trained computational defect probability model is applied to the second subsequent device after obtaining input data for the second subsequent device.

[0177] 67. The method of clause 66, wherein the input data for the first subsequent device is metrology or inspection results.

[0178] 68. The method of clause 66, wherein the input data for the second subsequent device is metrology or inspection results.

[0179] 69. The method of any of clauses 63-68, wherein the first plurality of devices and the first subsequent device are manufactured according to a same device manufacturing technology.

[0180] 70. The method of any of clauses 63-69, wherein the second plurality of devices and the second subsequent device are manufactured according to a same device manufacturing technology.

[0181] 71. The method of any of clauses 55-70, wherein the computational defect probability model is a computational guided inspection model.

[0182] 72. An apparatus for training a computational defect probability model to guide device inspection, comprising:

[0183] a memory storing a set of instructions; and

[0184] at least one processor configured to execute the set of instructions to cause the apparatus to perform operations comprising:

[0185] obtaining input data for a first plurality of devices manufactured according to a first device manufacturing technology and input data for a second plurality of devices manufactured according to a second device manufacturing technology;

[0186] correlating the input data for the first plurality of devices with the input data for the second plurality of devices;

[0187] training a first computational defect probability model based on the correlation of the input data for the first plurality of devices and training a second computational defect probability model based on the correlation of the input data for the second plurality of devices; and

[0188] generating a first sampling plan based on the first computational defect probability model to guide inspection of the first plurality of devices and generating a second sampling plan based on the second computational defect probability model to guide inspection of the second plurality of devices.

[0189] 73. The apparatus of clause 72, wherein the input data for the first plurality of devices is metrology or inspection results.

[0190] 74. The apparatus of clause 72, wherein the input data for the first plurality of devices is probe test information.

[0191] 75. The apparatus of clause 72, wherein the input data for the second plurality of devices is metrology or inspection results.

[0192] 76. The apparatus of clause 72, wherein the input data for the second plurality of devices is probe test information.

[0193] 77. The apparatus of any of clauses 72-76, wherein the first plurality of devices share a correlation between the input data for the first plurality of devices and defects present on devices in the first plurality of devices, and wherein the second plurality of devices share a correlation between the input data for the second plurality of devices and defects present on devices in the second plurality of devices.

[0194] 78. The apparatus of clause 77, wherein correlating the input for the first plurality of devices with defects present on devices in the first plurality of devices facilitates determining a link between the input data for the first plurality of devices and the defects.

[0195] 79. The apparatus of clause 77, wherein correlating the input for the second plurality of devices with defects present on devices in the second plurality of devices facilitates determining a link between the input data for the second plurality of devices and the defects.

[0196] 80. The apparatus of clause 72, wherein the operations further comprise:

[0197] applying a first trained computational defect probability model to a first subsequent device;

[0198] applying a second trained computational defect probability model to a second subsequent device;

[0199] generating a sampling plan to guide inspection of the first subsequent device; and

[0200] generating a sampling plan to guide inspection of the second subsequent device.

[0201] 81. The apparatus of clause 80, wherein the first subsequent device was not used to train the first computational defect probability model.

[0202] 82. The apparatus of clause 80, wherein the second subsequent device was not used to train the second computational defect probability model.

[0203] 83. The apparatus of clause 80, wherein the first trained computational defect probability model is applied to the first subsequent device after obtaining input data for the first subsequent device, and wherein the second trained computational defect probability model is applied to the second subsequent device after obtaining input data for the second subsequent device.

[0204] 84. The apparatus of clause 83, wherein the input data for the first subsequent device is metrology or inspection results.

[0205] 85. The apparatus of clause 83, wherein the input data for the second subsequent device is metrology or inspection results.

[0206] 86. The apparatus of any one of clauses 80-85, wherein the first plurality of devices and the first subsequent device are manufactured according to a same device manufacturing technology.

[0207] 87. The apparatus of any one of clauses 80-85, wherein the second plurality of devices and the second subsequent device are manufactured according to a same device manufacturing technology.

[0208] 88. The apparatus of any one of clauses 72-87, wherein the computational defect probability model is a computational guided inspection model.

[0209] 89. A non-transitory computer-readable medium comprising a set of instructions executable by one or more processors of a computing device to cause the computing device to perform operations for training computational defect probability models to guide inspection, the operations comprising:

[0210] obtaining input data for a first plurality of devices manufactured according to a first device manufacturing technology and input data for a second plurality of devices manufactured according to a second device manufacturing technology;

[0211] correlating the input data for the first plurality of devices with the input data for the second plurality of devices;

[0212] training a first computational defect probability model based on the correlation of the input data for the first plurality of devices and a second computational defect probability model based on the correlation of the input data for the second plurality of devices; and

[0213] generating a first sampling plan based on the first computational defect probability model to guide inspection of the first plurality of devices and a second sampling plan based on the second computational defect probability model to guide inspection of the second plurality of devices.

[0214] 90. The non-transitory computer-readable medium of clause 89, wherein the input data for the first plurality of devices is metrology or inspection results.

[0215] 91. The non-transitory computer-readable medium of clause 89, wherein the input data for the first plurality of devices is probe test information.

[0216] 92. The non-transitory computer-readable medium of clause 89, wherein the input data for the second plurality of devices is metrology or inspection results.

[0217] 93. The non-transitory computer-readable medium of clause 89, wherein the input data for the second plurality of devices is probe test information.

[0218] 94. The non-transitory computer-readable medium of any of clauses 89-93, wherein the first plurality of devices share a correlation between input data for the first plurality of devices and defects present on devices in the first plurality of devices, and wherein the second plurality of devices share a correlation between input data for the second plurality of devices and defects present on devices in the second plurality of devices.

[0219] 95. The non-transitory computer-readable medium of clause 94, wherein correlating the input to the first plurality of devices with defects present on devices in the first plurality of devices facilitates determining a link between input data for the first plurality of devices and the defects.

[0220] 96. The non-transitory computer-readable medium of clause 94, wherein correlating the input to the second plurality of devices with defects present on devices in the second plurality of devices facilitates determining a link between input data for the second plurality of devices and the defects.

[0221] 97. The non-transitory computer-readable medium of clause 89, wherein the operations further comprise:

[0222] applying a first trained computational defect probability model to a first subsequent device;

[0223] applying a second trained computational defect probability model to a second subsequent device;

[0224] generating a sampling plan to guide inspection of the first subsequent device; and

[0225] generating a sampling plan to guide inspection of the second subsequent device.

[0226] 98. The non-transitory computer-readable medium of clause 97, wherein the first subsequent device was not used to train the first computational defect probability model.

[0227] 99. The non-transitory computer-readable medium of clause 97, wherein the second subsequent device was not used to train the second computational defect probability model.

[0228] 100. The non-transitory computer-readable medium of clause 97, wherein the first trained computational defect probability model is applied to the first subsequent device after input data for the first subsequent device is obtained, and wherein the second trained computational defect probability model is applied to the second subsequent device after input data for the second subsequent device is obtained.

[0229] 101. The non-transitory computer-readable medium of clause 100, wherein the input data for the first subsequent device is metrology or inspection results.

[0230] 102. The non-transitory computer-readable medium of clause 100, wherein the input data for the second subsequent device is metrology or inspection results.

[0231] 103. The non-transitory computer-readable medium of any one of clauses 97-102, wherein the first plurality of devices and the first subsequent devices are manufactured according to a same device manufacturing technology.

[0232] 104. The non-transitory computer-readable medium of any one of clauses 97-102, wherein the second plurality of devices and the second subsequent devices are manufactured according to a same device manufacturing technology.

[0233] 105. The non-transitory computer-readable medium of any one of clauses 89-104, wherein the computational defect probability model is a computational guided inspection model.

[0234] The block diagrams in the drawings can illustrate the architectural, functional, and operational aspects of possible implementations of systems, methods, and computer hardware or software products according to various exemplary embodiments of the present disclosure. In this regard, each block in the schematic drawings can represent certain arithmetic and / or logical operations, which can be performed using hardware, such as an electronic circuit. The blocks can also represent modules, segments, or portions of code including one or more executable instructions for implementing the specified logical function(s). It should be understood that, in some alternative implementations, the functions indicated in the blocks can occur out of the order as shown in the figure. For example, two blocks shown in succession can, in some instances, be executed substantially concurrently, or in the reverse order, depending on the functionality involved. Some blocks can also be omitted, altogether. It should also be understood that each block of the block diagrams and combinations of blocks in the block diagrams can be implemented by dedicated hardware-based systems that perform the specified functions or acts, or combinations of dedicated hardware and computer instructions.

[0235] It will be appreciated that embodiments of the present disclosure are not limited to the exact construction that has been described and illustrated and that various modifications and changes can be made without departing from the scope of the present disclosure. The present disclosure has been described in relation to various embodiments, which have been presented by way of example only, and which are merely illustrative of the present disclosure. From inspection of the specification and practice of the technology disclosed herein, other embodiments will be readily apparent to those skilled in the art. The true scope of the present disclosure is to be indicated by the appended claims.

Claims

1. An apparatus for training a computational defect probability model to guide inspection of devices, comprising: a memory storing a set of instructions; and at least one processor configured to execute the set of instructions to cause the apparatus to perform operations comprising: obtaining input data for a plurality of devices manufactured according to a same device manufacturing technology; correlating the input data for the plurality of devices; training the computational defect probability model based on the correlation; and generating a sampling plan to guide inspection of the plurality of devices.

2. The apparatus of claim 1, wherein the input data is metrology or inspection results.

3. The apparatus of claim 2, wherein the metrology or inspection results are collected at different locations on a device in the plurality of devices.

4. The apparatus of claim 1, wherein the input data is probe test information.

5. The apparatus of claim 1, wherein the plurality of devices share a similar correlation between the input data and defects present on a device in the plurality of devices.

6. The apparatus of claim 5, wherein the operation of correlating the input data for the plurality of devices and the defects present on a device in the plurality of devices facilitates determining a link between the input data and the defects.

7. The apparatus of claim 5, wherein the defects are physical defects.

8. The apparatus of claim 5, wherein the defects are pattern defects.

9. The apparatus of claim 1, wherein the plurality of devices includes devices having different die layouts.

10. The apparatus of claim 1, wherein the plurality of devices includes devices having different die sizes.

11. The apparatus of claim 2, wherein the operations further comprise: applying the trained computational defect probability model to a subsequent device; and generating a sampling plan to guide inspection of the subsequent device.

12. The apparatus of claim 11, wherein the subsequent device is not used to train the computational defect probability model.

13. The apparatus of claim 11, wherein the trained computational defect probability model is applied to the subsequent device after obtaining input data for the subsequent device.

14. The apparatus of claim 13, wherein the input data for the subsequent device is metrology or inspection results.

15. The apparatus of claim 13, wherein the input data for the subsequent device is probe test information. ​

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