Multilayer ceramic capacitor

Abstract

The invention provides a laminated ceramic capacitor capable of improving adhesive force between a laminated body and an external electrode. A multilayer ceramic capacitor according to the present invention is provided with: a multilayer body including a plurality of dielectric layers that are laminated, and a plurality of internal electrode layers that are laminated on the dielectric layers, the first main surface and the second main surface are opposite to each other in the stacking direction of the dielectric layers, the first side surface and the second side surface are opposite to each other in the width direction orthogonal to the stacking direction, and the first end surface and the second end surface are opposite to each other in the length direction orthogonal to the stacking direction and the width direction. A first external electrode disposed on the first main surface and the first end surface of the laminate; and a second external electrode disposed on the first main surface and the second end surface of the laminated body, the internal electrode layer being exposed from the first end surface and the second end surface, respectively, and the first end surface and the second end surface from which the internal electrode layer is exposed being inclined so that the distal end becomes wider from the first main surface toward the second main surface. The first end surface and the second end surface are provided with a first convex part composed of a dielectric layer and an internal electrode layer.

Description

Technical Field

[0001] This invention relates to multilayer ceramic capacitors. Background Technology

[0002] In recent years, there has been progress in miniaturizing and thinning electronic devices such as portable telephones and portable music players. Along with this, miniaturization and thinning have also progressed in multilayer ceramic electronic components, such as multilayer ceramic capacitors, housed within these miniaturized and thinner electronic devices. In particular, in the pursuit of thinner multilayer ceramic electronic components, they are increasingly being used within wiring substrates, or even mounted on the surface of wiring substrates with very narrow gaps. As a result, the thinner the multilayer ceramic electronic components become, the lower their mechanical strength decreases, making it crucial to ensure their mechanical strength.

[0003] For example, Patent Document 1 discloses a multilayer ceramic capacitor that aims to achieve thinness. In the multilayer ceramic capacitor described in Patent Document 1, as a method for forming external electrodes, for the external electrodes located on the two main surfaces of the ceramic body (layer), a conductive paste is applied to the ceramic master block before it is monolithically shaped into chip pieces by screen printing. For the external electrodes located on the two end surfaces of the ceramic body, the conductive paste is applied by immersing the end surfaces of the ceramic body in the conductive paste.

[0004] Prior art literature

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2012-4180 Summary of the Invention

[0007] The problem the invention aims to solve

[0008] At this point, the area of ​​the internal electrode layer and the ceramic layer exposed at both ends of the laminated ceramic electronic component is small, which causes problems with the adhesion between the external electrode and the laminate.

[0009] Therefore, the main objective of this invention is to provide a multilayer ceramic capacitor that can improve the adhesion between the multilayer and the external electrode.

[0010] Technical solutions for solving the problem

[0011] The present application relates to a multilayer ceramic capacitor, which is a multilayer ceramic capacitor provided with: a laminate including a plurality of dielectric layers laminated and a plurality of internal electrode layers laminated on the dielectric layers, and having a first main surface and a second main surface opposed in a laminating direction of the plurality of dielectric layers, a first side surface and a second side surface opposed in a width direction orthogonal to the laminating direction, and a first end surface and a second end surface opposed in a length direction orthogonal to the laminating direction and the width direction; a first external electrode disposed on the first main surface and the first end surface of the laminate; and a second external electrode disposed on the first main surface and the second end surface of the laminate, the internal electrode layers being exposed from the first end surface and the second end surface, respectively, the first end surface and the second end surface where the internal electrode layers are exposed being inclined so as to widen toward the second main surface from the first main surface, and a first protrusion composed of the dielectric layers and the internal electrode layers being disposed on the first end surface and the second end surface.

[0012] According to the multilayer ceramic capacitor of the present application, the internal electrode layers are exposed from the first end surface and the second end surface, respectively, the first end surface and the second end surface where the internal electrode layers are exposed are inclined so as to widen toward the second main surface from the first main surface, and the first protrusion composed of the dielectric layers and the internal electrode layers is disposed on the first end surface and the second end surface, so that the surface area of the metal component and the dielectric component in the first protrusion increases, and thus the contact area of the metal component in at least the external electrode and the metal component of the laminate increases. As a result, the adhesion between the laminate and the external electrode can be improved.

[0013] Effects of the Invention

[0014] According to the present application, a multilayer ceramic capacitor in which the adhesion between a laminate and an external electrode can be improved can be provided.

[0015] The above objects, other objects, features, and advantages of the present application will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 is an appearance perspective view showing one example of a multilayer ceramic capacitor according to a first embodiment of the present application.

[0017] Figure 2 is a plan view showing one example of a multilayer ceramic capacitor according to the first embodiment of the present application.

[0018] Figure 3 is a front view showing one example of a multilayer ceramic capacitor according to the first embodiment of the present application.

[0019] Figure 4 is a side view showing one example of a multilayer ceramic capacitor according to the first embodiment of the present application.

[0020] Figure 5 is Figure 1 is a cross-sectional view of the line V-V involved.

[0021] Figure 6 is Figure 1 is a cross-sectional view of the line VI-VI involved.

[0022] Figure 7 is Figure 1 is a cross-sectional view of the line VII-VII involved.

[0023] Figure 8 (A) of FIG. 1 is an appearance perspective view of a laminate of a multilayer ceramic capacitor involved in the first embodiment of the present application, Figure 8 (B) of FIG. 1 is an appearance perspective view of the laminate viewed from a direction different from Figure 8 (A) of FIG. 1.

[0024] Figure 9 is a cross-sectional view showing one example of a multilayer ceramic capacitor involved in the first modification of the first embodiment of the present application.

[0025] Figure 10 is a cross-sectional view showing one example of a multilayer ceramic capacitor involved in the second modification of the first embodiment of the present application.

[0026] Figure 11 is a cross-sectional view showing one example of a multilayer ceramic capacitor involved in the third modification of the first embodiment of the present application.

[0027] Figure 12 is a cross-sectional view showing one example of a multilayer ceramic capacitor involved in the fourth modification of the first embodiment of the present application.

[0028] Figure 13 is a cross-sectional view showing one example of a multilayer ceramic capacitor involved in the fifth modification of the first embodiment of the present application.

[0029] Figure 14 is an appearance perspective view showing one example of a multilayer ceramic capacitor involved in the second embodiment of the present application.

[0030] Figure 15 is an appearance perspective view showing one example of a multilayer ceramic capacitor involved in the second embodiment of the present application.

[0031] Figure 16 is a front view showing one example of a multilayer ceramic capacitor involved in the second embodiment of the present application.

[0032] Figure 17is a side view showing one example of the multilayer ceramic capacitor according to the second embodiment of the present application.

[0033] Figure 18 is Figure 14 is a cross-sectional view taken along the line XVIII-XVIII.

[0034] Figure 19 is Figure 14 is a cross-sectional view taken along the line XIX-XIX.

[0035] Figure 20 is Figure 14 is a cross-sectional view taken along the line XX-XX.

[0036] Figure 21 is Figure 14 is a cross-sectional view taken along the line XXI-XXI.

[0037] Figure 22 (A) of FIG. 1 is an appearance perspective view of a multilayer body of a multilayer ceramic capacitor according to the second embodiment of the present application, Figure 22 (B) of FIG. 1 is an appearance perspective view of the multilayer body viewed from a different direction from Figure 22 (A) of FIG. 1.

[0038] Figure 23 is an appearance perspective view showing one example of a multilayer ceramic capacitor according to the third embodiment of the present application.

[0039] Figure 24 is Figure 23 is a cross-sectional view taken along the line XXIV-XXIV, and is a cross-sectional view for explaining the configuration of one example of a multilayer ceramic capacitor according to the third embodiment of the present application.

[0040] Figure 25 is Figure 23 is a cross-sectional view taken along the line XXV-XXV, and is a cross-sectional view for explaining the configuration of one example of a multilayer ceramic capacitor according to the third embodiment of the present application. DETAILED DESCRIPTION

[0041] Hereinafter, as one example of the present application, a multilayer ceramic capacitor is explained using the present embodiment.

[0042] A. First Embodiment

[0043] 1. Multilayer Ceramic Capacitor

[0044] One example of a multilayer ceramic capacitor 10 according to the embodiment of the present application is explained.

[0045] Figure 1 is an appearance perspective view showing one example of the multilayer ceramic capacitor according to the first embodiment of the present application. Figure 2 is a plan view showing one example of the multilayer ceramic capacitor according to the first embodiment of the present application. Figure 3 is a front view showing one example of the multilayer ceramic capacitor according to the first embodiment of the present application. Figure 4 is a side view showing one example of the multilayer ceramic capacitor according to the first embodiment of the present application. Figure 5 is Figure 1 is a cross-sectional view taken along the line V-V. Figure 6 is Figure 1 is a cross-sectional view taken along the line VI-VI. Figure 7 is Figure 1 is a cross-sectional view taken along the line VII-VII. Figure 8 (A) of FIG. 1 is an appearance perspective view of a multilayer body of a multilayer ceramic capacitor according to the first embodiment of the present application, Figure 8 (B) of FIG. 1 is an appearance perspective view of the multilayer body as viewed from a direction different from Figure 8 (A) of FIG. 1.

[0046] The multilayer ceramic capacitor 10 has a multilayer body 12, and an external electrode 24. Hereinafter, each structure will be described in the order of the multilayer body 12, the external electrode 24.

[0047] (Multilayer body)

[0048] The multilayer body 12 has a plurality of dielectric layers 14 and a plurality of internal electrode layers 16 stacked. Further, the multilayer body 12 includes a first main surface 12a and a second main surface 12b opposed in a height direction x which is a stacking direction of the plurality of dielectric layers 14, a first side surface 12c and a second side surface 12d opposed in a width direction y orthogonal to the height direction x, and a first end surface 12e and a second end surface 12f opposed in a length direction z orthogonal to the height direction x and the width direction y.

[0049] In this multilayer body 12, a rounded corner is provided at a corner portion and a rounded edge is provided at an edge portion. Note that the corner portion is a portion where three adjacent surfaces of the multilayer body 12 intersect, and the edge portion is a portion where two adjacent surfaces of the multilayer body 12 intersect. Further, a concave-convex or the like can be formed in part or all of the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, and the first end surface 12e and the second end surface 12f.

[0050] Furthermore, it is preferable that the first main surface 12a and the second main surface 12b, or one of them, are flat. If they are flat, the stress experienced by the nozzle picking up the multilayer ceramic capacitor 10 can be dispersed, thus increasing the strength of the multilayer ceramic capacitor 10 during installation. In the multilayer ceramic capacitor 10 according to this embodiment, the second main surface 12b is formed to be flat.

[0051] like Figure 5 as well as Figure 6 As shown, the laminate 12 has the following in the height direction x connecting the first main surface 12a and the second main surface 12b: an inner layer 15a with multiple inner electrode layers 16 facing each other, a first main surface side outer layer 15b1 formed by multiple dielectric layers 14 located between the inner electrode layer 16 on the side closest to the first main surface 12a and the first main surface 12a, and a second main surface side outer layer 15b2 formed by multiple dielectric layers 14 located between the inner electrode layer 16 on the side closest to the second main surface 12b and the second main surface 12b.

[0052] The first main surface outer layer 15b1 and the second main surface outer layer 15b2 are sometimes integrated after firing and are not distinguished piece by piece, but are an assembly of multiple outer dielectric layers.

[0053] The outer layer 15b1 on the first main surface side is located on the first main surface 12a side of the laminate 12, and is an assembly of multiple dielectric layers 14 located between the first main surface 12a and the inner electrode layer 16 closest to the first main surface 12a.

[0054] The outer layer 15b2 on the second main surface side is located on the second main surface 12b side of the laminate 12, and is an assembly of multiple dielectric layers 14 located between the second main surface 12b and the inner electrode layer 16 closest to the second main surface 12b.

[0055] The dimensions of the laminate 12 are not particularly limited, but preferably the dimensions in the length direction z are 0.1 mm or more and 1.6 mm or less, the dimensions in the width direction y are 0.1 mm or more and 1.6 mm or less, and the dimensions in the height direction x are 0.01 mm or more and 0.1 mm or less.

[0056] As the material of the dielectric layer 14, for example, it can be formed of a dielectric material. As the dielectric material, for example, it can have a plurality of crystal grains including a perovskite-type compound having BaTiO3 as a basic structure. As the material of the specific dielectric layer 14, in addition to BaTiO3, dielectric ceramics containing main components such as CaTiO3, SrTiO3, or CaZrO3 can also be used. In addition, according to the characteristics of the desired laminate, for example, a material added with a minor component such as a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound in a content ratio less than the main component can also be used.

[0057] In addition, as the external dielectric layer, for example, it can have a plurality of crystal grains including a perovskite-type compound having BaTiO3 as a basic structure. For example, dielectric ceramics containing main components such as BaTiO3, CaTiO3, SrTiO3, and CaZrO3 can be used. In addition, a material in which a minor component such as a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound is added to these main components can also be used. In addition, the dielectric layer 14 and the external dielectric layer can also be changed to different materials in consideration of the required functions. For example, if the external dielectric layer is made of a soft material, the stress applied to the laminate can be buffered, and if the external dielectric layer is made of a hard material, the generation of cracks can be suppressed.

[0058] The region sandwiched between the first main surface side outer layer portion 15b1 and the second main surface side outer layer portion 15b2 is the inner layer portion 15a.

[0059] As Figure 8 shown, when the area of the first main surface 12a is set as A and the area of the second main surface 12b is set as B in the stacking direction of the laminate 12, the condition A < B is satisfied.

[0060] The first end face 12e and the second end face 12f are inclined so that the ends widen from the first main surface 12a toward the second main surface 12b. In addition, it can also be that the first side face 12c and the second side face 12d are also inclined so that the ends widen from the first main surface 12a toward the second main surface 12b.

[0061] When the angle formed between the straight line obtained by drawing a perpendicular line on the extension line of the side of the first main surface 12a at the point where the first main surface 12a and the first end face 12e of the laminate 12 intersect and the first end face 12e is set as θ1, and the angle formed between the straight line obtained by drawing a perpendicular line on the extension line of the side of the first main surface 12a at the point where the first main surface 12a and the second end face 12f of the laminate intersect and the second end face 12f is set as θ2, it is preferably 5° ≤ θ1 ≤ 50° and 5° ≤ θ2 ≤ 50° respectively.

[0062] When the angle between the line drawing a perpendicular line from the point where the first main surface 12a and the first side surface 12c of the laminate 12 intersects with the extension line of the edge of the first main surface 12a and the first side surface 12c is set as θ3, and the angle between the line drawing a perpendicular line from the point where the first main surface 12a and the second side surface 12d of the laminate 12 intersects with the extension line of the edge of the first main surface 12a and the second side surface 12d is set as θ4, the preferred values ​​are 5°≤θ3≤50° and 5°≤θ4≤50°, respectively.

[0063] The number of stacked dielectric layers 14 is not particularly limited, but including the inner layer 15a, the first main surface side outer layer 15b1, and the second main surface side outer layer 15b2, the total number of these layers is preferably 3 or more and 700 or less. Furthermore, it is preferable that the thickness of the inner layer 15a is 0.4 μm or more and 2.0 μm or less, and the thickness of each of the first main surface side outer layer 15b1 and the second main surface side outer layer 15b2 is 2.0 μm or more and 10.0 μm or less.

[0064] (Internal electrode layer)

[0065] like Figure 5 as well as Figure 6 As shown, the internal electrode layer 16 has a first internal electrode layer 16a and a second internal electrode layer 16b. The first internal electrode layer 16a and the second internal electrode layer 16b are stacked alternately with a dielectric layer 14 in between.

[0066] The first internal electrode layer 16a is disposed on the surface of the dielectric layer 14. The first internal electrode layer 16a has a first opposing electrode portion 18a opposite to the second internal electrode layer 16b, and a first lead-out electrode portion 20a located at one end of the first internal electrode layer 16a and extending from the first opposing electrode portion 18a to the first end face 12e of the laminate 12. The first lead-out electrode portion 20a extends to and is exposed at its end at the first end face 12e.

[0067] The shape of the first opposing electrode portion 18a of the first inner electrode layer 16a is not particularly limited, but it is preferably rectangular in plan view. However, the corner portion can be rounded in plan view, or the corner portion can be formed into a plan view tilted (conical shape). Alternatively, it can be a plan view conical shape that tilts in either direction.

[0068] The shape of the first lead-out electrode portion 20a of the first internal electrode layer 16a is not particularly limited, but it is preferably rectangular in plan view. However, the corner portion can be rounded in plan view, or the corner portion can be formed into a plan view tilted (conical shape). Alternatively, it can be a plan view conical shape that tilts in any direction.

[0069] The width of the first opposing electrode portion 18a of the first internal electrode layer 16a and the width of the first lead electrode portion 20a of the first internal electrode layer 16a can be formed to be the same width, or can be formed to be narrower than either width.

[0070] The second internal electrode layer 16b is disposed on a surface of the dielectric layer 14 different from the dielectric layer 14 on which the first internal electrode layer 16a is disposed. The second internal electrode layer 16b has a second opposing electrode portion 18b opposing the first internal electrode layer 16a, and a second lead electrode portion 20b located on the one end side of the second internal electrode layer 16b and extending from the second opposing electrode portion 18b to the second end surface 12f of the laminate 12. The second lead electrode portion 20b has an end portion leading to the second end surface 12f and exposed.

[0071] The shape of the second opposing electrode portion 18b of the second internal electrode layer 16b is not particularly limited, but is preferably a plan view rectangular shape. However, the plan view corner portion can be rounded, or the corner portion can be formed in a plan view inclined (tapered) shape. Further, it can also be a plan view tapered shape with an inclination toward either direction.

[0072] The shape of the second lead electrode portion 20b of the second internal electrode layer 16b is not particularly limited, but is preferably a plan view rectangular shape. However, the plan view corner portion can be rounded, or the corner portion can be formed in a plan view inclined (tapered) shape. Further, it can also be a plan view tapered shape with an inclination toward either direction.

[0073] The width of the second opposing electrode portion 18b of the second internal electrode layer 16b and the width of the second lead electrode portion 20b of the second internal electrode layer 16b can be formed to be the same width, or can be formed to be narrower than either width.

[0074] The first lead electrode portion 20a of the first internal electrode layer 16a and the second lead electrode portion 20b of the second internal electrode layer 16b can also be a shape curved toward the first main surface 12a or the second main surface 12b. Further, the longest distance in the height direction x between the exposed portions of the first lead electrode portion 20a of the first internal electrode layer 16a leading to the second end surface 12f, and the longest distance in the height direction x between the exposed portions of the second lead electrode portion 20b of the second internal electrode layer 16b leading to the first end surface 12e can also be made shorter than the longest distance in the height direction x between the first opposing electrode portion 18a of the first internal electrode layer 16a and the second opposing electrode portion 18b of the second internal electrode layer 16b.

[0075] The number of stacked internal electrode layers 16 is not particularly limited, but is preferably 2 or more and 700 or less. Further, the thickness of the internal electrode layer 16 is preferably 0.2 μm or more and 2.0 μm or less.

[0076] The laminate 12 includes a side portion 22a (W gap) of the laminate 12 between the internal electrode layer 16 and the first side surface 12c, and between the internal electrode layer 16 and the second side surface 12d. Further, the laminate 12 includes an end portion 22b (L gap) of the laminate 12 between the internal electrode layer 16 and the first end surface 12e, and between the internal electrode layer 16 and the second end surface 12f.

[0077] The internal electrode layer 16 can be composed of, for example, a metal such as Ni, Cu, Ag, Pd, Au, or the like, an alloy containing at least one of these metals, such as an Ag-Pd alloy, or the like, but is not limited thereto.

[0078] Further, by including Sn in the first internal electrode layer 16a and the second internal electrode layer 16b, the concentration of the electric field to the interface of the internal electrode layer 16 and the dielectric layer 14 can be alleviated, and the improvement of the high-temperature load reliability can be brought about. At this time, even if Sn is included in only either of the first internal electrode layer 16a and the second internal electrode layer 16b, the effect can be sufficiently exhibited.

[0079] In the present embodiment, the first opposing electrode portion 18a of the first internal electrode layer 16a and the second opposing electrode portion 18b of the second internal electrode layer 16b oppose each other with the dielectric layer 14 interposed therebetween, thereby forming a static capacitor, and exhibiting the characteristics of a capacitor.

[0080] In order to make the capacitance of the capacitor high, the area of the internal electrode layer 16 needs to be made large, and therefore the LW surface coverage of the internal electrode layer 16 is preferably 90% or more. The LW surface coverage is defined as the proportion obtained by subtracting the area of the gap from the area of the inside of the edge portion of the internal electrode layer 16 as viewed from the LW surface of the laminate 12. The capacitance of the capacitor becomes high in the case where the LW surface coverage is high, but even if it is low, the joining strength between the layers becomes high because the dielectric layers 14 are joined to each other via the gap, and the generation of interlayer peeling can be suppressed.

[0081] (Protrusions)

[0082] The inner layer portion 15a has a first protrusion 40a disposed at the first end surface 12e and the second end surface 12f. In addition, in the case where the internal electrode layer 16 is drawn out to the first side surface 12c and the second side surface 12d and exposed, the inner layer portion 15a preferably has a second protrusion.

[0083] The first protrusion 40a is composed of an inner electrode layer 16 and a dielectric layer 14. More specifically, the first protrusion 40a disposed on the first end face 12e is composed of a first inner electrode layer 16a exposed from the first end face 12e and a dielectric layer 14. Furthermore, the first protrusion 40a disposed on the second end face 12f is composed of a second inner electrode layer 16b exposed from the second end face 12f and a dielectric layer 14. As a result, the surface area of ​​the metal and dielectric components of the first protrusion 40a is increased, thus increasing the contact area between at least the metal components in the outer electrode 24 and the metal components of the laminate 12. Consequently, the adhesion between the laminate 12 and the outer electrode 24 can be improved.

[0084] At this time, at least two first protrusions 40a are provided. If five or more first protrusions 40a are provided, the contact area between the laminate 12 and the external electrode 24 increases, which is therefore more preferable.

[0085] like Figure 5 As shown, in the width direction y, when the thickest part perpendicular to the end face is designated as the vertex T1 of the first protrusion, the endpoint of the first protrusion 40a on the first main surface 12a side is designated as P1, and the endpoint of the first protrusion 40a on the second main surface 12b side is designated as P2, it is preferable that ∠T1P1P2 ≥ ∠T1P2P1. Furthermore, ∠T1P1P2 and ∠T1P2P1 are preferably 15° or more and 75° or less. This reduces the stress applied to the first protrusion 40a.

[0086] The thickness in the direction perpendicular to the first end face 12e is defined as the thickness of the first protrusion 40a. That is, the thickness t1 of the first protrusion 40a is the shortest distance between the vertex T1 of the first protrusion 40a and the first end face 12e of the laminate 12. The thickness t1 of the first protrusion 40a is preferably 0.3 μm or more and 3.0 μm or less. When the thickness t1 of the first protrusion 40a is less than 0.3 μm, the end face becomes too smooth, making it difficult to sufficiently improve the adhesion between the laminate 12 and the external electrode 24.

[0087] (External electrode)

[0088] like Figure 1 to Figure 7 As shown, external electrodes 24 are disposed on the first end face 12e side and the second end face 12f side of the laminate 12.

[0089] The external electrode 24 includes a thin film layer 26 and a plating layer 30 formed to cover the thin film layer 26.

[0090] The external electrode 24 has a first external electrode 24a and a second external electrode 24b.

[0091] The first external electrode 24a is arranged on a portion of the first main surface 12a and the first end surface 12e of the laminate 12. In this case, the first external electrode 24a is electrically connected to the first lead electrode portion 20a of the first internal electrode layer 16a. In addition, the first external electrode 24a can also be arranged to slightly surround a portion of the second main surface 12b, the first side surface 12c, and a portion of the second side surface 12d.

[0092] The second external electrode 24b is arranged on a portion of the first main surface 12a and the second end surface 12f of the laminate 12. In this case, the second external electrode 24b is electrically connected to the second lead electrode portion 20b of the second internal electrode layer 16b. In addition, the second external electrode 24b can also be arranged to slightly surround a portion of the second main surface 12b, a portion of the first side surface 12c, and a portion of the second side surface 12d.

[0093] The external electrode 24 is composed of a thin film layer 26, an upper plating layer 34 that covers the thin film layer 26, and a surface plating layer 36 that covers the upper plating layer 34.

[0094] (Thin Film Layer)

[0095] The thin film layer 26 has a first thin film layer 26a and a second thin film layer 26b.

[0096] The first thin film layer 26a is arranged so as to cover a portion of the first main surface 12a on the first end surface 12e side of the laminate 12, and not to cover the first end surface 12e of the laminate 12. In addition, the first thin film layer 26a can also be arranged to surround any of the surfaces that are continuous with the first main surface 12a.

[0097] The second thin film layer 26b is arranged so as to cover a portion of the first main surface 12a on the second end surface 12f side of the laminate 12, and not to cover the second end surface 12f of the laminate 12. In addition, the second thin film layer 26b can also be arranged to surround any of the surfaces that are continuous with the first main surface 12a.

[0098] The first thin film layer 26a and the second thin film layer 26b are preferably thin film layers in which metal particles are deposited, formed by a sputtering method, an evaporation method, or the like. Due to this, the thickness of the first thin film layer 26a and the second thin film layer 26b in the direction that links the first main surface 12a and the second main surface 12b of the laminate 12 can be set to 1 μm or less, and the dimension in the height direction x of the multilayer ceramic capacitor 10 can be sufficiently reduced, and thus the height can be reduced.

[0099] Further, the method of measuring the dimension of the first thin film layer 26a and the second thin film layer 26b in the height direction x can be performed as follows. That is, in the case where the thin film layer is formed by deposition of metal particles, the thickness can be converted from the concentration of the given element based on the calibration line method for the metal type using a fluorescent X-ray device. In addition, the thickness can be measured from the actual observation image by observing the cross section of the member based on FIB using a scanning microscope.

[0100] Further, in the case where the first thin film layer 26a and the second thin film layer 26b are formed by a thin film formation method, these thin film layers can be composed of a metal such as Cu, Cr, Au, Pt, Ag, Sn, Ti, or Ni.

[0101] The first thin film layer 26a and the second thin film layer 26b can be composed in consideration of their respective functions. For example, in consideration of the adhesion to the laminate 12, NiCr or NiCu is preferably used as the main component. Further, the first thin film layer 26a and the second thin film layer 26b can be multiple pieces, or can be a two-layer structure of NiCr and NiCu.

[0102] The thin film layer 26 can also be a thin film layer containing a dielectric material and a metal component formed by screen printing, CVD, ALD method, or the like. According to these, the adhesion of the laminate to the external electrode can be further improved by the ceramic adhesion of the thin film layer 26 and the laminate 12. At this time, the thin film layer 26 can also have a discontinuous shape. By discontinuous, it means that it is discontinuously formed when viewed from the direction perpendicular to the length direction.

[0103] For example, in the case where the thin film layer 26 is formed of a material containing ceramic, there is a method of obtaining a cross-sectional photograph after cross-sectional polishing using a digital microscope (manufactured by Keyence Corporation: VHX-5000) or the like, and converting the thickness from the cross-sectional photograph or the like. In addition, there is a method of measuring the thickness from the actual observation image by observing the cross section of the member based on FIB using a scanning microscope or the like.

[0104] Further, in the case where the first thin film layer 26a and the second thin film layer 26b each contain the same main component as the dielectric layer 14, the adhesion can be further improved by simultaneously sintering the laminate 12 and the first thin film layer 26a and the second thin film layer 26b each. At this time, as the metal component, Ni, Cu, or the like is preferable, but can be appropriately changed depending on the metal component of the internal electrode layer 16.

[0105] (Plating layer)

[0106] The plating layer 30 includes a first plating layer 30a and a second plating layer 30b.

[0107] The first plating layer 30a is configured to cover the first thin film layer 26a and the first end surface 12e of the laminate 12.

[0108] The second plating layer 30b is configured to cover the second thin film layer 26b and the second end surface 12f of the laminate 12.

[0109] The plating layer 30 is formed of a plurality of layers. That is, the plating layer 30 has an upper plating layer 34 and a surface plating layer 36.

[0110] The upper plating layer 34 includes a first upper plating layer 34a included in the first plating layer 30a and a second upper plating layer 34b included in the second plating layer 30b. The surface plating layer 36 includes a first surface plating layer 36a included in the first plating layer 30a and a second surface plating layer 36b included in the second plating layer 30b.

[0111] The first upper plating layer 34a of the upper plating layer 34 is configured to cover the first direct plating layer 28a of the direct plating layer 28 and the first thin film layer 26a.

[0112] The second upper plating layer 34b of the upper plating layer 34 is configured to cover the second direct plating layer 28b of the direct plating layer 28 and the second thin film layer 26b.

[0113] The upper plating layer 34 is preferably Ni plating for preventing solder erosion.

[0114] The first surface plating layer 36a of the surface plating layer 36 is configured to cover the first upper plating layer 34a of the upper plating layer 34.

[0115] The second surface plating layer 36b of the surface plating layer 36 is configured to cover the second upper plating layer 34b of the upper plating layer 34.

[0116] The surface plating layer 36 is preferably Sn plating which has good joint properties with solder used when mounting the laminate ceramic capacitor 10. In addition, the surface plating layer 36 can also be provided as Cu plating. In this case, it is possible to improve the joint properties with a via hole formed when embedding the laminate ceramic capacitor 10 into a mounting substrate.

[0117] In addition, the plating layer 30 can also be formed of only the surface plating layer 36. In this case, the first surface plating layer 36a of the surface plating layer 36 is configured to cover the first thin film layer 26a, and the second surface plating layer 36b of the surface plating layer 36 is configured to cover the second thin film layer 26b.

[0118] The proportion of metal per unit volume of the plating layer 30 is preferably 99% by volume or more.

[0119] The thickness of each layer of the plating layer 30 is preferably 1.0 μm or more and 10.0 μm or less.

[0120] The shape of the external electrode 24 can also follow the shape of the outer shape of the laminate 12. That is, when the first protrusion 40a is formed, the external electrode 24 can also be provided with a concave-convex in the same manner as the shapes of the first end surface 12e and the second end surface 12f of the laminate 12.

[0121] The dimension of the length direction z of the multilayer ceramic capacitor 10 including the laminate 12, the first external electrode 24a, and the second external electrode 24b is set as an L dimension, the dimension of the height direction x of the multilayer ceramic capacitor 10 including the laminate 12, the first external electrode 24a, and the second external electrode 24b is set as a T dimension, and the dimension of the width direction y of the multilayer ceramic capacitor 10 including the laminate 12, the first external electrode 24a, and the second external electrode 24b is set as a W dimension.

[0122] The dimensions of the multilayer ceramic capacitor 10 are preferably an L dimension of the length direction z of 0.1 mm or more and 1.6 mm or less, a T dimension of the height direction x of 10 μm or more and 100 μm or less, and a W dimension of the width direction y of 0.1 mm or more and 1.6 mm or less. In Figure 1 In the multilayer ceramic capacitor 10 shown in FIG. 1, the L dimension is larger than the W dimension.

[0123] In addition, in the present embodiment, the effect of the present application can be effectively exerted when the T dimension of the height direction x of the multilayer ceramic capacitor 10 is 100 μm or less, and further, more effectively when it is 55 μm or less or 50 μm or less.

[0124] In Figure 1 The multilayer ceramic capacitor 10 related to the first embodiment shown in FIG. 1 has the first end surface 12e and the second end surface 12f inclined so as to become wider toward the end from the first main surface 12a toward the second main surface 12b, the first internal electrode layer 16a exposed from the first end surface 12e, the second internal electrode layer 16b exposed from the second end surface 12f, and the first protrusion 40a disposed at the first end surface 12e and the second end surface 12f, and is composed of the first internal electrode layer 16 and the dielectric layer 14, so that the surface area of the metal component and the dielectric component of the first protrusion 40a increases, and thus the contact area of the metal component of at least the external electrode 24 and the metal component of the laminate 12 increases. As a result, the adhesion of the laminate 12 and the external electrode 24 can be improved.

[0125] (1) First Modified Example

[0126] Next, one example of the multilayer ceramic capacitor 10A related to the first modified example of the first embodiment of the present application will be described. Figure 9is a cross-sectional schematic view showing one example of a multilayer ceramic capacitor according to the first modification of the first embodiment of the present application. However, the same or equivalent structures are denoted by the same reference numerals, and detailed description will be omitted. Figure 1 to Figure 8

[0127] In the multilayer ceramic capacitor 10A according to the first modification, as shown in Figure 9

[0128] Specifically, the first thin film layer 26a is formed so as to cover the first end surface 12e from the first main surface 12a. Further, the second thin film layer 26b is formed so as to cover the second end surface 12f from the first main surface 12a.

[0129] The first thin film layer 26a is directly electrically connected to the first lead electrode portion 20a of the first internal electrode layer 16a exposed from the first end surface 12e. Further, the second thin film layer 26b is directly electrically connected to the second lead electrode portion 20b of the second internal electrode layer 16b exposed from the second end surface 12f.

[0130] As for the first thin film layer 26a, the thin film layer formed on the first main surface 12a and the thin film layer formed on the first end surface 12e can be continuously connected, or can be discontinuously formed at the ridge line portion. Further, as for the second thin film layer 26b, the thin film layer formed on the first main surface 12a and the thin film layer formed on the second end surface 12f can be continuously connected, or can be discontinuously formed at the ridge line portion.

[0131] In the multilayer ceramic capacitor 10A according to the first embodiment shown in Figure 9

[0132] The first thin film layer 26a is arranged at the first end surface 12e, and the second thin film layer 26b is arranged at the second end surface 12f, so that the first protrusion 40a increases the contact area of the metal component in the multilayer body 12 and the metal component of the thin film layer 26, and increases the contact area of the dielectric component in the multilayer body 12 and the dielectric component of the thin film layer 26. As a result, the adhesion of the multilayer body 12 to the external electrode 24 can be further improved.

[0133] (2) Second Modification

[0134] Next, one example of a multilayer ceramic capacitor 10B according to the second modification of the first embodiment of the present application will be described. Figure 10 ​​​is a cross-sectional schematic view showing one example of a multilayer ceramic capacitor according to a second modification of the first embodiment of the present application. However, the same or equivalent structures are denoted by the same reference numerals, and detailed description thereof will be omitted. Figure 1 to Figure 8

[0135] As shown in FIG. 1, the multilayer ceramic capacitor 10B according to the second modification of the first embodiment includes a laminated body 12, a first thin film layer 26a, a second thin film layer 26b, and a base electrode layer 27. Figure 10

[0136] (Base electrode layer)

[0137] The base electrode layer 27 includes a first base electrode layer 27a and a second base electrode layer 27b.

[0138] The first base electrode layer 27a is arranged so as to cover the first end surface 12e of the laminated body 12. The first base electrode layer 27a is directly electrically connected to the first lead electrode portion 20a of the first internal electrode layer 16a.

[0139] The upper end of the first base electrode layer 27a can also be arranged so as to overlap with the lower side of the first thin film layer 26a on the ridge line portion formed by the first main surface 12a and the first end surface 12e of the laminated body 12.

[0140] The second base electrode layer 27b is arranged so as to cover the second end surface 12f of the laminated body 12. The second base electrode layer 27b is directly electrically connected to the second lead electrode portion 20b of the second internal electrode layer 16b.

[0141] The upper end of the second base electrode layer 27b can also be arranged so as to overlap with the lower side of the second thin film layer 26b on the ridge line portion formed by the first main surface 12a and the second end surface 12f of the laminated body 12.

[0142] In addition, a portion of the first thin film layer 26a can also be arranged so as to surround the first end surface 12e, and a portion of the second thin film layer 26b can also be arranged so as to surround the second end surface 12f.

[0143] The base electrode layer 27 is formed of, for example, a fired layer.

[0144] ​​In this case, the sintered layer comprises a metallic component and a glass component. The glass component of the sintered layer comprises at least one selected from B, Si, Ba, Mg, Al, Li, etc. The metallic component of the sintered layer comprises, for example, at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The sintered layer is formed by applying a conductive paste comprising glass and metal to a laminate and then sintering it. The sintered layer is formed by simultaneously sintering a laminated sheet having an internal electrode layer 16 and a dielectric layer 14 and a conductive paste applied to the laminated sheet, but it can also be sintered after the laminated sheet having an internal electrode layer 20 and a dielectric layer 14 has been sintered. The sintered layer can also be multilayered.

[0145] The thickness of each layer of the substrate electrode layer 27 is preferably 0.1 μm or more and 200 μm or less.

[0146] Alternatively, the upper ends of the first base electrode layer 27a and the second base electrode layer 27b can be separately disposed from the first thin film layer 26a and the second thin film layer 26b.

[0147] exist Figure 10 The multilayer ceramic capacitor 10B according to the first embodiment shown has the same effect as the multilayer ceramic capacitor 10 described above, and also has the following effect.

[0148] A first base electrode layer 27a is disposed on the first end face 12e, and a second base electrode layer 27b is disposed on the second end face 12f. Therefore, the surface area of ​​the metal and dielectric components of the first protrusion 40a increases, resulting in increased contact area between the metal components in the laminate 12 and the metal components of the base electrode layer 27, and also increased contact area between the dielectric components in the laminate 12 and the glass components of the base electrode layer 27. As a result, the adhesion between the laminate 12 and the external electrode 24 can be further improved.

[0149] (3) Third variation

[0150] Next, an example of a multilayer ceramic capacitor 10C according to the third variation of the first embodiment of the present invention will be described. Figure 11 This is a schematic cross-sectional view illustrating an example of a multilayer ceramic capacitor according to a third variation of the first embodiment of the present invention. However, for... Figure 1 to Figure 8 For identical or equivalent structures, use the same reference numerals and omit detailed descriptions.

[0151] like Figure 11 As shown, in the third variation of the first embodiment, the two end faces 12e and 12f of the multilayer ceramic capacitor 10C are provided with direct plating layers 28.

[0152] (Direct plating layer)

[0153] The direct plating layer 28 includes a first direct plating layer 28a and a second direct plating layer 28b.

[0154] The first direct plating layer 28a is arranged so as to cover the first end surface 12e of the laminate 12. The first direct plating layer 28a is directly electrically connected to the first lead electrode portion 20a of the first internal electrode layer 16a.

[0155] The upper end of the first direct plating layer 28a is arranged so as to overlap with the lower side of the first thin film layer 26a on the ridge line portion formed by the first main surface 12a and the first end surface 12e of the laminate 12.

[0156] The second direct plating layer 28b is arranged so as to cover the second end surface 12f of the laminate 12. The second direct plating layer 28b is directly electrically connected to the second lead electrode portion 20b of the second internal electrode layer 16b.

[0157] The upper end of the second direct plating layer 28b is arranged so as to overlap with the lower side of the second thin film layer 26b on the ridge line portion formed by the first main surface 12a and the second end surface 12f of the laminate 12.

[0158] In addition, a portion of the first direct plating layer 28a can also be arranged so as to surround the second main surface 12b, and a portion of the second direct plating layer 28b can also be arranged so as to surround the second main surface 12b.

[0159] The direct plating layer 28 may, for example, include at least one metal selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, and the like as a main component of the metal, and is not particularly limited. For example, in the case where the first internal electrode layer 16a and the second internal electrode layer 16b are formed using Ni, the direct plating layer 28 is preferably plated with Cu that has good adhesion to Ni.

[0160] The direct plating layer 28 is grown by plating from the internal electrode layer 16, and is formed so as to cover the first end surface 12e and the second end surface 12f.

[0161] The thickness of each layer of the direct plating layer 28 is preferably 2.0 μm or more and 10.0 μm or less.

[0162] In addition, the upper end of each of the first direct plating layer 28a and the second direct plating layer 28b can be arranged separately from each of the first thin film layer 26a and the second thin film layer 26b.

[0163] Accordingly, the thickness of the external electrode 24 formed on the first main surface 12a in the stacking direction can be further reduced, and thus a laminate ceramic capacitor that is further reduced in height without impairing the mountability at the time of mounting can be provided.

[0164] (4) Fourth variation

[0165] Next, an example of a multilayer ceramic capacitor 10D according to the fourth variation of the first embodiment of the present invention will be described. Figure 12 This is a schematic cross-sectional view showing an example of a multilayer ceramic capacitor according to a fourth variation of the first embodiment of the present invention. However, for... Figure 1 to Figure 8 For identical or equivalent structures, use the same reference numerals and omit detailed descriptions.

[0166] like Figure 12 As shown, in the multilayer ceramic capacitor 10D according to the fourth modification, the plating layer 30 of the external electrode 24 further has a lower plating layer 32 disposed between the thin film layer 26 and the upper plating layer 34. Thus, the upper plating layer 34 of the plating layer 30 is indirectly covered by the thin film layer 26 through the lower plating layer 32.

[0167] Therefore, in the multilayer ceramic capacitor 10D, the lower plating layer 32 can prevent moisture from entering from the outside.

[0168] according to Figure 12 The fourth variation shown involves a multilayer ceramic capacitor 10D, which serves as a capacitor for... Figure 1 The same effect is achieved with the laminated ceramic capacitor 10. Furthermore, it can suppress the intrusion of moisture from the outside.

[0169] (5) Fifth variation

[0170] Next, the multilayer ceramic capacitor 10E according to the fifth variation of the first embodiment of the present invention will be described. Figure 13 This is a schematic cross-sectional view illustrating an example of a multilayer ceramic capacitor according to a fifth variation of the first embodiment of the present invention. However, for... Figure 1 to Figure 8 For identical or equivalent structures, use the same reference numerals and omit detailed descriptions.

[0171] The fifth variation involves a multilayer ceramic capacitor 10E whose external electrode 24 does not contain a plating layer, but is composed of multiple thin film layers. Figure 13 In the stacked ceramic capacitor 10E shown, for example, the first external electrode 24a does not contain a plating layer but is composed of only four thin film layers 26a1 to 26a4, and the second external electrode 24b does not contain a plating layer but is composed of only four thin film layers 26b1 to 26b4.

[0172] In the first external electrode 24a, a thin film layer 26a1 is formed around the first main surface 12a to cover the first end surface 12e. Furthermore, thin film layers 26a2, 26a3, and 26a4 are sequentially formed on the surface of the thin film layer 26a1.

[0173] In the second external electrode 24b, the thin film layer 26b1 is formed so as to cover the second end surface 12f from the first main surface 12a. Further, the thin film layers 26b2, 26b3, and 26b4 are formed in this order on the surface of the thin film layer 26b1.

[0174] In addition, in the first external electrode 24a, each of the edge portions of the four thin film layers 26a1 to 26a4 near the center of the laminate 12 can be formed so as to cover the edge portion of each lower layer side, or can not be formed so as to cover the edge portion of each lower layer side. Similarly, in the second external electrode 24b, each of the edge portions of the four thin film layers 26b1 to 26b4 near the center of the laminate 12 can be formed so as to cover the edge portion of each lower layer side, or can not be formed so as to cover the edge portion of each lower layer side.

[0175] In Figure 13 The laminate ceramic capacitor 10E according to the first embodiment has the same effects as the laminate ceramic capacitor 10 described above, and also has the following effects.

[0176] That is, the laminate ceramic capacitor 10E does not include a plating layer, the first external electrode 24a is composed of only the thin film layers 26a1 to 26a4, and the second external electrode 24b is composed of only the thin film layers 26b1 to 26b4, whereby the size of the T dimension in the height direction x and the size of the L dimension in the length direction z can be reduced, and thus the size of the laminate ceramic capacitor can be reduced.

[0177] 2. Method of manufacturing a laminate ceramic capacitor

[0178] Hereinafter, a method of manufacturing a laminate ceramic capacitor according to the first embodiment will be described.

[0179] First, a dielectric sheet and a conductive paste for an internal electrode are prepared. The conductive paste for an internal electrode and the dielectric sheet contain a binder (for example, a publicly known organic binder) and an organic solvent (for example, a publicly known organic binder).

[0180] Next, the conductive paste for an internal electrode is printed on the dielectric sheet in a given pattern, for example, by screen printing, gravure printing, or the like, to form an internal electrode pattern. In addition, with respect to the dielectric sheet, a dielectric sheet for an outer layer on which an internal electrode pattern is not printed is also prepared.

[0181] The dielectric sheet for an outer layer on which an internal electrode pattern is not formed is laminated in a given number of sheets, and on the dielectric sheet, a dielectric sheet on which an internal electrode pattern corresponding to the first internal electrode layer 16a is formed and a dielectric sheet on which an internal electrode pattern corresponding to the second internal electrode layer 16b is formed are alternately laminated, and further, the dielectric sheet for an outer layer on which an internal electrode pattern is not formed is laminated in a given number of sheets, whereby a laminate sheet is prepared.

[0182] Further, the laminated block is manufactured by pressing the laminated sheet in the stacking direction by means of isostatic pressing or the like.

[0183] Next, the laminated block is cut to a given size to cut out laminated chips. Then, a wet-type cylinder can be used so that the corners and ridge portions of the laminated chips have rounded corners.

[0184] A tapered shape is made for the laminated chips. When the laminated block is cut into chip shapes, a chip cutter is used, and a blade having a taper is used to make an end surface shape having an angle. With respect to the angle of the taper, a blade having an angle of 10° or more and 80° or less is used, for example, in the case where a blade having no taper is set to 0°. The taper of the blade and the angle of the end surface of the chip after cutting do not necessarily always correspond, and a slight adjustment of the taper angle is made with respect to the target angle.

[0185] As a result, the two side surfaces and the two end surfaces are tapered so that the distal end widens from the first main surface side toward the second main surface side. As a result, the internal electrode pattern exposed from the two end surfaces can be confirmed from the direction of observation from the first main surface side.

[0186] Next, the laminated chips are fired to manufacture the laminated body 12. The firing temperature is also based on the ceramic and the material of the internal electrode layer 16, but is preferably 900°C or more and 1400°C or less.

[0187] Next, the laminated chips after firing are arranged on the adhesive tape so that the first main surface side faces upward. For example, using the fact that the internal electrode layer 16 can be confirmed from the two end surfaces in the case where the first main surface side faces upward, appearance screening is performed, and the direction of arrangement is performed.

[0188] From an angle perpendicular to the first main surface, the abrasive is subjected to a blasting treatment by sandblasting, and is polished. At this time, the outer layer portion of the two end surfaces close to the first main surface side is easily shaved off. However, with respect to the outer layer portion of the two end surfaces close to the second main surface side, since the internal electrode layer 16 exposed from the end surface becomes an umbrella shape, it is not easily shaved off. Furthermore, the cutting chips based on the sandblasting easily accumulate and are not easily shaved off. Therefore, the shaving easiness differs between the first main surface side outer layer portion and the second main surface side outer layer portion, and thus the protrusion 40 according to the present application can be formed on the end surface. With respect to the abrasive, for example, an alumina abrasive, a zirconia alumina abrasive, a silicon carbide abrasive, or the like is used.

[0189] Next, after the sandblasting, the cutting chips attached to the laminated chips are removed. The removal of the cutting chips is performed by blowing air, for example.

[0190] Next, the laminated chips on which the protrusions are formed are taken out from the adhesive tape. At this time, for example, if a foamed release sheet is used with respect to the adhesive tape, a plurality of laminated chips can be taken out together by heating.

[0191] Next, the laminate 12 formed with the first protrusion 40a is arranged on the work table, and the first thin film layer 26a and the second thin film layer 26b are formed on the first main surface 12a by a sputtering method or an evaporation method.

[0192] Next, the first upper plating layer 34a is formed so as to cover the first thin film layer 26a arranged on a part of the first main surface 12a of the laminate 12, and the first surface plating layer 36a is formed so as to cover the first upper plating layer 34a. Similarly, the second upper plating layer 34b is formed so as to cover the second thin film layer 26b arranged on a part of the first main surface 12a of the laminate 12, and the second surface plating layer 36b is formed so as to cover the second upper plating layer 34b. Specifically, the upper plating layer 34 is formed as a Ni plating by electrolytic plating or non-electrolytic plating, and the surface plating layer 36 is formed as a Sn plating.

[0193] In addition, in the case of forming the base electrode layer 27, the base electrode layer is formed by applying the prepared conductive paste which becomes the base electrode layer to both end surfaces of the laminate. The application of the conductive paste to both end surfaces of the laminate can be performed by, for example, dipping, screen printing, or the like. The temperature of the firing process at this time is preferably 700°C or higher and 900°C or lower.

[0194] Further, in the case of forming the direct plating layer 28, it is formed as follows.

[0195] That is, the first direct plating layer 28a and the second direct plating layer 28b are respectively formed on the first end surface 12e and the second end surface 12f of the laminate 12. Then, the laminate 12 formed with the formed direct plating layer 28 is subjected to heat treatment to remove the remaining moisture remaining in the plating film and at the interface between the laminate 12 and the direct plating layer 28. Then, the laminate 12 formed with the direct plating layer 28 is arranged on the work table, and the thin film layer 26 is formed on the first main surface 12a by a sputtering method or an evaporation method. In the case of forming the direct plating layer 28 on the thin film layer 26, the direct plating layer 28 is formed after the thin film layer 26 is formed by a sputtering method or an evaporation method.

[0196] Next, the first upper plating layer 34a is formed so as to cover the first thin film layer 26a arranged on a part of the first main surface 12a of the laminate 12 and the first direct plating layer 28a arranged on the first end surface 12e of the laminate 12. Similarly, the second upper plating layer 32b is formed so as to cover the second thin film layer 26b arranged on a part of the first main surface 12a of the laminate 12 and the second direct plating layer 28b arranged on the second end surface 12f of the laminate 12. The upper plating layer 34 is formed as a Ni plating by electrolytic plating or non-electrolytic plating.

[0197] Then, a first surface plating layer 36a is formed so as to cover the first upper plating layer 34a. Similarly, a second surface plating layer 36b is formed so as to cover the second upper plating layer 34b. The surface plating layers 36 are formed of Sn plating by electrolytic plating or electroless plating.

[0198] As above, a laminated ceramic capacitor 10 shown in Fig. 1 can be manufactured. Figure 1 The first embodiment shown in Fig. 1 relates to a laminated ceramic capacitor 10.

[0199] According to the manufacturing method of the laminated ceramic capacitor relating to the present embodiment, a laminated ceramic capacitor in which the adhesion of the laminated body 12 to the external electrode 24 is improved can be provided.

[0200] B. Second Embodiment

[0201] 1. Laminated Ceramic Capacitor

[0202] Next, one example of a laminated ceramic capacitor 510 relating to the second embodiment of the present application will be described.

[0203] Figure 14 is an appearance perspective view showing one example of a laminated ceramic capacitor relating to the second embodiment of the present application. Figure 15 is an appearance perspective view showing one example of a laminated ceramic capacitor relating to the second embodiment of the present application. Figure 16 is a front view showing one example of a laminated ceramic capacitor relating to the second embodiment of the present application. Figure 17 is a side view showing one example of a laminated ceramic capacitor relating to the second embodiment of the present application. Figure 18 is Figure 14 is a cross-sectional view at XVIII-XVIII relating to the second embodiment of the present application. Figure 19 is Figure 14 is a cross-sectional view at line XIX-XIX relating to the second embodiment of the present application. Figure 20 is Figure 14 is a cross-sectional view at line XX-XX relating to the second embodiment of the present application. Figure 21 is Figure 14 is a cross-sectional view at line XXI-XXI relating to the second embodiment of the present application. Figure 22 (A) of Fig. 17 is an appearance perspective view of a laminated body of a laminated ceramic capacitor relating to the second embodiment of the present application, Figure 22 (B) of Fig. 17 is an appearance perspective view of the laminated body viewed from a different direction from Figure 22 (A) of Fig. 17.

[0204] The laminated ceramic capacitor 510 includes a laminated body 512, and external electrodes 524, 525.

[0205] (Laminated Body)

[0206] The laminate 512 includes multiple dielectric layers 514 and multiple internal electrode layers 516. The laminate 512 has a first main surface 512a and a second main surface 512b facing each other in the height direction x, a first side surface 512c and a second side surface 512d facing each other in the width direction y, which is orthogonal to the height direction x, and a third side surface 512e and a fourth side surface 512f facing each other in the length direction z, which is orthogonal to both the height direction x and the width direction y. The first main surface 512a and the second main surface 512b extend along the width direction y and the length direction z, respectively. The first side surface 512c and the second side surface 512d extend along the height direction x and the length direction z, respectively. The third side surface 512e and the fourth side surface 512f extend along the height direction x and the width direction y, respectively. Therefore, the so-called height direction x is the direction that connects the first main surface 512a and the second main surface 512b, the so-called width direction y is the direction that connects the first side surface 512c and the second side surface 512d, and the so-called length direction z is the direction that connects the third side surface 512e and the fourth side surface 512f.

[0207] Furthermore, the laminate 512 preferably has rounded corners at its corners and edges. Here, the corners are the parts where three faces of the laminate 512 intersect, and the edges are the parts where two faces of the laminate 512 intersect.

[0208] Furthermore, it is preferable that the first main surface 512a and the second main surface 512b, or one of them, are flat. If they are flat, the stress experienced by the nozzle picking up the multilayer ceramic capacitor 510 can be dispersed, thus increasing the strength of the multilayer ceramic capacitor 510 during installation. Regarding the multilayer ceramic capacitor 510 according to this embodiment, the second main surface 512b is formed to be flat.

[0209] like Figure 18 to Figure 21 As shown, the laminate 512 has the following in the height direction x connecting the first main surface 512a and the second main surface 512b: an inner layer portion 515a with multiple inner electrode layers 516 facing each other, a first main surface side outer layer portion 515b1 formed by multiple dielectric layers 514 located between the inner electrode layer 516 disposed on the side closest to the first main surface 512a and the first main surface 512a, and a second main surface side outer layer portion 515b2 formed by multiple dielectric layers 514 located between the inner electrode layer 516 disposed on the side closest to the second main surface 512b and the second main surface 512b.

[0210] The first main surface outer layer 515b1 and the second main surface outer layer 515b2 are sometimes integrated after firing and are not distinguished piece by piece, but are an assembly of multiple outer dielectric layers.

[0211] The first major surface side outer layer portion 515b1 is located on the side of the first major surface 512a of the laminate 512, and is an aggregate of a plurality of dielectric layers 514 located between the first major surface 512a and the internal electrode layer 516 closest to the first major surface 512a.

[0212] The second major surface side outer layer portion 515b2 is located on the side of the second major surface 512b of the laminate 512, and is an aggregate of a plurality of dielectric layers 514 located between the second major surface 512b and the internal electrode layer 516 closest to the second major surface 512b.

[0213] As the material of the dielectric layer 514, for example, it can be formed of a dielectric material. As the dielectric material, for example, a dielectric ceramic containing a main component such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3 can be used. In addition, according to the characteristics of the desired laminate, for example, a material in which a sub-component having a content ratio less than the main component such as a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound is added can also be used.

[0214] As the external dielectric layer, for example, it can have a plurality of crystal grains containing a perovskite-type compound having BaTiO3 as a basic structure. For example, a dielectric ceramic containing a main component such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3 can be used. In addition, a material in which a sub-component such as a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound is added to these main components can also be used. In addition, the dielectric layer 514 and the external dielectric layer can also be changed to different materials in consideration of the required functions. For example, if the external dielectric layer is made of a soft material, the stress applied to the laminate can be buffered, and if the external dielectric layer is made of a hard material, the generation of cracks can be suppressed.

[0215] The region sandwiched between the first major surface side outer layer portion 515b1 and the second major surface side outer layer portion 515b2 is the inner layer portion 515a.

[0216] As Figure 22 shown, when the area of the first major surface 512a is set to A and the area of the second major surface 512b is set to B in the stacking direction of the laminate 512, the condition A < B is satisfied.

[0217] The first side surface 512c and the second side surface 512d are inclined to widen at the ends from the first major surface 512a toward the second major surface 512b. In addition, the third side surface 512e and the fourth side surface 512f are inclined to widen at the ends from the first major surface 512a toward the second major surface 512b.

[0218] When the angle between the line drawing a perpendicular line from the extension of the edge of the first main surface 512a and the first side surface 512c at the point where the first main surface 512a and the first side surface 512c intersect is set to θ5, and the angle between the line drawing a perpendicular line from the extension of the edge of the first main surface 512a at the point where the first main surface 512a and the second side surface 512d intersect is set to θ6, the preferred values ​​are 5°≤θ5≤50° and 5°≤θ6≤50°, respectively.

[0219] When the angle between the line drawing a perpendicular line from the extension of the edge of the first main surface 512a and the third side surface 512e at the point where the first main surface 512a and the third side surface 512e intersect is set to θ7, and the angle between the line drawing a perpendicular line from the extension of the edge of the first main surface 512a at the point where the first main surface 512a and the fourth side surface 512f intersect is set to θ8, the preferred values ​​are 5°≤θ7≤50° and 5°≤θ8≤50°, respectively.

[0220] The number of stacked dielectric layers 514 is not particularly limited, but including the inner layer 515a, the first main surface side outer layer 515b1, and the second main surface side outer layer 515b2, the total number of these layers is preferably 3 or more and 700 or less. Furthermore, it is preferable that the thickness of the inner layer 515a is 0.4 μm or more and 2.0 μm or less, and the thickness of each of the first main surface side outer layer 515b1 and the second main surface side outer layer 515b2 is 2.0 μm or more and 10.0 μm or less.

[0221] The dielectric layer 514 can be formed from a dielectric material, for example. The dielectric material can have multiple grains comprising a perovskite-type compound with BaTiO3 as its basic structure. Specifically, in addition to BaTiO3, dielectric ceramics containing main components such as CaTiO3, SrTiO3, or CaZrO3 can be used as the material for the dielectric layer 514. Furthermore, depending on the desired characteristics of the laminate, materials containing secondary components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds in smaller amounts than the main components can also be used.

[0222] (Internal electrode layer)

[0223] like Figure 18 to Figure 21 As shown, the internal electrode layer 516 has a plurality of first internal electrode layers 516a and a plurality of second internal electrode layers 516b. The first internal electrode layers 516a and the second internal electrode layers 516b are stacked alternately with a dielectric layer 514 in between.

[0224] The first internal electrode layer 516a is arranged on the surface of the dielectric layer 514. Further, the first internal electrode layer 516a has a first opposing electrode portion 518a which opposes the first main surface 512a and the second main surface 512b and which is stacked in a direction connecting the first main surface 512a and the second main surface 512b.

[0225] Further, the second internal electrode layer 516b is arranged on the surface of the dielectric layer 514 different from the dielectric layer 514 on which the first internal electrode layer 516a is arranged. The second internal electrode layer 516b has a second opposing electrode portion 518b which opposes the first main surface 512a and the second main surface 512b and which is stacked in a direction connecting the first main surface 512a and the second main surface 512b.

[0226] As shown in FIG. 5, the first internal electrode layer 516a is led out to the first side surface 512c and the third side surface 512e of the stacked body 512 by the first lead-out electrode portion 520a and is led out to the second side surface 512d and the fourth side surface 512f of the stacked body 512 by the second lead-out electrode portion 520b. Further, the width of the first lead-out electrode portion 520a led out to the first side surface 512c can be substantially equal to the width led out to the third side surface 512e, and the width of the second lead-out electrode portion 520b led out to the second side surface 512d can be substantially equal to the width led out to the fourth side surface 512f. Figure 18 to Figure 21 That is, the first lead-out electrode portion 520a is led out to the third side surface 512e side of the stacked body 512, and the second lead-out electrode portion 520b is led out to the fourth side surface 512f side of the stacked body 512.

[0227] The second internal electrode layer 516b is led out to the first side surface 512c and the fourth side surface 512f of the stacked body 512 by the third lead-out electrode portion 521a and is led out to the second side surface 512d and the third side surface 512e of the stacked body 512 by the fourth lead-out electrode portion 521b. Further, the width of the third lead-out electrode portion 521a led out to the first side surface 512c can be substantially equal to the width led out to the fourth side surface 512f, and the width of the fourth lead-out electrode portion 521b led out to the second side surface 512d can be substantially equal to the width led out to the third side surface 512e.

[0228] That is, the third lead-out electrode portion 521a is led out to the fourth side surface 512f side of the stacked body 512, and the fourth lead-out electrode portion 521b is led out to the third side surface 512e side of the stacked body 512.

[0229]

[0230] ​Furthermore, when viewing the stacked ceramic capacitor 510 from the stacking direction, the straight line connecting the first lead electrode portion 520a and the second lead electrode portion 520b of the first internal electrode layer 516a preferably intersects the straight line connecting the third lead electrode portion 521a and the fourth lead electrode portion 521b of the second internal electrode layer 516b.

[0231] Furthermore, in the first side surface 512c, the second side surface 512d, the third side surface 512e, and the fourth side surface 512f of the laminate 512, preferably the first lead-out electrode portion 520a of the first internal electrode layer 516a and the fourth lead-out electrode portion 521b of the second internal electrode layer 516b are led out to opposite positions, and the second lead-out electrode portion 520b of the first internal electrode layer 516a and the third lead-out electrode portion 521a of the second internal electrode layer 516b are led out to opposite positions.

[0232] In addition, such as Figure 18 as well as Figure 19 As shown, the laminate 512 includes a side portion (W gap) 522a formed between one end of the first counter electrode portion 518a in the width direction y and the first side surface 512c, and between the other end of the second counter electrode portion 518b in the width direction y and the second side surface 512d.

[0233] Furthermore, such as Figure 20 as well as Figure 21 As shown, the laminate 512 includes a side portion (L gap) 522b formed between one end of the first counter electrode portion 518a in the length direction z and the third side surface 512e, and between the other end of the second counter electrode portion 518b in the length direction z and the fourth side surface 512f.

[0234] The internal electrode layer 516 may be made of a suitable conductive material, such as metals like Ni, Cu, Ag, Pd, Au, or alloys containing at least one of these metals, such as Ag-Pd alloys, but is not limited thereto.

[0235] Furthermore, by including Sn in both the first internal electrode layer 516a and the second internal electrode layer 516b, the electric field concentration at the interface between the internal electrode layer 16 and the dielectric layer 14 can be mitigated, thereby improving reliability under high-temperature loads. In this case, even if Sn is contained only in either the first internal electrode layer 16a or the second internal electrode layer 16b, it can still exert a significant effect.

[0236] In this embodiment, the first opposing electrode portion 518a of the first internal electrode layer 516a and the second opposing electrode portion 518b of the second internal electrode layer 516b are opposed to each other across the dielectric layer 514, thereby forming an electrostatic capacitor and exhibiting the characteristics of a capacitor.

[0237] In order to make the capacitance of the capacitor high, it is necessary to make the area of the internal electrode layer 516 large, and therefore the LW surface coverage of the internal electrode layer 516 is preferably 90% or more. The LW surface coverage is defined as the proportion obtained by subtracting the area of the voids from the area of the inside of the edge portion of the internal electrode layer 516 when viewed from the LW surface of the laminate 512. The capacitance of the capacitor becomes high in the case where the LW surface coverage is high, but even if it is lower, the joining strength between the layers becomes high because the dielectric layers 514 are joined to each other via the voids, and the occurrence of interlayer peeling can be suppressed.

[0238] (Protrusions)

[0239] The inner layer portion 515a has a first protrusion 540a disposed on the first side surface 512c and the second side surface 512d. Further, the inner layer portion 515a has a second protrusion 540b on the third side surface 512e and the fourth side surface 512f.

[0240] The first protrusion 540a is composed of the internal electrode layer 516 and the dielectric layer 514. More specifically, the first protrusion 540a disposed on the first side surface 512c and the second side surface 512d is composed of the first internal electrode layer 516a and the dielectric layer 14 exposed from the first side surface 512c and the second side surface 512d, and the second internal electrode layer 516b and the dielectric layer 14 exposed from the first side surface 512c and the second side surface 512d. Thereby, the surface area of the metal component and the dielectric component of the first protrusion 540a increases, and therefore the contact area of the metal component of at least the external electrode and the metal component of the laminate 12 increases. As a result, the adhesion of the laminate 512 and the external electrode 524, 525 can be improved.

[0241] At this time, the first protrusion 540a is disposed in at least two or more. If the first protrusion 540a is disposed in five or more, the contact area of the laminate 512 and the external electrode 524, 525 increases, and therefore it is more preferable.

[0242] In the width direction y, when the portion having the greatest thickness in the direction perpendicular to the end surface is set as the apex Tl of the first protrusion, the end point of the first protrusion 540a on the first main surface 512a side is set as Pl, and the end point of the first protrusion 540a on the second main surface 512b side is set as P2, it is preferable that ∠T1P1P2≥∠T1P2P1. Further, ∠T1P1P2and ∠T1P2P1are preferably 15° or more and 75° or less. Thereby, the stress applied to the first protrusion 540a can be reduced.

[0243] The thickness in the direction perpendicular to the end surface is set to the thickness of the first protrusion 540a in the direction perpendicular to the first side surface 512c. That is, the thickness tl of the first protrusion 540a is the shortest distance between the apex Tl of the first protrusion 540a and the first side surface 512c of the laminate 512. The thickness tl of the first protrusion 540a is preferably 0.3 μm or more and 3.0 μm or less. In the case where the thickness tl of the first protrusion 540a is less than 0.3 μm, the end surface becomes too smooth, and thus it is difficult to sufficiently increase the adhesion of the laminate 512 to the external electrode 524.

[0244] The second protrusion 540b is composed of the internal electrode layer 516 and the dielectric layer 514. More specifically, the second protrusion 540b disposed at the third side surface 512e and the fourth side surface 512f is composed of the first internal electrode layer 516a and the dielectric layer 14 exposed from the third side surface 512e and the fourth side surface 512f, and the second internal electrode layer 516b and the dielectric layer 14 exposed from the third side surface 512e and the fourth side surface 512f. Thus, the surface area of the metal component and the dielectric component of the second protrusion 540b increases, and thus the contact area of the metal component of the external electrode and the metal component of the laminate 512, the dielectric component of the external electrode 524, 525, and the dielectric component or the glass component of the external electrode increases. As a result, it is possible to increase the adhesion of the laminate 512 to the external electrode 524, 525.

[0245] At this time, the second protrusion 540b is disposed in at least two or more. If the second protrusion 540b is disposed in five or more, the contact area of the laminate 512 and the external electrode 524, 525 increases, and thus it is more preferable.

[0246] In the width direction y, when the portion having the greatest thickness in the direction perpendicular to the end surface is set to the apex T2 of the second protrusion, the end point of the second protrusion 540b on the first main surface 512a side is set to P3, and the end point of the second protrusion 540b on the second main surface 512b side is set to P4, it is preferable that ∠T2P3P4≥∠T2P4P3. Further, ∠T2P3P4and ∠T2P4P3are preferably 15° or more and 75° or less. Thus, it is possible to reduce the stress applied to the second protrusion 540b.

[0247] The thickness in the direction perpendicular to the third side surface 512e is set to the thickness of the second protrusion 540b. That is, the thickness t2 of the second protrusion 540b is the shortest distance between the apex Tl of the second protrusion 540b and the third side surface 512e of the laminate 512. The thickness t2 of the second protrusion 540b is preferably 0.3 μm or more and 3.0 μm or less. In the case where the thickness t2 of the second protrusion 540b is less than 0.3 μm, the end surface becomes too smooth, and thus it is difficult to sufficiently increase the adhesion of the laminate 512 to the external electrode 524, 525.

[0248] (External electrode)

[0249] like Figure 14 to Figure 21 As shown, external electrodes 524 and 525 are disposed in the laminate 512.

[0250] The external electrode 524 includes a thin film layer 526 and a plating layer 530 formed as a coating of the thin film layer 526.

[0251] The external electrode 525 includes a thin film layer 527 and a plating layer 531 formed as a coating of the thin film layer 527.

[0252] The external electrode 524 has a first external electrode 524a and a second external electrode 524b.

[0253] The first external electrode 524a is configured to cover the first lead-out electrode portion 520a on the first side surface 512c and the third side surface 512e, and is configured to cover a portion of the first main surface 512a. The first external electrode 524a is electrically connected to the first lead-out electrode portion 520a of the first internal electrode layer 516a.

[0254] The second external electrode 524b is configured to cover the second lead-out electrode portion 520b on the second side surface 512d and the fourth side surface 512f, and is configured to cover a portion of the first main surface 512a. The second external electrode 524b is electrically connected to the second lead-out electrode portion 520b of the first internal electrode layer 516a.

[0255] The external electrode 525 has a third external electrode 525a and a fourth external electrode 525b.

[0256] The third external electrode 525a is configured to cover the third lead-out electrode portion 521a on the first side surface 512c and the fourth side surface 512f, and is configured to cover a portion of the first main surface 512a. The third external electrode 525a is electrically connected to the third lead-out electrode portion 521a of the second internal electrode layer 516b.

[0257] The fourth external electrode 525b is configured to cover the fourth lead-out electrode portion 521b on the second side surface 512d and the third side surface 512e, and is configured to cover a portion of the first main surface 512a. The fourth external electrode 525b is electrically connected to the fourth lead-out electrode portion 521b of the second internal electrode layer 516b.

[0258] Within the laminate 512, the first opposing electrode portion 518a of the first inner electrode layer 516a and the second opposing electrode portion 518b of the second inner electrode layer 516b are opposed to each other across a dielectric layer 514, thereby forming an electrostatic capacitance. Therefore, an electrostatic capacitance can be obtained between the first external electrode 524a and the second external electrode 524b connected to the first inner electrode layer 516a and the third external electrode 525a and the fourth external electrode 525b connected to the second inner electrode layer 516b, exhibiting the characteristics of a capacitor.

[0259] (Thin film layer)

[0260] The thin film layer 526 has a first thin film layer 526a and a second thin film layer 526b.

[0261] The thin film layer 527 has a third thin film layer 527a and a fourth thin film layer 527b.

[0262] The first thin film layer 526a is configured to cover a portion of the first main surface 512a of the laminate 512 covering the first side surface 512c and the third side surface 512e, but does not cover the first side surface 512c and the third side surface 512e of the laminate 12.

[0263] The second thin film layer 526b is configured to cover a portion of the first main surface 512a of the laminate 512 covering the second side 512d side and the fourth side 512f side, but does not cover the second side 512d and the fourth side 512f.

[0264] The third thin film layer 527a is configured to cover a portion of the first main surface 512a of the laminate 512 covering the first side surface 512c and the fourth side surface 512f, but does not cover the first side surface 512c and the fourth side surface 512f.

[0265] The fourth thin film layer 527b is configured to cover a portion of the first main surface 512a of the laminate 512 covering the third side 512e side and the second side 512d side, but does not cover the third side 512e and the second side 512d.

[0266] Each of the first thin film layers 526a to the fourth thin film layers 527b is preferably a thin film layer on which metal particles are deposited, formed by sputtering, vapor deposition, or the like. Therefore, the thickness of the first thin film layers 526a to the fourth thin film layers 527b in the direction connecting the first main surface 512a and the second main surface 512b of the laminate 512 can be set to 1 μm or less, which can sufficiently reduce the dimension in the height direction x of the laminated ceramic capacitor 510, thus enabling the laminated ceramic capacitor 510 to be made shorter.

[0267] Furthermore, the method for measuring the dimension in the height direction x of the first thin film layer 526a to the fourth thin film layer 527b can be performed as follows: When the thin film layers are formed by the deposition of metal particles, the thickness can be calculated based on the given element concentration using a fluorescence X-ray apparatus and a calibration line method for that metal type. Alternatively, the thickness can be measured based on the observed image by observing the cross-section of the FIB-based component using a scanning microscope.

[0268] Furthermore, when the first thin film layer 526a to the fourth thin film layer 527b are formed by the thin film formation method, these thin film layers can be composed of metals such as Cu, Cr, Au, Pt, Ag, Sn, Ti or Ni.

[0269] The first thin film layer 526a to the fourth thin film layer 527b can be configured with their respective functions in mind. For example, considering the adhesion to the laminate 512, they can be made of NiCr or the like. For example, considering the adhesion to the laminate 12, NiCr or NiCu is preferably used as the main component. Furthermore, the first thin film layer 526a to the fourth thin film layer 527b can be multiple sheets, or it can be a two-layer structure of NiCr and NiCu.

[0270] Thin film layers 526 and 527 can also be thin film layers containing dielectric materials and metallic components, formed by methods such as screen printing, CVD, and ALD. Based on these methods, the adhesion between the laminate and the external electrode can be further improved through ceramic bonding of thin film layer 26 and the laminate 12. In this case, thin film layers 526 and 527 can also have a discontinuous shape. Discontinuity refers to a shape that is not continuous when viewed from a direction perpendicular to the length direction.

[0271] For example, when thin film layers 526 and 527 are formed from ceramic-containing materials, methods include: after cross-sectional grinding, obtaining cross-sectional photographs using a digital microscope (Keyence VHX-5000), and calculating the thickness based on these photographs. Alternatively, methods include: using a scanning microscope to examine the cross-section of the FIB-based component and determining the thickness based on the observed image.

[0272] Furthermore, by ensuring that each of the first thin film layer 526a to the fourth thin film layer 527b contains the same main component as the dielectric layer 514, the adhesion can be further improved by simultaneously firing the laminate 512 and each of the first to fourth thin film layers. In this case, Ni, Cu, etc., are preferred as the metal component, but can be appropriately changed depending on the metal component of the internal electrode layer 516.

[0273] (plating layer)

[0274] The plating layer 530 includes a first plating layer 530a and a second plating layer 530b.

[0275] The first coating layer 530a is configured to cover the first thin film layer 526a and the first side surface 512c and the third side surface 512e of the laminate 512.

[0276] The second coating layer 530b is configured to cover the second thin film layer 526b and the second side surface 512d and the fourth side surface 512f of the laminate 512.

[0277] The plating layer 531 includes a third plating layer 531a and a fourth plating layer 531b.

[0278] The third coating layer 531a is configured to cover the first side 512c and the fourth side 512f of the third thin film layer 527a and the laminate 512.

[0279] The fourth coating layer 531b is configured to cover the second side 512d and the third side 512e of the fourth thin film layer 527b and the laminate 512.

[0280] The plating layers 530 and 531 are each formed in multiple layers. That is, plating layer 530 has an upper plating layer 534 and a surface plating layer 536. Plating layer 531 has an upper plating layer 535 and a surface plating layer 537.

[0281] The upper plating layer 534 includes the first upper plating layer 534a included in the first plating layer 530a and the second upper plating layer 534b included in the second plating layer 530b. The surface plating layer 536 includes the first surface plating layer 536a included in the first plating layer 530a and the second surface plating layer 536b included in the second plating layer 530b.

[0282] The upper plating layer 535 includes the third upper plating layer 535a included in the third plating layer 531a and the fourth upper plating layer 535b included in the fourth plating layer 531b. The surface plating layer 537 includes the third surface plating layer 537a included in the third plating layer 531a and the fourth surface plating layer 537b included in the fourth plating layer 531b.

[0283] The first upper plating layer 534a of the upper plating layer 534 is configured to be covered with a first thin film layer 526a.

[0284] The second upper plating layer 534b of the upper plating layer 534 is configured to be covered by the second thin film layer 526b.

[0285] The third upper plating layer 535a of the upper plating layer 535 is configured to be covered by a third thin film layer 527a.

[0286] The fourth upper plating layer 535b of the upper plating layer 535 is configured to be covered by the fourth thin film layer 527b.

[0287] The upper plating layer 534 and the upper plating layer 535 are preferably Ni plating layers used to prevent solder corrosion.

[0288] The first surface plating layer 536a of the surface plating layer 536 is configured as the first upper plating layer 534a covered by the upper plating layer 534.

[0289] The second surface plating layer 536b of the surface plating layer 536 is configured as a second upper plating layer 534b8 covered by the upper plating layer 534.

[0290] The third surface plating layer 537a of the surface plating layer 537 is configured as the third upper plating layer 535a covered by the upper plating layer 535.

[0291] The fourth surface plating layer 537b of the surface plating layer 537 is configured as the fourth upper plating layer 535b covered by the upper plating layer 535.

[0292] The surface plating layers 536 and 537 are preferably Sn plating layers that have good adhesion to the solder used when mounting the multilayer ceramic capacitor 510. Alternatively, the surface plating layers 536 and 537 can also be Cu plating layers. In this case, the adhesion to the vias formed when embedding the multilayer ceramic capacitor 510 into the mounting substrate can be improved.

[0293] Alternatively, the plating layer 530 may consist only of the surface plating layer 536. In this case, the first surface plating layer 536a of the surface plating layer 536 is configured to be coated with a first thin film layer 526a, and the second surface plating layer 536b of the surface plating layer 536 is configured to be coated with a second thin film layer 526b. Similarly, the plating layer 531 may consist only of the surface plating layer 537. In this case, the third surface plating layer 537a of the surface plating layer 537 is configured to be coated with a third thin film layer 527a, and the fourth surface plating layer 537b of the surface plating layer 537 is configured to be coated with a fourth thin film layer 527b.

[0294] The metal content per unit volume of plating layer 530 and plating layer 531 is preferably 99% or more by volume.

[0295] The thickness of each of the plating layers 530 and 531 is preferably 1.0 μm or more and 10.0 μm or less.

[0296] The dimension of the stacked ceramic capacitor 510, which includes the stacked body 512, the external electrode 524, and the external electrode 525, in the length direction z is set as dimension L. The dimension of the stacked ceramic capacitor 510 in the height direction x is set as dimension T. The dimension of the stacked ceramic capacitor 510 in the width direction y is set as dimension W.

[0297] Preferably, the dimensions of the multilayer ceramic capacitor 510 are as follows: the length dimension L in the z-direction is 0.1 mm or more and 1.6 mm or less; the height dimension T in the x-direction is 10 μm or more and 100 μm or less; and the width dimension W in the y-direction is 0.1 mm or more and 1.6 mm or less. The dimensions of the multilayer ceramic capacitor 510 are preferably set to 7 / 10 ≤ L / W ≤ 10 / 7. This results in a roughly cubic crystalline shape for the laminate 512, thus increasing the flexibility of its installation.

[0298] Furthermore, in this embodiment, the effect of the present invention can be effectively achieved when the T dimension in the height direction x of the stacked ceramic capacitor 510 is 100 μm or less, and it becomes even more effective when it is 55 μm or less or 50 μm or less.

[0299] exist Figure 14 In the stacked ceramic capacitor 510 shown, in the external electrode 524, a first thin film layer 528a is disposed on the first main surface 512a and the second main surface 512b of the stack 512, and a second thin film layer 528b is disposed on the first main surface 512a and the second main surface 512b of the stack 512.

[0300] Furthermore, in the multilayer ceramic capacitor 510, in the external electrode 525, the third thin film layer 529a is disposed on the first main surface 512a and the second main surface 512b of the multilayer body 512, and the fourth thin film layer 529b is disposed on the first main surface 512a and the second main surface 512b of the multilayer body 512.

[0301] Furthermore, in the multilayer ceramic capacitor 510, the electrical connection between the external electrode 524 and the internal electrode layer 516 is not made through the first thin film layer 528a to the fourth thin film layer 529b respectively, but through the plating layers 530 and 531 disposed on the first side surface 512c to the fourth side surface 512f.

[0302] The shapes of the external electrodes 524 and 525 can also follow the shape of the outer shape of the laminate 512. That is, when the first protrusion 540a and the second protrusion 540b are formed, the external electrodes 524 and 525 can also be provided with protrusions and concaves in the same way as the shapes of the first side surface 512c, the second side surface 512d, the third side surface 512e and the fourth side surface 512f of the laminate 512.

[0303] Figure 14 The laminated ceramic capacitor 510 shown in the second embodiment has the same effect as the laminated ceramic capacitor 10.

[0304] Alternatively, the multilayer ceramic capacitor 510 according to the second embodiment of the present invention may also be combined with all or part of the first to fourth modifications of the multilayer ceramic capacitor 10 of the first embodiment, as well as the other modifications shown in the figures.

[0305] 2. Manufacturing method of multilayer ceramic capacitors

[0306] Hereinafter, a method for manufacturing a multilayer ceramic capacitor, which is an example of a multilayer ceramic capacitor according to the second embodiment, will be described.

[0307] First, prepare a conductive paste for the dielectric sheet and internal electrodes. The conductive paste for the dielectric sheet and internal electrode layer contains an adhesive (e.g., a known organic adhesive) and a solvent (e.g., a known organic adhesive).

[0308] Next, a conductive paste for the internal electrodes is printed onto the dielectric sheet in a given pattern, for example, by screen printing or gravure printing, to form an internal electrode pattern. Specifically, a paste containing a conductive material is applied to the dielectric sheet using the aforementioned printing method, thereby forming a conductive paste layer. The paste containing the conductive material is, for example, a paste made by adding organic binders and organic solvents to metal powder. Additionally, a dielectric sheet for an outer layer without the internal electrode pattern is also manufactured.

[0309] Thus, a dielectric sheet having an internal electrode pattern corresponding to the first internal electrode layer 516a and a dielectric sheet having an internal electrode pattern corresponding to the second internal electrode layer 516b are prepared.

[0310] More specifically, a screen printing plate for printing the first internal electrode layer 516a and a screen printing plate for printing the second internal electrode layer 516b can be prepared separately, and the internal electrode layers of the present invention can be printed using a printing press that enables the two screen printing plates to be printed separately.

[0311] A laminate is fabricated using dielectric sheets with internal electrode patterns formed on them. Specifically, a given number of outer dielectric sheets without internal electrode patterns are laminated to form the first main surface side outer layer 515b1 on the first main surface 512a side. Dielectric sheets with internal electrode patterns corresponding to the first inner electrode layer 516a and those with internal electrode patterns corresponding to the second inner electrode layer 516b are alternately laminated on top to form the inner layer 515a. Then, a given number of outer dielectric sheets without internal electrode patterns are laminated on top to form the second main surface side outer layer 515b2. This fabricates a laminate.

[0312] Furthermore, laminated blocks are produced by pressing laminated sheets in the lamination direction using methods such as isostatic pressing.

[0313] Next, the stacked blocks are cut to the given dimensions to cut out stacked pieces. Then, a wet roller can be used to round the corners and edges of the stacked pieces.

[0314] For creating conical shapes from stacked pieces, a slicer is used when cutting the stacked blocks into small pieces. This is done by using a tapered blade to create angled end faces. Regarding the angle of the tapered shape, a blade with an angle between 10° and 80° is used, instead of a non-tapered blade with a 0° angle. The tapered shape of the blade and the angle of the end face of the cut piece may not necessarily correspond, so fine adjustments to the tapered angle are made for the target angle.

[0315] Therefore, all the sides are tilted so that they widen at the ends from the first main surface side toward the second main surface side. As a result, the internal electrode pattern exposed from all the sides can be identified from the direction of view from the first main surface side.

[0316] Next, the stacked sheets are fired to produce the stack 512. The firing temperature also depends on the ceramic and the material of the internal electrodes, but is preferably above 900°C and below 1400°C.

[0317] Next, the fired stacked sheets are arranged on the adhesive tape with the first main surface facing upwards. For example, taking advantage of the fact that the internal electrode layer 516 can be seen from all sides when the first main surface is facing upwards, appearance screening is performed and orientation is arranged.

[0318] The abrasive is blasted onto the first main surface at an angle perpendicular to it, and then ground. At this time, the outer layer portions near the first main surface of all sides are easily removed. However, the outer layer portions near the second main surface of all sides are difficult to remove because the exposed internal electrode layer 516 forms an umbrella shape. Furthermore, the cutting chips from the blasting tend to accumulate and are difficult to remove. Therefore, the ease of removal differs between the outer layer portions on the first and second main surfaces, allowing the protrusions 540 and 541 of this invention to be formed on all sides. For the abrasive, for example, alumina abrasive, zirconia-alumina abrasive, silicon carbide abrasive, etc., are used.

[0319] After sandblasting, the cutting chips adhering to the stacked small pieces are removed. The removal of cutting chips is done, for example, by blowing air.

[0320] Next, the stacked pieces with protrusions are removed from the adhesive tape. At this time, for example, if a foam release sheet is used for the adhesive tape, multiple stacked pieces can be removed at the same time by heating.

[0321] Next, the laminate 512 having the first protrusion 540a and the second protrusion 540b is arranged on a worktable, and thin film layers 526 and 527 are formed on the first main surface 512a by sputtering.

[0322] Next, the upper plating layer 534 and the upper plating layer 535, and the surface plating layer 536 and the surface plating layer 537 are formed in sequence.

[0323] That is, the first upper plating layer 534a forming the upper plating layer 534 covers a portion of the first main surface 512a of the laminate 512, and the first surface plating layer 536a forming the surface plating layer 536 covers the first upper plating layer 534a.

[0324] The second upper plating layer 534b forming the upper plating layer 534 covers a portion of the second thin film layer 526b disposed on the first main surface 512a of the laminate 512, and the second surface plating layer 536b forming the surface plating layer 536 covers the second upper plating layer 534b.

[0325] The third upper plating layer 535a forms an upper plating layer 535 such that a third thin film layer 527a is disposed on a portion of the first main surface 512a of the laminate 512, and the third surface plating layer 537a forms a surface plating layer 537 such that it covers the third upper plating layer 535a.

[0326] The fourth upper plating layer 535b forming the upper plating layer 535 covers a portion of the fourth thin film layer 527b disposed on the first main surface 512a of the laminate 512, and the fourth surface plating layer 537b forming the surface plating layer 537 covers the fourth upper plating layer 535b.

[0327] Specifically, the upper plating layer 534 and the upper plating layer 535 are formed as Ni plating by electrolytic plating or electroless plating, and the surface plating layer 536 and the surface plating layer 537 are formed as Sn plating.

[0328] As described above, it can be manufactured Figure 14 The second embodiment shown relates to a multilayer ceramic capacitor 510.

[0329] According to the manufacturing method of the multilayer ceramic capacitor of this embodiment, the thickness of the external electrode 524 and external electrode 525 formed on the first main surface 512a and the second main surface 512b in the height direction x dimension T can be reduced, thus providing a multilayer ceramic capacitor with a low height without compromising the installability during installation.

[0330] C. Third Implementation

[0331] 1. Multilayer ceramic capacitor

[0332] Next, an example of a multilayer ceramic capacitor 610 according to the third embodiment of the present invention will be described.

[0333] Figure 23 This is a perspective view showing an example of a multilayer ceramic capacitor according to the third embodiment of the present invention. Figure 24 yes Figure 23 The diagram shows a cross-sectional view along line XXIV-XXIV, and is used to illustrate the construction of an example of a multilayer ceramic capacitor according to the third embodiment of the present invention. Figure 25 yes Figure 23 The diagram shows a cross-sectional view along line XXIV-XXIV, and is used to illustrate the construction of an example of a multilayer ceramic capacitor according to the third embodiment of the present invention.

[0334] The third embodiment of the present invention relates to a multilayer ceramic capacitor 610, which includes a multilayer body 12 having the same structure as the multilayer ceramic capacitor 10 of the first embodiment, and an external electrode 24. However, the multilayer ceramic capacitor 610, compared to the multilayer ceramic capacitor 10 of the first embodiment, has an altered relationship between the size of the L dimension and the W dimension, with the W dimension being larger than the L dimension.

[0335] Having a structure as described above Figure 23The stacked ceramic capacitor 610 shown has the same effect as the stacked ceramic capacitor 10 of the first embodiment.

[0336] Furthermore, the multilayer ceramic capacitor according to the third embodiment of the present invention is preferably configured such that the external electrode 24 of the multilayer ceramic capacitor 610 is the same as all or part of the first to fourth modifications of the multilayer ceramic capacitor 10 of the first embodiment, and is configured to combine all or part of them.

[0337] 2. Manufacturing method of multilayer ceramic capacitors

[0338] Hereinafter, a method for manufacturing a multilayer ceramic capacitor, which is an example of a multilayer ceramic capacitor according to the third embodiment, will be described.

[0339] The manufacturing method of the multilayer ceramic capacitor according to the third embodiment is the same as that of the multilayer ceramic capacitor according to the first embodiment. However, the dimensions of L and W are interchanged compared to the multilayer ceramic capacitor 10 of the first embodiment.

[0340] As described above, it is possible to manufacture Figure 23 The third embodiment shown relates to a multilayer ceramic capacitor 610.

[0341] According to the manufacturing method of the multilayer ceramic capacitor of this embodiment as described above, the thickness of the T dimension in the height direction x of the external electrode 24 formed on the first main surface 12a can be reduced, thus providing a multilayer ceramic capacitor with further reduced height.

[0342] Furthermore, as described above, embodiments of the present invention have been disclosed in the above description, but the present invention is not limited thereto.

[0343] That is, various changes can be made to the above-described embodiments and variations in terms of mechanism, shape, material, quantity, position or configuration without departing from the technical concept and scope of the present invention, and these changes are also included in the present invention.

[0344] <1>

[0345] A multilayer ceramic capacitor, comprising:

[0346] A laminate includes a plurality of stacked dielectric layers and a plurality of internal electrode layers stacked on the dielectric layers, and has a first main surface and a second main surface opposite to each other in the stacking direction of the plurality of dielectric layers, a first side surface and a second side surface opposite to each other in a width direction orthogonal to the stacking direction, and a first end surface and a second end surface opposite to each other in a length direction orthogonal to the stacking direction and the width direction.

[0347] A first external electrode is disposed on the first main surface and the first end surface of the laminate; and

[0348] The second external electrode is disposed on the first main surface and the second end surface of the laminate.

[0349] The internal electrode layer is exposed from the first end face and the second end face, respectively.

[0350] The first end face and the second end face of the exposed internal electrode layer are inclined such that they widen at the ends from the first main face toward the second main face.

[0351] A first protrusion, consisting of the dielectric layer and the internal electrode layer, is disposed on the first end face and the second end face.

[0352] <2>

[0353] according to <1> The aforementioned multilayer ceramic capacitor, wherein,

[0354] have:

[0355] A third external electrode is disposed on the first side of the laminate; and

[0356] The fourth external electrode is disposed on the second side of the laminate.

[0357] The internal electrode layer is exposed from the first side and the second side, respectively.

[0358] The first and second sides of the exposed internal electrode layer are inclined so that they widen at the ends from the first main surface toward the second main surface.

[0359] The first side and the second side have a second protrusion formed by the dielectric layer and the internal electrode layer.

[0360] When the dimension in the length direction is set as L and the dimension in the width direction is set as W, 7 / 10≤L / W≤10 / 7.

[0361] <3>

[0362] according to <1> or <2> The aforementioned multilayer ceramic capacitor, wherein,

[0363] At least two of the first protrusions are respectively disposed on the first end face and the second end face.

[0364] <4>

[0365] according to <2> The aforementioned multilayer ceramic capacitor, wherein,

[0366] At least two of the second protrusions are respectively disposed on the first side and the second side.

[0367] <5>

[0368] according to <1> to <4> The multilayer ceramic capacitor described in any one of the following statements, wherein,

[0369] In the width direction, in the first protrusion,

[0370] The thickest part in the direction perpendicular to the end face is designated as the vertex T1 of the first protrusion.

[0371] Let the endpoint of the first protrusion on the first main surface side be P1, and

[0372] When the endpoint of the first protrusion on the second main surface side is set to P2,

[0373] ∠T1P1P2≥∠T1P2P1.

[0374] <6>

[0375] according to <2> or <4> The aforementioned multilayer ceramic capacitor, wherein,

[0376] In the length direction, in the second protrusion,

[0377] The thickest part in the direction perpendicular to the side is designated as the vertex T2 of the second protrusion.

[0378] Let P3 be the endpoint of the second protrusion on the first main surface side.

[0379] When the endpoint of the second protrusion on the second main surface side is set to P4,

[0380] ∠T2P1P2≥∠T2P2P1.

[0381] <7>

[0382] according to <5> The aforementioned multilayer ceramic capacitor, wherein,

[0383] The ∠T1P1P2 and the ∠T1P2P1 are each greater than 15° and less than 75°.

[0384] <8>

[0385] according to <6> The aforementioned multilayer ceramic capacitor, wherein,

[0386] The ∠T2P1P2 and the ∠T2P2P1 are respectively above 15° and below 75°.

[0387] <9>

[0388] according to <1> to <8> The multilayer ceramic capacitor described in any one of the following statements, wherein,

[0389] In a direction perpendicular to the end face, the thickness of the first protrusion is 0.3 μm or more and 3.0 μm or less.

[0390] <10>

[0391] according to <1> The aforementioned multilayer ceramic capacitor, wherein,

[0392] The dimension in the width direction is larger than the dimension in the length direction.

[0393] Explanation of reference numerals in the attached figures

[0394] 10, 10A, 10B, 10C, 10D, 10E, 510, 610: Multilayer ceramic capacitors;

[0395] 12, 512: Layered bodies;

[0396] 12a, 512a: First principal face;

[0397] 12b, 512b: Second main face;

[0398] 12c, 512c: First side view;

[0399] 12d, 512d: Second side view;

[0400] 12e: First end face;

[0401] 12f: Second end face;

[0402] 14, 514: Dielectric layer;

[0403] 15a, 515a: Inner layer;

[0404] 15b1, 515b1: Outer layer of the first main surface;

[0405] 15b2, 515b2: Outer layer of the second main surface;

[0406] 16, 516: Internal electrode layer;

[0407] 16a, 516a: First internal electrode layer;

[0408] 16b, 516b: Second internal electrode layer;

[0409] 18a, 518a: First opposing electrode section;

[0410] 18b, 518b: Second opposing electrode section;

[0411] 20a, 520a: First lead-out electrode section;

[0412] 20b, 520b: Second lead-out electrode section;

[0413] 22a, 522a, 522b: Side part;

[0414] 22b: End;

[0415] 24, 524, 525: External electrodes;

[0416] 24a, 524a: First external electrode;

[0417] 24b, 524b: Second external electrode;

[0418] 26, 526, 527: Thin film layer;

[0419] 26a, 526a: First thin film layer;

[0420] 26b, 526b: Second thin film layer;

[0421] 28: Substrate electrode layer;

[0422] 28a: First base electrode layer;

[0423] 28b: Second base electrode layer;

[0424] 28: Direct plating layer;

[0425] 28a: First direct plating layer;

[0426] 28b: Second direct plating layer;

[0427] 30, 530, 531: Plating layer;

[0428] 30a, 530a: First plating layer;

[0429] 30b, 530b: Second plating layer;

[0430] 32: Lower plating layer;

[0431] 32a: First lower plating layer;

[0432] 32b: Second lower plating layer;

[0433] 34, 534, 535: Top plating layer;

[0434] 34a, 534a: the first upper plating layer;

[0435] 34b, 534b: Second upper plating layer;

[0436] 36, 536, 537: Surface plating;

[0437] 36a, 536a: First plating layer;

[0438] 36b, 536b: Second plating layer;

[0439] 512e: Third side;

[0440] 512f: Fourth side view;

[0441] 521a: Third lead-out electrode section;

[0442] 521b: Fourth lead-out electrode section;

[0443] 525a: Third external electrode;

[0444] 525b: Fourth external electrode;

[0445] 527a: Third thin film layer;

[0446] 527b: Fourth thin film layer;

[0447] 531a: Third plating layer;

[0448] 531b: Fourth plating layer;

[0449] 535a: Third upper plating layer;

[0450] 535b: Fourth upper plating layer;

[0451] 537a: Third surface plating layer;

[0452] 537b: Surface 4 plating.

Claims

1. A multilayer ceramic capacitor, comprising: A laminate includes a plurality of stacked dielectric layers and a plurality of internal electrode layers stacked on the dielectric layers, and has a first main surface and a second main surface opposite to each other in the stacking direction of the plurality of dielectric layers, a first side surface and a second side surface opposite to each other in a width direction orthogonal to the stacking direction, and a first end surface and a second end surface opposite to each other in a length direction orthogonal to the stacking direction and the width direction. A first external electrode is disposed on the first main surface and the first end surface of the laminate; and The second external electrode is disposed on the first main surface and the second end surface of the laminate. The internal electrode layer is exposed from the first end face and the second end face, respectively. The first end face and the second end face of the exposed internal electrode layer are inclined such that they widen at the ends from the first main face toward the second main face. A first protrusion, consisting of the dielectric layer and the internal electrode layer, is disposed on the first end face and the second end face.

2. The multilayer ceramic capacitor according to claim 1, wherein, have: A third external electrode is disposed on the first side of the laminate; and The fourth external electrode is disposed on the second side of the laminate. The internal electrode layer is exposed from the first side and the second side, respectively. The first and second sides of the exposed internal electrode layer are inclined so that they widen at the ends from the first main surface toward the second main surface. The first side and the second side have a second protrusion formed by the dielectric layer and the internal electrode layer. When the dimension in the length direction is set as L and the dimension in the width direction is set as W, 7 / 10≤L / W≤10 / 7.

3. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein, At least two of the first protrusions are respectively disposed on the first end face and the second end face.

4. The multilayer ceramic capacitor according to claim 2, wherein, At least two of the second protrusions are respectively disposed on the first side and the second side.

5. The multilayer ceramic capacitor according to any one of claims 1 to 4, wherein, In the width direction, in the first protrusion, The thickest part in the direction perpendicular to the end face is designated as the vertex T1 of the first protrusion. Let the endpoint of the first protrusion on the first main surface side be P1, and When the endpoint of the first protrusion on the second main surface side is set to P2, ∠T1P1P2≥∠T1P2P1.

6. The multilayer ceramic capacitor according to claim 2 or claim 4, wherein, In the length direction, in the second protrusion, The thickest part in the direction perpendicular to the side is designated as the vertex T2 of the second protrusion. The endpoint of the second protrusion on the first main surface side is designated as P3, and When the endpoint of the second protrusion on the second main surface side is set to P4, ∠T2P1P2≥∠T2P2P1.

7. The multilayer ceramic capacitor according to claim 5, wherein, The ∠T1P1P2 and the ∠T1P2P1 are respectively above 15° and below 75°.

8. The multilayer ceramic capacitor according to claim 6, wherein, The ∠T2P1P2 and the ∠T2P2P1 are respectively above 15° and below 75°.

9. The multilayer ceramic capacitor according to any one of claims 1 to 8, wherein, In a direction perpendicular to the end face, the thickness of the first protrusion is 0.3 μm or more and 3.0 μm or less.

10. The multilayer ceramic capacitor according to claim 1, wherein, The dimension in the width direction is larger than the dimension in the length direction.

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