Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor having both AC voltage characteristics and DC bias characteristics. A multilayer ceramic capacitor (1) is provided with: a laminated body provided with an inner layer section (6) in which dielectric layers (4) and internal electrode layers (5) are alternately laminated, an outer layer section (7) disposed so as to sandwich the inner layer section (6) from the lamination direction (T), and a side gap section (8) disposed so as to sandwich the inner layer section (6) from the width direction (W); and external electrodes (3), which are respectively disposed on both end surfaces of the laminated body (2) in the longitudinal direction (L), and which are connected to the internal electrode layers. The average particle diameter Rd of ceramic crystal grains in the dielectric layer (4), the average particle diameter Rs of ceramic crystal grains in the side gap portion (8), and the average particle diameter Ro of ceramic crystal grains in the outer layer portion (7) satisfy the following relational expression (1): Rd < = Rslt; ro... (1).

Description

TECHNICAL FIELD

[0001] The present application relates to a multilayer ceramic capacitor. BACKGROUND

[0002] In recent years, in a multilayer ceramic capacitor, downsizing and large capacitance of electrostatic capacitance are required. Therefore, in an inner layer portion in which a capacitor is formed, in order to form a dielectric layer of high dielectric constant, growth of ceramic grains constituting the dielectric layer is promoted, and generally, the ceramic grains in the dielectric layer of the inner layer portion are designed to have a larger particle diameter than the ceramic grains in the outer layer portion and the side gap portion.

[0003] However, even if it is assumed that the dielectric constant of the dielectric layer is increased by promoting the growth of the ceramic grains, if such a multilayer ceramic capacitor is mounted, depending on the environment of use, there can be cases where the AC voltage characteristics and the DC bias characteristics deteriorate.

[0004] Further, in the case where the dielectric layer is thinned in response to the large capacitance, the growth of the ceramic grains can damage the smoothness of the dielectric layer, making it easy to cause a short circuit, poor insulation, and thus also easily leading to a problem of a decrease in reliability of the multilayer ceramic capacitor.

[0005] Therefore, development of a multilayer ceramic capacitor that takes into account the AC voltage characteristics and the DC bias characteristics is required.

[0006] PRIOR ART DOCUMENTS

[0007] PATENT DOCUMENTS

[0008] Patent Document 1: Japanese Patent Application Publication No. 2012-227260 SUMMARY

[0009] PROBLEMS TO BE SOLVED BY THE INVENTION

[0010] An object of the present application is to provide a multilayer ceramic capacitor that takes into account the AC voltage characteristics and the DC bias.

[0011] TECHNICAL SOLUTION TO THE PROBLEM

[0012] The present inventors have found that, in the case where the average particle diameter Rd of the ceramic grains in the dielectric layer, the average particle diameter Rs of the ceramic grains in the side gap portion, and the average particle diameter Ro of the ceramic grains in the outer layer portion satisfy a given relationship, the AC voltage characteristics and the DC bias can be taken into account, and the present application has been completed as a result.

[0013] That is, the present application is a multilayer ceramic capacitor having:

[0014] A laminated body comprising an inner layer portion in which dielectric layers and internal electrode layers are alternately stacked, an outer layer portion configured to sandwich the inner layer portion from a stacking direction, and a side gap portion configured to sandwich the inner layer portion from a width direction intersecting the stacking direction; and

[0015] External electrodes are respectively disposed on both end faces of the laminate along the length direction intersecting the lamination direction and the width direction, and are connected to the internal electrode layer.

[0016] in,

[0017] The average grain size Rd of the ceramic grains in the dielectric layer, the average grain size Rs of the ceramic grains in the side gap, and the average grain size Ro of the ceramic grains in the outer layer satisfy the following relationship (1).

[0018] Rd≤Rs <Ro ···(1)。

[0019] Invention Effects

[0020] According to the present invention, a multilayer ceramic capacitor that combines AC voltage characteristics and DC bias characteristics can be provided. Attached Figure Description

[0021] Figure 1 This is a schematic three-dimensional view of the multilayer ceramic capacitor 1.

[0022] Figure 2 yes Figure 1 The cross-sectional view of the multilayer ceramic capacitor shown is along line II-II.

[0023] Figure 3 yes Figure 1 The cross-sectional view of the multilayer ceramic capacitor shown is along line III-III.

[0024] Figure 4 The images are obtained by taking cross-sectional photos of various regions of the multilayer ceramic capacitor of the present invention using an electron microscope (the accompanying photos are substitute photographs).

[0025] Figure 5 Images of various regions of the cross-section of the present invention and conventional multilayer ceramic capacitors obtained by electron microscopy (see attached photographs). Detailed Implementation

[0026] The following describes a multilayer ceramic capacitor according to an embodiment of the present invention, but the present invention is not limited thereto. Furthermore, for the purpose of illustrating the invention, the drawings are sometimes schematically simplified, and sometimes the dimensions of the depicted components or the ratios between the dimensions of the components differ from those described in the specification. Additionally, the components described in the specification are sometimes omitted in the drawings, and sometimes the number of components is omitted, etc.

[0027] (Laminated ceramic capacitor)

[0028] exist Figures 1-3 The shape and structure of the multilayer ceramic capacitor 1 are shown in the figure. Figure 1 This is a schematic three-dimensional view of the multilayer ceramic capacitor 1. Figure 2 Is Figure 1 A cross-sectional view (LT view) of the multilayer ceramic capacitor 1 cut off at line II-II in the central part of the width direction W shown. Figure 3 Is Figure 1 A cross-sectional view (WT view) of the multilayer ceramic capacitor 1 cut off at line III-III in the central part of the length direction L. Figure 4 The images are obtained by taking cross-sectional images of the multilayer ceramic capacitor 1 of the present invention using an electron microscope. Figure 5 Images of various regions of the WT cross-section of the multilayer ceramic capacitor 1 of the present invention and a conventional multilayer ceramic capacitor are obtained by taking pictures with an electron microscope. Furthermore, the orientation of the multilayer dielectric layer 4 and the internal electrode layer 5 is defined as the stacking direction T, and the length direction L, which is orthogonal to the stacking direction T, and the width direction W, which is orthogonal to both the stacking direction T and the length direction L, are used to describe the structure of the multilayer ceramic capacitor 1. In addition, in the embodiment, the width direction W, the length direction L, and the stacking direction T are orthogonal to each other, but they are not necessarily mutually orthogonal; they may also be mutually intersecting.

[0029] The multilayer ceramic capacitor 1 is generally rectangular in shape and includes a multilayer body 2 and a pair of external electrodes 3 disposed at both ends of the multilayer body 2. The multilayer body 2 includes an inner layer 6, which contains multiple sets of dielectric layers 4 and internal electrode layers 5.

[0030] Furthermore, among the six outer surfaces of the laminate 2, a pair of opposite outer surfaces in the lamination direction T are designated as the first main surface A1 and the second main surface A2, a pair of opposite outer surfaces in the width direction W are designated as the first side surface B1 and the second side surface B2, and a pair of opposite outer surfaces in the length direction L are designated as the first end surface C1 and the second end surface C2.

[0031] Furthermore, unless there is a specific distinction between the first main surface A1 and the second main surface A2, they will be uniformly referred to as main surface A. Unless there is a specific distinction between the first side surface B1 and the second side surface B2, they will be uniformly referred to as side surface B. Unless there is a specific distinction between the first end surface C1 and the second end surface C2, they will be uniformly referred to as end surface C.

[0032] (Layered structure)

[0033] The laminate 2 includes an inner layer 6, an outer layer 7 disposed on the main surface A side of the inner layer 6, and a side gap 8 disposed on the side surface B side of the inner layer 6. Preferably, the laminate 2 has rounded corners at the edge portion E. The edge portion E is the portion where two surfaces of the laminate 2 intersect, namely the main surface A and the side surface B, the main surface A and the end surface C, or the side surface B and the end surface C, and also includes a corner where the main surface A, the side surface B, and the end surface C intersect.

[0034] (Inner layer)

[0035] The inner layer 6 includes multiple sets of dielectric layers 4 and internal electrode layers 5 that are alternately stacked along the stacking direction T.

[0036] (Dielectric layer)

[0037] The dielectric layer 4 is formed of a ceramic material. For example, a dielectric ceramic with BaTiO3 as the main component can be used. Alternatively, materials incorporating at least one of the following secondary components—Mn compound, Fe compound, Cr compound, Co compound, Ni compound, etc.—can also be used as the ceramic material.

[0038] (Internal electrode layer)

[0039] The internal electrode layer 5 is preferably formed of metallic materials such as Ni, Cu, Ag, Pd, Ag-Pd alloy, and Au.

[0040] The internal electrode layer 5 includes a plurality of first internal electrode layers 5A and a plurality of second internal electrode layers 5B. The first internal electrode layers 5A and the second internal electrode layers 5B are arranged alternately, sandwiching the dielectric layer 4 in between. In addition, unless there is a need to specifically distinguish between the first internal electrode layers 5A and the second internal electrode layers 5B, they are referred to as the internal electrode layer 5.

[0041] The internal electrode layer 5 includes opposing portions 52 that face each other between the first internal electrode layer 5A and the second internal electrode layer 5B, and lead-out portions 51 that are not facing each other between the first internal electrode layer 5A and the second internal electrode layer 5B but extend from the opposing portions 52 to an end face C side. The end of the lead-out portion 51 is exposed at the end face C and is electrically connected to the external electrode 3. The direction in which the lead-out portion 51 extends is different in the first internal electrode layer 5A and the second internal electrode layer 5B, and it is alternately led out to the first end face C1 side and the second end face C2 side. Moreover, by opposing the first internal electrode layer 5A and the second internal electrode layer 5B which are adjacent in the stacking direction T, charge is accumulated between the opposing portions 52, thereby functioning as a capacitor.

[0042] (Outer layer)

[0043] The outer layer 7 is disposed on both main surfaces A of the inner layer 6. The outer layer 7 is formed of ceramic material and can be formed of the same material as the dielectric layer 4 of the inner layer 6.

[0044] (Side gap)

[0045] Side gaps 8 are provided on both sides B of the inner layer 6 in the laminate 2. The side gaps 8 can be integrally formed of the same material as the dielectric layer 4, or they can be formed by attaching the same ceramic material as the dielectric layer 4 to both sides of the inner layer 6 in the width direction W. The side gaps 8 are also referred to as W gaps.

[0046] (External electrode)

[0047] The external electrode 3 can adopt a known structure. For example, it can be configured as a stacked structure including a base electrode layer 30, a first plating layer 31a, and a second plating layer 31b from the end face C side of the laminate 2. The base electrode layer 30 can contain metals such as Ni and Cu. In addition, ceramic powder can also be included as a common material. The first plating layer 31a is, for example, a Ni plating layer. The second plating layer 31b is, for example, a Sn plating layer. Furthermore, a conductive resin layer can be provided between the base electrode layer 30 and the first plating layer 31a. The conductive resin layer is a layer containing conductive metal particles such as Cu, Ag, and Ni and resin. The external electrode 3 is not limited in shape as long as it is electrically connected to the internal electrode layer 5 and functions as an external input / output terminal.

[0048] (Manufacturing method of multilayer ceramic capacitors)

[0049] Next, the manufacturing method of the multilayer ceramic capacitor 1 according to the embodiment will be described.

[0050] The manufacturing method of multilayer ceramic capacitors consists of the following steps: multilayer manufacturing process, firing process, and external electrode formation process.

[0051] (Laminated body manufacturing process)

[0052] In the laminate manufacturing process, firstly, a ceramic slurry obtained by adding solvents to a ceramic material is prepared for forming the dielectric layer 4, and a conductive paste obtained by adding solvents to a metal material is prepared for forming the internal electrode layer 5.

[0053] Then, a raw material sheet is prepared by printing the internal electrode pattern of the internal electrode layer 5 onto the surface of a ceramic raw sheet for forming a sheet from ceramic slurry using conductive paste.

[0054] Next, multiple raw material sheets are stacked so that the internal electrode patterns are staggered by half a spacing in the length direction between adjacent raw material sheets.

[0055] Furthermore, on both sides of the multiple layers of raw material sheets, outer ceramic green sheets are stacked to form the outer layer, and then hot-pressed together to form the mother block component.

[0056] Multiple chips are manufactured by cutting the master block component along a cutting line corresponding to the dimensions of the laminate. The chips are then tumble-ground to round the corners and edges before being fired. This firing process combines the ceramic and metal materials contained in the chips to form a laminate 2 containing multiple dielectric layers 4 and multiple internal electrode layers 5.

[0057] According to the above process, the side gap portion 8 can be formed simultaneously with the formation of the laminate 2. Alternatively, an inner layer portion can be formed first by cutting out from the mother block component, where the ends of the inner electrode layer in the width direction W are exposed on both sides. Then, the side gap portion 8 is attached to both sides of the inner layer portion, covering the exposed ends of the inner electrode layer, thus forming the laminate 2. In this case, the attached side gap portion 8 can be made of the same dielectric ceramic material as the dielectric layer 4.

[0058] (Firing process)

[0059] In the firing process, the laminated sheets undergo debinding and firing treatments to form the main body. Through firing, the conductive paste layer and dielectric layer are co-sintered from the green sheet, becoming the internal electrode layer 5 and dielectric layer 4, respectively. The conditions for the debinding treatment are determined based on the type of organic binder contained in the green sheet and the conductive paste layer. Furthermore, the firing treatment is performed at a temperature sufficient to densify the laminated sheets. For example, it can be performed at a temperature of 1200°C or higher and 1300°C for 0 minutes to 10 minutes. Furthermore, the firing is performed in an atmosphere where the BaTiO3-based compounds, as the main component, are not reduced and the oxidation of the conductive material is suppressed. For example, at an oxygen partial pressure of 1.8 × 10⁻⁶. -9 ~8.7×10 -10 The process can be carried out using a N2-H2-H2O gas flow at MPa. Furthermore, annealing can be performed after firing. The grain growth of the ceramic can be adjusted by controlling the conditions of the firing and annealing processes.

[0060] (External electrode formation process)

[0061] In the external electrode formation process, an external electrode 3 is formed on the laminate 2 to create a multilayer ceramic capacitor 1. The formation of the external electrode 3 can be performed using known methods. For example, a conductive paste, mainly composed of conductive components such as Cu and Ni, is applied and fired onto the exposed end face of the internal electrode phase 5 of the laminate 2 to form a base electrode layer 30. The base electrode layer 30 can also be formed by applying conductive paste to both end faces of the green body before firing and then performing a firing process. After forming the base electrode layer 30, electrolytic plating is performed to form a Ni, Sn, or other plating film on the surface of the base electrode layer 30. The multilayer ceramic capacitor 1 is thus manufactured.

[0062] (Evaluation Test)

[0063] The following evaluation tests were performed on the multilayer ceramic capacitors.

[0064] (a) Specifications

[0065] The specifications related to size, ceramic material, dielectric layer thickness, capacitance, and rated voltage of each multilayer ceramic capacitor in Comparative Examples 1-4 and Examples 1-7 are as follows.

[0066] • Dimensions: L×W×T = 1.0mm×0.5mm×0.5mm

[0067] Ceramic material: BaTiO3

[0068] • Dielectric layer thickness: 0.5μm

[0069] • Capacitance: 13μF

[0070] Rated voltage: 6.3V

[0071] (b) Average grain size of ceramic grains

[0072] (b-1) Preparation of the test sample

[0073] The sample was ground until the WT section was exposed approximately at the center of the sample's length direction L. To clarify the boundaries (grain boundaries) between ceramic grains in the dielectric layer, the sample was heat-treated. The heat treatment temperature was set at a temperature that prevents ceramic grain growth and clarifies the grain boundaries; in this example, the treatment was performed at 1000°C.

[0074] (b-2) Determination of the average grain size of ceramic grains

[0075] The ceramic grains in the dielectric layer 4, the side gap 8, and the outer layer 7 were observed at 30,000x magnification using a scanning electron microscope (SEM). Figure 4 ).

[0076] The average grain size of the ceramic grains is set as the median diameter of the equivalent circle diameter obtained from image analysis based on observations from a scanning electron microscope (SEM). The median diameter of the equivalent circle diameter is the grain size at which the cumulative percentage (D50) of the grain size distribution curve represents 50% of the total grain size.

[0077] (c) Measurement conditions and evaluation criteria

[0078] The following shows the measurement conditions and evaluation criteria for dielectric constant, AC voltage characteristics, and DC bias characteristics.

[0079] (Dielectric constant)

[0080] The dielectric constant is measured using DC3V 100kHz 0.01V. A dielectric constant of 1100 or higher is set to 0 (pass), a dielectric constant of 900 or higher but less than 1100 is set to △ (allowable pass), and a dielectric constant less than 900 is set to × (fail).

[0081] (AC voltage characteristics)

[0082] The capacitance change rate is measured relative to 120Hz 0.5V when the measured voltage changes by 0.01V. A capacitance change rate less than -16% is set as 0 (pass), a capacitance change rate greater than -16% but less than -25% is set as △ (passable), and a capacitance change rate greater than -25% is set as × (fail).

[0083] (DC bias characteristics)

[0084] The capacitance change rate is measured under the condition of 0.01V DC applied voltage changing within the range of 0 to 3.15V at 100kHz. A capacitance change rate less than -55% is set as 0 (pass), a capacitance change rate of more than -55% but less than -65% is set as △ (allowable pass), and a capacitance change rate of more than -65% is set as × (fail).

[0085] (d) Results

[0086] Table 1 shows the average particle size and evaluation results at various locations in the examples and comparative examples.

[0087] [Table 1]

[0088]

[0089] According to the results in Table 1, the average grain size Rd of the ceramic grains in the dielectric layer 4, the average grain size Rs of the ceramic grains in the side gap 8, and the average grain size Ro of the ceramic grains in the outer layer 7 can be represented by the following relationship (1).

[0090] Rd≤Rs <Ro ···(1)

[0091] As shown in the results of Examples 2-4 in Table 1, the average grain size Rd of the ceramic grains in the dielectric layer 4 is more preferably 140 nm or more and 165 nm or less, thereby reliably balancing AC voltage characteristics and DC bias characteristics. When the average grain size Rdc is less than 140 nm, the AC voltage characteristics and DC bias characteristics tend to deteriorate. Furthermore, when it exceeds 165 nm, the AC voltage characteristics and DC bias characteristics tend to deteriorate.

[0092] As shown in the results of Examples 2 to 4 in Table 1, the average grain size Rs of the ceramic grains in the side gap portion 8 is more preferably 151 nm or more and 178 nm or less, thereby reliably balancing AC voltage characteristics and DC bias characteristics. When the average grain size Rs is less than 151 nm, the AC voltage characteristics and DC bias characteristics tend to deteriorate. Furthermore, when it exceeds 178 nm, the AC voltage characteristics and DC bias characteristics tend to deteriorate.

[0093] As shown in the results of Examples 2 to 4 in Table 1, the average grain size Ro of the ceramic grains in the outer layer 7 is more preferably 195 nm or more and 223 nm or less, thereby reliably balancing AC voltage characteristics and DC bias characteristics. When the average grain size Rs is less than 195 nm, the AC voltage characteristics and DC bias characteristics tend to deteriorate. Furthermore, when it exceeds 223 nm, the AC voltage characteristics and DC bias characteristics tend to deteriorate.

[0094] When the average grain size Rdc of the ceramic grains in the central part of the width direction W of the dielectric layer 4 is 137 nm or more and 172 nm or less, and the average grain size Rde of the ceramic grains at both ends of the width direction W of the dielectric layer 4 is 140 nm or more and 152 nm or less, it is possible to reliably balance AC voltage characteristics and DC bias characteristics.

[0095] When the average particle size Rdc is less than 137 nm, the AC voltage characteristics and DC bias characteristics tend to deteriorate. Furthermore, when the particle size exceeds 172 nm, the AC voltage characteristics and DC bias characteristics tend to deteriorate.

[0096] Furthermore, when the average particle size Rde is less than 140 nm, the AC voltage characteristics and DC bias characteristics tend to deteriorate. In addition, when it exceeds 152 nm, the AC voltage characteristics and DC bias characteristics tend to deteriorate.

[0097] Furthermore, the so-called central part of the width direction W of the dielectric layer 4 is a range different from the two ends of the width direction W of the dielectric layer 4, and refers to a range of 25μm from the center of the width direction W.

[0098] Furthermore, the two ends of the width direction W of the dielectric layer 4 refer to the range of 25 μm from the imaginary line hanging down from the two ends of the internal electrode layer 5 disposed on the dielectric layer 4 along the stacking direction T toward the center of the internal electrode layer 4.

[0099] Based on the above, the average grain size Rdc of the ceramic grains in the central part of the width direction W of the dielectric layer 4 and the average grain size Rde of the ceramic grains in the two ends of the width direction W of the dielectric layer 4 can be represented by the following relationship (2).

[0100] 0.81 <Rde / Rdc<1.11 ···(2)

[0101] (e) Determination of Si concentration

[0102] (e-1) Determination Method

[0103] The concentration of Si in dielectric layer 4 was determined by grinding the WT profile of the multilayer ceramic capacitor to expose the profile, and then using energy dispersive X-ray diffraction (EDX) based compositional analysis to detect Si.

[0104] (e-2) Measurement results

[0105] The results showed that by setting the concentration of Si in dielectric layer 4 to be between 0.6 mol and 1.2 mol relative to 100 mol of BaTiO3, both AC voltage and DC bias characteristics could be balanced. When the Si concentration was less than 0.6 mol, both AC voltage and DC bias characteristics tended to deteriorate; furthermore, when the Si concentration exceeded 1.2 mol, both AC voltage and DC bias characteristics tended to deteriorate as well.

[0106] Furthermore, the concentration of Si [Si]dc in the central part of the width direction W of the dielectric layer 4, the concentration of Si [Si]de in the region 25 μm from both ends of the width direction W of the dielectric layer 4, and the concentration of Si [Si]s in the side gap 8 can be expressed by the following relationship (3). By satisfying relationship (3), both AC voltage characteristics and DC bias characteristics can be taken into account.

[0107] [Si]dc≤[Si]de≤[Si]s···(3)

[0108] (f) Thickness of the dielectric layer

[0109] (f-1) Determination method

[0110] Each sample was ground until the WT section was exposed approximately at the center of the length direction L. Then, to eliminate the collapse of the internal electrodes caused by grinding, the ground surfaces were machined by ion milling after grinding. The thickness of the dielectric layer was measured using a scanning electron microscope (SEM).

[0111] (f-2) Measurement results

[0112] In Examples 4 to 6, the thickness of the dielectric layer 4 in the stacking direction T is 0.4 μm or more and 0.8 μm or less. It is suitable to set the thickness of the dielectric layer 4 in the stacking direction T to be 0.4 μm or more and 0.8 μm or less.

[0113] (g) Method for determining the number of ceramic grains in the dielectric layer

[0114] (g-1) Determination Method

[0115] In the WT section, a baseline is determined in the stacking direction T such that it is orthogonal to the inner electrode layer 5, and the number of ceramic grains in the dielectric layer passing through the baseline is determined using a scanning electron microscope (SEM).

[0116] (g-2) Measurement Results

[0117] It is suitable to set the average number of ceramic grains arranged in the stacking direction T in the dielectric layer 4 to 3.3 or more. By forming the dielectric layer with a dense dielectric, a high effective capacitance can be achieved.

[0118] like Figure 5 As shown, by making the ceramic grains in the dielectric layer 4 smaller than those in conventional multilayer ceramic capacitors and forming a uniform core-shell structure, a ceramic capacitor with low dielectric constant and both AC voltage characteristics and DC bias characteristics can be obtained.

[0119] Furthermore, reducing the grain size of ceramic grains can suppress the deformation of stacked flakes during the firing process, thereby improving electrical characteristics such as short-circuit failure rate, insulation resistance, and insulation breakdown voltage (BDV).

[0120] Furthermore, increasing the number of grain boundaries can also improve reliability.

[0121] The embodiments of the present invention have been described above, but the present invention is not limited to these embodiments and can be implemented in various ways without departing from the spirit of the present invention. The present invention includes the following combinations.

[0122] <1> A multilayer ceramic capacitor having:

[0123] A laminated body comprising an inner layer portion in which dielectric layers and internal electrode layers are alternately stacked, an outer layer portion configured to sandwich the inner layer portion from a stacking direction, and a side gap portion configured to sandwich the inner layer portion from a width direction intersecting the stacking direction; and

[0124] External electrodes are respectively disposed on both end faces of the laminate along the length direction intersecting the lamination direction and the width direction, and are connected to the internal electrode layer.

[0125] in,

[0126] The average grain size Rd of the ceramic grains in the dielectric layer, the average grain size Rs of the ceramic grains in the side gap, and the average grain size Ro of the ceramic grains in the outer layer satisfy the following relationship (1).

[0127] Rd≤Rs <Ro ···(1)。

[0128] <2> according to <1> The documented multilayer ceramic capacitors, among which,

[0129] The average grain size Rd of the ceramic grains in the dielectric layer is above 140 nm and below 165 nm.

[0130] <3> according to <1> or <2> The documented multilayer ceramic capacitors, among which,

[0131] The average grain size Rdc of the ceramic grains in the central part of the width direction of the dielectric layer and the average grain size Rde of the ceramic grains in the two ends of the width direction of the dielectric layer satisfy the following relationship (2).

[0132] 0.81 <Rde / Rdc<1.11 ···(2)。

[0133] <4> according to <1> to <3> Any of the described multilayer ceramic capacitors, in which,

[0134] The concentration of Si [Si]dc in the central part of the dielectric layer in the width direction, the concentration of Si [Si]de in both ends of the dielectric layer in the width direction, and the concentration of Si [Si]s in the side gap satisfy the following relationship (3).

[0135] [Si]dc≤[Si]de≤[Si]s···(3).

[0136] <5> according to <1> to <4> Any of the described multilayer ceramic capacitors, in which,

[0137] The thickness of the dielectric layer in the stacking direction is 0.4 μm or more and 0.8 μm or less.

[0138] <6> according to <1> to <5> Any of the described multilayer ceramic capacitors, in which,

[0139] The average number of ceramic grains arranged in the stacking direction in the dielectric layer is 3.3 or more.

[0140] Explanation of reference numerals in the attached figures

[0141] 1. Multilayer ceramic capacitor

[0142] 2-layered body

[0143] 3 External Electrodes

[0144] 4. Dielectric layer

[0145] 5 Internal electrode layer

[0146] 6 Inner layer

[0147] 7 Outer layer

[0148] 8. Side gap section

[0149] 30 Substrate electrode layer

[0150] 31 Coating Layer

[0151] 31a Ni plating

[0152] 31b Sn plating layer

[0153] A main surface

[0154] A1 1st main side

[0155] A2 Second Main Side

[0156] B Side

[0157] B1 First Side

[0158] B2 Second Side

[0159] C end face

[0160] C1 First end face

[0161] C2 Second end face

[0162] E. Ridge section.

Claims

1. A multilayer ceramic capacitor, comprising: A laminated body comprising an inner layer portion in which dielectric layers and internal electrode layers are alternately stacked, an outer layer portion configured to sandwich the inner layer portion from a stacking direction, and a side gap portion configured to sandwich the inner layer portion from a width direction intersecting the stacking direction; and External electrodes are respectively disposed on both end faces of the laminate along the length direction intersecting the lamination direction and the width direction, and are connected to the internal electrode layer. in, The average grain size Rd of the ceramic grains in the dielectric layer, the average grain size Rs of the ceramic grains in the side gap, and the average grain size Ro of the ceramic grains in the outer layer satisfy the following relationship (1). Rd≤Rs <Ro ···(1)。 2. The multilayer ceramic capacitor according to claim 1, wherein, The average grain size Rd of the ceramic grains in the dielectric layer is above 140 nm and below 165 nm.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein, The average grain size Rdc of the ceramic grains in the central part of the width direction of the dielectric layer and the average grain size Rde of the ceramic grains in the two ends of the width direction of the dielectric layer satisfy the following relationship (2). 0.81 <Rde / Rdc<1.11 ···(2)。 4. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein, The concentration of Si [Si]dc in the central part of the dielectric layer in the width direction, the concentration of Si [Si]de in both ends of the dielectric layer in the width direction, and the concentration of Si [Si]s in the side gap satisfy the following relationship (3). [Si]dc≤[Si]de≤[Si]s···(3).

5. The multilayer ceramic capacitor according to any one of claims 1 to 4, wherein, The thickness of the dielectric layer in the stacking direction is 0.4 μm or more and 0.8 μm or less.

6. The multilayer ceramic capacitor according to any one of claims 1 to 5, wherein, The average number of ceramic grains arranged in the stacking direction in the dielectric layer is 3.3 or more.

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