Semiconductor device

Abstract

The base layer (12) is an ion implanted layer, the second base layer (12b) has a peak position (P2) at which the impurity concentration is maximum at a depth different from the boundary of the emitter region (17) and the boundary of the barrier region (16) between the emitter region (17) and the barrier region (16), and a stabilizing layer (19) of the first conductivity type is formed in the surface layer portion of the second base layer (12b) in the FWD region (2) together with the contact region (18). The first electrode (22) is electrically connected to the contact region (18) and the stabilization layer (19) in the FWD region (2).

Description

Cross-reference of related applications

[0001] This application is based on Japanese Patent Application No. 2023-121047, filed on July 25, 2023, the contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to a semiconductor device having an insulated gate bipolar transistor (IGBT) element and a freewheeling diode (FWD) element having an insulated gate structure formed on a common semiconductor substrate. Background Technology

[0003] Previously, semiconductor devices incorporating IGBT elements have been proposed (see, for example, Patent Document 1). Specifically, such semiconductor devices have a P-type base layer disposed on an N-type drift layer, and an N-type emitter region formed on the surface of the base layer. Furthermore, in this semiconductor device, an N-type barrier region dividing the base layer in the thickness direction is disposed within the base layer, thereby suppressing the inflow of holes (i.e., charge carriers) from the drift layer to the base layer side when the IGBT region is in a conducting state.

[0004] Furthermore, in this semiconductor device, the base layer is composed of an ion-implanted layer in which P-type impurities have been implanted. Specifically, if the portion of the base layer on the drift layer side is designated as the first base layer, and the portion located on the opposite side of the first base layer, separated by a barrier region, is designated as the second base layer, the base layer is configured as follows: That is, the first base layer is formed such that a first peak position where the P-type impurity concentration is greatest is located between the barrier region and the drift layer. The second base layer is formed such that a second peak position where the P-type impurity concentration is greatest is located between the emitter region and the barrier region. Furthermore, the first peak position is adjusted to be different from the boundary of the barrier region or the drift layer; for example, it is adjusted to be approximately the center between the barrier region and the drift layer. The second peak position is adjusted to be different from the boundary of the emitter region or the barrier region; for example, it is adjusted to be approximately the center between the emitter region and the barrier region.

[0005] Existing technical documents Patent documents Patent document 1: Japanese Patent Application Publication No. 2010-103326. Summary of the Invention

[0006] Furthermore, the inventors have investigated a semiconductor device with a so-called RC (Reverse Conducting)-IGBT structure, in which IGBT elements and FWD elements are formed on a common semiconductor substrate. Moreover, to simplify the manufacturing process, the inventors have investigated making the base layer in the FWD element the same structure as the IGBT element. In addition, in this semiconductor device, the base layer, emitter region, etc., are formed on one side of the semiconductor substrate.

[0007] In this case, when the second peak position of the second base layer is adjusted as described above, since the base layer is composed of an ion-implanted layer, the impurity concentration gradually decreases from the second peak position for the portion of the second base layer that forms the semiconductor substrate, making it prone to deviation in impurity concentration. Therefore, in the FWD device, the forward voltage may deviate.

[0008] The purpose of this disclosure is to provide a semiconductor device capable of suppressing deviations in the forward voltage.

[0009] According to one aspect of this disclosure, a semiconductor device comprises: a semiconductor substrate having an IGBT region and an FWD region, including: a drift layer of a first conductivity type; a base layer of a second conductivity type formed on the drift layer; a collector layer of the second conductivity type formed in the IGBT region on a side of the drift layer opposite to the base layer side; and a cathode layer of the first conductivity type formed in the FWD region on a side of the drift layer opposite to the base layer side; the semiconductor substrate having one side on the base layer side and the other side on the collector and cathode layer sides; a barrier region of the first conductivity type formed within the base layer, dividing the base layer into a first base layer on the drift layer side and a second base layer on one side of the semiconductor substrate; and a trench gate structure having: a gate insulating film formed on the wall of a trench penetrating the base layer and the barrier region of the IGBT region to reach the drift layer; and a gate... An electrode is formed on a gate insulating film; an emitter region of a first conductivity type is formed on the surface of the second base layer in the IGBT region and is connected to a trench; a contact region of a second conductivity type is formed on the surface of the base layer in the FWD region and has a higher impurity concentration than the base layer; a first electrode is disposed on one side of the semiconductor substrate and is electrically connected to the emitter region and the contact region; and a second electrode is disposed on the other side of the semiconductor substrate and is electrically connected to the collector layer and the cathode layer. The base layer is an ion implantation layer. The second base layer has a peak position with the highest impurity concentration at a depth between the emitter region and the barrier region, which is different from the boundary between the emitter region and the barrier region. A stabilization layer of the first conductivity type is formed on the surface of the second base layer in the FWD region together with the contact region. The first electrode is electrically connected to the contact region and the stabilization layer in the FWD region.

[0010] Therefore, in the FWD region, one side of the semiconductor substrate connected to the first electrode is configured to include a stabilization layer of a first conductivity type, and the first electrode is electrically connected to the contact region and the stabilization layer. Thus, compared to the case where one side of the semiconductor substrate in the FWD region is only composed of the contact region and the second base layer, the proportion of the second base layer, which is prone to impurity concentration deviation in one side of the semiconductor substrate, can be reduced, thereby suppressing the forward voltage deviation of the FWD device.

[0011] Furthermore, the parenthesized reference numerals attached to each constituent element indicate an example of the correspondence between that constituent element and the specific constituent elements described in the embodiments described later. Attached Figure Description

[0012] Figure 1 This is a cross-sectional view of the semiconductor device in the first embodiment.

[0013] Figure 2 yes Figure 1 The diagram shows a plan view of the semiconductor device.

[0014] Figure 3 This is a three-dimensional sectional view of the FWD component.

[0015] Figure 4 This is a graph showing the relationship between the depth of the semiconductor substrate and the impurity concentration of P-type impurities.

[0016] Figure 5 This is a graph showing the relationship between the forward voltage and forward current in the FWD element and the surface concentration of the stabilization layer.

[0017] Figure 6 This is a plan view of the semiconductor device in the second embodiment.

[0018] Figure 7 This is a graph showing the relationship between the collector-emitter voltage and collector current in an IGBT element and the surface concentration of the stabilization layer.

[0019] Figure 8 This is a graph showing the relationship between the gate-emitter voltage and collector current in an IGBT element and the peak position of the stabilization layer. Detailed Implementation

[0020] Hereinafter, embodiments of the present disclosure will be described based on the accompanying drawings. Furthermore, in the following embodiments, the same reference numerals will be used to describe the same or equivalent parts.

[0021] (First Implementation) Reference Figures 1-4The semiconductor device of the first embodiment will be described. Furthermore, the semiconductor device of this embodiment is preferably used, for example, as a power switching element in a power supply circuit such as an inverter or a DC / DC converter.

[0022] The semiconductor device has an IGBT region 1 that functions as an IGBT element and an FWD region 2 adjacent to the IGBT region 1 that functions as an FWD element. That is, the semiconductor device of this embodiment is configured as an RC-IGBT in which the IGBT region 1 and the FWD region 2 are formed within a common semiconductor substrate 10 described later. Furthermore, as will be described later, but in this embodiment, the portion located on the collector layer 24 on the other side 10b of the semiconductor substrate 10 is the IGBT region 1, and the portion located on the cathode layer 25 on the other side 10b of the semiconductor substrate 10 is the FWD region 2.

[0023] Semiconductor devices have N - The semiconductor substrate 10 has a drift layer 11. A P-type base layer 12 is formed on the drift layer 11. Hereinafter, the surface of the semiconductor substrate 10 on the side of the base layer 12 will also be referred to as surface 10a, and the surface of the semiconductor substrate 10 opposite to surface 10a will also be referred to as surface 10b. Furthermore, the semiconductor substrate 10 is, for example, made of a silicon substrate.

[0024] On the semiconductor substrate 10, a plurality of trenches 13 are formed such that they extend from one side 10a through the base layer 12 to the drift layer 11. Thus, the base layer 12 is separated into multiple trenches 13. In this embodiment, the plurality of trenches 13 are formed in the IGBT region 1 and the FWD region 2, respectively. Furthermore, in this embodiment, the plurality of trenches 13 are arranged in a direction intersecting the arrangement directions of the IGBT region 1 and the FWD region 2 (i.e., Figure 1 The groove 13 is formed in a strip shape with its length direction (the depth direction of the paper surface) as the length direction. Furthermore, the length direction of the groove 13 will also be referred to as the length direction below. Figure 2 The vertical direction on the paper surface is the length direction. In addition, the spacing between adjacent grooves 13 (i.e., the pitch interval) is, for example, about 2 μm.

[0025] Each trench 13 is filled with a gate insulating film 14 formed in such a way as to cover the walls of each trench 13 and a gate electrode 15 made of polysilicon or the like formed on the gate insulating film 14. Thus, a trench gate structure is formed.

[0026] Furthermore, the gate electrode 15 disposed in the trench 13 formed in the IGBT region 1 is connected to a drive circuit (not shown) via a gate wiring (not shown). Moreover, a predetermined pulsed gate voltage is applied to this gate electrode 15. Additionally, the gate electrode 15 disposed in the trench 13 formed in the FWD region 2 is electrically connected to the upper electrode 22 (described later) and maintained at a predetermined potential.

[0027] In the base layer 12, an N-type barrier region 16 with a higher impurity concentration than the drift layer 11 is formed by dividing the base layer 12 in the depth direction of the semiconductor substrate 10. Hereinafter, the portion of the base layer 12 on the drift layer 11 side is also referred to as the first base layer 12a, and the portion of the base layer 12 on the semiconductor substrate 10 side is also referred to as the second base layer 12b. Furthermore, the base layer 12 in the IGBT region 1 and the base layer 12 in the FWD region 2 have the same structure.

[0028] Furthermore, in the surface portion of the second base layer 12b, within the IGBT region 1, an N2 layer with a higher impurity concentration than the drift layer 11 is formed. + The emitter region 17 of the type, and the P impurity concentration is higher than that of the base layer 12. + The contact region 18 is of the type. In this embodiment, the emitter region 17 and the contact region 18 are formed such that a portion of the surface layer of the second base layer 12b remains. That is, the emitter region 17 and the contact region 18 are formed such that, in the IGBT region 1, one side 10a of the semiconductor substrate 10 includes the second base layer 12b, the emitter region 17, and the contact region 18. In this embodiment, in the IGBT region 1, the emitter region 17 and the contact region 18 are formed between adjacent trenches 13 in a manner that the contact region 18, the emitter region 17, the contact region 18, and the second base layer 12b are arranged sequentially and repeatedly along the length direction.

[0029] Furthermore, in the surface portion of the base layer 12, in the FWD region 2, a P layer with a higher impurity concentration than the base layer 12 is formed. + The contact region 18 is of the same type as that of the IGBT region 1. Furthermore, an N-type stabilization layer 19 is formed in the FWD region 2 on the surface of the base layer 12. In this embodiment, one side 10a of the semiconductor substrate 10 in the FWD region 2 is composed of the contact region 18 and the stabilization layer 19. That is, in the FWD region 2 of this embodiment, the stabilization layer 19 is formed in the entire area of ​​one side 10a of the semiconductor substrate 10, different from the area where the contact region 18 is formed.

[0030] Furthermore, in this embodiment, the length of the contact region 18 along the length direction in FWD region 2 is shorter than the length of the contact region 18 along the length direction in IGBT region 1. However, the lengths of the contact region 18 along the length direction in FWD region 2 and the contact region 18 along the length direction in IGBT region 1 can be appropriately varied. For example, in FWD region 2, the longer the length of the contact region 18 along the length direction, the smaller the forward voltage Vf when the FWD element performs diode operation.

[0031] In this embodiment, the first base layer 12a and the second base layer 12b are configured as ion-implanted layers formed by ion implantation of P-type impurities into the semiconductor substrate 10 and diffusion of the P-type impurities. Furthermore, as... Figure 4 As shown, the second base layer 12b is formed such that there is a second peak position P2 with the highest impurity concentration between the emitter region 17 and the barrier region 16. The first base layer 12a is formed such that there is a first peak position P1 with the highest impurity concentration between the barrier region 16 and the drift layer 11.

[0032] in addition, Figure 4 Indicates along Figure 1 The relationship between the P-type impurity concentration of the IV-IV line portion and the depth from one side 10a of the semiconductor substrate 10 is shown. Furthermore, the first peak position P1 is adjusted to be different from the boundary between the first base layer 12a and the barrier region 16 or the drift layer 11, for example, adjusted to be approximately the center between the barrier region 16 and the drift layer 11. The second peak position P2 is adjusted to be different from the boundary between the second base layer 12b and the emitter region 17 or the barrier region 16, for example, adjusted to be approximately the center between the emitter region 17 and the barrier region 16. By forming the first base layer 12a and the second base layer 12b in this way, even if the thickness (i.e., position) of the emitter region 17 and the thickness (i.e., position) of the barrier region 16 vary slightly due to manufacturing errors, the maximum values ​​of the impurity concentration in the first base layer 12a and the second base layer 12b become the respective peak positions P1 and P2. Therefore, variations in the threshold voltage Vth can be suppressed. Furthermore, although the illustration is omitted, the emitter region 17, the barrier region 16, and the drift layer 11 are all N-type by setting the corresponding portions to have an N-type impurity concentration that is higher than that of the P-type impurity concentration.

[0033] An interlayer insulating film 21, composed of BPSG (Borophosphosilicate Glass) or similar material, is formed on one side 10a of the semiconductor substrate 10. In the interlayer insulating film 21, a contact hole 21a is formed in the IGBT region 1, exposing the emitter region 17, the contact region 18, and the second base layer 12b. In the interlayer insulating film 21, a contact hole 21b is formed in the FWD region 2, exposing the contact region 18 and the stabilization layer 19.

[0034] Furthermore, on the interlayer insulating film 21, in the IGBT region 1, an upper electrode 22 is formed that is electrically connected to the emitter region 17, the contact region 18, and the second base layer 12b through contact holes 21a formed in the interlayer insulating film 21. On the interlayer insulating film 21, in the FWD region 2, an upper electrode 22 is formed that is electrically connected to the contact region 18 and the stabilization layer 19 through contact holes 21b formed in the interlayer insulating film 21. That is, an upper electrode 22 is formed on the interlayer insulating film 21 that functions as an emitter electrode in the IGBT region 1 and as an anode electrode in the FWD region 2.

[0035] In addition, in this embodiment, the upper electrode 22 is ohmically bonded to the emitter region 17 and the contact region 18, and Schottky bonded to the second base layer 12b.

[0036] Furthermore, in this embodiment, a contact hole 21c is formed in the interlayer insulating film 21 within the FWD region 2, exposing the gate electrode 15. The upper electrode 22 is also connected to the gate electrode 15 through this contact hole 21c. Thus, the gate electrode 15 formed in the FWD region 2 is maintained at the same potential as the upper electrode 22. In this embodiment, the upper electrode 22 corresponds to the first electrode.

[0037] On the side of the drift layer 11 opposite to the base layer 12 (i.e., the other side 10b of the semiconductor substrate 10), an N-type field stop (hereinafter also referred to as the FS layer) 23 with a higher impurity concentration than the drift layer 11 is formed. This FS layer 23 is not necessary, but it is included to improve the breakdown voltage and steady-state loss performance by preventing the expansion of the depletion layer, and to control the amount of holes injected from the other side 10b of the semiconductor substrate 10.

[0038] Furthermore, in IGBT region 1, a P layer is formed on the side opposite to the drift layer 11, separated by the FS layer 23. + The current collector layer 24 of the type, in the FWD region 2, has an N-type current collector layer formed on the side opposite to the drift layer 11, separated by the FS layer 23. +The cathode layer 25 is of the type IGBT. That is, the IGBT region 1 and the FWD region 2 are divided according to whether the layer formed on the other side 10b of the semiconductor substrate 10 is the collector layer 24 or the cathode layer 25. Furthermore, the region on the collector layer 24 is designated as the IGBT region 1, and the region on the cathode layer 25 is designated as the FWD region 2.

[0039] On the side opposite to the drift layer 11 (i.e., the other side 10b of the semiconductor substrate 10) separated from the collector layer 24 and the cathode layer 25, a lower electrode 26 electrically connected to the collector layer 24 and the cathode layer 25 is formed. That is, a lower electrode 26 is formed that functions as a collector electrode in the IGBT region 1 and as a cathode electrode in the FWD region 2. In this embodiment, the lower electrode 26 is ohmically bonded to the collector layer 24 and the cathode layer 25. Furthermore, in this embodiment, the lower electrode 26 corresponds to a second electrode.

[0040] The semiconductor device of this embodiment is configured such that, in IGBT region 1, an IGBT element is formed with base layer 12 and contact region 18 as the base, emitter region 17 as the emitter, and collector layer 24 as the collector. Furthermore, in FWD region 2, an FWD element is formed with base layer 12 and contact region 18 as the anode, and drift layer 11, FS layer 23, and cathode layer 25 forming a PN junction.

[0041] The above describes the structure of the semiconductor device in this embodiment. Furthermore, in this embodiment, N-type, N... + Type, N - Type P is equivalent to the first conductivity type, P-type, P-type + This type is equivalent to the second conductivity type. Furthermore, in this embodiment, the semiconductor substrate 10 is configured as described above, including a collector layer 24, a cathode layer 25, a drift layer 11, a base layer 12, a barrier region 16, an emitter region 17, a contact region 18, a stabilization layer 19, etc.

[0042] Next, the operation of the aforementioned semiconductor device will be explained, and the detailed structure of the semiconductor device will be further explained.

[0043] In a semiconductor device like the described above, when a voltage higher than that of the upper electrode 22 is applied to the lower electrode 26, the PN junction formed between the base layer 12 and the drift layer 11 becomes reverse-conductive, forming a depletion layer. Furthermore, when a low-level (e.g., 0V) gate voltage less than the threshold voltage Vth of the insulating gate structure is applied to the gate electrode 15, no collector current flows between the upper electrode 22 and the lower electrode 26.

[0044] To enable the IGBT element to conduct, a high-level gate voltage, exceeding the threshold voltage Vth of the insulating gate structure, is applied to the gate electrode 15 of the IGBT region 1, while a higher voltage is applied to the lower electrode 26 than to the upper electrode 22. Consequently, an inversion layer is formed in the base layer 12 of the IGBT region 1, at the portion connected to the trench 13. Furthermore, the IGBT element supplies electrons from the emitter region 17 to the drift layer 11 via the inversion layer, thereby supplying holes from the collector layer 24 to the drift layer 11. As a result, the resistance of the drift layer 11 decreases due to conductivity modulation, and a collector current flows between the upper electrode 22 and the lower electrode 26.

[0045] In this embodiment, due to the barrier region 16, holes supplied to the drift layer 11 are difficult to penetrate to the base layer 12. Therefore, the on-state voltage can be reduced.

[0046] Furthermore, when the IGBT element is in the off state and the FWD element is in the on state (i.e., the FWD element operates as a diode), the voltages applied to the upper electrode 22 and the lower electrode 26 are switched, and a forward bias voltage higher than that applied to the lower electrode 26 is applied to the upper electrode 22. Thus, by supplying holes to the base layer 12 and electrons to the cathode layer 25, the FWD element operates as a diode.

[0047] In this embodiment, in the FWD region 2, one side 10a of the semiconductor substrate 10 is formed by a P-type contact region 18 and an N-type stabilization layer 19. That is, in the FWD region 2, the second base layer 12b, where impurity concentration is prone to deviation, is not exposed on one side 10a of the semiconductor substrate 10, and the upper electrode 22 is not in contact with the second base layer 12b. Therefore, the forward voltage Vf of the FWD element depends on the contact region 18. Thus, deviations in the forward voltage Vf of the FWD element can be suppressed.

[0048] Furthermore, in this embodiment, in the IGBT region 1, the second base layer 12b is exposed from one side 10a of the semiconductor substrate 10, and the second base layer 12b is Schottky-bonded to the upper electrode 22. Therefore, for example, compared to a semiconductor device where a portion of the second base layer 12b is set as the contact region 18, when the FWD element is in the on state, the number of holes that can be injected into the second base layer 12b of the IGBT region 1 can be reduced. Therefore, when the voltage between the upper electrode 22 and the lower electrode 26 switches to reverse bias, hole injection is suppressed, thereby reducing the recovery current and shortening the recovery time. Therefore, switching losses can be reduced.

[0049] Furthermore, the inventors conducted in-depth research on the stabilization layer 19 and obtained the following results. For example... Figure 5As shown, it has been confirmed that the higher the surface concentration of the stabilization layer 19, the higher the forward voltage Vf of the FWD element. Therefore, the surface concentration of the stabilization layer 19 is preferably adjusted appropriately according to the application. Furthermore, the surface concentration of the stabilization layer 19 here refers to the N-type impurity concentration of the stabilization layer 19 in one side 10a of the semiconductor substrate 10.

[0050] According to the embodiment described above, the FWD region 2 is configured such that one side 10a of the semiconductor substrate 10 connected to the upper electrode 22 includes an N-type stabilization layer 19. Furthermore, the upper electrode 22 is electrically connected to the contact region 18 and the stabilization layer 19. Therefore, compared to the case where one side 10a of the semiconductor substrate 10 in the FWD region 2 is composed of the contact region 18 and the second base layer 12b, the proportion of the second base layer 12b, which is prone to impurity concentration deviation in one side 10a of the semiconductor substrate 10, can be reduced, and deviation of the forward voltage Vf of the FWD element can be suppressed.

[0051] (1) In this embodiment, one side 10a of the semiconductor substrate 10 of the FWD region 2 is composed of a contact region 18 and a stabilization layer 19. Therefore, the upper electrode 22 is no longer in direct contact with the second base layer 12b, thereby suppressing the deviation of the positive voltage Vf of the FWD element.

[0052] (Second Implementation) The second embodiment will be described. In this embodiment, compared to the first embodiment, a stabilization layer 19 is also formed in the IGBT region 1. Everything else is the same as in the first embodiment, so descriptions are omitted here.

[0053] The semiconductor device in this embodiment is as follows: Figure 6 As shown, a stabilization layer 19 is formed on the surface portion of the second base layer 12b, together with the emitter region 17 and the contact region 18. Furthermore, one side 10a of the semiconductor substrate 10 in the IGBT region 1 is formed by the emitter region 17, the contact region 18, and the stabilization layer 19. Specifically, in the IGBT region 1, the contact region 18, the emitter region 17, the contact region 18, and the stabilization layer 19 are sequentially and repeatedly formed along the length direction between adjacent trenches 13. That is, in the IGBT region 1 of this embodiment, the stabilization layer 19 is formed on one side 10a of the semiconductor substrate 10 in the portion where the second base layer 12b is exposed in the first embodiment. Additionally, the impurity concentration of the stabilization layer 19 is lower than that of the contact region 18.

[0054] The above describes the structure of the semiconductor device in this embodiment. Furthermore, the stabilization layer 19 in such a semiconductor device is formed as follows: After forming the emitter region 17 and the contact region 18 on the surface portion of the second base layer 12b, an N-type impurity is implanted to form the stabilization layer 19. In this case, since the impurity concentration of the stabilization layer 19 is lower than that of the contact region 18, the contact region 18 will not flip into an N-type state even if an N-type impurity is implanted without a mask. Therefore, in this embodiment, by forming the stabilization layer 19 also in the IGBT region 1, an N-type impurity can be implanted without a mask to form the stabilization layer 19, simplifying the manufacturing process.

[0055] Here, with the stabilization layer 19 formed in IGBT region 1, there is concern that the latch-up tolerance might decrease due to the increase in the number of N-type layers, since the stabilization layer 19 is N-type. However, according to the inventors' research, the relationship between the collector-emitter voltage Vce and the collector current Ic and the surface concentration of the stabilization layer 19 was obtained. Figure 7 The results are shown. Furthermore... Figure 7 The surface concentration of emitter region 17 is set to 2.0 × 10⁻⁶. 20 / cm 3 The result under the circumstances.

[0056] like Figure 7 As shown, it was confirmed that when the surface concentration of the stabilization layer 19 is lower than that of the emitter region 17, the latch-up current remains almost unchanged. Therefore, in order to suppress the decrease in latch-up tolerance, the stabilization layer 19 is preferably set to have a lower impurity concentration than that of the emitter region 17.

[0057] Furthermore, when a stabilization layer 19 is formed in IGBT region 1, the stabilization layer 19 may affect the threshold voltage Vth (i.e., the gate-emitter voltage Vge) of the IGBT element. According to the inventors' research, the relationship between the gate-emitter voltage Vge and the collector current Ic and the peak position of the stabilization layer 19 was obtained... Figure 8 The results are shown. Additionally... Figure 8 The peak position of the stabilization layer 19 is defined as the depth from one side 10a of the semiconductor substrate 10 to the location where the impurity concentration of the stabilization layer 19 is the highest. Furthermore, Figure 8 The depth from one side 10a of the semiconductor substrate 10 to the second peak position P2 of the second base layer 12b is set to 0.86 μm. Figure 8 The peak position of the stabilization layer 19 is 0, which means that the stabilization layer 19 has not been formed.

[0058] like Figure 8As shown, it was confirmed that if the peak position of the maximum impurity concentration in the stabilization layer 19 is 0.5 μm or less, the threshold voltage Vth hardly changes. That is, it was confirmed that if the depth from one side 10a of the semiconductor substrate 10 to the peak position of the maximum impurity concentration in the stabilization layer 19 is 58% or less of the depth from one side 10a of the semiconductor substrate 10 to the second peak position P2 of the second base layer 12b, the threshold voltage Vth does not change. Therefore, it is preferable that the depth of the stabilization layer 19 to the peak position of the maximum impurity concentration is 58% or less relative to the depth from one side 10a of the semiconductor substrate 10 to the second peak position P2 of the second base layer 12b.

[0059] According to the embodiment described above, the FWD region 2 is configured such that one side 10a of the semiconductor substrate 10 connected to the upper electrode 22 includes an N-type stabilization layer 19. Therefore, the same effects as in the first embodiment described above can be obtained.

[0060] (1) In this embodiment, a stabilization layer 19 is also formed in the IGBT region 1, and the impurity concentration of the stabilization layer 19 is lower than that in the contact region 18. Therefore, the stabilization layer 19 can be formed by ion implantation of N-type impurities without the need for a mask, which simplifies the manufacturing process.

[0061] (2) In this embodiment, the stabilization layer 19 can suppress the decrease in latch-up tolerance by making the surface concentration lower than that of the emitter region 17.

[0062] (3) In this embodiment, by forming the stabilization layer 19 such that the peak position of the stabilization layer 19 is less than 58% of the second peak position P2 of the second base layer 12b, the threshold voltage Vth variation can be suppressed.

[0063] (Other implementation methods) This disclosure is based on embodiments, but it should be understood that it is not limited to those embodiments or structures. This disclosure also includes various modifications and variations within the same scope. Furthermore, various combinations, forms, and other combinations and forms including only one element, or more than or less thereof, also fall within the scope and spirit of this disclosure.

[0064] For example, in the above embodiments, a semiconductor device with the first conductivity type set to N-type and the second conductivity type set to P-type is described, but it is also possible to have a semiconductor device with the first conductivity type set to P-type and the second conductivity type set to N-type. Furthermore, in the above embodiments, a trench gate structure may not be formed in the FWD region 2.

[0065] Furthermore, in the above embodiments, an example was described in which one side 10a of the semiconductor substrate 10 in the FWD region 2 is formed by the contact region 18 and the stabilization layer 19. However, the stabilization layer 19 may also be formed on a portion of the surface layer of the second base layer 12b, exposing the second base layer 12b from one side 10a of the semiconductor substrate 10. As such a semiconductor device, compared to the case where one side 10a of the semiconductor substrate 10 in the FWD region 2 is composed of the contact region 18 and the second base layer 12b, the proportion of the second base layer 12b, which is prone to impurity concentration deviation, can be reduced in one side 10a of the semiconductor substrate 10. Therefore, the same effect as the first embodiment described above can be obtained.

[0066] Similarly, in the second embodiment described above, an example was given in which one side 10a of the semiconductor substrate 10 in the IGBT region 1 is formed by the emitter region 17, the contact region 18, and the stabilization layer 19. However, the stabilization layer 19 may also be formed in the IGBT region 1 as a part of the surface portion of the second base layer 12b, so that the second base layer 12b is exposed from one side 10a of the semiconductor substrate 10.

[0067] Furthermore, in the second embodiment described above, the surface concentration of the stabilization layer 19 can also be higher than the surface concentration of the emitter region 17. Additionally, the stabilization layer 19 can be formed such that the peak position of the stabilization layer 19 is at a depth greater than 58% relative to the second peak position P2 of the second base layer 12b. As such a semiconductor device, compared to the case where one side 10a of the semiconductor substrate 10 in the FWD region 2 is composed of the contact region 18 and the second base layer 12b, the proportion of the second base layer 12b, where the impurity concentration is prone to deviation in one side 10a of the semiconductor substrate 10, can be reduced. Therefore, the same effects as in the first embodiment described above can be obtained.

[0068] [Disclosure of the Invention] The above disclosure can be understood, for example, as shown in the following viewpoint.

[0069] [First Viewpoint] A semiconductor device comprising an IGBT region (1) having an IGBT element and an FWD region (2) having an FWD element formed on a common semiconductor substrate (10), comprising: the semiconductor substrate having the IGBT region and the FWD region, comprising: a drift layer (11) of a first conductivity type; a base layer (12) of a second conductivity type formed on the drift layer; a collector layer (24) of the second conductivity type formed on the side of the drift layer opposite to the base layer side in the IGBT region; and a cathode layer (25) of the first conductivity type. The FWD region is formed on the side opposite to the base layer side in the drift layer; the semiconductor substrate has the base layer side as one side (10a) and the collector layer and cathode layer side as the other side (10b); a first conductivity type barrier region (16) is formed in the base layer, dividing the base layer into a first base layer (12a) on the drift layer side and a second base layer (12b) on one side of the semiconductor substrate; a trench gate structure has: a gate insulating film (14) formed in the base layer and the barrier layer that penetrate the IGBT region. The wall of the trench (13) reaching the drift layer from the barrier region; and the gate electrode (15) formed on the gate insulating film; the emitter region (17) of the first conductivity type formed on the surface portion of the second base layer of the IGBT region and connected to the trench; the contact region (18) of the second conductivity type formed on the surface portion of the base layer of the FWD region, having a higher impurity concentration than the base layer; the first electrode (22) disposed on one side of the semiconductor substrate and electrically connected to the emitter region and the contact region; and the second electrode (26) disposed on one side of the semiconductor substrate. The second base layer is located on the other side of the semiconductor substrate and is electrically connected to the collector layer and the cathode layer. The base layer is an ion implantation layer. The second base layer has a peak position (P2) with the largest impurity concentration at a depth between the emitter region and the barrier region, which is different from the boundary with the emitter region and the boundary with the barrier region. On the surface of the second base layer in the FWD region, a first conductivity type stabilization layer (19) is formed together with the contact region. The first electrode is electrically connected to the contact region and the stabilization layer in the FWD region.

[0070] [Second Viewpoint] According to the semiconductor device of the first viewpoint, the stabilization layer is formed in the FWD region over the entire area of ​​a portion of one side of the semiconductor substrate that is different from the contact region.

[0071] [Third Viewpoint] According to the semiconductor device described in the first or second viewpoint, the stabilization layer is further formed on the surface portion of the second base layer in the IGBT region.

[0072] [Fourth viewpoint] According to the semiconductor device of the first or second viewpoint, the contact region is also formed in the surface portion of the second base layer in the IGBT region, the stabilization layer is formed in the FWD region in the entire region of a portion of one side of the semiconductor substrate that is different from the contact region, and further in the IGBT region in the entire region of a portion of one side of the semiconductor substrate that is different from the emitter region and the contact region, wherein the impurity concentration of the stabilization layer is lower than that of the contact region.

[0073] [Fifth Viewpoint] According to the third or fourth viewpoint, for the stabilization layer of the IGBT region, the depth from one side of the semiconductor substrate to the peak position where the impurity concentration in the second base layer is the maximum is 58% or less.

Claims

1. A semiconductor device comprising an IGBT region (1) having IGBT elements and an FWD region (2) having FWD elements formed on a common semiconductor substrate (10), characterized in that, have: The semiconductor substrate, having the IGBT region and the FWD region, includes: a drift layer (11) of a first conductivity type; a base layer (12) of a second conductivity type formed on the drift layer; a collector layer (24) of a second conductivity type formed in the IGBT region on the side of the drift layer opposite to the base layer side; and a cathode layer (25) of the first conductivity type formed in the FWD region on the side of the drift layer opposite to the base layer side; the semiconductor substrate has the base layer side as one side (10a) and the collector layer and cathode layer side as another side (10b). A barrier region (16) of the first conductivity type is formed in the base layer, dividing the base layer into a first base layer (12a) on the drift layer side and a second base layer (12b) on one side of the semiconductor substrate. The trench gate structure has: a gate insulating film (14) formed on the wall of a trench (13) that extends through the base layer and the barrier region of the IGBT region to the drift layer; and a gate electrode (15) formed on the gate insulating film. The emitter region (17) of the first conductivity type is formed on the surface of the second base layer of the IGBT region and is in contact with the trench; The second conductivity type contact region (18) is formed on the surface of the base layer in the FWD region and has a higher impurity concentration than the base layer. The first electrode (22) is disposed on one side of the semiconductor substrate and is electrically connected to the emitter region and the contact region; as well as The second electrode (26) is disposed on the other side of the semiconductor substrate and is electrically connected to the collector layer and the cathode layer. The base layer is an ion implantation layer. The second base layer, at a depth between the emitter region and the barrier region, different from the boundary with both the emitter region and the barrier region, has a peak position (P2) with the highest impurity concentration. In the surface portion of the second base layer in the FWD region, a stabilizing layer (19) of a first conductivity type is formed together with the contact region. The first electrode is electrically connected to the contact area and the stabilization layer in the FWD region.

2. The semiconductor device according to claim 1, characterized in that, The stabilization layer is formed in the FWD region over the entire area of ​​a portion of one side of the semiconductor substrate that is different from the contact region.

3. The semiconductor device according to claim 1, characterized in that, The stabilization layer is also formed on the surface portion of the second base layer in the IGBT region.

4. The semiconductor device according to claim 1, characterized in that, The contact area is also formed in the surface portion of the second base layer in the IGBT region. The stabilization layer is formed in the FWD region over the entire area of ​​one side of the semiconductor substrate that is different from the contact region, and further in the IGBT region over the entire area of ​​one side of the semiconductor substrate that is different from the emitter region and the contact region, wherein the impurity concentration of the stabilization layer is lower than that of the contact region.

5. The semiconductor device according to claim 3 or 4, characterized in that, For the stabilization layer of the IGBT region, the depth from one side of the semiconductor substrate to the peak position where the impurity concentration in the second base layer is the maximum is less than 58%.

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