Semiconductor device

Abstract

Provided is a semiconductor device having a high operating speed. The semiconductor device includes an oxide semiconductor disposed on a substrate, a first insulator, a second insulator, a first conductor, a second conductor, and a third conductor, the first conductor and the second conductor being disposed on the oxide semiconductor. The first insulator is disposed on the first conductor and the second conductor and includes an opening overlapping a region between the first conductor and the second conductor, the second insulator is disposed in the opening so as to overlap the oxide semiconductor, and the third conductor is disposed on the second insulator in the opening. The height of the oxide semiconductor is greater than the width of the oxide semiconductor, and the semiconductor device has two or more regions in which the oxide semiconductor overlaps the third conductor in plan view.

Description

TECHNICAL FIELD

[0001] One embodiment of the present application relates to a semiconductor device, a memory device, and an electronic appliance using an oxide semiconductor layer. Another embodiment of the present application relates to a method for manufacturing the above semiconductor device.

[0002] Note that one embodiment of the present application is not limited to the above technical field. Examples of a technical field to which one embodiment of the present application pertains include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic appliance, a lighting device, an input device (e.g., a touch sensor), an input-output device (e.g., a touch panel), a method for driving the above device, and a method for manufacturing the above device.

[0003] Note that in this specification and the like, a semiconductor device generally means a device that can function by utilizing semiconductor characteristics. A semiconductor element such as a transistor and a semiconductor circuit are one embodiment of the semiconductor device. A display device (a liquid crystal display device, a light-emitting display device, etc.), a projection device, a lighting device, an electro-optical device, a power storage device, a memory device, a semiconductor circuit, an imaging device, an electronic appliance, and the like may, in some cases, be included in the semiconductor device. BACKGROUND

[0004] In recent years, semiconductor devices have been developed, and LSI (Large Scale Integration), a CPU (Central Processing Unit), a memory, and the like are mainly used as semiconductor devices. The CPU is a collection of semiconductor integrated circuits (at least including a transistor and a memory) formed by processing a semiconductor wafer into chips and formed with a semiconductor element having an electrode as a connection terminal.

[0005] The semiconductor circuit (IC chip) of the LSI, the CPU, the memory, and the like is mounted on a circuit board, e.g., a printed wiring board, and is used as one of components of various electronic appliances.

[0006] Further, a technique for forming a transistor using a semiconductor thin film formed over a substrate having an insulating surface has attracted attention. The transistor is widely applied to electronic devices such as integrated circuits (ICs), image display devices (simply referred to as display devices), and the like. As a semiconductor thin film which can be used for transistors, a silicon-based semiconductor material is widely known, and an oxide semiconductor has attracted attention as another material.

[0007] In addition, it is known that a transistor using an oxide semiconductor has extremely small off-state current. For example, Patent Document 1 discloses a low-power CPU or the like which utilizes the characteristic of small off-state current of a transistor using an oxide semiconductor. Further, for example, Patent Document 2 discloses a storage device or the like which utilizes the characteristic of small off-state current of a transistor using an oxide semiconductor to achieve long-term retention of stored contents.

[0008] [Patent Literature]

[0009] [Patent Literature]

[0010] [Patent Document 1] Japanese Published Patent Application No. 2012-257187

[0011] [Patent Document 2] Japanese Published Patent Application No. 2011-151383 SUMMARY

[0012] PROBLEMS TO BE SOLVED BY THE INVENTION

[0013] One of objects of one embodiment of the present application is to provide a semiconductor device with high operation speed. One of objects of one embodiment of the present application is to provide a semiconductor device which can be miniaturized or highly integrated. One of objects of one embodiment of the present application is to provide a semiconductor device with good electric characteristics. One of objects of one embodiment of the present application is to provide a semiconductor device in which electric characteristics of transistors are less likely to be non-uniform. One of objects of one embodiment of the present application is to provide a semiconductor device with high reliability. One of objects of one embodiment of the present application is to provide a semiconductor device with large on-state current. One of objects of one embodiment of the present application is to provide a semiconductor device with low power consumption. One of objects of one embodiment of the present application is to provide a novel semiconductor device. One of objects of one embodiment of the present application is to provide a manufacturing method of a semiconductor device with high productivity. One of objects of one embodiment of the present application is to provide a manufacturing method of a novel semiconductor device.

[0014] One of objects of one embodiment of the present application is to provide a storage device which can be miniaturized or highly integrated. One of objects of one embodiment of the present application is to provide a storage device with large storage capacity. One of objects of one embodiment of the present application is to provide a storage device with high operation speed. One of objects of one embodiment of the present application is to provide a storage device with low power consumption. One of objects of one embodiment of the present application is to provide a novel storage device.

[0015] Note that the description of these objects does not preclude the existence of other objects. One embodiment of the present application does not necessarily achieve all the above-described objects. An object other than the above-described objects can be extracted from the description, drawings, and claims.

[0016] Means for solving technical problems

[0017] One embodiment of the present application is a semiconductor device including an oxide semiconductor, a first and a second insulator, and a first to a third conductor, in which the oxide semiconductor is provided over a substrate, the first and the second conductor are provided over the oxide semiconductor, the first insulator is provided over the first and the second conductor and includes an opening overlapping a region between the first and the second conductor, the second insulator is provided in the opening so as to overlap the oxide semiconductor, the third conductor is provided in the opening over the second insulator, a height of the oxide semiconductor is larger than a width of the oxide semiconductor when viewed in a cross section in a channel width direction, and the semiconductor device has two or more regions where the oxide semiconductor and the third conductor overlap each other when viewed in a plan view.

[0018] One embodiment of the present application is a semiconductor device including an oxide semiconductor, a first to a third insulator, and a first to a third conductor, in which the oxide semiconductor is provided over a substrate, the first and the second conductor are provided over the oxide semiconductor, the first insulator is provided over the first and the second conductor and includes an opening overlapping a region between the first and the second conductor, the second insulator is provided in the opening so as to overlap the oxide semiconductor, the third conductor is provided in the opening over the second insulator, the third insulator is provided below the oxide semiconductor and overlaps the oxide semiconductor when viewed in a plan view, a thickness of the third insulator is larger than a thickness of the second insulator, a height of the oxide semiconductor is larger than a width of the oxide semiconductor when viewed in a cross section in a channel width direction, and the semiconductor device has two or more regions where the oxide semiconductor and the third conductor overlap each other when viewed in a plan view.

[0019] In the above embodiment, a bottom surface of the third conductor preferably has a portion positioned below a bottom surface of the oxide semiconductor.

[0020] In the above embodiment, the oxide semiconductor preferably has a circumferential shape in which both end portions align with each other when viewed in a plan view.

[0021] In the above embodiment, a side surface of the opening of the first insulator preferably aligns or substantially aligns with a side surface of the first conductor and a side surface of the second conductor when viewed in a plan view.

[0022] In the above embodiment, it is preferable that the width of the oxide semiconductor be greater than or equal to 5 nm and less than or equal to 50 nm when viewed in a cross section in a channel width direction, and the height of the oxide semiconductor be greater than or equal to twice and less than or equal to ten times the width of the oxide semiconductor when viewed in a cross section in a channel width direction.

[0023] In the above, preferably, the oxide semiconductor contains indium, and the oxide semiconductor is formed perpendicular or substantially perpendicular to the surface of the substrate, and when the oxide semiconductor is observed in cross section using a transmission electron microscope, bright spots arranged in layers in a direction perpendicular to the surface of the substrate are confirmed.

[0024] In the above, preferably, the oxide semiconductor comprises indium, and the oxide semiconductor is formed perpendicular or substantially perpendicular to the surface of the substrate. The oxide semiconductor includes a first region, a second region in contact with the first region, and a third region in contact with the second region. When the oxide semiconductor is observed in cross section using a transmission electron microscope, bright spots arranged in layers in a direction perpendicular to the surface of the substrate are identified in each of the first region, the second region, and the third region.

[0025] In the above, preferably, the second region contains zinc and has a crystal, the c-axis of which is substantially parallel to the normal direction of the side surface of the oxide semiconductor.

[0026] In the above, it is preferred that the indium content in the first region is higher than that in the second region, and the indium content in the third region is higher than that in the second region.

[0027] One aspect of the present invention is a semiconductor device comprising first and second oxide semiconductors, first to third insulators, and first to fourth conductors, wherein the first and second oxide semiconductors are disposed on a substrate, the first conductor is disposed on the first oxide semiconductor, the second conductor is disposed on the first and second oxide semiconductors, the first insulator is disposed on the first and second conductors and includes a first opening and a second opening, the first opening overlapping the region between the first and second conductors and reaching the first oxide semiconductor, the second opening overlapping the second oxide semiconductor and reaching the second conductor, the second insulator overlapping the first oxide semiconductor and disposed within the first opening, the third conductor disposed within the first opening on the second insulator, the third insulator overlapping the second conductor and disposed within the second opening, and the fourth conductor disposed within the second opening on the third insulator. In a cross-section viewed from the channel width direction, the height of the first oxide semiconductor is greater than the width of the first oxide semiconductor, and the semiconductor device, in a top view, has two or more regions where the first oxide semiconductor and the third conductor overlap.

[0028] In the above, it is preferable that, when viewed in cross-section from the channel width direction, the height of the second oxide semiconductor is greater than the width of the second oxide semiconductor, and the semiconductor device has two or more regions where the second oxide semiconductor and the fourth conductor overlap when viewed from above.

[0029] One embodiment of the present application is a semiconductor device including a first oxide semiconductor, a first to third insulator, and a first to fourth conductor, in which the first oxide semiconductor is provided over a substrate, the first and second conductors are provided over the first oxide semiconductor, the first insulator is provided over the first and second conductors and includes a first opening and a second opening, the first opening overlaps with a region between the first and second conductors and reaches the first oxide semiconductor, the second opening overlaps with the first oxide semiconductor and reaches the second conductor, the second insulator is provided in the first opening so as to overlap with the first oxide semiconductor, the third conductor is provided over the second insulator in the first opening, the third insulator is provided in the second opening so as to overlap with the second conductor, the fourth conductor is provided over the third insulator in the second opening, the height of the first oxide semiconductor is greater than the width of the first oxide semiconductor when viewed in a cross section in a channel width direction, and the semiconductor device includes two or more regions where the first oxide semiconductor overlaps with the third conductor and two or more regions where the first oxide semiconductor overlaps with the fourth conductor when viewed in a plan view.

[0030] In the above embodiment, preferably, the semiconductor device further includes a first layer and a second layer over the first layer, in which the first layer includes a first transistor including silicon in a channel formation region, the second layer includes a second transistor and a capacitor, the first transistor is electrically connected to the second transistor and the capacitor, the second transistor includes the first oxide semiconductor, a first to third conductor, and a second insulator, and the capacitor includes the second conductor, a fourth conductor, and a third insulator.

[0031] In the above embodiment, the first transistor is preferably a fin-type transistor. In the above embodiment, the first transistor preferably has a portion overlapping with the second transistor.

[0032] Effects of Invention

[0033] According to one embodiment of the present application, a semiconductor device with high operation speed can be provided. According to one embodiment of the present application, a semiconductor device in which miniaturization or high integration can be achieved can be provided. According to one embodiment of the present application, a semiconductor device with good electrical characteristics can be provided. According to one embodiment of the present application, a semiconductor device in which electrical characteristics of transistors are less likely to be non-uniform can be provided. According to one embodiment of the present application, a semiconductor device with high reliability can be provided. According to one embodiment of the present application, a semiconductor device with large on-state current can be provided. According to one embodiment of the present application, a semiconductor device with low power consumption can be provided. According to one embodiment of the present application, a novel semiconductor device can be provided. According to one embodiment of the present application, a method for manufacturing a semiconductor device with high productivity can be provided. According to one embodiment of the present application, a novel method for manufacturing a semiconductor device can be provided.

[0034] In addition, according to one embodiment of the present application, a storage device which can be miniaturized or highly integrated can be provided. According to one embodiment of the present application, a storage device with a large storage capacity can be provided. According to one embodiment of the present application, a storage device with high operation speed can be provided. According to one embodiment of the present application, a storage device with low power consumption can be provided. According to one embodiment of the present application, a novel storage device can be provided.

[0035] Note that the description is not intended to limit other effects. One embodiment of the present application does not necessarily have all the effects described above. Other effects will be apparent from and will be derived from the description of the specification, the attached drawings, the detailed description of the embodiments, and the claims. BRIEF DESCRIPTION OF DRAWINGS

[0036] FIG. 1A is a plan view illustrating one embodiment of a semiconductor device. FIG. 1B to FIG. 1D is a cross-sectional view illustrating one embodiment of a semiconductor device.

[0037] FIG. 2A and FIG. 2B is a cross-sectional view illustrating one embodiment of a semiconductor device.

[0038] FIG. 3A to FIG. 3C is a cross-sectional view illustrating one embodiment of a semiconductor device.

[0039] FIG. 4A and FIG. 4B is a cross-sectional view illustrating one embodiment of a part of a semiconductor device.

[0040] FIG. 5A and FIG. 5B is a plan view illustrating one embodiment of a part of a semiconductor device.

[0041] FIG. 6A to FIG. 6C is a cross-sectional view illustrating one embodiment of a semiconductor device.

[0042] FIG. 7A and FIG. 7B is a cross-sectional view illustrating one embodiment of a semiconductor device.

[0043] FIG. 8A to FIG. 8D is a cross-sectional view illustrating one embodiment of a method for manufacturing an oxide semiconductor.

[0044] FIG. 9A to FIG. 9D is a cross-sectional view illustrating one embodiment of an oxide semiconductor.

[0045] FIG. 10A is a plan view illustrating one embodiment of a semiconductor device. FIG. 10B to FIG. 10D is a cross-sectional view illustrating one embodiment of a semiconductor device. is a cross-sectional view illustrating one embodiment of a semiconductor device.

[0046] FIG. 11 is a cross-sectional view illustrating one example of a semiconductor device.

[0047] FIG. 12A is a plan view illustrating one example of a semiconductor device. FIG. 12B to FIG. 12D is a cross-sectional view illustrating one example of a semiconductor device.

[0048] FIG. 13A and FIG. 13B is a cross-sectional view illustrating one example of a semiconductor device.

[0049] FIG. 14A to FIG. 14C is a cross-sectional view illustrating one example of a semiconductor device.

[0050] FIG. 15A and FIG. 15B is a cross-sectional view illustrating one example of a semiconductor device.

[0051] FIG. 16A is a plan view illustrating one example of a method for manufacturing a semiconductor device. FIG. 16B to FIG. 16D is a cross-sectional view illustrating one example of a method for manufacturing a semiconductor device.

[0052] FIG. 17A is a plan view illustrating one example of a method for manufacturing a semiconductor device. FIG. 17B to FIG. 17D is a cross-sectional view illustrating one example of a method for manufacturing a semiconductor device.

[0053] FIG. 18A is a plan view illustrating one example of a method for manufacturing a semiconductor device. FIG. 18B to FIG. 18D is a cross-sectional view illustrating one example of a method for manufacturing a semiconductor device.

[0054] FIG. 19A is a plan view illustrating one example of a method for manufacturing a semiconductor device. FIG. 19B to FIG. 19D is a cross-sectional view illustrating one example of a method for manufacturing a semiconductor device.

[0055] FIG. 20A is a plan view illustrating one example of a method for manufacturing a semiconductor device. FIG. 20B to FIG. 20D is a cross-sectional view illustrating one example of a method for manufacturing a semiconductor device.

[0056] FIG. 21A is a plan view illustrating one example of a method for manufacturing a semiconductor device. FIG. 21B to FIG. 21D is a cross-sectional view illustrating one example of a method for manufacturing a semiconductor device.

[0057] FIG. 22A is a plan view illustrating one example of a method for manufacturing a semiconductor device. FIG. 22B to FIG. 22Dis a cross-sectional view showing one example of a manufacturing method of a semiconductor device.

[0058] FIG. 23A is a plan view showing one example of a manufacturing method of a semiconductor device. FIG. 23B to FIG. 23D is a cross-sectional view showing one example of a manufacturing method of a semiconductor device.

[0059] FIG. 24A is a plan view showing one example of a manufacturing method of a semiconductor device. FIG. 24B to FIG. 24D is a cross-sectional view showing one example of a manufacturing method of a semiconductor device.

[0060] FIG. 25A is a plan view showing one example of a manufacturing method of a semiconductor device. FIG. 25B to FIG. 25D is a cross-sectional view showing one example of a manufacturing method of a semiconductor device.

[0061] FIG. 26A and FIG. 26B is a cross-sectional view showing one example of a manufacturing method of a semiconductor device.

[0062] FIG. 27A and FIG. 27B is a cross-sectional view showing one example of a manufacturing method of a semiconductor device.

[0063] FIG. 28 is a block diagram showing a structure example of a semiconductor device.

[0064] FIG. 29A to FIG. 29H is a diagram showing a circuit structure example of a memory cell.

[0065] FIG. 30A and FIG. 30B is a perspective view showing a structure example of a semiconductor device.

[0066] FIG. 31 is a block diagram showing a CPU.

[0067] FIG. 32 is a block diagram showing a CPU.

[0068] FIG. 33A and FIG. 33B is a perspective view of a semiconductor device.

[0069] FIG. 34A and FIG. 34B is a perspective view of a semiconductor device.

[0070] FIG. 35A and FIG. 35B is a diagram showing a hierarchy of a memory device in a semiconductor device.

[0071] FIG. 36A andFIG. 36B is a diagram showing one example of an electronic device, FIG. 36C to FIG. 36E is a diagram showing one example of a large-sized computer.

[0072] FIG. 37 is a diagram showing one example of a space device.

[0073] FIG. 38 is a diagram showing one example of a storage system that can be used for a data center. DETAILED DESCRIPTION

[0074] Embodiments are described in detail with reference to the accompanying drawings. Note that the application is not limited to the following description, and it is readily apparent to those skilled in the art that the present application can be carried out in various changes and modifications of form without departing from the spirit and scope of the present application. Therefore, the present application should not be interpreted as being limited to the content of the following description of the embodiments.

[0075] Note that, in the structure of the application described below, the same symbols are used to show the same parts or parts having the same function common between different drawings, and repetitive explanation thereof is omitted. Further, the same hatching pattern is sometimes used when showing parts having the same function, without particularly adding the same symbol.

[0076] In addition, in order to facilitate understanding, the position, size, and range, and the like of each constituent element shown in the drawings are not necessarily shown as the actual position, size, and range, and the like. Therefore, the disclosed application is not necessarily limited to the position, size, and range, and the like disclosed in the drawings.

[0077] In addition, especially in a plan view (also referred to as a "top view") or a perspective view and the like, in order to facilitate understanding of the application, the description of part of the constituent elements is sometimes omitted. In addition, the description of part of the hidden lines is sometimes omitted.

[0078] Note that, in this specification and the like, "first", "second", and the like are added to the description for the convenience of explanation, and do not limit the number of the constituent elements or the order of the constituent elements (e.g., the order of the steps or the order of the layers). Further, the order of the constituent elements added with the ordinal numbers in one part of this specification is sometimes different from that in another part of this specification or in the claims.

[0079] In addition, depending on the case or the situation, "film" and "layer" can be switched with each other. For example, "conductive layer" can be switched to "conductive film". Further, "insulating film" can be switched to "insulating layer". In addition, depending on the case or the situation, "conductor" can be switched to "conductive layer" or "conductive film". In addition, depending on the case or the situation, "insulator" can be switched to "insulating layer" or "insulating film".

[0080] Furthermore, in this specification, "parallel" refers to a state where the angle formed by two straight lines is between -10 degrees and 10 degrees. Therefore, it also includes a state where the angle is between -5 degrees and 5 degrees. Additionally, "approximately parallel" refers to a state where the angle formed by two straight lines is between -20 degrees and 20 degrees. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is between 80 degrees and 100 degrees. Therefore, it also includes a state where the angle is between 85 degrees and 95 degrees. Additionally, "approximately perpendicular" refers to a state where the angle formed by two straight lines is between 70 degrees and 110 degrees.

[0081] Openings include, for example, grooves and slits. Furthermore, the area where an opening is formed is sometimes referred to as an opening portion.

[0082] Furthermore, the accompanying drawings used in this embodiment show the case where the sidewall of the insulator in the opening of the insulator is perpendicular or substantially perpendicular to the substrate surface or the surface to which it is formed, but the sidewall may also be tapered.

[0083] Note that in this specification, a conical shape refers to a shape in which at least a portion of the side surface of a constituent element is inclined relative to the substrate surface or the surface to be formed. For example, this shape preferably has an area where the angle (hereinafter sometimes referred to as the cone angle) formed by the inclined side surface and the substrate surface or the surface to be formed is less than 90°. Note that the side surface of the constituent element and the substrate surface do not necessarily have to be completely flat; they may also be approximately planar with slight curvature or approximately planar with slight irregularities.

[0084] Note that in this specification, "height consistent or substantially consistent" refers to a structure in which the height from a reference surface (e.g., a flat surface such as a substrate surface) is equal in cross-section. For example, in the manufacturing process of memory devices, sometimes a planarization process (typically CMP) is performed to expose the surfaces of one or more layers. In this case, the surface being processed in the CMP process is at the same height from the reference surface. Note that depending on the processing apparatus, processing method, or material of the surface being processed during CMP, the heights of multiple layers may differ. In this specification, "height consistent or substantially consistent" also includes the above-mentioned cases. For example, when a layer includes two heights relative to a reference surface (referred to herein as the first layer and the second layer), the difference between the height of the top surface of the first layer and the height of the top surface of the second layer being less than 20 nm can also be described as "height consistent or substantially consistent".

[0085] In this specification and the like, "alignment or substantially alignment of side end portions" means a case where at least a part of the outline of each layer in the stack is overlapped when viewed from above. For example, a case where an upper layer and a lower layer are processed by the same mask pattern or a part thereof is included. However, strictly speaking, a case where the outline of the upper layer is positioned inside the outline of the lower layer or the outline of the upper layer is positioned outside the outline of the lower layer, in which the outlines are not overlapped, is also referred to as "alignment or substantially alignment of side end portions".

[0086] (Embodiment 1)

[0087] In this embodiment, a semiconductor device including an oxide semiconductor layer and a method for manufacturing the semiconductor device are described with reference to FIGS. 1 to 25.

[0088] Structure Example of Semiconductor Device

[0089] A structure example of a semiconductor device is described with reference to FIGS. 1 to 15. FIG. 1A to FIG. 1D is a plan view and cross-sectional views of a semiconductor device including a transistor 200 over a substrate (not shown).

[0090] FIG. 1A is a plan view of the above semiconductor device. Note that, FIG. 1B to FIG. 1D is a cross-sectional view of the semiconductor device. Here, FIG. 1B is a cross-sectional view of a portion along the dot-dash line A1-A2 in FIG. 1A , and is a cross-sectional view in the channel width direction of the transistor 200. Note that, FIG. 1C is a cross-sectional view of a portion along the dot-dash line A3-A4 in FIG. 1A , and is a cross-sectional view in the channel width direction of the transistor 200. Note that, FIG. 1D is a cross-sectional view of a portion along the dot-dash line A5-A6 in FIG. 1A , and is a cross-sectional view in the channel length direction of the transistor 200. Here, the dot-dash line A5-A6 is orthogonal to the dot-dash line A1-A2 and the dot-dash line A3-A4, and the dot-dash line A1-A2 and the dot-dash line A3-A4 are parallel to each other. Note that, in the plan view of FIG. 1A , part of the components is omitted and is shown through part of the components. Note that, FIG. 2A is an enlarged view of the vicinity of the conductive body 260 in FIG. 1D . Note that, FIG. 2B is an enlarged view of the vicinity of the oxide semiconductor 230 in FIG. 1B . Note that, FIG. 6A is an enlarged view of the vicinity of the oxide semiconductor 230 in FIG. 1C .

[0091] The semiconductor device of this embodiment includes an insulator 216 over a substrate (not illustrated), an insulator 221 over the insulator 216, an insulator 222 over the insulator 221, an oxide semiconductor 230 over the insulator 222, a conductive body 242a and a conductive body 242b over the oxide semiconductor 230 and the insulator 222, an insulator 250 over the oxide semiconductor 230, and a conductive body 260 (a conductive body 260a and a conductive body 260b) over the insulator 250. Note that hereinafter, the conductive body 242a and the conductive body 242b are collectively referred to as a conductive body 242 in some cases.

[0092] The insulator 275 is provided over the conductive body 242, and the insulator 280 is provided over the insulator 275. The insulator 250 and the conductive body 260 are provided inside an opening provided in the insulator 280 and the insulator 275. The opening reaches the oxide semiconductor 230, and the insulator 250 is in contact with the oxide semiconductor 230 in the opening. Further, the insulator 282 is provided over the insulator 280 and the conductive body 260. Further, the insulator 283 is provided over the insulator 282. Further, the insulator 215 is provided under the insulator 216.

[0093] The insulator 241a is provided in contact with an inner wall of the opening in the insulator 280 and the like, and the conductive body 240a is provided in contact with a side surface of the insulator 241a. A bottom surface of the conductive body 240a is in contact with a top surface of the conductive body 242a. The insulator 241b is provided in contact with an inner wall of the opening in the insulator 280 and the like, and the conductive body 240b is provided in contact with a side surface of the insulator 241b. A bottom surface of the conductive body 240b is in contact with a top surface of the conductive body 242b. Hereinafter, the conductive body 240a and the conductive body 240b are collectively referred to as a conductive body 240 in some cases. Further, the insulator 241a and the insulator 241b are collectively referred to as an insulator 241 in some cases.

[0094] The oxide semiconductor 230 has a region serving as a channel formation region of the transistor 200. Further, the conductive body 260 has a region serving as a first gate electrode (an upper gate electrode) of the transistor 200. The insulator 250 has a region serving as a first gate insulator of the transistor 200.

[0095] The conductive body 242a has a region serving as one of a source electrode and a drain electrode of the transistor 200. The conductive body 240a is used as a plug connected to the conductive body 242a. The conductive body 242b has a region serving as the other of the source electrode and the drain electrode of the transistor 200. The conductive body 240b is used as a plug connected to the conductive body 242b.

[0096] The oxide semiconductor 230 is formed over the insulator 222 in contact with the insulator 222. As FIG. 2B and FIG. 6AAs shown, the oxide semiconductor 230 has a high aspect ratio when viewed in cross-section along the channel width direction. Therefore, it can also be said that the oxide semiconductor 230 has a fin-like shape.

[0097] Here, the aspect ratio of the oxide semiconductor 230 when viewed in cross-section along the channel width direction refers to the ratio of the length L of the oxide semiconductor 230 in the A1-A2 direction (also referred to as the width L of the oxide semiconductor 230) to the length H (also referred to as the height H of the oxide semiconductor 230) in the direction perpendicular to the formed surface (e.g., insulator 222) of the oxide semiconductor 230. Preferably, the aspect ratio of the oxide semiconductor 230 is as large as possible within the range that the oxide semiconductor 230 will not fall over during the manufacturing process of the transistor 200. In the transistor 200, the height H of the oxide semiconductor 230 is at least greater than the width L of the oxide semiconductor 230. The height H of the oxide semiconductor 230 can be greater than 1 times and less than 400 times the width L of the oxide semiconductor 230, preferably more than 2 times and less than 100 times, more preferably more than 5 times and less than 40 times, and even more preferably more than 10 times and less than 20 times. In addition, for example, the height H can also be more than 2 times and less than 10 times the width L. For example, the width L can be 5 nm or more and 100 nm or less, preferably 5 nm or more and 50 nm or less, more preferably 10 nm or more and 30 nm or less. Furthermore, for example, the height H can be 50 nm or more and 2000 nm or less, preferably 100 nm or more and 1000 nm or less. Furthermore, for example, the height H can also be 50 nm or more and 100 nm or less.

[0098] In addition, such as FIG. 2B As shown, when viewed in a cross-section along the channel width direction, the angle θ formed by the side surface of the oxide semiconductor 230 and the top surface of the insulator 222 is preferably perpendicular or substantially perpendicular. For example, the angle θ is preferably 80° or more and 100° or less, more preferably 85° or more and 95° or less.

[0099] The insulator 250, conductor 260, and conductor 242 are arranged to cover the high aspect ratio oxide semiconductor 230. In the transistor 200, as... FIG. 2BThe insulator 250 and a portion of the conductor 260 are provided so as to sandwich the oxide semiconductor 230 in a folded state, as illustrated. Thus, the oxide semiconductor 230 and the conductor 260 are provided so as to face each other with the insulator 250 interposed therebetween in the upper portion of the oxide semiconductor 230, the side surface on the Al side, and the side surface on the A2 side, when viewed in the cross section in the channel width direction. That is, the upper portion of the oxide semiconductor 230, the side surface on the Al side, and the side surface on the A2 side are all used as channel formation regions. Thus, the channel width of the transistor 200 is increased by the portions of the oxide semiconductor 230 on the Al side and the A2 side, as compared with the case where the oxide semiconductor 230 is formed in a planar shape.

[0100] As described above, the on-state current, the transconductance, the frequency characteristics, and the like of the transistor 200 can be improved by increasing the channel width. Thus, a semiconductor device with high operation speed can be provided. Furthermore, the operation speed of a memory device using the semiconductor device can be improved. Furthermore, in the above structure, the channel width can be increased without increasing the area occupied by the transistor 200 by providing the oxide semiconductor 230. Thus, the semiconductor device can be miniaturized or highly integrated. In addition, the storage capacity of a memory device using the semiconductor device can be increased. Furthermore, by employing the above structure, the area of the conductor 260 facing the oxide semiconductor 230 is increased, and the threshold value can be controlled so that the transistor 200 is always off.

[0101] In addition, as illustrated in FIG. 6A, the upper portion of the oxide semiconductor 230 can have a curved shape. By having such a curved shape, formation of a void or the like in the insulator 250 and the conductor 242 near the upper portion of the oxide semiconductor 230 can be prevented. Note that, as illustrated in FIG. 6B, the upper portion of the oxide semiconductor 230 can have a flat shape. FIG. 2B FIG. 2B FIG. 6A FIGS. 6A and 6B illustrate a structure in which both the Al side (A3 side) and the A2 side (A4 side) of the upper portion of the oxide semiconductor 230 have a curved shape, but the present application is not limited thereto. For example, a structure in which one of the Al side (A3 side) and the A2 side (A4 side) of the upper portion of the oxide semiconductor 230 has a curved shape is sometimes employed.

[0102] The oxide semiconductor 230 has a shape with a high aspect ratio, and thus is preferably formed in a sidewall shape on the side surface of a pillar (the insulator 223 to be described later). Thus, the oxide semiconductor 230 is preferably formed by an ALD method with good coverage. In the case where the oxide semiconductor 230 has a stacked structure, at least one layer is preferably deposited by an ALD method, and preferably a layer in contact with the pillar is deposited.

[0103] The oxide semiconductor 230 is formed in a sidewall shape in contact with the pillar, and thus the oxide semiconductor 230 is formed in a shape in which the upper portion is curved, as illustrated in FIG. 6A.​​FIG. 1A The top surface shape of the oxide semiconductor 230 is a shape of a circle (also referred to as a frame, a ring, a loop, or a closed curve) in which both end portions are aligned. Further, it can be said that the oxide semiconductor 230 has a shape including an opening in a central portion. Note that in the case where the oxide semiconductor 230 has a shape including an opening in a central portion, the shape of the oxide semiconductor 230 is not limited to a shape in which both end portions are aligned. For example, the oxide semiconductor 230 can have a shape in which one end portion is aligned. FIG. 1A In the case where the top surface shape of the oxide semiconductor 230 is a line-symmetrical shape with A1-A2 as a center, the present application is not limited thereto. For example, the top surface shape of the oxide semiconductor 230 can be an asymmetrical shape.

[0104] FIG. 1A The structure illustrated in FIG. 6A is a structure in which two pillars are arranged in the A1-A2 direction and the circular oxide semiconductor 230 is formed so as to be in contact with side surfaces of the respective pillars. As illustrated in FIG. 6B, the oxide semiconductor 230 is formed so as to be in contact with the side surfaces of the respective pillars. Thus, the oxide semiconductor 230 is formed so as to be in contact with the side surfaces of the respective pillars. FIG. 1A As illustrated in FIG. 6A, it is preferable that the oxide semiconductor 230 overlap with the conductive body 260 in two or more portions when viewed in plan view. That is, the above structure has two or more regions in which the oxide semiconductor 230 overlaps with the conductive body 260. By employing such a structure, as illustrated in FIG. 6B, the oxide semiconductor 230 can be formed so as to be in contact with the side surfaces of the respective pillars. Thus, the oxide semiconductor 230 can be formed so as to be in contact with the side surfaces of the respective pillars. FIG. 1B As illustrated in FIG. 6A, it is preferable that the oxide semiconductor 230 overlap with the conductive body 260 in two or more portions when viewed in plan view. That is, the above structure has two or more regions in which the oxide semiconductor 230 overlaps with the conductive body 260. By employing such a structure, as illustrated in FIG. 6B, the oxide semiconductor 230 can be formed so as to be in contact with the side surfaces of the respective pillars. Thus, the oxide semiconductor 230 can be formed so as to be in contact with the side surfaces of the respective pillars.

[0105] Note that the above describes a structure in which two circular oxide semiconductors 230 are provided, but the present application is not limited thereto. For example, a structure in which one or three or more circular oxide semiconductors 230 are provided can be employed. Alternatively, the circular oxide semiconductors 230 can be joined to form an oxide semiconductor 230 having a shape including a plurality of openings. For example, as illustrated in FIG. 7A, an oxide semiconductor 230 having a shape in which three openings are arranged in the A1-A2 direction when viewed in plan view can be formed. In this case, three pillars can be formed adjacent to each other at a short distance, and the oxide semiconductor 230 can be formed between the pillars. Alternatively, for example, as illustrated in FIG. 7B, an oxide semiconductor 230 having a shape in which a lattice is formed when viewed in plan view can be formed. In this case, a lattice-shaped trench can be formed in the pillars, and the oxide semiconductor 230 can be formed so as to be embedded in the trench. FIG. 5A As illustrated in FIG. 6A, it is preferable that the oxide semiconductor 230 overlap with the conductive body 260 in two or more portions when viewed in plan view. That is, the above structure has two or more regions in which the oxide semiconductor 230 overlaps with the conductive body 260. By employing such a structure, as illustrated in FIG. 6B, the oxide semiconductor 230 can be formed so as to be in contact with the side surfaces of the respective pillars. Thus, the oxide semiconductor 230 can be formed so as to be in contact with the side surfaces of the respective pillars. FIG. 5B As illustrated in FIG. 6A, it is preferable that the oxide semiconductor 230 overlap with the conductive body 260 in two or more portions when viewed in plan view. That is, the above structure has two or more regions in which the oxide semiconductor 230 overlaps with the conductive body 260. By employing such a structure, as illustrated in FIG. 6B, the oxide semiconductor 230 can be formed so as to be in contact with the side surfaces of the respective pillars. Thus, the oxide semiconductor 230 can be formed so as to be in contact with the side surfaces of the respective pillars.

[0106] [Oxide semiconductor layer]

[0107] Here, an oxide semiconductor layer used for the oxide semiconductor 230 is described. The oxide semiconductor layer includes a metal oxide.

[0108] When a metal oxide is used for a semiconductor layer of a transistor, lattice defects in the metal oxide can cause generation or trapping of carriers, and the like. Thus, when a metal oxide having a large number of lattice defects is used for a semiconductor layer of a transistor, the electrical characteristics of the transistor can be unstable. Therefore, the number of lattice defects in a metal oxide used for a semiconductor layer of a transistor is preferably small. Lattice defects refer to point defects such as atomic vacancies and impurities, line defects such as dislocations, surface defects such as grain boundaries, and bulk defects such as voids.

[0109] By using a metal oxide having crystallinity for an oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. As a structure of a metal oxide having crystallinity, a CAAC (c-axis aligned crystal) structure, a poly-crystal structure, and an nc (nano-crystal) structure can be given, for example.

[0110] The metal oxide included in the oxide semiconductor layer of one embodiment of the present application has a plurality of microcrystals. In addition, no clear grain boundary is observed between the plurality of microcrystals. Preferably, the metal oxide included in the oxide semiconductor layer of one embodiment of the present application has a plurality of microcrystals which are aligned in a direction and has a crystal structure in which the plurality of microcrystals are connected without clear grain boundaries when viewed from the direction in which the microcrystals are aligned.

[0111] The oxide semiconductor layer of one embodiment of the present application includes a metal oxide having a crystal structure different from that of a single crystal structure and a poly-crystal structure. In particular, the oxide semiconductor layer of one embodiment of the present application preferably includes a metal oxide having a CAAC structure.

[0112] The CAAC structure refers to a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) are aligned in a c-axis direction and in which the plurality of microcrystals are connected to each other in an a-b plane. When a cross-sectional TEM image of an oxide semiconductor layer having the CAAC structure is observed, a lattice image in which a plurality of dots are aligned in a dot matrix is observed in some cases. In this case, the distance between adjacent dots included in the dot matrix (pitch of the dot matrix) is substantially constant. This is referred to as a CAAC structure. Further, in the CAAC structure, metal atoms are arranged in a triangular or hexagonal configuration in the a-b plane, and c-axes are aligned in a vertical direction with respect to the a-b plane.

[0113] Note that each of the plurality of microcrystals has a structure in which metal atoms are arranged in a layered manner in a direction parallel or approximately parallel to a formation surface, and the layers are stacked in a direction perpendicular or approximately perpendicular to the formation surface, and the structure is sometimes referred to as a CAAC structure. In the case where the microcrystal has the above structure, the crystal structure of the microcrystal is not limited to a hexagonal crystal structure. For example, part of the plurality of microcrystals can have a crystal structure other than a hexagonal crystal structure (e.g., a cubic crystal structure).

[0114] The CAAC structure is formed in such a manner that a c-axis is aligned in a direction perpendicular or approximately perpendicular to a formation surface. In the CAAC structure, metal atoms are arranged in a layered manner in a direction parallel or approximately parallel to a formation surface. In a region having the CAAC structure, an angle formed by the c-axis and the formation surface is preferably 90° ± 20° (greater than or equal to 70° and less than or equal to 110°), further preferably 90° ± 15° (greater than or equal to 75° and less than or equal to 105°), still further preferably 90° ± 10° (greater than or equal to 80° and less than or equal to 100°), and even further preferably 90° ± 5° (greater than or equal to 85° and less than or equal to 95°).

[0115] The polycrystalline structure has a grain boundary. In addition, when heat treatment is performed after the formation of the oxide semiconductor layer in which a polycrystalline structure is formed, a minute gap (also referred to as a nanocrack or a microcrack) or a minute space (also referred to as a nanospace or a microspace) is likely to be formed between crystal parts. If a minute gap or a minute space is formed in the oxide semiconductor layer, the resistance of the oxide semiconductor layer becomes high. This is because the resistance of a minute gap or a minute space is extremely high, for example, infinite. When the oxide semiconductor layer including a minute gap or a minute space is used for a channel formation region of a transistor, the contact resistance between the oxide semiconductor layer and one or both of a source electrode and a drain electrode becomes high. Thus, this can have a negative impact on the initial characteristics or reliability of the transistor. In this regard, in the CAAC structure, no clear grain boundary is observed in the a-b plane, and thus a semiconductor device with high reliability can be achieved. In addition, since the number of grain boundaries is small, the energy barrier to the conduction of carriers in the channel of the transistor is small and an increase in on-state current can be expected. Furthermore, the increase in the resistance of the semiconductor layer of the transistor using the oxide semiconductor layer is suppressed or the initial characteristics (particularly, the on-state current) of the transistor are improved, and thus a transistor suitable for high-speed driving can be achieved.

[0116] The channel formation region of the transistor preferably uses a metal oxide capable of increasing the on-state current of the transistor. In order to increase the on-state current of the transistor, it is preferable to increase the mobility of the metal oxide used for the transistor. In order to increase the mobility of the metal oxide, it is necessary to increase the transfer of carriers (electrons in the case of an n-channel transistor) or to reduce a scattering factor that has a negative impact on the transfer of carriers. In addition, carriers flow from the source to the drain through the channel formation region. Thus, by providing a channel formation region through which carriers easily flow in the channel length direction, the on-state current of the transistor can be increased.

[0117] The crystallinity of the oxide semiconductor layer can be analyzed by X-ray diffraction (XRD), TEM, or electron diffraction (ED), for example. Alternatively, a plurality of the above methods can be combined and used for analysis.

[0118] When electron diffraction is performed on an oxide semiconductor layer having a CAAC structure, a spot (a bright spot) indicating c-axis alignment is observed in an electron diffraction pattern. The c-axis of the CAAC structure is aligned in the direction parallel to the normal vector to the formation surface of the oxide semiconductor layer.

[0119] In addition, an FFT pattern obtained by performing fast Fourier transform (FFT) processing on a TEM image reflects the same information in the reciprocal space as an electron diffraction pattern.

[0120] By obtaining a cross-sectional TEM image of the oxide semiconductor layer having a CAAC structure and performing FFT processing on each region of the cross-sectional TEM image to form an FFT pattern, the direction of a crystal axis of each region can be found from the FFT pattern. Specifically, in the FFT pattern, a line segment connecting two spots having high luminance and substantially the same distance from the center is the direction of the crystal axis. A region whose angle with respect to a plane where the CAAC structure is formed is within a range of, preferably, 70° or more and 110° or less (within 90° ± 20°), further preferably, 75° or more and 105° or less (within 90° ± 15°), still further preferably, 80° or more and 100° or less (within 90° ± 10°), and in particular, 85° or more and 95° or less (within 90° ± 5°) is regarded as a CAAC structure.

[0121] When the oxide semiconductor layer having a CAAC structure is observed from a direction perpendicular to a plane where the CAAC structure is formed, a triangular or hexagonal atomic arrangement is observed in an a-b plane, and crystal parts are aligned in the a-b plane. In a Voronoi diagram generated using a TEM image observed in a direction perpendicular to a plane where the CAAC structure is formed, a region surrounded by a circle is referred to as a "circle region", a region surrounded by a square is referred to as a "square region", a region surrounded by a triangle is referred to as a "triangle region", and a region surrounded by a hexagon is referred to as a "hexagon region". Note that in any of the above cases, a region surrounded by a polygonal shape that is not one of the above shapes is referred to as a "polygonal region". In the Voronoi diagram, the ratio of the area of the hexagon region is higher than or equal to 30 % and lower than 100 %, preferably higher than or equal to 50 % and lower than 100 %, more preferably higher than or equal to 80 % and lower than 100 %, and in particular, higher than or equal to 90 % and lower than 100 %.

[0122] A method for manufacturing a Voronoi diagram will be described. First, when image analysis is performed on a TEM image, after FFT processing, only information in a certain range is left by filtering, and inverse fast Fourier transform is performed to manufacture an FFT filtered image. Lattice points are extracted from the manufactured FFT filtered image, and perpendicular bisectors of line segments connecting adjacent lattice points are manufactured. Points at which three perpendicular bisectors intersect are set as Voronoi points, and a polygonal region surrounded by lines connecting the Voronoi points is set as a Voronoi region. As described above, a Voronoi diagram can be manufactured.

[0123] In addition, as one example of an observation range of a TEM at the time of manufacturing a Voronoi diagram, a rectangular region with a length of 50 nm and a width of 50 nm can be observed. Note that the observation range is not limited to this.

[0124] In addition, when the distribution of the directions of the hexagonal crystal is analyzed using the lattice points extracted by image analysis of a planar TEM image, the following state is observed at the boundary between two structures in which the directions of the hexagonal crystals are different: the difference in the directions of the hexagonal crystals is small, the boundary is blurred, and the two structures are connected in a manner in which they are intertwined. That is, a clear boundary portion is not observed in the CAAC structure.

[0125] Note that the direction of the hexagonal crystal can be calculated from the direction of a hexagon formed by six lattice points closest to each lattice point.

[0126] Note that there is no limitation on the crystallinity of the semiconductor material included in the oxide semiconductor layer. The oxide semiconductor layer sometimes includes one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single crystal semiconductor (a semiconductor having a single crystal structure), and a semiconductor having crystallinity other than a single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part thereof). When the oxide semiconductor layer has crystallinity, deterioration of the transistor characteristics can be suppressed in some cases.

[0127] The metal oxide of one embodiment of the present application preferably contains at least indium (In) or zinc (Zn), and particularly preferably contains indium as a main component. Here, the metal oxide contains indium as a main component and can further contain an element M. Further, the metal oxide preferably contains two or three of indium, the element M, and zinc, and particularly preferably contains indium and zinc as main components. Here, the metal oxide contains indium and zinc as main components and can further contain an element M. Note that the element M is a metal element or a semi-metal element having high bond energy with oxygen, such as a metal element or a semi-metal element having higher bond energy with oxygen than indium. Specifically, examples of the element M are aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably any one or a plurality of the above elements, further preferably one or a plurality of elements selected from gallium, tin, yttrium, and aluminum, and still further preferably one or a plurality of elements selected from gallium and tin. In the case where the element M contained in the metal oxide is gallium, the metal oxide of one embodiment of the present application preferably contains any one or a plurality of indium, gallium, and zinc. Note that in this specification and the like, a metal element and a semi-metal element are collectively referred to as a "metal element" in some cases, and the "metal element" described in this specification and the like includes a semi-metal element in some cases.

[0128] For example, the main component of the metal oxide refers to a metal element whose proportion is greater than or equal to 0.1 at.% or greater than or equal to 1 at.% with respect to all the metal elements in the metal oxide.

[0129] In a cross section of the oxide semiconductor layer observed using a TEM image, it is confirmed that metal atoms are arranged in a layered manner in a direction parallel or substantially parallel to the formed surface. In a TEM image, metal atoms are observed as bright spots. For example, in a metal oxide containing indium, it is confirmed that indium is arranged in a layered manner. Also, for example, in a metal oxide containing indium and zinc, it is confirmed that indium and zinc are arranged in a layered manner.

[0130] As the metal oxide of one embodiment of the present application, for example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO), or the like can be used. Alternatively, indium tin oxide containing silicon (also referred to as ITSO), gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), or the like can be given. Further, as the metal oxide of one embodiment of the present application, indium oxide can be used. Furthermore, as the metal oxide of one embodiment of the present application, gallium oxide, zinc oxide, or the like can be used.

[0131] When the proportion of the number of atoms of indium to the total of the numbers of atoms of all metal elements in the metal oxide is increased, a transistor can have a large on-state current and high frequency characteristics.

[0132] Further, by increasing the proportion of the number of atoms of zinc to the total of the numbers of atoms of all metal elements in the metal oxide, the metal oxide can have high crystallinity, and thus diffusion of impurities in the metal oxide can be inhibited. Thus, variation in electrical characteristics of a transistor can be inhibited, and reliability can be improved.

[0133] Further, by increasing the proportion of the number of atoms of element M with respect to the sum of the number of atoms of all metal elements in the metal oxide, formation of oxygen vacancies in the metal oxide can be suppressed. Thus, generation of carriers due to oxygen vacancies is suppressed, whereby a transistor with a small off-state current can be achieved. Furthermore, variation in electrical characteristics of the transistor is suppressed, and reliability can be improved.

[0134] Note that the metal oxide can contain one or plural kinds of metal elements having a large period number in the periodic table instead of indium. Further, the metal oxide can contain one or plural kinds of metal elements having a large period number in addition to indium. The larger the overlap of the orbitals of the metal elements, the greater the tendency of the carrier conduction in the metal oxide. Thus, by containing a metal element having a large period number, the field-effect mobility of the transistor can be increased in some cases. As the metal element having a large period number, a metal element belonging to the 5th period and a metal element belonging to the 6th period, and the like can be given. Specifically, as the metal element, yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium, and the like can be given. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0135] Further, the metal oxide can contain one or plural kinds of non-metal elements. When the metal oxide contains a non-metal element, the field-effect mobility of the transistor can be increased in some cases. As the non-metal element, carbon, nitrogen, phosphorus, sulfur, fluorine, chlorine, bromine, hydrogen, and the like can be given.

[0136] [Method for manufacturing oxide semiconductor layer]

[0137] The oxide semiconductor layer of one embodiment of the present application can be manufactured using two deposition methods to form a metal oxide.

[0138] In manufacturing the oxide semiconductor layer of one embodiment of the present application, a metal oxide having a CAAC structure is deposited. At this time, by using a sputtering method as the deposition method, a metal oxide with high crystallinity can be formed. Further, a deposition method such as a pulsed laser deposition (PLD) method can be used.

[0139] Here, when forming a metal oxide using the aforementioned deposition method (hereinafter, the first deposition method), a mixed layer sometimes forms at the interface between the metal oxide and the surface to be formed. This mixed layer raises concerns about hindering the crystallization of the metal oxide. By first forming a metal oxide as a first layer on the surface to be formed using a deposition method that causes less damage compared to sputtering, PLD, or similar methods (hereinafter, the second deposition method), and then using the first deposition method to set the metal oxide as a second layer, the formation of a mixed layer at the interface between the oxide semiconductor layer and the surface to be formed can be suppressed. Furthermore, the incorporation of impurities from the surface to be formed into the second layer can also be suppressed. This further improves the crystallinity of the second layer.

[0140] Compared to sputtering, atomic layer deposition (ALD) and chemical vapor deposition (CVD) can suppress damage to the surface being formed, making them suitable as secondary deposition methods. Other examples of secondary deposition methods include molecular beam epitaxy (MBE) and wet deposition. Examples of CVD methods include plasma enhanced CVD (PECVD), thermal CVD, photoluminescent CVD, and metal-organic CVD (MOCVD). MBE is a deposition method that grows thin films with a crystal structure reflecting the crystal system of the substrate, and it can be considered one of the deposition methods that causes minimal damage to the surface being formed. Wet deposition methods are also among the deposition methods that cause minimal damage to the surface being formed. Examples of wet deposition methods include spraying.

[0141] Furthermore, a third layer can be formed on top of the second layer. For example, a second deposition method can be used to form the third layer.

[0142] It is preferable to perform heat treatment after depositing the oxide semiconductor layer.

[0143] In one embodiment of the oxide semiconductor layer deposition method of the present invention, the crystallinity of the upper and lower oxide semiconductor layers (first and third layers) can be improved by using a highly crystalline second layer (i.e., CAAC) as a nucleus or seed. This improves the overall crystallinity of the oxide semiconductor layer. In other words, a highly crystalline oxide semiconductor layer can be formed by solid-phase growth of metal oxides in the upper and lower oxide semiconductor layers using the second layer as a nucleus or seed. Specifically, an oxide semiconductor layer with a CAAC structure formed using this deposition method can be referred to as AxialGrowth CAAC (AG CAAC).

[0144] Even when the deposition method of the first layer and the third layer does not use a method that easily forms a metal oxide with high crystallinity, the deposition method of the oxide semiconductor layer of one embodiment of the present application can improve the crystallinity of the first layer and the third layer. Further, heat treatment has a function of assisting in improving the crystallinity of the first layer and the third layer.

[0145] Hereinafter, an example of a method for manufacturing an oxide semiconductor 30 will be described with reference to FIG. 8. FIG. 8A to FIG. 8D An example of a method for manufacturing an oxide semiconductor 30 will be described.

[0146] First, a layer 29 is formed. The layer 29 corresponds to an insulating film or a conductive film included in a semiconductor device. As the layer 29, an insulating film such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, a hafnium oxide film, or the like can be used, for example. Alternatively, as the layer 29, a conductive film serving as an electrode of a semiconductor device can be used, for example. The layer 29 does not necessarily have crystallinity. In other words, the layer 29 can have an amorphous structure. Further, in the case where the layer 29 has crystallinity, the layer 29 can have a crystal structure with low lattice matching with a metal oxide included in the oxide semiconductor 30.

[0147] Next, the oxide semiconductor 30a is formed over the layer 29 by a deposition method which causes less damage to a formed surface. FIG. 8A ).

[0148] As described later, in the manufacturing method of one embodiment of the present application, the oxide semiconductor 30b is formed by a sputtering method. In the case where a metal oxide film is deposited by a sputtering method, a mixed layer (which can be referred to as an alloy) of a deposited metal oxide and a component of a layer of a formed surface is sometimes formed due to sputtered particles released from a target or the like or energy applied to a substrate side by sputtered particles or the like. There is a concern that crystallization of an oxide semiconductor layer of an upper layer is hindered by alloying. Further, when alloying occurs, it is difficult to improve the crystallinity of an alloyed region even when heat treatment described later is performed. When an oxide semiconductor layer having an alloyed region is used for a transistor, there is a possibility that the initial characteristics or reliability of the transistor are adversely affected.

[0149] Thus, before the oxide semiconductor 30b is formed, the oxide semiconductor 30a is formed in advance by a deposition method which causes less damage to a formed surface. Thus, alloying of a component in the oxide semiconductor 30 and a component in the layer 29 can be suppressed, and the thickness of an alloyed region can be reduced or an alloyed region can be reduced to an extent that is not observed. Here, the oxide semiconductor 30a is formed by an ALD method.

[0150] As the ALD method, a thermal ALD (Thermal ALD) method in which only thermal energy is used to cause a precursor and a reactant to react, a plasma ALD (PEALD: Plasma Enhanced ALD) method in which a reactant is excited by plasma, and the like can be given.

[0151] The ALD method is a deposition method in which a film is formed by a reaction at a surface of a processed object, unlike a deposition method in which particles released from a target or the like are deposited. The ALD method can deposit atoms one by one, and thus has the following effects: a very thin film can be deposited; a structure with a high aspect ratio or a surface with a large step can be deposited; a film with few defects such as pinholes can be deposited; a film with high coverage can be deposited; a film can be deposited at low temperature, and the like. When the ALD method is used as a deposition method of the oxide semiconductor 30a and the oxide semiconductor 30c which will be described later, the coverage of the oxide semiconductor layer can be increased. Thus, the oxide semiconductor layer can be favorably covered over a step with a high aspect ratio, an opening portion, or the like.

[0152] Further, in the PEALD method, deposition can be performed at a lower temperature by using plasma, and thus the PEALD method is sometimes preferable. In addition, a precursor used in the ALD method contains, in some cases, an element such as carbon or chlorine. Thus, a film formed by the ALD method contains, in some cases, more elements such as carbon or chlorine than a film formed by another deposition method.

[0153] Here, a method in which the In-M-Zn oxide is formed by the ALD method as the oxide semiconductor 30a is described.

[0154] First, a source gas including a precursor containing indium is introduced into a processing chamber and the precursor is adsorbed to a surface of the layer 29. Next, an oxidizing agent as a reactant is introduced into the processing chamber and the oxidizing agent is reacted with the adsorbed precursor, and components other than indium are desorbed in a state where indium is adsorbed to the substrate, whereby a layer in which indium is bonded to oxygen is formed.

[0155] Next, a source gas including a precursor containing an element M is introduced into the processing chamber and the precursor is adsorbed to the layer in which indium is bonded to oxygen. Next, an oxidizing agent as a reactant is introduced into the processing chamber and the oxidizing agent is reacted with the adsorbed precursor, and components other than the element M are desorbed in a state where the element M is adsorbed to the substrate, whereby a layer in which the element M is bonded to oxygen is formed.

[0156] Next, a source gas including a precursor containing zinc is introduced into the processing chamber and the precursor is adsorbed to the layer in which the element M is bonded to oxygen. Next, an oxidizing agent as a reactant is introduced into the processing chamber and the oxidizing agent is reacted with the adsorbed precursor, and components other than zinc are desorbed in a state where zinc is adsorbed to the substrate, whereby a layer in which zinc is bonded to oxygen is formed.

[0157] By repeating the above process, an In-M-Zn oxide can be formed on the layer 29 as the oxide semiconductor 30a by the ALD method.

[0158] The temperature of the substrate is preferably set to a temperature at which the precursor is decomposed. In the case of the ALD method in which triethylindium is used as the precursor containing indium, triethylgallium is used as the precursor containing gallium, and diethylzinc is used as the precursor containing zinc, for example, the temperature of the substrate is higher than or equal to 100 °C and lower than or equal to 350 °C, preferably higher than or equal to 150 °C and lower than or equal to 300 °C.

[0159] In the above, it is preferable that after the precursor is adsorbed, the introduction of the source gas containing the precursor be stopped and the processing chamber be purged, and then the remaining precursor and reaction products and the like be exhausted from the processing chamber. In the above, after the adsorbed precursor is reacted with the oxidizing agent, the introduction of the oxidizing agent be stopped and the processing chamber be purged, and then the remaining reactant and reaction products and the like be exhausted from the processing chamber.

[0160] Further, in the case where nothing is particularly mentioned in the description of the present specification and the like, in the case where ozone, oxygen, or water is used as a reactant or an oxidizing agent, they are not limited to a gaseous or molecular state, but also include a plasma state, a radical state, and an ionic state.

[0161] Further, in the case where the oxide semiconductor 30a is formed by the ALD method, an oxide semiconductor layer having a microcrystalline structure or an amorphous structure with lower crystallinity than the CAAC structure is sometimes formed.

[0162] Next, an In-M-Zn oxide is formed on the oxide semiconductor 30a as an oxide semiconductor 30b by a sputtering method. FIG. 8B The oxide semiconductor 30b preferably has a composition suitable for forming a CAAC structure.

[0163] In this case, when the oxide semiconductor 30b is formed by a sputtering method, a mixed layer 31 is formed on or near the surface of the oxide semiconductor 30a. Further, a fine crystalline region is sometimes formed in the mixed layer 31 due to sputtering particles or energy applied to the substrate side by the sputtering particles or the like at the time of formation of the oxide semiconductor 30b. In a heat treatment step to be described later, the mixed layer 31 or the fine crystalline region formed in the mixed layer 31 is used as a nucleus, and at least part of the oxide semiconductor 30a is sometimes crystallized.

[0164] As the sputtering method, there are an RF sputtering method in which a high-frequency power source is used as a sputtering power source, a DC sputtering method in which a direct-current power source is used, and a pulse DC sputtering method in which a voltage applied to an electrode is changed in a pulse manner. The DC sputtering method can be appropriately used in the case of depositing a metal conductive film because the deposition rate is high and thus the production rate can be increased. The pulse DC sputtering method can be appropriately used in the case of depositing a metal conductive film and a semiconductor film. Further, in the deposition of an insulating film, the RF sputtering method can be appropriately used. A compound such as an oxide, a nitride, and a carbide can be deposited by a reactive sputtering method using a reactive gas. In the deposition of a metal oxide used for the oxide semiconductor layer of one embodiment of the present application, a method can be selected as appropriate depending on the conductivity of a target and the like of the sputtering method.

[0165] As the target used for the sputtering method, an In-M-Zn oxide can be used. In the formation of a metal oxide by a sputtering method, as a sputtering gas, oxygen or a mixed gas of oxygen and an inert gas can be used. Further, by increasing the proportion of oxygen in the sputtering gas, the excess oxygen in the deposited oxide film can be increased.

[0166] Further, the higher the flow rate ratio of oxygen gas (hereinafter also referred to as an oxygen flow rate ratio) to the entire deposition gas used at the time of formation, the higher the crystallinity of the metal oxide can be in some cases.

[0167] In the formation of a metal oxide by a sputtering method, by deposition in a state where the proportion of oxygen in the sputtering gas is greater than 30 % and less than or equal to 100 %, preferably greater than or equal to 70 % and less than or equal to 100 %, an oxygen-excess type metal oxide can be formed in some cases. A transistor in which an oxygen-excess type oxide semiconductor layer is used for a channel formation region can have high reliability. However, one embodiment of the present application is not limited to this. By deposition in a state where the proportion of oxygen in the sputtering gas is greater than or equal to 1 % and less than or equal to 30 %, preferably greater than or equal to 5 % and less than or equal to 20 %, an oxygen-deficient type metal oxide can be formed. A transistor in which an oxygen-deficient type metal oxide is used for a channel formation region can have high field-effect mobility.

[0168] In the formation of a metal oxide by a sputtering method, the composition of the metal oxide after formation is in some cases different from that of the sputtering target. In particular, the content of zinc in the metal oxide after formation is in some cases reduced to approximately 50 % of the content of zinc in the sputtering target.

[0169] In the deposition of the oxide semiconductor 30b by a sputtering method, the substrate is preferably heated. In the formation of a metal oxide, by increasing the substrate temperature (stage temperature) at the time of formation of the metal oxide, a metal oxide with high crystallinity can be formed in some cases. In the deposition of the oxide semiconductor 30b by a sputtering method, the heating temperature of the substrate is preferably, for example, higher than or equal to 100 °C and lower than or equal to 400 °C, further preferably higher than or equal to 200 °C and lower than or equal to 300 °C.

[0170] Next, the oxide semiconductor 30c is formed over the oxide semiconductor 30b. FIG. 8C Here, the oxide semiconductor 30c is formed by the ALD method. In the formation of the oxide semiconductor 30c by the ALD method, the formation method of the oxide semiconductor 30a can be referred to.

[0171] When the oxide semiconductor 30c having lower crystallinity than the CAAC structure is formed over the oxide semiconductor 30b having the CAAC structure by the ALD method, the oxide semiconductor 30c is sometimes epitaxially grown using the oxide semiconductor 30b as a nucleus. Thus, the oxide semiconductor 30c sometimes includes a region having the CAAC structure at the time of formation of the oxide semiconductor 30c. Note that the region having the CAAC structure is preferably formed in the entire oxide semiconductor 30c.

[0172] The oxide semiconductor 30c can be used as a layer in contact with a gate insulating layer of a transistor, for example. By increasing the crystallinity of the layer in contact with the gate insulating layer, the carrier mobility can be increased in the transistor in an on state.

[0173] In addition, by forming the oxide semiconductor 30c by the ALD method, damage to the oxide semiconductor 30b is reduced, and thus the entire oxide semiconductor 30 can have high crystallinity.

[0174] When the ALD method, which has high coverage, is used as a deposition method of the oxide semiconductor 30a and the oxide semiconductor 30c, the oxide semiconductor layers can have coverage. Further, since the oxide semiconductor 30b having high crystallinity is formed by the sputtering method and the like and the layer is epitaxially grown, the crystallinity of the oxide semiconductor layers (the oxide semiconductor 30a and the oxide semiconductor 30c) is also increased, and thus the crystallinity of the entire layer of the oxide semiconductor 30 can be increased. Thus, the oxide semiconductor 30 can have both high coverage and high crystallinity.

[0175] Next, a heat treatment step can be performed.

[0176] The temperature of the heat treatment can be higher than or equal to 100 °C and lower than or equal to 800 °C, preferably higher than or equal to 250 °C and lower than or equal to 650 °C, more preferably higher than or equal to 350 °C and lower than or equal to 550 °C, for example. Typically, the temperature can be set to be higher than or equal to 375 °C and lower than or equal to 425 °C (± 25 °C). Note that the time for the heat treatment can be longer than or equal to 1 minute and shorter than or equal to 5 hours, longer than or equal to 1 minute and shorter than or equal to 2 hours, or longer than or equal to 10 hours and shorter than or equal to 20 hours, for example. In the case of using an RTA (rapid thermal anneal) apparatus, the time for the heat treatment can be shorter than or equal to 5 minutes, for example. With this heat treatment, the voids of the atomic order of the crystal part included in the CAAC structure of the oxide semiconductor 30b can be repaired with the oxide semiconductor 30c (in other words, each crystal molecule formed using the ALD method).

[0177] There is no particular limitation on the heating apparatus used for the heat treatment, and an apparatus for heating an object by thermal conduction or thermal radiation from a heater such as a resistance heater can be used. For example, an electric furnace or an RTA (Lamp Rapid Thermal Anneal) apparatus, a GRTA (Gas Rapid Thermal Anneal) apparatus, or the like can be used. The RTA apparatus is an apparatus for heating an object by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA apparatus is an apparatus for heating treatment using a high-temperature gas.

[0178] With this heat treatment, the crystallinity of the region having the CAAC structure in the oxide semiconductor 30c is in some cases improved. In the case where the region is formed only below the oxide semiconductor 30c after deposition by the ALD method, the region is in some cases expanded to the upper part of the oxide semiconductor 30c by the heat treatment. FIG. 8D That is, by the heat treatment, a region having the CAAC structure is in some cases formed in the entire layer of the oxide semiconductor 30c.

[0179] In addition, by the heat treatment, the oxide semiconductor 30b can in some cases be further repaired with the oxide semiconductor 30c (in other words, each crystal molecule formed using the ALD method) that fills the voids of the atomic order of the crystal part included in the CAAC structure of the oxide semiconductor 30b.

[0180] In addition, by the heat treatment, at least part of the oxide semiconductor 30a is in some cases CAACized. FIG. 8D). It is expected that the mixed layer 31 formed in the oxide semiconductor 30a at the time of deposition of the oxide semiconductor 30b serves as a nucleus or seed for easy CAACization. The CAACized region of the oxide semiconductor 30a is preferably large and preferably reaches the vicinity of the layer 29.

[0181] In addition, CAACization occurs from the upper portion to the lower portion of the oxide semiconductor 30a, and thus the CAACized region can reach the vicinity of the layer 29 without being limited by the material or crystallinity of the layer 29. For example, even if the layer 29 has an amorphous structure, the oxide semiconductor 30a with high crystallinity can be formed. Thus, the method for manufacturing the oxide semiconductor layer of one embodiment of the present application is particularly suitable for a case where the layer to be formed has an amorphous structure.

[0182] In addition, the microwave treatment can be performed after the oxide semiconductor 30c is formed.

[0183] Here, the microwave treatment refers to treatment using a device including a power source that generates high-density plasma using microwaves, for example. Note that in this specification and the like, a microwave refers to an electromagnetic wave with a frequency of 300 MHz or more and 300 GHz or less. The microwave treatment can also be referred to as microwave-excited high-density plasma treatment.

[0184] It is preferable that the microwave treatment be performed in an atmosphere containing oxygen, so as to reduce the impurity concentration in the oxide semiconductor 30. Note that hydrogen and carbon can be given as examples of impurities. Note that the structure in which the microwave treatment is performed on the metal oxide in an atmosphere containing oxygen is described above, but is not limited thereto. For example, the microwave treatment can be performed on an insulating film in the vicinity of the metal oxide, and more specifically, on a silicon oxide film in an atmosphere containing oxygen. In addition, the crystallinity of the oxide semiconductor layer is sometimes improved by heat at the time of the microwave treatment.

[0185] The microwave treatment is preferably performed under reduced pressure, and the pressure is preferably higher than or equal to 10 Pa and lower than or equal to 1000 Pa, further preferably higher than or equal to 300 Pa and lower than or equal to 700 Pa. The microwave plasma treatment is preferably performed in a state where the substrate is heated. The substrate temperature is preferably higher than or equal to room temperature (e.g., 25 °C) and lower than or equal to 500 °C, preferably higher than or equal to 100 °C and lower than or equal to 500 °C, further preferably higher than or equal to 200 °C and lower than or equal to 500 °C, still further preferably higher than or equal to 300 °C and lower than or equal to 500 °C, and still further preferably higher than or equal to 400 °C and lower than or equal to 500 °C. For example, it can be higher than or equal to 400 °C and lower than or equal to 450 °C.

[0186] In addition, the heating treatment can be continuously performed without exposure to the atmosphere after the microwave treatment. The temperature of the heating treatment is preferably higher than or equal to 100 °C and lower than or equal to 750 °C, further preferably higher than or equal to 300 °C and lower than or equal to 500 °C, still further preferably higher than or equal to 400 °C and lower than or equal to 450 °C, for example.

[0187] The microwave treatment can be performed using, for example, an oxygen gas and an argon gas. By performing the microwave treatment in an oxygen-containing atmosphere, high frequency such as microwave or RF can be used to plasma-treat the oxygen gas and cause the oxygen plasma to act on the oxide semiconductor layer. By the action of plasma, microwave, or the like, hydrogen in the oxide semiconductor layer can be separated into oxygen vacancies and hydrogen, and the hydrogen serving as an impurity can be removed from the oxide semiconductor layer. Thus, the V O H) in the oxide semiconductor layer can be reduced. In addition, at this time, carbon bonded to oxygen or hydrogen or the like can also be removed. Thus, by performing the microwave treatment, impurities such as carbon or hydrogen can be reduced. Furthermore, by supplying oxygen radicals generated in the above oxygen plasma to the oxygen vacancies formed in the oxide semiconductor layer, the oxygen vacancies in the oxide semiconductor layer can be further reduced. O H. In addition, at this time, carbon bonded to oxygen or hydrogen or the like can also be removed. Thus, by performing the microwave treatment, impurities such as carbon or hydrogen can be reduced. Furthermore, by supplying oxygen radicals generated in the above oxygen plasma to the oxygen vacancies formed in the oxide semiconductor layer, the oxygen vacancies in the oxide semiconductor layer can be further reduced.

[0188] As the oxygen to be implanted into the oxide semiconductor layer, there are various forms such as an oxygen atom, an oxygen molecule, an oxygen ion, and an oxygen radical (also referred to as an atom, molecule, or ion having an unpaired electron of an oxygen radical). Note that the oxygen to be implanted into the oxide semiconductor layer is any one or a plurality of the above forms, and an oxygen radical is particularly preferable.

[0189] As described above, impurities in the oxide semiconductor layer can be reduced. By performing crystal growth in a state where the impurity concentration in the oxide semiconductor layer is reduced, the crystallinity can be further improved.

[0190] In addition, either or both of the above heat treatment and the microwave treatment can be performed directly on the oxide semiconductor layer, or can be performed after an insulating film or the like is formed on the oxide semiconductor layer.

[0191] In addition, any one or a plurality of the relative dielectric constant, the film density, and the hardness of the film of the oxide semiconductor layer having a CAAC structure formed using the two deposition methods described above is higher than that of the CAAC structure oxide semiconductor layer formed using one deposition method.

[0192] By using the oxide semiconductor layer having a CAAC structure formed using the two deposition methods described above for a channel formation region of a transistor, a transistor with excellent characteristics (e.g., a transistor with a large on-state current, a transistor with a high field-effect mobility, a transistor with a small S value, a transistor with a high frequency characteristic (also referred to as f characteristic), a transistor with high reliability, or the like) can be implemented.

[0193] In the oxide semiconductor 30, a region having a CAAC structure is preferably present widely in the entire layer including the oxide semiconductor 30a and the oxide semiconductor 30c. FIG. 9AA state in which the oxide semiconductor 30a, the oxide semiconductor 30b, and the oxide semiconductor 30c are all crystallized is shown. The crystal of the region having the CAAC structure in the oxide semiconductor 30a is connected to the crystal of the region having the CAAC structure in the oxide semiconductor 30b. The crystal of the region having the CAAC structure in the oxide semiconductor 30c is connected to the crystal of the region having the CAAC structure in the oxide semiconductor 30b. The oxide semiconductor 30 can sometimes be expressed as one layer in which a clear interface is not observed. The oxide semiconductor 30 can sometimes be expressed as a single layer.

[0194] The region having the CAAC structure in the oxide semiconductor 30a, the oxide semiconductor 30b, and the oxide semiconductor 30c is observed as bright spots arranged in parallel to the plane formed in cross-sectional observation using a high-resolution TEM, for example. Further, the c-axes of the CAAC structures included in the oxide semiconductor 30a, the oxide semiconductor 30b, and the oxide semiconductor 30c are each preferably parallel or approximately parallel to the normal direction of the plane formed.

[0195] Further, part of the oxide semiconductor 30a or the oxide semiconductor 30c is not crystallized in some cases. FIG. 9B In the example shown, the interface with the layer 29 in the oxide semiconductor 30a is not crystallized. FIG. 9C A case where the surface of the oxide semiconductor 30c is not crystallized is shown. FIG. 9D A case where the interface with the layer 29 in the oxide semiconductor 30a and the surface of the oxide semiconductor 30c are not crystallized is shown.

[0196] The oxide semiconductor layer of one embodiment of the present application has high crystallinity in the entire layer. Thus, in the oxide semiconductor 30, the boundaries between the stacked films of the oxide semiconductor 30a, the oxide semiconductor 30b, and the oxide semiconductor 30c are not always confirmed. In particular, after heat treatment, the boundaries between the stacked films are not always confirmed. The presence or absence of the boundaries between the stacked films can be confirmed using cross-sectional TEM, cross-sectional STEM, or the like, for example.

[0197] Further, the degree of lattice mismatch between the crystal included in the oxide semiconductor 30b and the crystal included in the oxide semiconductor 30a or the oxide semiconductor 30c is preferably small. Thus, the oxide semiconductor 30a or the oxide semiconductor 30c can form a crystal reflecting the orientation of the crystal included in the oxide semiconductor 30b. At this time, for example, when cross-sectional observation is performed on the oxide semiconductor 30 using a high-resolution TEM, bright spots arranged in layers in the direction parallel to the plane are confirmed in the oxide semiconductor 30a or the oxide semiconductor 30c.

[0198] As long as the degree of lattice mismatch between the crystal of the oxide semiconductor 30b and the crystal of the oxide semiconductor 30a or the oxide semiconductor 30c is small, there is no particular limitation on the crystal structure of the oxide semiconductor 30a or the oxide semiconductor 30c. The crystal structure of the oxide semiconductor 30a or the oxide semiconductor 30c can be any of cubic crystal, tetragonal crystal, orthorhombic crystal, hexagonal crystal, monoclinic crystal, and trigonal crystal.

[0199] The oxide semiconductor layer of one embodiment of the present application can be used as a semiconductor layer of a transistor.

[0200] In the case where the oxide semiconductor 30 is used as a semiconductor layer of a transistor, the thickness of the oxide semiconductor 30 is preferably greater than or equal to 3 nm and less than or equal to 200 nm, preferably greater than or equal to 3 nm and less than or equal to 100 nm, more preferably greater than or equal to 5 nm and less than or equal to 100 nm, further preferably greater than or equal to 10 nm and less than or equal to 100 nm, still further preferably greater than or equal to 10 nm and less than or equal to 70 nm, further preferably greater than or equal to 15 nm and less than or equal to 70 nm, further preferably greater than or equal to 15 nm and less than or equal to 50 nm, and further preferably greater than or equal to 20 nm and less than or equal to 50 nm, for example. In a transistor used for a more miniaturized semiconductor device, the thickness of the oxide semiconductor 30 is preferably greater than or equal to 1 nm and less than or equal to 20 nm, more preferably greater than or equal to 3 nm and less than or equal to 15 nm, and further preferably greater than or equal to 5 nm and less than or equal to 12 nm.

[0201] The oxide semiconductor 30b is preferably less than or equal to 200 nm, for example. In the case where the oxide semiconductor 30b is layered, the thickness is preferably greater than or equal to 1 nm and less than or equal to 200 nm, more preferably greater than or equal to 1 nm and less than or equal to 100 nm, and further preferably greater than or equal to 2 nm and less than or equal to 100 nm, for example.

[0202] Alternatively, in the case where the oxide semiconductor 30b can be used as a crystal nucleus, the oxide semiconductor 30b is sometimes a collection of island-shaped regions, instead of being layered. In that case, for example, the island-shaped regions of the oxide semiconductor 30b are dispersedly present.

[0203] The oxide semiconductor 30a and the oxide semiconductor 30c are preferably greater than or equal to 1 nm and less than or equal to 50 nm, preferably greater than or equal to 1 nm and less than or equal to 30 nm, more preferably greater than or equal to 1 nm and less than or equal to 20 nm, and further preferably greater than or equal to 2 nm and less than or equal to 20 nm, for example.

[0204] The thickness of the region where the components included in the oxide semiconductor 30 and the components included in the layer 29 are alloyed is greater than or equal to 0 nm and less than or equal to 3 nm, preferably greater than or equal to 0 nm and less than or equal to 2 nm, more preferably greater than or equal to 0 nm and less than or equal to 1 nm, and further preferably greater than or equal to 0 nm and less than 0.3 nm. Note that, FIG. 8A andFIG. 8B An example in which an alloyed region is not formed between the layer 29 and the oxide semiconductor 30a is shown.

[0205] Note that the thickness of the alloyed region can be calculated by performing composition line analysis on the region and its periphery by secondary ion mass spectrometry (SIMS) or energy dispersive X-ray spectroscopy (EDX).

[0206] For example, line analysis by EDX is performed on the above region and its periphery in a direction perpendicular to the formed surface of the oxide semiconductor 30a, which is the depth direction. Then, in a distribution of the quantitative values of each element with respect to the depth direction obtained by the analysis, the depth at which the quantitative value of a metal (In when the oxide semiconductor 30a contains In) which is the main component of the oxide semiconductor 30a but not the main component of the layer (here, the layer 29) which is the layer on the formed surface reaches half the value is defined as the depth (position) of the interface between the above region and the oxide semiconductor 30a. Further, the depth at which the quantitative value of an element (e.g., Si) which is the main component of the layer on the formed surface but not the main component of the oxide semiconductor 30a reaches half the value is defined as the depth (position) of the interface between the above region and the layer on the formed surface. As described above, the thickness of the alloyed region can be calculated.

[0207] In addition, for example, in the case of performing SIMS analysis on the oxide semiconductor 30 formed over the layer 29 using a silicon oxide layer as the layer 29, it is preferable that the interface be the depth at which the silicon concentration reaches 50 % of the maximum value of the concentration in the layer 29, and the silicon concentration be reduced to 1.0 x 10 21 atoms / cm 3 , preferably 5.0 x 10 20 atoms / cm 3 , and more preferably 1.0 x 10 20 atoms / cm 3 The distance from the interface to the depth at which the silicon concentration is reduced to 1.0 x 10

[0208] Note that by reducing the alloyed region, a CAAC structure can be formed in the vicinity of the formed surface. Here, the vicinity of the formed surface refers to, for example, a region in a substantially perpendicular direction from the formed surface of the oxide semiconductor 30a at greater than or equal to 0 nm and less than or equal to 3 nm, preferably greater than or equal to 0 nm and less than or equal to 2 nm, and more preferably greater than or equal to 1 nm and less than or equal to 2 nm.

[0209] The oxide semiconductor 30a has, for example, a region of 0 nm or more and 3 nm or less from the top surface of the layer 29. The oxide semiconductor 30c is positioned, for example, at a position of 0 nm or more and 3 nm or less from the top surface of the oxide semiconductor 30b. The thicknesses of the oxide semiconductor 30a, the oxide semiconductor 30b, and the oxide semiconductor 30c are, for example, substantially the same. Alternatively, the thicknesses of the oxide semiconductor 30a, the oxide semiconductor 30b, and the oxide semiconductor 30c can be different.

[0210] [c-axis alignment degree]

[0211] The oxide semiconductor layer of one embodiment of the present application has a CAAC structure. The degree of crystallinity of the oxide semiconductor layer of one embodiment of the present application can be evaluated with the use of crystalline orientation, for example.

[0212] The CAAC structure of the oxide semiconductor layer can be evaluated with the use of a graph representing crystalline orientation. In a region having the CAAC structure, a state where crystal is aligned in the c-axis direction is observed, for example.

[0213] The graph representing crystalline orientation can be obtained by obtaining a cross-sectional TEM image and performing a fast Fourier transform (FFT) process on each region in the cross-sectional TEM image to create an FFT pattern, and calculating the direction of a crystal axis of each region. Specifically, two spots having high intensity are observed in the FFT pattern of a region having a layered crystal part, for example. The direction of the crystal axis of the region is found from the angle of the line segment connecting the two spots. The FFT pattern reflects the same reciprocal space information as an electron diffraction pattern.

[0214] The c-axis alignment degree can be calculated by calculating the proportion of regions where the c-axes are aligned in the graph representing crystalline orientation.

[0215] In the oxide semiconductor layer of one embodiment of the present application, the c-axis alignment degree can be calculated by performing TEM observation on a cross section or a plane of the oxide semiconductor layer and using the above-described graph representing crystalline orientation. The region on which FFT is performed (also referred to as an FFT window) can be a circle with a diameter of 1.0 nm, for example. Note that the region on which FFT is performed is not limited to a circle.

[0216] Further, when analysis is performed using a cross-sectional TEM image, the observation range of the cross-sectional TEM image can be set to a region of 100 nm in width in the lateral direction when the direction perpendicular to the formed surface is the vertical direction, for example. Note that the observation range is not limited to this.

[0217] When the proportion of a region where the degree of c-axis alignment is calculated to be within 20° from the c-axis, for example, is calculated in the oxide semiconductor layer of one embodiment of the present application, the degree of c-axis alignment is preferably 50 % or more, more preferably 60 % or more, more preferably 70 % or more, more preferably 80 % or more, more preferably 90 % or more, and further preferably 95 % or more.

[0218] In addition, the degrees of c-axis alignment of the region where the oxide semiconductor 30a is deposited, the region where the oxide semiconductor 30b is deposited, and the region where the oxide semiconductor 30c is deposited are denoted by Rc1, Rc2, and Rc3, respectively. Here, the degree of c-axis alignment is calculated as the proportion of a region where the difference from the c-axis is within 20°, for example. Rc2 is preferably 50 % or more, more preferably 60 % or more, more preferably 70 % or more, more preferably 80 % or more, more preferably 90 % or more, and further preferably 95 % or more. In addition, Rc3 is preferably 50 % or more, more preferably 60 % or more, more preferably 70 % or more, more preferably 80 % or more, more preferably 90 % or more, and further preferably 95 % or more. Rc3 / Rc1 is preferably greater than 1. In addition, Rc2 / Rc1 is preferably greater than 1.

[0219] [Composition of oxide semiconductor layer]

[0220] The composition of the oxide semiconductor 30a is preferably different from that of the oxide semiconductor 30b. Furthermore, the composition of the oxide semiconductor 30c is preferably different from that of the oxide semiconductor 30b. Furthermore, the oxide semiconductor 30a can have the same composition as the oxide semiconductor 30c. Alternatively, the composition of the oxide semiconductor 30a can be different from that of the oxide semiconductor 30c.

[0221] The oxide semiconductor 30b preferably has a composition suitable for forming a CAAC structure. The oxide semiconductor 30b preferably contains zinc, for example. By containing zinc, a metal oxide with high crystallinity can be obtained. Further, the oxide semiconductor 30b preferably contains an element M in addition to zinc. When the oxide semiconductor 30b contains an element M, formation of oxygen vacancies in the metal oxide can be suppressed, for example. Specifically, as the oxide semiconductor 30b, a metal oxide with a composition of In:M:Zn = 1:1:1 [atomic ratio] or a neighborhood thereof, a composition of In:M:Zn = 1:1:1.2 [atomic ratio] or a neighborhood thereof, a composition of In:M:Zn = 1:1:0.5 [atomic ratio] or a neighborhood thereof, a composition of In:M:Zn = 1:1:2 [atomic ratio] or a neighborhood thereof, a composition of In:M:Zn = 4:2:3 [atomic ratio] or a neighborhood thereof, a composition of In:M:Zn = 1:3:2 [atomic ratio] or a neighborhood thereof, or a composition of In:M:Zn = 1:3:4 [atomic ratio] or a neighborhood thereof can be used. Note that the neighborhood of the composition includes a range of ±30 % of the desired atomic ratio. Further, one or more of gallium, tin, yttrium, and aluminum is preferably used as the element M.

[0222] The oxide semiconductor 30b can not contain an element M. For example, an In-Zn oxide can be used. Specifically, a composition of In:Zn = 1:1 [atomic ratio] or a neighborhood thereof, a composition of In:Zn = 2:1 [atomic ratio] or a neighborhood thereof, or a composition of In:Zn = 4:1 [atomic ratio] or a neighborhood thereof can be used. Alternatively, an indium oxide can be used. Further, a trace amount of an element M can be contained. For example, a composition of In:Ga:Zn = 4:0.1:1 [atomic ratio] or a neighborhood thereof or a composition of In:Ga:Zn = 2:0.1:1 [atomic ratio] or a neighborhood thereof can be used. Further, for example, a composition of In:Sn:Zn = 4:0.1:1 [atomic ratio] or a neighborhood thereof or a composition of In:Sn:Zn = 2:0.1:1 [atomic ratio] or a neighborhood thereof can be used.

[0223] The oxide semiconductor 30a and the oxide semiconductor 30c can use a metal oxide with a high proportion of In. The oxide semiconductor 30a and the oxide semiconductor 30c particularly preferably use a metal oxide with a higher proportion of In than the oxide semiconductor 30b. The oxide semiconductor 30a and the oxide semiconductor 30c can be formed by an ALD method, for example. Further, particularly preferably, a metal oxide with a higher proportion of In than an element M is used. By using a metal oxide with a high proportion of In, the on-state current can be increased and the frequency characteristics can be improved in the case where the oxide semiconductor layer is used for a transistor.

[0224] The oxide semiconductor with a high content of In has a tendency to be polycrystallized. When a metal oxide with a polycrystalline structure is used for a transistor, the initial characteristics or reliability of the transistor are adversely affected. The oxide semiconductor layer of one embodiment of the present application can reflect the orientation of the crystal of the oxide semiconductor 30b to the oxide semiconductor 30a and the oxide semiconductor 30c with a high content of In. Thus, even when a metal oxide with a high content of In is used as the oxide semiconductor 30a and the oxide semiconductor 30c, polycrystallization can be suppressed.

[0225] In addition, the oxide semiconductor 30a and the oxide semiconductor 30c can not contain the element M. For example, an In-Zn oxide can be used. Specifically, a composition of In:Zn = 1 : 1 [atomic ratio] or near the composition, a composition of In:Zn = 2: 1 [atomic ratio] or near the composition, or a composition of In:Zn = 4: 1 [atomic ratio] or near the composition can be used. Alternatively, an indium oxide can be used. Further, the oxide semiconductor 30a and the oxide semiconductor 30c can contain a small amount of the element M. Specifically, a composition of In:Ga:Zn = 4:0.1: 1 [atomic ratio] or near the composition, a composition of In:Ga:Zn = 2:0.1: 1 [atomic ratio] or near the composition, a composition of In:Sn:Zn = 4:0.1: 1 [atomic ratio] or near the composition, or a composition of In:Sn:Zn = 2:0.1: 1 [atomic ratio] or near the composition can be used.

[0226] In addition, a metal oxide in which the proportion of Ga is higher than that of the oxide semiconductor 30b can be used for the oxide semiconductor 30a and the oxide semiconductor 30c. For example, the oxide semiconductor 30a and the oxide semiconductor 30c can be formed using a metal oxide in which the proportion of Ga is higher than that of the oxide semiconductor 30b. For example, the oxide semiconductor 30a and the oxide semiconductor 30c preferably include a metal oxide in which the composition is In:Ga:Zn = 1:1:1 [atomic ratio] or in the vicinity thereof, a metal oxide in which the composition is In:Ga:Zn = 1:3:2 [atomic ratio] or in the vicinity thereof, or a metal oxide in which the composition is In:Ga:Zn = 1:3:4 [atomic ratio] or in the vicinity thereof. By increasing the proportion of Ga, the band gap of the oxide semiconductor 30a and the oxide semiconductor 30c can be larger than that of the oxide semiconductor 30b. Thus, the oxide semiconductor 30b is sandwiched between the oxide semiconductor 30a and the oxide semiconductor 30c with a large band gap, and the oxide semiconductor 30b can be used mainly as a current path (channel). In addition, the interface of the oxide semiconductor 30b and a trap level in the vicinity thereof can be reduced. Thus, a buried channel transistor in which the channel is away from the interface of the insulating layer can be implemented, and the field-effect mobility can be increased. Furthermore, the influence of an interface level formed on the back channel side can be reduced, and photo degradation (e.g., photo negative bias temperature instability) of the transistor can be suppressed, which can increase the reliability of the transistor.

[0227] In addition, a metal oxide in which the proportion of Ga is higher than that of the oxide semiconductor 30b can be used for the oxide semiconductor 30a and the oxide semiconductor 30c. For example, the oxide semiconductor 30a and the oxide semiconductor 30c can be formed using a metal oxide in which the proportion of Ga is higher than that of the oxide semiconductor 30b. For example, the oxide semiconductor 30a and the oxide semiconductor 30c preferably include a metal oxide in which the composition is In:Ga:Zn = 1:1:1 [atomic ratio] or in the vicinity thereof, a metal oxide in which the composition is In:Ga:Zn = 1:3:2 [atomic ratio] or in the vicinity thereof, or a metal oxide in which the composition is In:Ga:Zn = 1:3:4 [atomic ratio] or in the vicinity thereof. By increasing the proportion of Ga, the band gap of the oxide semiconductor 30a and the oxide semiconductor 30c can be larger than that of the oxide semiconductor 30b. Thus, the oxide semiconductor 30b is sandwiched between the oxide semiconductor 30a and the oxide semiconductor 30c with a large band gap, and the oxide semiconductor 30b can be used mainly as a current path (channel). In addition, the interface of the oxide semiconductor 30b and a trap level in the vicinity thereof can be reduced. Thus, a buried channel transistor in which the channel is away from the interface of the insulating layer can be implemented, and the field-effect mobility can be increased. Furthermore, the influence of an interface level formed on the back channel side can be reduced, and photo degradation (e.g., photo negative bias temperature instability) of the transistor can be suppressed, which can increase the reliability of the transistor.

[0228] In addition, the oxide semiconductor 30a, the oxide semiconductor 30b, and the oxide semiconductor 30c can each include a plurality of layers having the above composition. For example, the oxide semiconductor 30c can include a metal oxide in which the proportion of In is higher and a metal oxide in which the proportion of Ga is higher.

[0229] In addition, the oxide semiconductor 30a and the oxide semiconductor 30c can include a metal oxide having the same composition as the oxide semiconductor 30b. By using the same composition, CAAC-formation after heat treatment can be easily performed.

[0230] In addition, in the oxide semiconductor layer of one embodiment of the present application, even when the composition which is difficult to form a CAAC structure when a single layer is formed is used for the oxide semiconductor 30a and the oxide semiconductor 30c, the entire oxide semiconductor layer including the oxide semiconductor 30a and the oxide semiconductor 30c can have a CAAC structure by crystal growth with the oxide semiconductor 30b as a nucleus. Alternatively, a region including at least a part of each of the oxide semiconductor 30a and the oxide semiconductor 30c to the oxide semiconductor 30b can have a CAAC structure.

[0231] In analyzing the composition of the metal oxide used for the oxide semiconductor 30, for example, EDX, X-ray photoelectron spectroscopy (XPS), inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES) can be used. Alternatively, a plurality of the above methods can be combined for analysis. Note that the content of an element with a low content ratio is sometimes affected by the analysis accuracy, and the actual content ratio can be different from the content ratio obtained by analysis. For example, when the content of an element M is low, the content of the element M obtained by analysis is sometimes lower than the actual content.

[0232] [Impurities in oxide semiconductor]

[0233] Here, the effects of each impurity in the oxide semiconductor are described. The quantification of impurities contained in the oxide semiconductor can be performed using XPS, SIMS, EDX, ICP-MS, ICP-AES, or the like.

[0234] In a transistor whose channel formation region is formed using an oxide semiconductor, it is preferable that the concentration of impurities such as oxygen vacancies, hydrogen, nitrogen, and metal elements be lower than that in a source region and a drain region. When oxygen vacancies (Vo O ) and impurities exist in the channel formation region of the oxide semiconductor, the electrical characteristics easily fluctuate and the reliability can be reduced. In addition, hydrogen near an oxygen vacancy forms V O H, which can generate an electron serving as a carrier. Thus, when an oxygen vacancy is included in the channel formation region of the oxide semiconductor, a transistor easily has a normally-on characteristic. Therefore, it is preferable that no Vo OH is also reduced. Thus, the channel formation region of the transistor is a high-resistance region in which the carrier concentration is low. Therefore, the channel formation region of the transistor can be said to be i-type (intrinsic) or substantially i-type.

[0235] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. As the impurity, hydrogen, carbon, nitrogen, and the like can be given. Note that the impurity in the oxide semiconductor refers to, for example, an element other than the main components of the oxide semiconductor. For example, an element whose concentration is lower than 1 atomic% or 0.1 atomic% is sometimes referred to as an impurity.

[0236] When the oxide semiconductor contains silicon or carbon which is one of Group 14 elements, a defect state is formed in the oxide semiconductor. Thus, the carbon concentration in the channel formation region of the oxide semiconductor is set to be lower than or equal to 1 x 10 20 atoms / cm 3 Here, it is preferable that the carbon concentration be lower than or equal to 5 x 10 19 atoms / cm 3 Here, it is more preferable that the carbon concentration be lower than or equal to 3 x 10 19 atoms / cm 3 Here, it is further preferable that the carbon concentration be lower than or equal to 1 x 10 19 atoms / cm 3 Here, it is more preferable that the carbon concentration be lower than or equal to 3 x 10 18 atoms / cm 3 Here, it is further preferable that the carbon concentration be lower than or equal to 1 x 10 18 atoms / cm 3 Here, it is further preferable that the carbon concentration be lower than or equal to 1 x 10 20 atoms / cm 3 Here, it is preferable that the silicon concentration be lower than or equal to 5 x 10 19 atoms / cm 3 Here, it is more preferable that the silicon concentration be lower than or equal to 3 x 10 19 atoms / cm 3 Here, it is more preferable that the silicon concentration be lower than or equal to 1 x 10 19 atoms / cm 3 Here, it is more preferable that the silicon concentration be lower than or equal to 3 x 10 18 atoms / cm 3 Here, it is further preferable that the silicon concentration be lower than or equal to 1 x 10 18 atoms / cm 3 Here, it is further preferable that the silicon concentration be lower than or equal to 1 x 10

[0237] In addition, when the oxide semiconductor contains nitrogen, electrons serving as carriers are generated, the carrier concentration increases, and the oxide semiconductor is easily n- doped. As a result, a transistor using an oxide semiconductor containing nitrogen easily has a normally-on characteristic. Alternatively, when the oxide semiconductor contains nitrogen, a trap level is sometimes formed. As a result, the electric characteristics of the transistor are sometimes unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor is preferably set to 1 x 10 20 atoms / cm 3 Here, the nitrogen concentration in the channel formation region of the oxide semiconductor is preferably 5 x 10 19 atoms / cm 3 Here, the nitrogen concentration in the channel formation region of the oxide semiconductor is more preferably 1 x 10 19 atoms / cm 3 Here, the nitrogen concentration in the channel formation region of the oxide semiconductor is more preferably 5 x 10 18 atoms / cm 3 Here, the nitrogen concentration in the channel formation region of the oxide semiconductor is more preferably 1 x 10 18 atoms / cm 3 Here, the nitrogen concentration in the channel formation region of the oxide semiconductor is further preferably 5 x 10 17 atoms / cm 3 or less.

[0238] In addition, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to generate water, and thus an oxygen vacancy is sometimes formed. When hydrogen enters the oxygen vacancy, electrons serving as carriers are sometimes generated. Furthermore, electrons serving as carriers are sometimes generated because part of hydrogen is bonded to oxygen bonded to a metal atom. Thus, a transistor using an oxide semiconductor containing hydrogen easily has a normally-on characteristic. Therefore, it is preferable to reduce hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor is preferably set to less than 1 x 10 20 atoms / cm 3 , more preferably less than 5 x 10 19 atoms / cm 3 , further preferably less than 1 x 10 19 atoms / cm 3 , still further preferably less than 5 x 10 18 atoms / cm 3 , yet further preferably less than 1 x 10 18 atoms / cm 3 , and even further preferably less than 1 x 10 17 atoms / cm 3 .

[0239] Furthermore, when oxide semiconductors contain alkali metals or alkaline earth metals, defect states are sometimes formed, generating charge carriers. Therefore, transistors using oxide semiconductors containing alkali metals or alkaline earth metals tend to exhibit always-on characteristics. Consequently, the concentration of alkali metals or alkaline earth metals in the channel formation region of the oxide semiconductor, as measured by SIMS, is set to 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferred: 2×10 16 atoms / cm 3 the following.

[0240] By using oxide semiconductors with sufficiently reduced impurities in the channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0241] The average thickness of the channel formation region of the oxide semiconductor 30 is preferably 30 nm or less, more preferably 15 nm or less, and even more preferably 10 nm or less.

[0242] The oxide semiconductor 30a is an oxide semiconductor layer formed on the surface to be formed. The thickness of the oxide semiconductor 30a is preferably 0.5 nm or more and 3 nm or less.

[0243] Furthermore, in one aspect of the semiconductor device of the present invention, when observing a cross-section of the oxide semiconductor 230, it can sometimes be confirmed that the metal atoms of the metal oxide in the region having the CAAC structure are arranged in a layered manner. In this case, for example, the metal atoms are arranged in a direction perpendicular or substantially perpendicular to the substrate surface.

[0244] When observing the cross-section of the oxide semiconductor layer using TEM images, layered metal atoms arranged as bright spots can be observed in regions with CAAC structures. Thus, in a semiconductor device according to one aspect of the present invention, when observing the cross-section of the oxide semiconductor 230, it can sometimes be confirmed that the bright spots are arranged in a direction perpendicular or substantially perpendicular to the substrate surface.

[0245] The oxide semiconductor 30 of AG CAAC can be used in the oxide semiconductor 230 of transistor 200. For example, as FIG. 2B As shown, the oxide semiconductor 230 may have a structure including oxide semiconductor 230a, oxide semiconductor 230b in contact with oxide semiconductor 230a, and oxide semiconductor 230c in contact with oxide semiconductor 230b. Here, oxide semiconductor 230a corresponds to oxide semiconductor 30a, oxide semiconductor 230b corresponds to oxide semiconductor 30b, and oxide semiconductor 230c corresponds to oxide semiconductor 30c.

[0246] In this case, the above-described column (the insulator 223 to be described later) corresponds to the layer 29. That is, the formed surface of the oxide semiconductor 230 is a column which is removed in the transistor 200. In the manufacturing process, one side of the side surface of the oxide semiconductor 230a is in contact with the column and the other side of the side surface is in contact with the oxide semiconductor 230b. After the column is removed, one side of the side surface of the oxide semiconductor 230a is in contact with the insulator 250. One side of the side surface of the oxide semiconductor 230b is in contact with the oxide semiconductor 230a and the other side of the side surface is in contact with the oxide semiconductor 230c. One side of the side surface of the oxide semiconductor 230c is in contact with the oxide semiconductor 230b and the other side of the side surface is in contact with the insulator 250. In this case, the side surface of the column is perpendicular or substantially perpendicular to the surface of the substrate (which can be referred to as the surface of the insulator 222), and thus the side surface of the oxide semiconductor 230 (the oxide semiconductor 230a to the oxide semiconductor 230c) is also perpendicular or substantially perpendicular to the surface of the substrate.

[0247] As described above, in the cross section of the oxide semiconductor 230 (the oxide semiconductor 230a to the oxide semiconductor 230c) observed using a TEM image, it is confirmed that metal atoms are arranged in a layered manner in a direction parallel or substantially parallel to the formed surface. In other words, in the cross section of the oxide semiconductor 230 (the oxide semiconductor 230a to the oxide semiconductor 230c) observed using a TEM image, it is confirmed that metal atoms are arranged in a layered manner in a direction perpendicular or substantially perpendicular to the surface of the substrate. In addition, it can be said that the c-axes of the Axial Growth CAAC are substantially parallel to the normal direction of the side surface of the oxide semiconductor 230.

[0248] Thus, when the oxide semiconductor 230 using the AG CAAC is used in the channel formation region of the transistor 200, a transistor with favorable on-state current, field-effect mobility, S value, frequency characteristics, and reliability can be provided.

[0249] In addition, as described above, in the case where the oxide semiconductor 230 has the three-layer structure of the oxide semiconductor 230a to the oxide semiconductor 230c, the oxide semiconductor 230a, the oxide semiconductor 230b, and the oxide semiconductor 230c are sequentially formed with the region where the column is formed as a center. Thus, as FIG. 4AAs shown, the oxide semiconductor 230c, the oxide semiconductor 230b, the oxide semiconductor 230a, the oxide semiconductor 230a, the oxide semiconductor 230b, and the oxide semiconductor 230c are arranged in this order in symmetry when viewed from the channel width direction. That is, in order to have a structure in which the oxide semiconductor 230 is symmetrical left and right when viewed from the cross section, the composition of the oxide semiconductor 230a is preferably substantially the same as that of the oxide semiconductor 230c. Further, the thickness of the oxide semiconductor 230a is preferably substantially the same as that of the oxide semiconductor 230c. Further, in the case where the angle θ of the side surface of the oxide semiconductor 230 is 80° or more and less than 90°, that is, in the case where the side surface of the oxide semiconductor 230 is slightly inclined, the oxide semiconductor 230 is arranged in a manner in which the inclination of the oxide semiconductor 230 is symmetrical, as shown in FIG. 6B. FIG. 2B FIG. 4B Further, in the case where the oxide semiconductor 230 is formed to be inclined, the upper portion of the oxide semiconductor 230 is sometimes thinner than the lower portion of the oxide semiconductor 230, as shown in FIG. 6C. FIG. 4B

[0250] The channel formation region of the transistor 200 and the source region and the drain region provided so as to sandwich the channel formation region are formed in the oxide semiconductor 230. At least a part of the channel formation region overlaps with the conductive body 260. The source region overlaps with the conductive body 242a, and the drain region overlaps with the conductive body 242b. Note that the source region and the drain region can be interchanged.

[0251] Since the number of oxygen vacancies or the impurity concentration is lower in the channel formation region than in the source region and the drain region, the channel formation region is a high-resistance region in which the carrier concentration is low. Thus, the channel formation region can be said to be i-type (intrinsic) or substantially i-type.

[0252] Further, the source region and the drain region have a high concentration of oxygen vacancies or impurities such as hydrogen, nitrogen, and metal elements, and thus are low-resistance regions in which the carrier concentration is high. That is, the source region and the drain region are regions (low-resistance regions) in which the carrier concentration is higher than that in the channel formation region and which are n-type.

[0253] Further, the carrier concentration of the channel formation region is preferably 1 x 10 18 cm -3 -1 x 10 17 cm -3 -1 x 10 16 cm -3 -1 x 10 15 cm -3 -1 x 10 14 cm -3 -1 x 10 13 cm -3 -1 x 10​​12 cm -3 , less than 1 x 10 11 cm -3 , or less than 1 x 10 10 cm -3 . Note that there is no particular limitation on the lower limit of the carrier concentration of the channel formation region, and for example, it can be 1 x 10 -9 cm -3 .

[0254] In addition, in the case where the carrier concentration of the oxide semiconductor 230 is reduced, the impurity concentration in the oxide semiconductor 230 can be reduced to reduce the density of defect states. In this specification and the like, a state in which the impurity concentration and the density of defect states are both low is referred to as highly purified intrinsic or substantially highly purified intrinsic. Furthermore, an oxide semiconductor (or a metal oxide) in which the carrier concentration is low is sometimes referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor (or a metal oxide).

[0255] In order to stabilize the electrical characteristics of the transistor 200, it is effective to reduce the impurity concentration in the channel formation region of the oxide semiconductor 230. In order to reduce the impurity concentration of the oxide semiconductor 230, it is preferable to also reduce the impurity concentration in a film in the vicinity. As the impurities, there are hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like. Note that the impurities in the oxide semiconductor 230 refer to, for example, elements other than the main components of the oxide semiconductor 230. For example, an element with a concentration of less than 0.1 atomic% can be regarded as an impurity.

[0256] In the oxide semiconductor 230, it is sometimes difficult to clearly observe the boundaries of the regions. The concentration of the metal element and the impurity elements such as hydrogen and nitrogen detected in each region is not limited to change in stages for each region, but can gradually change in each region. That is, the closer to the channel formation region, the lower the concentration of the metal element and the impurity elements such as hydrogen and nitrogen can be.

[0257] In a transistor using an oxide semiconductor, if impurities and oxygen vacancies exist in a region of the oxide semiconductor where a channel is formed, the electrical characteristics easily vary, which can reduce the reliability. In addition, hydrogen in the vicinity of an oxygen vacancy forms a defect in which hydrogen enters an oxygen vacancy (hereinafter referred to as V O H) and can generate an electron which is a carrier. Thus, when an oxygen vacancy is included in the channel formation region of the oxide semiconductor, the transistor easily has a normally-on characteristic (a characteristic in which a channel exists even when no voltage is applied to a gate electrode and current flows in the transistor). Thus, in the channel formation region of the oxide semiconductor, it is preferable to reduce impurities, oxygen vacancies, and V O H as much as possible. In other words, it is preferable that the carrier concentration of the channel formation region in the oxide semiconductor be reduced and be i-type (intrinsic) or substantially i-type.

[0258] In view of the above, by providing an insulator containing oxygen which is released by heating (hereinafter referred to as excess oxygen) in the vicinity of the oxide semiconductor and performing heat treatment, oxygen can be supplied from the insulator to the oxide semiconductor, so that oxygen vacancies and V O H. Note that when excess oxygen is supplied to the source or drain region, the on-state current or the field-effect mobility of the transistor 200 can be decreased. Further, when the amount of oxygen supplied to the source or drain region is not uniform in the substrate surface, characteristics of a semiconductor device including the transistor are not uniform. Moreover, when oxygen supplied from the insulator to the oxide semiconductor diffuses to a conductor such as a gate electrode, a source electrode, and a drain electrode, the conductor is sometimes oxidized, which leads to a loss of conductivity, and thus has a negative impact on the electrical characteristics and reliability of the transistor.

[0259] Therefore, it is preferable that the carrier concentration of the channel formation region in the oxide semiconductor be reduced and be i-type or substantially i-type, whereas the carrier concentration of the source and drain regions be high and be n-type. In other words, it is preferable to reduce oxygen vacancies and V O H in the channel formation region of the oxide semiconductor and to increase the amount of V O H in the source and drain regions. Further, it is preferable to have a structure in which reduction in the conductivity of the conductor 260, the conductor 242a, and the conductor 242b, or the like is suppressed. For example, it is preferable to have a structure in which oxidation of the conductor 260, the conductor 242a, and the conductor 242b, or the like is suppressed. Note that hydrogen in the oxide semiconductor can form V O H, and thus in order to reduce the amount of V O H, it is necessary to reduce the hydrogen concentration.

[0260] Thus, in this embodiment, the semiconductor device has a structure in which the hydrogen concentration in the channel formation region is reduced, oxidation of the conductor 242a, the conductor 242b, and the conductor 260 is suppressed, and reduction in the hydrogen concentration in the source and drain regions is suppressed.

[0261] The insulator 250 in contact with the channel formation region in the oxide semiconductor 230 preferably has a function of trapping or fixing hydrogen. Thus, the hydrogen concentration in the channel formation region of the oxide semiconductor 230 can be reduced. Accordingly, V O H in the channel formation region can be reduced so that the channel formation region is i-type or substantially i-type.

[0262] Here, as FIG. 2AAs shown in FIG. 1, the insulator 250 preferably has a stacked structure of the insulator 250a in contact with the oxide semiconductor 230, the insulator 250b over the insulator 250a, the insulator 250c over the insulator 250b, and the insulator 250d over the insulator 250c. At this time, the insulator 250a and the insulator 250c preferably have a function of trapping or fixing hydrogen.

[0263] As the insulator having a function of trapping or fixing hydrogen, a metal oxide having an amorphous structure can be given. As the insulator 250a and the insulator 250c, for example, a metal oxide such as magnesium oxide or an oxide containing one or both of aluminum and hafnium is preferably used. The metal oxide having an amorphous structure has a property in which an oxygen atom has a dangling bond and traps or fixes hydrogen by the dangling bond in some cases. That is, it can be said that the metal oxide having an amorphous structure has high capability of trapping or fixing hydrogen.

[0264] In addition, the insulator 250a and the insulator 250c are preferably formed using a high-k material. As one example of the high-k material, an oxide containing one or both of aluminum and hafnium is given. When the high-k material is used as the insulator 250a and the insulator 250c, the gate potential applied at the time of transistor operation can be lowered while the physical thickness of the gate insulator is kept. Further, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced.

[0265] As the insulator 250a and the insulator 250c, an oxide containing one or both of aluminum and hafnium is preferably used, and an oxide having an amorphous structure and containing one or both of aluminum and hafnium is more preferably used.

[0266] In this embodiment, an aluminum oxide film is used as the insulator 250a. In addition, the aluminum oxide preferably has an amorphous structure. Here, by providing the insulator 250a in contact with the oxide semiconductor 230, hydrogen contained in the oxide semiconductor 230 and the like can be more efficiently trapped and fixed.

[0267] In this embodiment, hafnium oxide is used as the insulator 250c. Here, by providing the insulator 250c between the insulator 250b and the insulator 250d, hydrogen contained in the insulator 250b and the like can be more efficiently trapped and fixed.

[0268] Next, as the insulator 250b, a thermally stable insulator such as silicon oxide or silicon oxynitride is preferably used. Note that in this specification and the like, an oxynitride refers to a material which contains oxygen and nitrogen as its constituent elements, and the content of oxygen is higher than that of nitrogen. Further, a nitride oxide refers to a material which contains nitrogen and oxygen as its constituent elements, and the content of nitrogen is higher than that of oxygen. For example, in the case where "silicon oxynitride" is mentioned, a material which contains oxygen and nitrogen as its constituent elements and the content of oxygen is higher than that of nitrogen is meant. In the case where "silicon nitride oxide" is mentioned, a material which contains nitrogen and oxygen as its constituent elements and the content of nitrogen is higher than that of oxygen is meant.

[0269] The silicon oxide film used as the insulator 250b is preferably formed by a PEALD method.

[0270] In order to suppress oxidation of the conductive body 242a, the conductive body 242b, and the conductive body 260, an oxygen barrier insulator is preferably provided in the vicinity of each of the conductive body 242a, the conductive body 242b, and the conductive body 260. In the semiconductor device described in this embodiment, the insulator is, for example, the insulator 250a, the insulator 250d, the insulator 250c, and the insulator 275.

[0271] Note that in this specification and the like, a barrier insulator refers to an insulator having a barrier property. In this specification and the like, having a barrier property means having a property of blocking the passage of a corresponding substance (also referred to as low permeability). For example, an insulator having a barrier property has a property that a corresponding substance is not easily diffused into the insulator. For example, an insulator having a barrier property has a function of trapping or fixing (also referred to as gettering) a corresponding substance in the insulator.

[0272] As the oxygen barrier insulator, for example, an oxide containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, silicon nitride, and silicon oxynitride can be given. Further, as the oxide containing one or both of aluminum and hafnium, for example, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate) can be given. For example, the insulator 250a, the insulator 250c, the insulator 250d, and the insulator 275 preferably have a single-layer structure or a stacked-layer structure of the above-described oxygen barrier insulator.

[0273] The insulator 250a preferably has an oxygen barrier property. The insulator 250a is preferably less likely to transmit oxygen than the insulator 280. The insulator 250a has a region in contact with a side surface of the conductive body 242a and a side surface of the conductive body 242b. When the insulator 250a has an oxygen barrier property, the side surfaces of the conductive body 242a and the conductive body 242b can be prevented from being oxidized to form an oxide film thereon. Thus, a decrease in on-state current or a decrease in field-effect mobility of the transistor 200 can be suppressed.

[0274] The insulator 250a is provided in contact with the top surface and side surface of the oxide semiconductor 230 and the top surface of the insulator 222. When the insulator 250a has oxygen barrier properties, oxygen is prevented from being released from the channel formation region of the oxide semiconductor 230 at the time of heat treatment or the like. Thus, the formation of oxygen vacancies in the oxide semiconductor 230 can be reduced.

[0275] Further, by providing the insulator 250a, an excess amount of oxygen can be prevented from being supplied from the insulator 280 to the oxide semiconductor 230, and a proper amount of oxygen can be supplied to the oxide semiconductor 230. Thus, a decrease in on-state current or a decrease in field-effect mobility of the transistor 200 due to excessive oxidation of the source region and the drain region can be suppressed.

[0276] Since an oxide containing one or both of aluminum and hafnium has oxygen barrier properties, it is preferably used as the insulator 250a.

[0277] The insulator 250d is preferably also provided with oxygen barrier properties. The insulator 250d is provided between the channel formation region of the oxide semiconductor 230 and the conductor 260 and between the insulator 280 and the conductor 260. With this structure, oxygen in the channel formation region of the oxide semiconductor 230 can be prevented from diffusing to the conductor 260 and forming oxygen vacancies in the channel formation region of the oxide semiconductor 230. Further, oxygen in the oxide semiconductor 230 and oxygen in the insulator 280 can be prevented from diffusing to the conductor 260 and causing oxidation of the conductor 260. The insulator 250d is preferably at least less likely to transmit oxygen than the insulator 280. For example, a silicon nitride film is preferably used as the insulator 250d. In that case, the insulator 250d is an insulator containing at least nitrogen and silicon.

[0278] Furthermore, the insulator 250d is preferably provided with hydrogen barrier properties. With this structure, impurities such as hydrogen contained in the conductor 260 can be prevented from diffusing to the oxide semiconductor 230.

[0279] The insulator 275 is preferably also provided with oxygen barrier properties. The insulator 275 is provided between the insulator 280 and the conductor 242a and between the insulator 280 and the conductor 242b. The insulator 275 is provided in contact with the side surface of the conductor 242, the side surface of the oxide semiconductor 230, and the top surface of the insulator 222. With this structure, oxygen contained in the insulator 280 can be prevented from diffusing to the conductor 242. Thus, oxygen contained in the insulator 280 can be prevented from causing oxidation of the conductor 242 so that the resistivity increases. The insulator 275 is preferably at least less likely to transmit oxygen than the insulator 280. For example, a silicon nitride is preferably used as the insulator 275. In that case, the insulator 275 is an insulator containing at least nitrogen and silicon.

[0280] In order to suppress a decrease in the hydrogen concentration in the source region and the drain region in the oxide semiconductor 230, it is preferable to provide a hydrogen-blocking insulator in the vicinity of the source region and in the vicinity of the drain region. In the semiconductor device described in this embodiment, the hydrogen-blocking insulator is, for example, the insulator 275.

[0281] As the hydrogen-blocking insulator, an oxide such as aluminum oxide, hafnium oxide, or tantalum oxide, and a nitride such as silicon nitride can be given. For example, a single-layer structure or a stacked-layer structure of the above hydrogen-blocking insulator is preferably employed as the insulator 275.

[0282] By providing the above insulator 275, the hydrogen in the source region and the drain region can be reduced in diffusivity to the outside, and thus a decrease in the hydrogen concentration in the source region and the drain region can be suppressed. Thus, the source region and the drain region can be n-type.

[0283] With the above structure, the channel formation region can be i-type or substantially i-type and the source region and the drain region can be n-type, and thus a semiconductor device with good electrical characteristics can be provided. With the above structure, a semiconductor device with good electrical characteristics can be obtained even if the semiconductor device is miniaturized or highly integrated. Furthermore, the frequency characteristics can be improved by miniaturizing the transistor 200. Specifically, the cutoff frequency can be increased.

[0284] The insulator 250a to the insulator 250d are used as part of the gate insulator. The insulator 250a to the insulator 250d are provided in openings formed in the insulator 280, together with the conductor 260. In order to achieve miniaturization of the transistor 200, the thickness of the insulator 250a to the insulator 250d is preferably small. The thickness of each of the insulator 250a to the insulator 250d is preferably greater than or equal to 0.1 nm and less than or equal to 10 nm, more preferably greater than or equal to 0.1 nm and less than or equal to 5.0 nm, further preferably greater than or equal to 0.5 nm and less than or equal to 5.0 nm, still further preferably greater than or equal to 1.0 nm and less than 5.0 nm, and still further preferably greater than or equal to 1.0 nm and less than or equal to 3.0 nm. Note that at least a part of the insulator 250a to the insulator 250d can include a region with the above thickness.

[0285] Note that the thickness of the silicon oxide film used as the insulator 250b is preferably greater than or equal to 0.7 nm and less than or equal to 3 nm.

[0286] In order to reduce the thickness of the insulator 250a to the insulator 250d as described above, deposition is preferably performed using an ALD method. In addition, in order to provide the insulator 250a to the insulator 250d in the opening of the insulator 280 and the like, deposition is preferably performed using an ALD method. The ALD method includes a thermal ALD (Thermal ALD) method in which only thermal energy is used to cause a precursor and a reactant to react, a PEALD (Plasma Enhanced ALD) method in which a reactant is excited by plasma, and the like. In the PEALD method, deposition can be performed at a lower temperature by using plasma, and is thus sometimes preferable.

[0287] The ALD method can deposit atoms one layer at a time, and thus has effects such as being able to deposit an extremely thin film, being able to deposit a structure with a high aspect ratio, being able to deposit with few defects such as pinholes, being able to deposit with high coverage, and being able to deposit at a low temperature. Thus, the insulator 250 whose thickness is thin as described above can be deposited with high coverage on the side surface of the opening portion formed in the insulator 280, the side end portion of the conductive object 242a and the conductive object 242b, and the like.

[0288] Note that the precursor used in the ALD method sometimes contains carbon or the like. Thus, a film formed by the ALD method sometimes contains more impurities such as carbon than a film formed by another deposition method. Note that the amount of impurities can be measured by SIMS, XPS, or AES (Auger Electron Spectroscopy).

[0289] Note that the insulator 250 is described as having a four-layer structure of the insulator 250a to the insulator 250d in the above description, but the present application is not limited to this. The insulator 250 can have a structure including at least one of the insulator 250a to the insulator 250d. By the insulator 250 being formed of one, two, or three of the insulator 250a to the insulator 250d, the manufacturing process of the semiconductor device can be simplified, and thus the productivity can be improved.

[0290] For example, as illustrated in FIG. 8A, the insulator 250 can have a three-layer structure. In this case, the insulator 250 preferably has a stacked structure of the insulator 250a, the insulator 250b over the insulator 250a, and the insulator 250c over the insulator 250b. That is, the insulator 250 has a structure in which the insulator 250d is removed from the structure illustrated in FIG. 7A. FIG. 3A FIG. 2A

[0291] ​​When the insulator 250 is formed, it is preferable to perform the ALD process twice or more. For example, it is preferable that the insulator 250 have a stacked structure of a plurality of insulating films, and that two or more of the plurality of insulating films be formed using the ALD process. By forming at least two or more insulating films using the ALD process, the coverage and thickness uniformity of the insulator 250 can be improved. Further, by successively forming two or more different films such as two or more insulating films using the ALD process, the yield can be improved.

[0292] It is preferable that a structure for suppressing the entry of hydrogen into the transistor 200 and the like be further included in addition to the above structure. For example, it is preferable that an insulator having a function of suppressing the diffusion of hydrogen be provided so as to cover one or both of the upper side and the lower side of the transistor 200 and the like. In the semiconductor device described in this embodiment, the insulator is, for example, the insulator 283, the insulator 282, the insulator 222, the insulator 221, and the like. Further, the insulator 215 provided below the transistor 200 can have the same structure as either or both of the insulator 282 and the insulator 283. In that case, the insulator 215 can have a stacked structure of the insulator 282 and the insulator 283, can have a structure in which the insulator 282 is positioned below and the insulator 283 is positioned above, or can have a structure in which the insulator 282 is positioned above and the insulator 283 is positioned below.

[0293] One or more of the insulator 283, the insulator 282, the insulator 222, and the insulator 221 is preferably used as a barrier insulator for suppressing the diffusion of impurities such as water and hydrogen from the substrate side or the upper side of the transistor 200 and the like into the transistor 200 and the like. Thus, one or more of the insulator 283, the insulator 282, the insulator 222, and the insulator 221 preferably includes an insulating material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, and the like), copper atoms, and the like (not easy to allow the impurities to pass through). Further, an insulating material having a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, and the like) (not easy to allow the oxygen to pass through) is preferably included.

[0294] The insulator 283, the insulator 282, the insulator 222, and the insulator 221 preferably each include an insulator having a function of inhibiting diffusion of impurities such as water, hydrogen, and oxygen, and for example, an aluminum oxide, a magnesium oxide, a hafnium oxide, a zirconium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and zirconium (hafnium zirconium oxide), a gallium oxide, silicon nitride, silicon nitride oxide, or the like can be used. For example, the insulator 283 and the insulator 221 preferably use silicon nitride or the like which has higher hydrogen barrier properties. Further, for example, the insulator 282 preferably uses an aluminum oxide or the like which has high capability of trapping or fixing hydrogen. Further, for example, the insulator 222 preferably uses a hafnium oxide or the like which has high capability of trapping or fixing hydrogen and is a high-k material.

[0295] Note that at least one of the insulator 221 and the insulator 222 can have a stacked-layer structure including a silicon oxide or a silicon oxynitride in addition to the above-described material. For example, the insulator 221 can have a stacked-layer structure of silicon nitride and a silicon oxide. Further, for example, the insulator 222 can have a stacked-layer structure of a hafnium oxide and a silicon oxide.

[0296] With such a structure, diffusion of impurities such as water and hydrogen from an interlayer insulating film or the like provided above the insulator 283 to the transistor 200 or the like can be inhibited. Further, diffusion of impurities such as water and hydrogen from an interlayer insulating film or the like provided below the insulator 221 to the transistor 200 or the like can be inhibited. Further, hydrogen in the insulator 280 and the insulator 250 or the like can be trapped or fixed in the insulator 282 or the insulator 222. Further, by provision of the insulator 282 and the insulator 283, diffusion of oxygen in the insulator 280 or the like to above the transistor 200 or the like can be inhibited. Further, by provision of the insulator 222 and the insulator 221, diffusion of oxygen in the oxide semiconductor 230 or the like to below the transistor 200 or the like can be inhibited. Thus, by employing a structure in which the transistor 200 is surrounded by insulators having a function of inhibiting diffusion of impurities such as water, hydrogen, and oxygen, above and below, diffusion of excess oxygen and hydrogen to the oxide semiconductor can be reduced. Thus, improvement in electric characteristics and reliability of the semiconductor device can be achieved.

[0297] Further, the insulator 275 and the insulator 250d preferably use silicon nitride or the like which has higher hydrogen barrier properties. Further, the insulator 250a preferably uses an aluminum oxide or the like which has high capability of trapping or fixing hydrogen. Further, the insulator 250c preferably uses a hafnium oxide or the like which has high capability of trapping or fixing hydrogen.

[0298] As the conductive body 242a, the conductive body 242b, and the conductive body 260, a conductive material which is not easily oxidized or a conductive material having a function of suppressing diffusion of oxygen is preferably used. As the conductive material, for example, a conductive material containing nitrogen and a conductive material containing oxygen can be given. By this, the conductivity of the conductive body 242a, the conductive body 242b, and the conductive body 260 can be suppressed from being reduced. In the case where a conductive material containing metal and nitrogen is used as the conductive body 242a, the conductive body 242b, and the conductive body 260, the conductive body 242a, the conductive body 242b, and the conductive body 260 are conductive bodies containing at least metal and nitrogen.

[0299] The conductive body 242a and the conductive body 242b are arranged apart from each other and are both in contact with the oxide semiconductor 230. As FIG. 6A indicated in FIG. 6A, the conductive body 242 is provided so as to cover the oxide semiconductor 230 having a high aspect ratio. Further, as FIG. 1C indicated in FIG. 6B, the conductive body 242a (the conductive body 242b) preferably has a structure in contact with two or more of the fin-shaped oxide semiconductors 230 when viewed in cross section.

[0300] Here, as FIG. 6A indicated in FIG. 7A, the conductive body 242a is provided in the vicinity of the source or the drain of the transistor 200 in a manner that the oxide semiconductor 230 is folded in half. By this, the conductive body 242a is in contact with the oxide semiconductor 230 on the upper portion of the oxide semiconductor 230, the side surface on the A3 side, and the side surface on the A4 side when viewed in cross section in the channel width direction. By this, the contact area of the conductive body 242a with the oxide semiconductor 230 is increased by a portion corresponding to the side surface on the A3 side and the side surface on the A4 side of the oxide semiconductor 230, as compared to the case where the oxide semiconductor 230 is formed in a planar shape. Further, as FIG. 1C indicated in FIG. 7B, in the case where a plurality of fin-shaped oxide semiconductors 230 are in contact with the conductive body 242a, the contact area can be further increased. Note that the conductive body 242b is the same as the conductive body 242a. FIG. 6A FIG. 1C indicated in FIG. 7A, the conductive body 242a is provided in the vicinity of the source or the drain of the transistor 200 in a manner that the oxide semiconductor 230 is folded in half. By this, the conductive body 242a is in contact with the oxide semiconductor 230 on the upper portion of the oxide semiconductor 230, the side surface on the A3 side, and the side surface on the A4 side when viewed in cross section in the channel width direction. By this, the contact area of the conductive body 242a with the oxide semiconductor 230 is increased by a portion corresponding to the side surface on the A3 side and the side surface on the A4 side of the oxide semiconductor 230, as compared to the case where the oxide semiconductor 230 is formed in a planar shape. Further, as

[0301] As described above, in the case where the contact area of the conductive body 242 with the oxide semiconductor 230 is increased, the on-state current, the frequency characteristics, or the like of the transistor 200 can be improved without increasing the area occupancy of the transistor 200. By this, a semiconductor device with high operation speed can be provided. Further, the operation speed of a memory device using the semiconductor device can be improved. By this, the miniaturization or the high integration of the semiconductor device can be achieved. Further, the storage capacity of a memory device using the semiconductor device can be increased. ​

[0302] Since the conductive body 242a and the conductive body 242b are in contact with the oxide semiconductor 230, a conductive material which is not easily oxidized or a conductive material having a function of inhibiting the diffusion of oxygen is preferably used. This can inhibit a decrease in the conductivity of the conductive body 242a and the conductive body 242b. In addition, the extraction of oxygen from the oxide semiconductor 230 can be inhibited, so that excess oxygen vacancies are not formed. Furthermore, by using a material which easily extracts (extracts) hydrogen as the conductive body 242a and the conductive body 242b, the hydrogen concentration of the oxide semiconductor 230 can be reduced, and thus this is preferable.

[0303] As the conductive body 242, a metal nitride is preferably used, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, a nitride containing titanium and aluminum, or the like is preferably used. In one embodiment of the present application, a nitride containing tantalum is particularly preferably used. In addition, for example, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like can be used. These materials are a conductive material which is not easily oxidized or a material which maintains conductivity even when oxygen is absorbed, and thus are preferable.

[0304] Note that hydrogen contained in the oxide semiconductor 230 or the like sometimes diffuses into the conductive body 242a or the conductive body 242b. In particular, when a nitride containing tantalum is used as the conductive body 242a and the conductive body 242b, hydrogen contained in the oxide semiconductor 230 or the like sometimes easily diffuses into the conductive body 242a or the conductive body 242b, and the diffused hydrogen is sometimes bonded to nitrogen contained in the conductive body 242a or the conductive body 242b. That is, hydrogen contained in the oxide semiconductor 230 or the like is sometimes extracted by the conductive body 242a or the conductive body 242b.

[0305] In addition, in order to inhibit a decrease in the conductivity of the conductive body 242a and the conductive body 242b, a metal oxide containing indium, zinc, and one or more selected from gallium, aluminum, and tin can be used as the oxide semiconductor 230. When a CAAC-OS is used, the extraction of oxygen from the oxide semiconductor 230 to the conductive body 242a or the conductive body 242b can be inhibited. In addition, a decrease in the conductivity of the conductive body 242a and the conductive body 242b can be inhibited.

[0306] As FIG. 3BAs shown, conductors 242a and 242b can also have a two-layer structure. Conductor 242a can be a stacked film of conductor 242a1 and conductor 242a2 on conductor 242a1, and conductor 242b can be a stacked film of conductor 242b1 and conductor 242b2 on conductor 242b1. In this case, the conductive materials that are not easily oxidized or conductive materials that have the function of inhibiting oxygen diffusion are preferably used as the layers (conductors 242a1 and conductor 242b1) in contact with the oxide semiconductor 230. This can suppress the decrease in conductivity of conductors 242a and 242b. In addition, it can suppress the formation of excessive oxygen vacancies due to the extraction of oxygen from the oxide semiconductor 230. Furthermore, by using materials that easily absorb (extract) hydrogen as the layers (conductors 242a1 and conductor 242b1) in contact with the oxide semiconductor 230, the hydrogen concentration of the oxide semiconductor 230 can be reduced, which is preferred.

[0307] The conductivity of conductors 242a2 and 242b2 is preferably higher than that of conductors 242a1 and 242b1. For example, the thickness of conductors 242a2 and 242b2 is preferably greater than that of conductors 242a1 and 242b1. Conductors suitable for conductor 260b (described later) can be used as conductors 242a2 and 242b2. By adopting the above structure, the resistance of conductors 242a2 and 242b2 can be reduced. Therefore, the on-state current of transistor 200 can be increased, thereby improving the operating speed of the semiconductor device according to this embodiment.

[0308] For example, tantalum nitride or titanium nitride can be used as conductors 242a1 and 242b1, and tungsten can be used as conductors 242a2 and 242b2.

[0309] In addition, such as FIG. 3C As shown, a structure can also be adopted in which, when viewed in cross-section along the channel length of transistor 200, conductors 242a1 and 242b1 protrude beyond conductors 242a2 and 242b2, respectively. The protrusions of conductors 242a1 and 242b1 are covered by insulator 250. Here, the distance between conductors 242a1 and 242b1 is smaller than the distance between conductors 242a2 and 242b2. By adopting this structure, the distance between the source and drain can be further reduced, and the channel length can be correspondingly reduced. Therefore, the frequency characteristics of transistor 200 can be improved. Thus, by miniaturizing the semiconductor device, a semiconductor device with improved operating speed can be provided.

[0310] like FIG. 1B and FIG. 1DAs shown in FIG. 2, the conductive body 260 is arranged in the opening formed in the insulator 280 and the insulator 275. In the opening, the conductive body 260 is arranged so as to cover the top surface of the insulator 222, the side surface of the oxide semiconductor 230, and the top surface of the oxide semiconductor 230 with the insulator 250 interposed therebetween. Further, the top surface of the conductive body 260 is arranged so as to be in accordance with or substantially in accordance with the height of the uppermost portion of the insulator 250 and the top surface of the insulator 280.

[0311] In addition, in the above-described opening in which the conductive body 260 and the insulator 250 are arranged, the side wall of the opening can be perpendicular or substantially perpendicular to the top surface of the insulator 222 or can have a tapered shape. By having a tapered shape, the side wall can improve the coverage of the insulator 250 or the like arranged in the opening of the insulator 280, and thus can reduce defects such as voids.

[0312] The conductive body 260 is used as the first gate electrode of the transistor 200. Here, as shown in FIG. 2, the conductive body 260 is preferably arranged so as to extend in the channel width direction. By employing such a structure, the conductive body 260 is used as a wiring when a plurality of transistors are arranged. FIG. 1A and FIG. 1B As shown in FIG. 2, the conductive body 260 is preferably arranged so as to extend in the channel width direction. By employing such a structure, the conductive body 260 is used as a wiring when a plurality of transistors are arranged.

[0313] A portion of the conductive body 260 is arranged so as to be folded in half with the fin-shaped oxide semiconductor 230 interposed therebetween. Thus, as shown in FIG. 2, the oxide semiconductor 230 and the conductive body 260 are arranged so as to face each other with the insulator 250 interposed therebetween, at the upper portion of the oxide semiconductor 230, the side surface on the Al side, and the side surface on the A2 side, when viewed in the cross section in the channel width direction. That is, the upper portion of the oxide semiconductor 230, the side surface on the Al side, and the side surface on the A2 side each serve as a channel formation region. Thus, the channel width of the transistor 200 is larger than that in the case where the oxide semiconductor 230 has a planar shape, by the portions of the oxide semiconductor 230 on the Al side and the A2 side. FIG. 2B In FIG. 2 and the like, the conductive body 260 has a two-layer structure. Here, the conductive body 260 preferably includes a conductive body 260a and a conductive body 260b arranged on the conductive body 260a. For example, the conductive body 260a is preferably arranged so as to surround the bottom surface and the side surface of the conductive body 260b. At this time, as the conductive body 260a, a conductive material which is not easily oxidized or a conductive material which has a function of suppressing diffusion of oxygen is preferably used.

[0314] FIG. 1D In FIG. 2 and the like, the conductive body 260 has a two-layer structure. Here, the conductive body 260 preferably includes a conductive body 260a and a conductive body 260b arranged on the conductive body 260a. For example, the conductive body 260a is preferably arranged so as to surround the bottom surface and the side surface of the conductive body 260b. At this time, as the conductive body 260a, a conductive material which is not easily oxidized or a conductive material which has a function of suppressing diffusion of oxygen is preferably used.

[0315] ​As the conductive body 260a, a conductive material having a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, and the like is preferably used. Further, a conductive material having a function of suppressing diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, and the like) is preferably used.

[0316] Further, when the conductive body 260a has a function of suppressing diffusion of oxygen, oxidation of the conductive body 260b due to oxygen contained in the insulator 280 or the like can be suppressed, which leads to a decrease in conductivity. As the conductive material having a function of suppressing diffusion of oxygen, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used.

[0317] Further, the conductive body 260b preferably uses a conductive body having high conductivity. For example, the conductive body 260b can use a conductive material in which tungsten, copper, or aluminum is a main component. Further, the conductive body 260b can have a stacked structure, and for example, can have a stacked structure of titanium or titanium nitride and the above conductive material.

[0318] Further, in the transistor 200, the conductive body 260 is formed in a self-aligned manner so as to fill an opening formed in the insulator 280 or the like. Here, a side surface of the insulator 280 in the above opening is aligned or substantially aligned with a side surface of the conductive body 242a and a side surface of the conductive body 242b. Thus, the conductive body 260 can be arranged so as to overlap with a region between the conductive body 242a and the conductive body 242b without alignment.

[0319] The dielectric constant of each of the insulator 216 and the insulator 280 is preferably lower than that of the insulator 222. By using a material having a low dielectric constant for an interlayer film, parasitic capacitance generated between wirings can be reduced.

[0320] For example, the insulator 216 and the insulator 280 each preferably contain one or more of silicon oxide, silicon oxynitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having a void.

[0321] In particular, silicon oxide and silicon oxynitride have heat stability, and thus are preferable. In particular, since a material such as silicon oxide, silicon oxynitride, and silicon oxide having a void easily forms a region containing oxygen which is separated by heating, it is preferable.

[0322] Further, the top surface of the insulator 216 and the insulator 280 can be planarized.

[0323] The concentration of impurities such as water and hydrogen in the insulator 280 is preferably reduced. For example, as the insulator 280, silicon oxide, silicon oxynitride, or the like containing silicon is preferably used.

[0324] The conductive body 240a and the conductive body 240b are each formed in the opening of the insulator 275, the insulator 280, the insulator 282, and the insulator 283. The bottom surface of the conductive body 240a is in contact with the top surface of the conductive body 242a, and the bottom surface of the conductive body 240b is in contact with the top surface of the conductive body 242b. Here, the height of the top surface of the conductive body 240 is substantially the same as the height of the top surface of the insulator 283.

[0325] The conductive body 240 preferably uses a conductive material in which tungsten, copper, or aluminum is the main component. Alternatively, the conductive body 240 can have a stacked structure in which a first conductive body is provided so as to be in contact with the side surface of the insulator 241 and a second conductive body is provided inside the first conductive body. In this case, as the second conductive body, the above-described conductive material can be used. Here, the above-described first conductive body corresponds to the conductive body 240a1 illustrated in FIG. 5A, and the above-described second conductive body corresponds to the conductive body 240a2 illustrated in FIG. 5B. FIG. 6A FIG. 6A

[0326] Alternatively, when the conductive body 240 has a stacked structure, as the first conductive body provided in the vicinity of the insulator 283, the insulator 282, the insulator 280, and the insulator 275, a conductive material having a function of inhibiting the penetration of impurities such as water and hydrogen is preferably used. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like is preferably used. Alternatively, a single layer or a stack of a conductive material having a function of inhibiting the penetration of impurities such as water and hydrogen can be used. With such a structure, the penetration of impurities such as water and hydrogen included in the layer over the insulator 283 into the oxide semiconductor 230 through the conductive body 240a and the conductive body 240b can be inhibited.

[0327] The insulator 241a and the insulator 241b are each formed so as to be in contact with the inner wall of the opening of the insulator 275, the insulator 280, the insulator 282, and the insulator 283. The side surface of the inner side of the insulator 241a is in contact with the conductive body 240a, and the side surface of the inner side of the insulator 241b is in contact with the conductive body 240b.

[0328] As the insulator 241, a barrier insulating film which can be used for the insulator 275 and the like can be used. For example, as the insulator 241, an insulator such as silicon nitride, aluminum oxide, silicon oxynitride, or the like can be used. With the provision of the insulator 241, the penetration of impurities such as water and hydrogen included in the insulator 280 and the like into the oxide semiconductor 230 through the conductive body 240a and the conductive body 240b can be inhibited. In particular, silicon nitride has high barrier properties against hydrogen and is thus preferable. Furthermore, absorption of oxygen included in the insulator 280 by the conductive body 240a and the conductive body 240b can be prevented.

[0329] In the case where the insulator 241 has a structure as illustrated in FIG. 5A, the conductive body 240a is preferably formed so as to be in contact with the side surface of the insulator 241a. In the case where the insulator 241 has a structure as illustrated in FIG. 5B, the conductive body 240b is preferably formed so as to be in contact with the side surface of the insulator 241b. FIG. 1D ​​When the stacked structure as illustrated is used, it is preferable that an oxygen barrier insulating film and a hydrogen barrier insulating film be used in combination as the first insulating film in contact with the inner wall of the opening of the insulator 280 and the second insulating film on the inner side thereof.

[0330] For example, an aluminum oxide deposited by a thermal ALD method can be used as the first insulating film, and a silicon nitride deposited by a PEALD method can be used as the second insulating film. With such a structure, oxidation of the conductor 240 can be suppressed, and entry of hydrogen into the conductor 240 can be reduced.

[0331] Note that, although the above example illustrates the case where the insulator 241 has a two-layer stacked structure, the present application is not limited to this. For example, the insulator 241 can have a single-layer structure or a three-layer or more stacked structure. In addition, although the above example illustrates the case where the conductor 240 has a two-layer stacked structure, the present application is not limited to this. For example, the conductor 240 can have a single-layer or a three-layer or more stacked structure.

[0332] For example, as illustrated in FIG. 8A, the conductor 240a can be in contact with the conductor 242a in the vicinity of the side surface of the oxide semiconductor 230. FIG. 6A In this case, the conductor 240a is in contact with the conductor 242a in the vicinity of the side surface of the oxide semiconductor 230. Thus, the contact area of the conductor 240a with the conductor 242a is increased by a portion corresponding to the side surface of the oxide semiconductor 230, as compared with the case where the oxide semiconductor 230 is formed in a planar shape. FIG. 1C In this case, the conductor 240a is in contact with the conductor 242a in the vicinity of the side surface of the oxide semiconductor 230. Thus, the contact area of the conductor 240a with the conductor 242a is increased by a portion corresponding to the side surface of the oxide semiconductor 230, as compared with the case where the oxide semiconductor 230 is formed in a planar shape. FIG. 6A FIG. 1C The same applies to the conductor 240b and the conductor 242b. That is, like the conductor 240a and the conductor 242a, the contact area of the conductor 240b with the conductor 242b is increased.

[0333] ​As described above, when the contact area of the conductive body 240 and the conductive body 242 is increased, the contact resistance between the conductive body 240 and the conductive body 242 can be reduced. Thus, the on-state current, the frequency characteristics, or the like of the transistor 200 can be increased without greatly increasing the area occupancy of the transistor 200. Thus, a semiconductor device with high operation speed can be provided. Further, the operation speed of a memory device using the semiconductor device can be increased. Thus, the miniaturization or high integration of the semiconductor device can be achieved. In addition, the storage capacity of a memory device using the semiconductor device can be increased.

[0334] Note that in the above embodiment, as illustrated in FIG. 1A, the shape of the opening provided with the conductive body 240 and the insulator 241 is a quadrangular shape in plan view, but is not limited thereto. For example, the opening can have a circular shape, an approximately circular shape such as an elliptical shape or a polygonal shape such as a quadrangular shape, or a shape in which a corner of a polygonal shape such as a quadrangular shape is rounded in plan view. Further, as illustrated in FIG. 1A, the opening is formed so as to overlap with the plurality of fin-shaped oxide semiconductors 230, but is not limited thereto, and can be formed so as to overlap with at least the conductive body 242a or the conductive body 242b. For example, as illustrated in FIG. 1B, a structure in which a part of the opening (which can be said to be a part of the conductive body 240) overlaps with the oxide semiconductor 230 and another part of the opening (which can be said to be another part of the conductive body 240) does not overlap with the oxide semiconductor 230 can be employed. In this case, when a structure in which a part of the conductive body 240 overlaps with the oxide semiconductor 230 is employed, the margin for arrangement of the conductive body 240 can be increased. Further, for example, as illustrated in FIG. 1C, the opening and the conductive body 240 can be provided in a region which does not overlap with the oxide semiconductor 230. FIG. 1A FIG. 1C FIG. 6B FIG. 6C

[0335] FIG. 1D FIG. 6B FIG. 6C FIG. 7A FIG. 7B

[0336] FIG. 10A to FIG. 10D ​​​​​​​​​​​In this embodiment, the semiconductor device of this embodiment can also have a structure in which the insulator 224 is provided below the oxide semiconductor 230. The top surface of the insulator 224 has the same shape as that of the oxide semiconductor 230, and the insulator 224 overlaps with the oxide semiconductor 230 when viewed from the top. The bottom surface of the insulator 224 is in contact with the insulator 222, the side surface of the insulator 224 is in contact with the insulator 250 and the conductor 242, and the top surface of the insulator 224 is in contact with the bottom surface of the oxide semiconductor 230. Note that the insulator 224 can be formed using an insulating material that can be used for the insulator 250b. For example, silicon oxide can be used as the insulator 224. In this case, FIG. 10A to FIG. 10D Corresponding to FIG. 1A to FIG. 1D Therefore, the above description can be referred to for the detailed structure.

[0337] In this case, as FIG. 11 illustrated, the thickness t2 of the insulator 250 in the opening of the insulator 280 and the insulator 275 is preferably smaller than the thickness t1 of the insulator 224. With such a structure, the position of the bottom surface of the conductor 260 (the conductor 260a) positioned in the opening can be made lower than the bottom surface of the oxide semiconductor 230 by the difference (t1-t2) between the thickness t1 and the thickness t2.

[0338] When the bottom surface of the conductor 260 is positioned below the bottom surface of the oxide semiconductor 230, the gate electric field can be sufficiently applied to the upper end portion to the lower end portion of the oxide semiconductor 230. In other words, the entire oxide semiconductor 230 can be surrounded by the electric field of the conductor 260 in the opening of the insulator 280 or the like, and thus the oxide semiconductor 230 can be used as a channel formation region. With such a structure, the lower end portion of the oxide semiconductor 230 can be prevented from being used as a parasitic channel and the leakage current between the source and the drain can be reduced. In addition, characteristics such as the always-on of the transistor due to the parasitic channel can be suppressed. That is, the electrical characteristics of the transistor 200 can be improved.

[0339] In addition, as described above, the channel width can be increased by using the upper end portion to the lower end portion of the oxide semiconductor 230 as a channel formation region. Thus, the on-state current, the transconductance, the frequency characteristics, and the like of the transistor 200 can be improved.

[0340] Note that in this specification and the like, the above-described transistor structure in which a channel formation region is surrounded by an electric field of a gate electrode is referred to as a surrounded channel (S-channel) structure. In the S-channel structure, a gate electrode is arranged so as to surround a channel on two or more surfaces (specifically, two surfaces, three surfaces, four surfaces, or the like) of the channel. In the case of employing the S-channel structure, the resistance to short channel effects can be improved, in other words, a transistor which is less likely to have a short channel effect can be realized.

[0341] Note that the S-channel structure is a structure in which a channel formation region is electrically surrounded, and thus the structure can also be said to be substantially the same as a Gate All Around (GAA) structure or a Lateral Gate All Around (LGAA) structure. By making the transistor 200 have an S-channel structure, a GAA structure, or an LGAA structure, a channel formation region formed at or near an interface of the oxide semiconductor 230 and the gate insulator can be regarded as the entire bulk of the oxide semiconductor 230. Thus, since the current density flowing through the transistor can be increased, an increase in on-state current of the transistor or an increase in field-effect mobility of the transistor can be expected. In one embodiment of the present application, the oxide semiconductor 230 has a CAAC structure and a fin structure. With this structure, it is possible to be in a state where a current path flowing through the source and the drain of the transistor is parallel to the ab plane of the crystal axis. In other words, the oxide semiconductor having a CAAC structure and a fin structure has a conduction path that seems to be equivalent to that of a two-dimensional semiconductor material. By using such an oxide semiconductor, a device capable of two-dimensional conduction can be manufactured.

[0342] In addition, as FIG. 12A to FIG. 12D indicated in the drawings, the semiconductor device of this embodiment can also have a structure in which the conductor 205 is provided below the insulator 221. The conductor 205 has a region serving as a second gate electrode (lower gate electrode) of the transistor 200. Further, the insulator 222 and the insulator 221 each have a region serving as a second gate insulator of the transistor 200. Here, FIG. 12A to FIG. 12D corresponding to FIG. 1A to FIG. 1D the above description can be referred to.

[0343] In the transistor 200, the conductor 205 is provided so as to overlap with the oxide semiconductor 230 and the conductor 260. Here, the conductor 205 is preferably provided so as to be embedded in an opening formed in the insulator 216. Further, as FIG. 12A and FIG. 12B indicated in the drawings, the conductor 205 is preferably provided so as to extend in the channel width direction. With this structure, the conductor 205 is used as a wiring when a plurality of transistors are provided.

[0344] As FIG. 12B and FIG. 12D indicated in the drawings, the conductor 205 preferably includes a conductor 205a and a conductor 205b. The conductor 205a is provided so as to be in contact with the bottom surface and the side wall of the opening portion. The conductor 205b is provided so as to fill recesses of the conductor 205a formed along the opening portion. Here, the height of the top surface of the conductor 205 coincides with or approximately coincides with the height of the top surface of the insulator 216.

[0345] Here, the conductive body 205a preferably includes a conductive material having a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, or the like), copper atoms, and the like. Alternatively, a conductive material having a function of suppressing diffusion of oxygen (at least one of, for example, oxygen atoms, oxygen molecules, and the like) is preferable.

[0346] By using a conductive material having a function of reducing hydrogen diffusion as the conductive body 205a, diffusion of impurities such as hydrogen included in the conductive body 205b to the oxide semiconductor 230 through the insulator 216 and the like can be prevented. Further, by using a conductive material having a function of suppressing diffusion of oxygen as the conductive body 205a, oxidation of the conductive body 205b and reduction in conductivity can be suppressed. As the conductive material having a function of suppressing diffusion of oxygen, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide can be given, for example. The conductive body 205a can have a single-layer structure or a stacked-layer structure of the above conductive materials. For example, the conductive body 205a preferably includes titanium nitride.

[0347] Further, the conductive body 205b preferably uses a conductive material mainly including tungsten, copper, or aluminum. For example, the conductive body 205b preferably includes tungsten.

[0348] The conductive body 205 can be used as a second gate electrode. In this case, by independently changing the potential applied to the conductive body 205 without linkage with the potential applied to the conductive body 260, the threshold voltage (Vth) of the transistor 200 can be controlled. In particular, by applying a negative potential to the conductive body 205, the Vth of the transistor 200 can be further increased and the off-state current can be reduced. Thus, as compared with the case where no negative potential is applied to the conductive body 205, the drain current at the time when the potential applied to the conductive body 260 is 0 V can be reduced in the case where a negative potential is applied to the conductive body 205.

[0349] Further, the resistivity of the conductive body 205 is designed in consideration of the potential applied to the conductive body 205, and the thickness of the conductive body 205 is set in accordance with the resistivity. Further, the thickness of the insulator 216 is substantially the same as that of the conductive body 205. Here, it is preferable to reduce the thickness of the conductive body 205 and the insulator 216 within a range allowed by the design of the conductive body 205. By reducing the thickness of the insulator 216, the absolute amount of impurities such as hydrogen included in the insulator 216 can be reduced, and thus diffusion of the impurities to the oxide semiconductor 230 can be suppressed.

[0350] Note that the above structure shows a stacked structure of conductors 205a and 205b, but the present invention is not limited thereto. Conductor 205 can have a single-layer structure or a stacked structure of three or more layers. For example, when conductor 205 has a three-layer stacked structure, the above-described stacked structure of conductors 205a and 205b can be used, and a conductor containing the same material as conductor 205a can be provided on conductor 205b. In this case, the conductor can also be formed by filling the recess formed by conductors 205a and 205b, wherein the top surface of conductor 205b is lower than the uppermost part of conductor 205a.

[0351] In addition, such as FIG. 13A As shown, the transistor 200, capacitor 460, and transistor 310 formed on the silicon substrate described above can be used as a 2T (transistor) 1C (capacitor) type memory cell. FIG. 13A As shown, a layer including transistor 200 and capacitor 460 can be disposed on a layer including transistor 310. Additionally... FIG. 14A This is a cross-sectional view of the channel width of transistor 200. FIG. 14B This is a cross-sectional view of the capacitor at 460° in this direction. FIG. 14C This is a cross-sectional view of the channel width of transistor 310.

[0352] Transistor 310 is disposed on substrate 311 and includes a conductor 316 serving as a gate, an insulator 315 serving as a gate insulator, a semiconductor region 313 comprising a portion of substrate 311, and low-resistance regions 314a and 314b serving as source or drain regions. Transistor 310 can be a p-channel transistor or an n-channel transistor. For example, a single-crystal silicon substrate can be used as substrate 311.

[0353] like FIG. 14C As shown, the semiconductor region 313 (a portion of the substrate 311) forming the channel in the transistor 310 has a convex shape. Furthermore, a conductor 316 is provided such that it covers the sides and top surface of the semiconductor region 313 with an insulator 315 in between. Additionally, the conductor 316 can also be made of a material with an adjustable work function. The transistor 310 described above utilizes the convex portion of the semiconductor substrate and is therefore also referred to as a finned transistor. Furthermore, an insulator may be included that contacts the upper part of the convex portion and serves as a mask for forming the convex portion. While this example shows the convex portion formed by processing a portion of the semiconductor substrate, an SOI (Silicon on Insulator) substrate can also be processed to form a semiconductor film with a convex shape.

[0354] Notice, FIG. 13AThe structure of transistor 310 shown is only an example and is not limited to this structure. Appropriate transistors can be used depending on the circuit structure or driving method.

[0355] Wiring layers, including interlayer films, wiring, and plugs, can also be provided between the various structures. Furthermore, multiple wiring layers can be configured according to the design. In this specification, wiring and plugs electrically connected to the wiring can also be considered as components. In other words, a portion of a conductor is sometimes used as wiring, and a portion of a conductor is sometimes used as a plug.

[0356] For example, in transistor 310, insulators 320, 322, 324, and 326 are sequentially stacked as interlayer films. Furthermore, conductors such as 328 are embedded in insulators 320 and 322. Furthermore, conductors such as 330 are embedded in insulators 324 and 326. Note that conductors 328 and 330 are used as contact plugs or wiring.

[0357] Alternatively, the insulator used as an interlayer film can also be used as a planarization film covering the uneven shape underneath. For example, to improve flatness, the top surface of the insulator 322 can be planarized by using a planarization process such as chemical mechanical polishing (CMP).

[0358] A transistor 200 and a capacitor 460 are disposed on an insulator 326. Here, the transistor 200 is used. FIG. 3C The transistor 200 is shown. The structure of the transistor 200 and the layer forming the transistor 200 is the same as described above, and is shown using the same shading lines and symbols. For detailed structure, please refer to the above description. Additionally, an insulator 285 is formed on the insulator 283, and a conductor 413 electrically connected to the conductor 240a is formed on the insulator 285. The insulator 285 can use an insulating material suitable for the insulator 216. Furthermore, the conductor 413 can use a conductive material suitable for the conductor 242.

[0359] Capacitor 460 includes an oxide semiconductor 452, a conductor 242b1 on the oxide semiconductor 452, an insulator 454 on the conductor 242b1, and a conductor 456 on the insulator 454. For example... FIG. 13A , FIG. 14A and FIG. 14BAs shown, oxide semiconductor 452 has the same structure as oxide semiconductor 230 and can be formed through the same process. Capacitor 460 and transistor 200 share conductor 242b1. Insulator 454 has the same structure as insulator 250 and can be formed through the same process. Conductor 456 has the same structure as conductor 260 and can be formed through the same process. Furthermore, conductors 456 and 260 can be extended and used as wiring.

[0360] Here, capacitor 460 includes a conductor 242b1 serving as a first electrode, a conductor 456 serving as a second electrode, and an insulator 454 serving as a dielectric. That is, capacitor 460 constitutes a MIM (Metal-Insulator-Metal) capacitor.

[0361] The capacitor 460 has a structure similar to that of the transistor 200 and can be fabricated on the same layer as the transistor 200. Thus, the insulator 454 and conductor 456 are disposed within the openings formed in the insulators 280 and 275. However, unlike the transistor 200, the conductor 242b1 in the capacitor 460 is disposed overlapping the conductor 456 and the insulator 454. Therefore, the openings reach the conductor 242b1, and the insulator 454 contacts the top surface of the conductor 242b1 within the openings.

[0362] like FIG. 14B As shown, the oxide semiconductor 452 of capacitor 460, like oxide semiconductor 230, has a high aspect ratio structure, wherein multiple oxide semiconductors 230 can be disposed. Therefore, similar to oxide semiconductor 230, in oxide semiconductor 452, when viewed in cross-section along the channel width direction, the height of oxide semiconductor 452 is greater than the width of oxide semiconductor 452. Furthermore, similar to oxide semiconductor 230, oxide semiconductor 452 has two or more regions overlapping with conductor 456 when viewed from above. Therefore, the area of ​​the conductor 242b1, insulator 454, and conductor 456 disposed along the top and side surfaces of oxide semiconductor 452 can be increased. Thus, the electrostatic capacitance can be increased without increasing the occupied area of ​​capacitor 460.

[0363] Furthermore, a conductor 458 is provided in the openings formed in insulators 215, 216, 221, and 222. The conductor 458 can, for example, have the same structure as the conductor 240. The top surface of the conductor 458 contacts the bottom surface of the conductor 242b1 and can be electrically connected to the conductor 330. Note that in FIG. 13AOnly one conductor 458 is shown, but it is not limited to this; two or more conductors can be used to electrically connect conductor 242b1 and conductor 330. Alternatively, a structure can be adopted in which a portion of conductor 242b1 is embedded in an opening formed in insulator 215, insulator 216, insulator 221, and insulator 222.

[0364] By employing the structure described above, one of the source and drain electrodes of transistor 200, one electrode of capacitor 460, and the gate of transistor 310 can be electrically connected to form a 2T1C type memory cell. Alternatively, by employing a structure without transistor 310, a 1T1C type memory cell can be formed. Furthermore, by employing a structure without capacitor 460, a 2T0C type memory cell can be formed.

[0365] Here, transistor 310 is preferably arranged overlapping at least one of transistor 200 and capacitor 460. For example, transistor 310 may overlap with transistor 200. By adopting the above structure, the occupied area of ​​the memory cell can be reduced.

[0366] In addition, FIG. 13A In the structure shown, transistor 200 and capacitor 460 respectively have oxide semiconductor 230 and oxide semiconductor 452, but the present invention is not limited to this structure. For example, as FIG. 13B As shown, a structure in which an insulator 250, a conductor 260, an insulator 454, and a conductor 456 are formed on the oxide semiconductor 230 can also be used. That is, a structure in which the transistor 200 and the capacitor 460 share the oxide semiconductor 230 can also be used. Therefore, it is not necessary to form a separate pattern of the oxide semiconductor 230 between the transistor 200 and the capacitor 460, thus reducing the area occupied by the transistor 200 and the capacitor 460.

[0367] in addition, FIG. 13A The structure shown includes a transistor 310 formed on a silicon substrate, but the present invention is not limited to this structure. For example, as FIG. 15A As shown, the transistor 200 described above can also be configured with two transistors (hereinafter referred to as transistor 200a and transistor 200b) having the same structure. Here, transistor 200a and transistor 200b are disposed in the same layer and are arranged to cross each other in the channel length direction. Note that since transistors 200a and 200b have the same structure as transistor 200, the same shading lines and symbols are used for the constituent elements. For detailed structure, please refer to the description above.

[0368] In addition, FIG. 15AIn the illustrated structure, the capacitor 400 is provided on the insulator 285. The capacitor 400 includes the conductor 410 on the insulator 285, the insulator 430 on the conductor 410, and the conductor 420 on the insulator 430. The conductor 240b, the insulator 241b, the conductor 240c, and the insulator 241c are provided in contact with the bottom surface of the conductor 410. Here, the conductor 240c and the insulator 241c are embedded in the openings of the insulator 282, the insulator 283, and the insulator 285, and have the same structure as the conductor 240b and the insulator 241c. The bottom surface of the conductor 240c is in contact with the top surface of the conductor 260 of the transistor 200b. With this structure, one of the source and drain of the transistor 200a, one electrode of the capacitor 400, and the gate of the transistor 200b can be electrically connected.

[0369] The capacitor 400 includes the conductor 410 as a first electrode, the conductor 420 as a second electrode, and the insulator 430 as a dielectric. That is, the capacitor 400 constitutes an MIM capacitor.

[0370] The conductors 410 and 420 can use the same conductive material as that used for the conductor 260. For example, the conductors 410 and 420 can use tungsten. Here, with the structure in which the conductor 420 covers the conductor 410, the side surface of the conductor 410 can be used as the capacitor 400. Thus, the electrostatic capacitance of the capacitor 400 can be increased. Further, the conductor 413 and the conductor 410 can be formed at the same time.

[0371] The conductors 410, 413, and 420 have a single-layer structure, but are not limited to this structure and can have a stacked-layer structure of two or more layers. For example, a stacked-layer structure of a conductor having barrier properties and a conductor having high conductivity can be used. For example, a stacked-layer structure of titanium nitride and tungsten on the titanium nitride can be used.

[0372] As the insulator 430 included in the capacitor 400, a high-k material having a high relative dielectric constant is preferably used. As the high-k material, gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, or a nitride containing silicon and hafnium, or the like is used. By using the above high-k material, the thickness of the insulator 430 can be set to a level at which the leakage current can be suppressed, and the electrostatic capacitance of the capacitor 400 can be sufficiently ensured. Further, the insulator 430 is formed so as to cover the conductor 410, and thus a deposition method having high coverage such as an ALD method or a CVD method is preferably used for deposition.

[0373] Further, the insulator 430 can also have a stacked structure. A stacked structure of a high-k material and a material having a large dielectric strength compared to the high-k material is preferably used. As the material having a large dielectric strength (low-k material), there are silicon oxide, silicon oxynitride, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and the like. As the insulator 430, a stacked structure of aluminum oxide which is a high-k material and silicon oxide which has a large dielectric strength on aluminum oxide can be used.

[0374] Further, for example, an insulator in which zirconium oxide, aluminum oxide, and zirconium oxide are sequentially stacked can be used as the insulator 430. Further, for example, an insulator in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are sequentially stacked can be used. Further, for example, an insulator in which hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide are sequentially stacked can be used. By using an insulator having a large dielectric strength such as aluminum oxide, the dielectric strength is increased, and the static breakdown of the capacitor 400 can be suppressed.

[0375] Further, a material which can have ferroelectricity can also be used as the insulator 430. As the material which can have ferroelectricity, there are hafnium oxide, zirconium oxide, HfZrO X (X is a real number greater than 0) and the like. Further, as the material which can have ferroelectricity, there is a material to which an element J1 (here, the element J1 is one or a plurality of elements selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, and the like) is added to hafnium oxide. Here, the ratio of the number of atoms of hafnium to the number of atoms of the element J1 can be appropriately set, and for example, the ratio of the number of atoms of hafnium to the number of atoms of the element J1 can be set to 1:1 or the vicinity thereof. Further, as the material which can have ferroelectricity, there is a material to which an element J2 (here, the element J2 is one or a plurality of elements selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, and the like) is added to zirconium oxide, and the like. Further, the ratio of the number of atoms of zirconium to the number of atoms of the element J2 can be appropriately set, and for example, the ratio of the number of atoms of zirconium to the number of atoms of the element J2 can be set to 1:1 or the vicinity thereof. Further, as the material which can have ferroelectricity, a lead titanate (PbTiO X ), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), barium titanate, and the like which have a perovskite structure.

[0376] In addition, as a material that can have ferroelectricity, a metal nitride containing an element Ml, an element M2, and nitrogen can be given. Here, the element Ml is one or more selected from aluminum, gallium, indium, and the like. The element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, and the like. Note that the proportion of the number of atoms of the element Ml to the number of atoms of the element M2 can be set as appropriate. In addition, a metal oxide containing the element Ml and nitrogen sometimes has ferroelectricity even if the element M2 is not contained. Furthermore, as a material that can have ferroelectricity, a material obtained by adding an element M3 to the above metal nitride can be given. In addition, the element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, and the like. Here, the proportion of the number of atoms of the element Ml, the number of atoms of the element M2, and the number of atoms of the element M3 can be set as appropriate.

[0377] Furthermore, as a material that can have ferroelectricity, perovskite-type oxynitride such as SrTaO2N and BaTaO2N, GaFeO3 which is κ-type aluminum oxide, and the like can be given.

[0378] Note that in the above description, examples of the metal oxide and the metal nitride are shown, but the present application is not limited thereto. For example, a metal oxynitride obtained by adding nitrogen to the above metal oxide or a metal oxynitride obtained by adding oxygen to the above metal nitride, or the like can be used.

[0379] Furthermore, as a material that can have ferroelectricity, for example, a mixture or a compound composed of a plurality of materials selected from the above materials can be used. Alternatively, as the insulator 430, a stacked structure composed of a plurality of materials selected from the above materials can be used. Since the above materials and the like can have a change in crystal structure (properties) depending on deposition conditions and various processes and the like, a material exhibiting ferroelectricity in this specification and the like is referred to not only as a ferroelectric but also as a material that can have ferroelectricity.

[0380] Note that, FIG. 15A The shape of the capacitor 400 in the storage device shown in the drawing is a planar shape, but the storage device shown in this embodiment is not limited thereto. For example, the shape of the capacitor 400 can be a cylindrical shape or a columnar shape.

[0381] The insulator 487 is provided so as to cover the capacitor 400, and the insulator 488 is provided so as to cover the insulator 487. As the insulator 487, an insulator having a function of trapping or fixing hydrogen is preferably used. For example, the insulator 487 can be aluminum oxide. As the insulator 488, an insulator having a function of suppressing diffusion of hydrogen is preferably used. For example, the insulator 488 can be silicon nitride having higher hydrogen barrier properties.

[0382] In addition, in the case where the capacitor 400 is provided in the storage device, the capacitor 400 is preferably provided in a region where the insulator 430 is not provided. FIG. 15AIn the structure shown, the transistor 200a and the transistor 200b are provided in the same layer, but the present application is not limited to this structure. For example, as shown in FIG. 12B, a structure in which a layer 401a including the transistor 200a is provided to be stacked over a layer 401b including the transistor 200b can be employed. Further, the layer 401a and the layer 401b have the same structure as that of the layer 401 shown in FIG. 12A. FIG. 15B In the structure shown, the transistor 200a and the transistor 200b are provided in the same layer, but the present application is not limited to this structure. For example, as shown in FIG. 12B, a structure in which a layer 401a including the transistor 200a is provided to be stacked over a layer 401b including the transistor 200b can be employed. Further, the layer 401a and the layer 401b have the same structure as that of the layer 401 shown in FIG. 12A. FIG. 15A The layers of the insulators 215 to 285 shown in FIG. 12A have the same structure as that of the layer 401 shown in FIG. 12A.

[0383] As shown in FIG. 12B, the insulator 282 to the insulator 285 of the layer 401b and the insulator 215 to the insulator 285 of the layer 401a can be formed in openings. FIG. 15B As shown in FIG. 12B, the insulator 282 to the insulator 285 of the layer 401b and the insulator 215 to the insulator 285 of the layer 401a can be formed in openings.

[0384] Here, the transistor 200b is preferably provided to overlap at least one of the transistor 200a and the capacitor 400. For example, the oxide semiconductor 230 of the transistor 200b is preferably provided to overlap at least one of the oxide semiconductor 230 of the transistor 200a and the conductor 410 of the capacitor 400. With this structure, the area occupied by the memory cell can be reduced.

[0385] <Materials for a semiconductor device>

[0386] Hereinafter, a material for a semiconductor device will be described. Note that each layer included in a semiconductor device can have a single-layer structure or a stacked-layer structure.

[0387] <<Substrate>>

[0388] As a substrate for forming a transistor, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate can be used. As an insulator substrate, for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (a yttria-stabilized zirconia substrate or the like), and a resin substrate can be given. Further, as a semiconductor substrate, for example, a semiconductor substrate using silicon or germanium as a material, and a compound semiconductor substrate composed of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide can be given. Further, a semiconductor substrate having an insulator region in the above semiconductor substrate, such as an SOI (Silicon On Insulator) substrate or the like can be given. As a conductor substrate, for example, a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate can be given. Further, as a substrate, for example, a substrate containing a metal nitride, a substrate containing a metal oxide, an insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, and a conductor substrate provided with a semiconductor or an insulator can be given. Alternatively, a substrate provided with one or a plurality of elements over these substrates can be used. As an element provided over a substrate, for example, a capacitor, a resistor, a switching element, a light emitting element, and a memory element can be given.

[0389] <insulator>

[0390] As an insulator, for example, an oxide, a nitride, an oxynitride, an oxynitride, a metal oxide, a metal oxynitride, and a metal oxynitride having insulating properties can be given.

[0391] For example, when miniaturization and high integration of a transistor are performed, a problem such as a leakage current occurs due to thinning of a gate insulator. By using a high-k material as an insulator used for a gate insulator, low voltage during operation of a transistor can be realized while the physical thickness is maintained. On the other hand, by using a material with a low relative dielectric constant as an insulator used for an interlayer film, a parasitic capacitance generated between wirings can be reduced. Thus, a material can be selected in accordance with a function of an insulator.

[0392] As an insulator with a high relative dielectric constant, for example, gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, or a nitride containing silicon and hafnium can be given.

[0393] As an insulator with a low relative dielectric constant, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having a void, and a resin can be given.

[0394] Further, by using an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen around a transistor using a metal oxide, the electric characteristics of the transistor can be stabilized. As the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, a single layer or a stack of an insulator containing one or more of boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum can be used. Specifically, as the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and a metal nitride such as aluminum nitride, silicon nitride oxide, and silicon nitride can be given.

[0395] Further, the insulator used as the gate insulator is preferably an insulator having a region containing oxygen which is separated by heating. For example, by employing a structure in which silicon oxide or silicon oxynitride having a region containing oxygen which is separated by heating is in contact with the oxide semiconductor 230, oxygen vacancies contained in the oxide semiconductor 230 can be filled.

[0396] <Conductive Member>

[0397] As the conductive member, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing the above metal element, or an alloy in which the above metal elements are combined, or the like is preferably used. As the conductive member, for example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel can be given. Further, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel are a conductive material which is not easily oxidized or a material which maintains conductivity even when oxygen is absorbed, and thus are preferable. Further, a semiconductor having high conductivity typified by polysilicon containing an impurity element such as phosphorus or a silicide such as nickel silicide can be used.

[0398] In the case of using a conductive member having a stacked structure, for example, a stacked structure in which a material containing the above metal element and a conductive material containing oxygen are combined, a stacked structure in which a material containing the above metal element and a conductive material containing nitrogen are combined, or a stacked structure in which a material containing the above metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined can be employed.

[0399] Further, in the case where the oxide is used for the channel formation region of the transistor, a stacked-layer structure in which a material containing the above metal element and a conductive material containing oxygen are combined is preferably employed as the conductor used for the gate electrode. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0400] In particular, as the conductor used for the gate electrode, a conductive material containing a metal element contained in the metal oxide formed in the channel and oxygen is preferably used. Further, a conductive material containing the above metal element and nitrogen can be used. For example, a conductive material containing nitrogen such as titanium nitride, tantalum nitride, or the like can be used. Further, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide to which silicon is added can be used. Further, indium gallium zinc oxide containing nitrogen can be used. By using the above material, hydrogen contained in the metal oxide formed in the channel can be trapped. Alternatively, hydrogen mixed from the outside of an insulator or the like can be trapped.

[0401] Example of a method for manufacturing a semiconductor device

[0402] Example of a method for manufacturing a semiconductor device FIG. 16A to FIG. 25D An example of a method for manufacturing a semiconductor device of one embodiment of the present application will be described below. Here, a case where a semiconductor device illustrated in FIG. 1A is manufactured will be described. FIG. 1A to FIG. 1D An example of a method for manufacturing a semiconductor device

[0403] A in each of the drawings is a plan view. B in each of the drawings is a cross-sectional view of a portion along a dot-dash line Al-A2 of A in each of the drawings, and is a cross-sectional view in the channel width direction of the transistor 200. Further, C in each of the drawings is a cross-sectional view of a portion along a dot-dash line A3-A4 of A in each of the drawings, and is a cross-sectional view in the channel width direction of the transistor 200. D in each of the drawings is a cross-sectional view of a portion along a dot-dash line A5-A6 of A in each of the drawings, and is a cross-sectional view in the channel length direction of the transistor 200. Note that part of the components is omitted from the plan view of A in each of the drawings for clarity.

[0404] Hereinafter, an insulating material used for forming an insulator, a conductive material used for forming a conductor, or a semiconductor material used for forming a semiconductor can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.

[0405] As the sputtering method, there are an RF sputtering method in which a high-frequency power is used for a sputtering power source, a DC sputtering method in which a direct-current power source is used, and a pulse DC sputtering method in which a voltage applied to an electrode is changed in a pulse manner. The RF sputtering method is mainly used when an insulating film is deposited, and the DC sputtering method is mainly used when a metal conductive film is deposited. Further, the pulse DC sputtering method is mainly used when a compound such as an oxide, a nitride, or a carbide is deposited by a reactive sputtering method.

[0406] Note that the CVD method can be classified into a plasma CVD (PECVD) method using plasma, a thermal CVD (TCVD) method using heat, a photo CVD method using light, and the like. Further, the CVD method can be classified into a metal CVD (MCVD) method, a metal organic CVD (MOCVD) method, and the like, depending on a source gas used.

[0407] By using the plasma CVD method, a high-quality film can be obtained at a low temperature. Further, since plasma is not used in the thermal CVD method, plasma damage to a processed object can be reduced. For example, a wiring, an electrode, a device (a transistor, a capacitor, or the like), and the like included in a semiconductor device sometimes generate charge up due to reception of electric charges from plasma. At this time, the wiring, the electrode, the device, and the like included in the semiconductor device are sometimes destroyed by the accumulated electric charges. On the other hand, since the above plasma damage does not occur in the thermal CVD method which does not use plasma, the yield of the semiconductor device can be improved. Further, in the thermal CVD method, plasma damage at the time of deposition does not occur, so that a film with few defects can be obtained.

[0408] As the ALD method, there are a thermal ALD method in which only thermal energy is used to cause a precursor and a reactant to react, a PEALD method in which a reactant is excited by plasma is used, and the like.

[0409] The CVD method and the ALD method are different from the sputtering method in which particles released from a target or the like are deposited. Thus, the CVD method and the ALD method are deposition methods which are less affected by the shape of a processed object and have high step coverage. In particular, the ALD method has high step coverage and thickness uniformity, and thus the ALD method is suitable for a case where a surface of an opening portion with a high aspect ratio is covered, or the like. However, the deposition speed of the ALD method is slow, and thus the ALD method is sometimes preferably used in combination with another deposition method such as the CVD method which has a high deposition speed.

[0410] Further, when the CVD method is used, a film of an arbitrary composition can be deposited in accordance with the flow ratio of source gases. For example, when the CVD method is used, a film whose composition continuously changes can be deposited by changing the flow ratio of source gases while deposition is performed. When deposition is performed while the flow ratio of source gases is changed, the deposition time can be shortened as compared with the case where deposition is performed using a plurality of deposition chambers because the time required for transferring or adjusting pressure is not needed. Thus, the productivity of semiconductor devices can be improved in some cases.

[0411] When the ALD method is used, a film of an arbitrary composition can be deposited by simultaneously introducing different kinds of precursors. Alternatively, a film of an arbitrary composition can be deposited by controlling the number of cycles of each precursor when different kinds of precursors are introduced.

[0412] First, a substrate (not shown) is prepared, and an insulator 215 is deposited on the substrate (see FIG. 2A). FIG. 16A to FIG. 16D As described above, the insulator 215 can use the same insulator as the stacked film of any one or more of the insulator 282 and the insulator 283. For example, the insulator 215 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. By using a sputtering method which does not need to use a molecule containing hydrogen as a deposition gas, the hydrogen concentration in the insulator 215 can be reduced, and thus the sputtering method is preferable.

[0413] Next, an insulator 216 is deposited on the insulator 215. The insulator 216 is preferably deposited by a sputtering method. By using a sputtering method which does not need to use a molecule containing hydrogen as a deposition gas, the hydrogen concentration in the insulator 216 can be reduced. Note that the deposition method of the insulator 216 is not limited to a sputtering method, and for example, a CVD method, an MBE method, a PLD method, an ALD method, or the like can be appropriately used. In this embodiment, as the insulator 216, silicon oxide is deposited by a sputtering method.

[0414] The insulator 215 and the insulator 216 are preferably continuously deposited without exposure to the air. For example, a deposition apparatus of a multi-chamber system can be used. Thus, the insulator 215 and the insulator 216 can be deposited with reduced hydrogen in the films, and hydrogen can be less likely to be mixed into the films between deposition steps.

[0415] Here, an opening reaching the insulator 215 is formed in the insulator 216, and a conductor 205 is formed in the opening, whereby a transistor 200 illustrated in FIG. 2B can be formed. FIG. 12A to FIG. 12D As the conductor 205 is formed, the conductive film used for the conductor 205 is deposited so as to fill the opening, and part of the conductive film is removed by CMP treatment, for example.

[0416] Next, an insulator 221 is deposited on the insulator 216 (see FIG. 2C). FIG. 16A to FIG. 16D Thus, the insulator 221 can be formed.

[0417] The insulator 221 can be formed using an insulator having a barrier property against oxygen, hydrogen, and water as described above. The insulator 221 can be formed, for example, by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, as the insulator 221, silicon nitride is formed by a PEALD method.

[0418] Next, an insulator 222 is formed over the insulator 221 (see FIG. 5A). FIG. 16A to FIG. 16D

[0419] As the insulator 222, an insulator containing an oxide of one or both of aluminum and hafnium can be formed. As the insulator containing an oxide of one or both of aluminum and hafnium, for example, an aluminum oxide, a hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used. Alternatively, a hafnium zirconium oxide is preferably used. The insulator containing an oxide of one or both of aluminum and hafnium has a barrier property against oxygen, hydrogen, and water. When the insulator 222 has a barrier property against hydrogen and water, hydrogen and water contained in a structure around the transistor can be prevented from diffusing into the inside of the transistor through the insulator 222, so that generation of an oxygen vacancy in the oxide semiconductor 230 can be inhibited.

[0420] The insulator 222 can be formed, for example, by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, as the insulator 222, hafnium oxide is formed by a thermal ALD method.

[0421] In this embodiment, silicon nitride is formed by a PEALD method as the insulator 221 and hafnium oxide is formed by a thermal ALD method as the insulator 222. In this manner, by using silicon nitride having a function of inhibiting diffusion of hydrogen as the insulator 221, diffusion of hydrogen from a lower layer of the transistor 200 can be inhibited. Furthermore, by using hafnium oxide having a function of trapping or fixing hydrogen as the insulator 222, hydrogen contained in the oxide semiconductor 230 can be trapped or fixed using the insulator 222. Thus, the hydrogen concentration in and around the oxide semiconductor 230 can be reduced.

[0422] Next, an insulating film is formed over the insulator 222 and etched to form an insulator 223 (see FIG. 5B). FIG. 16A to FIG. 16D The insulator 223 is used as a template for forming the oxide semiconductor 230. As the insulator 223, an insulator which can be used for the insulator 216 can be used, for example.

[0423] The insulator 223 can be formed, for example, by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, as the insulator 223, silicon oxide is formed by a sputtering method.

[0424] ​The insulator 223 can be processed into an island shape by photolithography. This processing can be performed by dry etching or wet etching. The processing by dry etching is suitable for fine processing. In this embodiment, as shown in FIG. 1A, two insulators 223 are formed in a columnar shape in the A1-A2 direction. FIG. 16A to FIG. 16C

[0425] As shown in FIG. 1A, the side surface of the insulator 223 can be perpendicular or substantially perpendicular to the top surface of the insulator 222. By employing such a structure, miniaturization and high integration can be achieved when a plurality of transistors are provided. FIG. 16B FIG. 16C As shown in FIG. 1A, the side surface of the insulator 223 can be perpendicular or substantially perpendicular to the top surface of the insulator 222. By employing such a structure, miniaturization and high integration can be achieved when a plurality of transistors are provided.

[0426] Next, an oxide semiconductor film 230f which will be the oxide semiconductor 230 is deposited so as to cover the insulator 223 (see FIG. 1A). FIG. 17A to FIG. 17D The oxide semiconductor film 230f is a metal oxide film which becomes the oxide semiconductor 230 through a later step, and the above metal oxide film can be used. The oxide semiconductor film 230f can be deposited by sputtering, CVD, MBE, PLD, or ALD.

[0427] Since the oxide semiconductor film 230f is deposited along the insulator 223, it is preferable that the oxide semiconductor film 230f have high coverage. Thus, the oxide semiconductor film 230f is preferably deposited by ALD or the like which has good coverage. In addition, the oxide semiconductor 230 preferably has a high aspect ratio, and thus the thickness of the oxide semiconductor film 230f is preferably small. Therefore, it is preferable that the oxide semiconductor film 230f be deposited by ALD which can adjust the thickness to be small. By thus depositing the oxide semiconductor film 230f, the oxide semiconductor film 230f is formed so as to be in contact with the top surface and the side surface of the insulator 223.

[0428] Here, the same method as the deposition method of the oxide semiconductor 30 described above is preferably used when the oxide semiconductor film 230f is deposited.

[0429] For example, as shown in FIG. 1A, the side surface of the insulator 223 can be perpendicular or substantially perpendicular to the top surface of the insulator 222. By employing such a structure, miniaturization and high integration can be achieved when a plurality of transistors are provided. FIG. 2B ​​In the case where the oxide semiconductor 230 has a three-layer structure of the oxide semiconductor 230a to the oxide semiconductor 230c, the film to be the oxide semiconductor 230a and the oxide semiconductor 230c can be deposited by the ALD method and the film to be the oxide semiconductor 230b can be deposited by the sputtering method, as illustrated in FIG. 8. Specifically, the film to be the oxide semiconductor 230a can be deposited so as to have a composition of In:Zn = 2: 1 [atom ratio] or its neighborhood. Alternatively, indium oxide can be used as the film to be the oxide semiconductor 230a. Further, the film to be the oxide semiconductor 230b can be deposited using an oxide target having a composition of In:Sn:Zn = 4:0.1:1 [atom ratio] or its neighborhood. Further, the film to be the oxide semiconductor 230c can be deposited so as to have a composition of In:Zn = 2: 1 [atom ratio] or its neighborhood. Alternatively, indium oxide can be used as the film to be the oxide semiconductor 230c.

[0430] Next, heat treatment is preferably performed. The heat treatment is preferably performed at a temperature at which the oxide semiconductor film 230f is not crystallized. The heat treatment of the oxide semiconductor film 230f can be performed by the same method as the heat treatment of the oxide semiconductor 230.

[0431] For example, as the heat treatment, treatment can be performed at 450 °C for 1 hour in a nitrogen atmosphere with a flow ratio of nitrogen gas to oxygen gas of 4: 1.

[0432] The oxide semiconductor 230 is deposited by the above method and heat treatment is performed, whereby the oxide semiconductor 230 can be made into an Axial Growth CAAC. Thus, the on-state current, the S value, the field-effect mobility, the frequency characteristics, and the like of the transistor 200 can be improved, and a semiconductor device with good electrical characteristics can be provided. Further, a semiconductor device with high reliability can be provided.

[0433] Note that the heat treatment is preferably performed in a nitrogen atmosphere or an atmosphere of an inert gas or an atmosphere containing an oxidizing gas at 10 ppm or more, 1 % or more, or 10 % or more. The heat treatment can be performed in a reduced-pressure state. Alternatively, the heat treatment can be performed in a nitrogen atmosphere or an atmosphere of an inert gas, and then heat treatment can be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1 % or more, or 10 % or more in order to fill the desorbed oxygen.

[0434] Further, the gas used in the above heat treatment is preferably high in purity. For example, the amount of moisture contained in the gas used in the above heat treatment is preferably 1 ppb or lower, more preferably 0.1 ppb or lower, and further preferably 0.05 ppb or lower. By performing heat treatment using a gas high in purity, moisture or the like can be prevented from being absorbed by the oxide semiconductor film 230f and the like as much as possible. Note that the heat treatment before and after this process is performed using a gas high in purity as well.

[0435] In addition, by the above heat treatment with the use of an oxygen-containing gas, impurities such as carbon, water, and hydrogen in the oxide semiconductor film 230f can be reduced. By reducing impurities in the film as described above, the crystallinity of the oxide semiconductor film 230f is improved, and a dense structure with higher density can be achieved. Thus, the crystal region in the oxide semiconductor film 230f can be increased, and the in-plane unevenness of the crystal region in the oxide semiconductor film 230f can be reduced. Thus, the in-plane unevenness of the electrical characteristics of the transistor can be reduced.

[0436] In addition, by performing heat treatment, oxygen vacancies in the oxide semiconductor film 230f can be reduced by supplying oxygen to the oxide semiconductor film 230f. Thus, the reliability of the transistor 200 can be improved.

[0437] Further, by performing heat treatment, hydrogen in the oxide semiconductor film 230f is moved to and absorbed by the insulator 222. That is, hydrogen in the oxide semiconductor film 230f is diffused to the insulator 222. Thus, the hydrogen concentration in the oxide semiconductor film 230f is reduced, although the hydrogen concentration in the insulator 222 is increased. In addition, when the insulator 221 is provided in contact with the bottom surface of the insulator 222, entry of moisture or impurities such as hydrogen from the lower side of the insulator 221 into the insulator 222 due to the heat treatment can be prevented.

[0438] In particular, the oxide semiconductor film 230f (the oxide semiconductor 230 in later stages) is used as a channel formation region of the transistor 200. The transistor 200 formed using the oxide semiconductor film 230f whose hydrogen concentration is reduced has good reliability, and is thus preferable.

[0439] Next, a part of the oxide semiconductor film 230f is removed by anisotropic etching, and the insulator 223 is also removed (see FIG. 5B). FIG. 18A to FIG. 18D A part of the oxide semiconductor film 230f parallel to the substrate surface is mainly etched, whereby a side wall-shaped oxide semiconductor 230 in contact with the side surface of the insulator 223 is formed. Here, FIG. 18B and FIG. 18CThe diagram shows a structure with curved shapes on both sides of the upper portion of the oxide semiconductor 230, on the A1 side (A3 side) and the A2 side (A4 side). However, this is not a limitation; sometimes a structure with a curved shape is only present on the side of the oxide semiconductor 230 that does not contact the insulator 223. Note that when a portion of the oxide semiconductor film 230f is removed by anisotropic etching, an insulator serving as a hard mask may also be provided on that portion. Silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, etc., can be suitably used as this insulating film.

[0440] Anisotropic etching can form an oxide semiconductor 230 with a high aspect ratio. By using the oxide semiconductor 230, the channel width of the transistor 200 can be increased without increasing the area occupied, thereby improving the on-state current and frequency characteristics of the transistor 200. In addition, since the contact area between the oxide semiconductor 230 and the conductors 242a and 242b can be increased without increasing the area occupied, the on-state current and frequency characteristics of the transistor 200 can be improved.

[0441] An oxide semiconductor film 230f is deposited in a manner that makes contact with the sides of multiple insulators 223, and the oxide semiconductor 230f is formed as a sidewall, thereby... FIG. 18A to FIG. 18C As shown, multiple oxide semiconductors 230 can be formed simultaneously. By forming multiple oxide semiconductors 230 in this way, the distance between each oxide semiconductor 230 can be set according to the size and shape of the insulator 223. Therefore, by reducing the distance between each oxide semiconductor 230 and reducing the occupied area of ​​the transistor 200, high integration of the semiconductor device can be achieved.

[0442] In addition, such as FIG. 18A As shown, the top surface shape of the oxide semiconductor 230 is a circumferential shape with two ends aligned. The oxide semiconductor 230 can be described as having an opening in the central portion. Furthermore, as described above, when the oxide semiconductor 230 has a three-layer structure of oxide semiconductors 230a to 230c, as a circumferential oxide semiconductor 230, oxide semiconductors 230a, 230b, and 230c are sequentially formed around the region where the insulator 223 is formed. Thus, as... FIG. 4A As shown, when viewed in cross-section from the channel width direction, oxide semiconductors 230c, 230b, 230a, 230b, and 230c are arranged symmetrically in sequence.

[0443] Note that the structure in which two peripheral oxide semiconductors 230 are provided is described above, but the present application is not limited to this. For example, a structure in which one or more than three peripheral oxide semiconductors 230 are provided can be employed. Further, the peripheral oxide semiconductors 230 can be bonded to form an oxide semiconductor 230 having a shape including a plurality of openings. For example, as illustrated in FIG. 16B, an oxide semiconductor 230 having a shape in which three openings are arranged in the A1-A2 direction in plan view can be formed. In this case, in the process illustrated in FIG. 16, three insulators 223 can be formed adjacent to each other at a short distance. Further, for example, as illustrated in FIG. 16C, an oxide semiconductor 230 having a lattice shape in plan view can be formed. In this case, in the process illustrated in FIG. 16, a trench having a lattice shape can be formed in the insulator 223. FIG. 5A FIG. 5B

[0444] In addition, in the case where the oxide semiconductor 230 has a peripheral shape in plan view and a part of the oxide semiconductor 230 is removed by etching treatment, the oxide semiconductor 230 can have a shape in which a part of the oxide semiconductor 230 is removed in plan view. For example, in the structure illustrated in FIG. 16D, a part of the oxide semiconductor 230 can be removed to have a rectangular shape extending in the A5-A6 direction in plan view. FIG. 18A FIG. 18A

[0445] The anisotropic etching of the oxide semiconductor film 230f is preferably performed using a dry etching method.

[0446] As the etching gas used for the dry etching treatment, an etching gas containing a halogen can be used, and specifically, an etching gas containing one or more of fluorine, chlorine, and bromine can be used. As the etching gas, one of C4F6 gas, C5F6 gas, C4F8 gas, CF4 gas, SF6 gas, CHF3 gas, CH2F2 gas, Cl2 gas, BCl3 gas, SiCl4 gas, and BBr3 gas, or a gas in which two or more of the above gases are mixed can be used, for example. In addition, an oxygen gas, a carbon oxide gas, a nitrogen gas, a helium gas, an argon gas, a hydrogen gas, or a hydrocarbon gas, or the like can be appropriately added to the above etching gas. In addition, depending on the object of the dry etching treatment, a gas containing a hydrocarbon gas or a hydrogen gas without containing a halogen gas can be used as the etching gas. As the hydrocarbon used for the etching gas, one or more of methane (CH4), ethane (C2H6), propane (C3H8), butane (C4H 10

[0447] ​​​​​As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus including parallel-plate electrodes can be used. The capacitively coupled plasma etching apparatus including the parallel-plate electrodes can also employ a structure in which a high-frequency voltage is applied to one of the parallel-plate electrodes. Alternatively, a structure in which the same high-frequency voltage is applied to each of the parallel-plate electrodes can be employed. Alternatively, a structure in which a plurality of different high-frequency voltages are applied to the parallel-plate electrodes can be employed. Such a CCP etching apparatus is referred to as a dual frequency capacitively coupled plasma (DF-CCP) etching apparatus. The DF-CCP etching apparatus can also employ a structure in which different high-frequency voltages are applied to each of the parallel-plate electrodes. Alternatively, a structure in which a plurality of different high-frequency voltages are applied to one of the parallel-plate electrodes can be employed. Alternatively, a dry etching apparatus with a high-density plasma source can be used. For example, as the dry etching apparatus with the high-density plasma source, an inductively coupled plasma (ICP) etching apparatus or the like can be used. The etching apparatus can be appropriately set depending on an object to be etched. Note that in the above-described dry etching apparatus, self-bias voltage is generated by application of a high-frequency voltage to an electrode on the substrate side, and thus reactive ion etching can be performed. In the reactive ion etching, etching is performed by accelerating ions in plasma to collide with a processed object, and thus anisotropic etching treatment with high anisotropy can be performed.

[0448] In addition, the insulator 223 can be removed by a dry etching method or a wet etching method. For example, the insulator 223 can be removed by a wet etching method.

[0449] In addition, by using a hard-etchable material such as hafnium oxide as the insulator 222, the insulator 222 can be used as an etching stopper layer at the time of etching treatment of the oxide semiconductor film 230f and the insulator 223.

[0450] In addition, FIGS. 17 and 18 employ a structure in which two insulators 223 and two oxide semiconductors 230 are provided for the transistor 200, but the present application is not limited thereto. As FIG. 26A indicated, a structure in which two insulators 223 and two oxide semiconductors 230 are provided for each of two transistors (the transistor 200_1 and the transistor 200_2) can be employed. Further, as FIG. 26BAs shown, a structure in which an insulator 223 having a different width is provided and three fin-shaped oxide semiconductors 230 are provided for each of the transistor 200_1 and the transistor 200_2 when viewed in the cross-sectional view in the A1-A2 direction can also be employed. In this case, the top surface shape is made to have a linear shape extending in the A5-A6 direction by removing a portion of the oxide semiconductor 230, and thus the oxide semiconductor 230 of the transistor 200_1 and the oxide semiconductor 230 of the transistor 200_2 are separated.

[0451] Note that FIG. 18 illustrates a structure in which the insulator 223 is removed, but the present application is not limited to this. For example, as shown in FIG. 19, a structure in which a portion of the insulator 223 remains can also be employed. In this case, a structure in which the insulator 223 remains in a region where the conductor 240 is provided in a later step is employed. For example, when the insulator 223 is removed in the above step, the insulator 223 in the region where the conductor 240 is provided can be left by providing a mask using photolithography. As shown in FIG. 19, the insulator 223 is formed so as to be embedded in the inside of the peripheral oxide semiconductor 230. As shown in FIG. 20, the conductor 242a (the conductor 242b) and the conductor 240a (the conductor 240b) are formed so as to cover the oxide semiconductor 230 and the insulator 223 in the transistor 200. In this case, the conductor 242a (the conductor 242b) is in contact with the side surface and the top surface of the oxide semiconductor 230 and the top surface of the insulator 223. FIG. 27A FIG. 27A FIG. 27B

[0452] Next, a conductive film 242f is deposited over the insulator 222 and the oxide semiconductor 230 (see FIG. 21). FIG. 19A to FIG. 19D As the conductive film 242f, a conductor corresponding to the above-described conductor 242a and the conductor 242b can be used.

[0453] The conductive film 242f can be deposited by sputtering, CVD, MBE, PLD, or ALD, for example. As the conductive film 242f, tantalum nitride can be deposited by sputtering, for example. Alternatively, as shown in FIG. 22, a stacked structure of tantalum nitride and tungsten over the tantalum nitride can also be employed. The conductive film 242f is deposited so as to cover the oxide semiconductor 230, which makes it possible to increase the contact area of the oxide semiconductor 230 with the conductor 242a and the conductor 242b without increasing the occupied area. This makes it possible to improve the on-state current and the frequency characteristics of the transistor 200. FIG. 3B

[0454] Next, the conductive film 242f is processed into an island shape by photolithography, which forms a conductor 242A (see FIG. 23). FIG. 20A to FIG. 20D ​​​​). At this time, the conductive body 242A is preferably formed so as to cover the oxide semiconductor 230. Note that the insulator 222 is exposed in a region where the conductive body 242A is not overlapped.

[0455] The above processing can be performed by a dry etching method or a wet etching method. The processing by the dry etching method is suitable for fine processing. The conditions and the dry etching apparatus for the dry etching method can be as described above.

[0456] The side surface of the conductive body 242A can also be perpendicular or substantially perpendicular to the top surface of the insulator 222. With this structure, miniaturization and high-density integration can be achieved when a plurality of transistors are provided.

[0457] However, the side surface of the oxide semiconductor 230 and the conductive body 242A is not limited to the above structure and can have a tapered shape. The taper angle of the side surface of the oxide semiconductor 230 and the conductive body 242A can be, for example, 60° or more and less than 90°. With such a tapered shape of the side surface, the coverage of the insulator 275 and the like is improved in a later step, and defects such as voids can be reduced.

[0458] Note that in photolithography, first, a resist is exposed through a mask. Next, a developing solution is used to remove or leave the exposed region, and a resist mask is formed. Next, etching treatment is performed through the resist mask to process a conductive body, a semiconductor, or an insulator into a desired shape. For example, a resist can be exposed using a KrF excimer laser, an ArF excimer laser, EUV (Extreme Ultraviolet) light, or the like to form a resist mask. In addition, a liquid immersion technique in which exposure is performed in a state where a liquid (e.g., water) is filled between a substrate and a projection lens can be used. Further, an electron beam or an ion beam can be used instead of the above light. Further, in the case of using an electron beam or an ion beam, a mask can not be used.

[0459] In addition, the resist mask which is not needed after processing can be removed by performing dry etching treatment such as ashing using oxygen plasma (hereinafter, sometimes referred to as oxygen plasma treatment), performing wet etching treatment, performing wet etching treatment after dry etching treatment, or performing dry etching treatment after wet etching treatment.

[0460] Further, a hard mask made of an insulator or a conductor can be used under the resist mask. When the hard mask is used, an insulating film or a conductive film that becomes a hard mask material can be formed on the conductive film 242f and a resist mask can be formed thereon, and then the hard mask material can be etched to form a hard mask having a desired shape. The etching of the conductive film 242f or the like can be performed after the resist mask is removed or can be performed without removing the resist mask. In the latter case, the resist mask is sometimes removed when the etching is performed. The hard mask can be removed by etching after the etching of the conductive film 242f or the like. Alternatively, the hard mask does not necessarily need to be removed in a case where the hard mask material does not affect a subsequent process or can be used in the subsequent process.

[0461] In addition, a SOC (Spin On Carbon) film or a SOG (Spin On Glass) film can be deposited between the object to be processed and the resist mask. By using the SOC film or the SOG film as a mask, the durability of the mask pattern can be improved. For example, a SOC film, a SOG film, and a resist mask can be sequentially deposited on the object to be processed to perform photolithography.

[0462] Next, an insulator 275 is deposited so as to cover the conductor 242A, and an insulator 280 is deposited on the insulator 275 (see FIG. 6B). FIG. 21A to FIG. 21D As the insulator 275 and the insulator 280, the above-described insulator can be used.

[0463] Here, the insulator 275 is preferably in contact with the top surface of the insulator 222.

[0464] As the insulator 280, the insulator is preferably formed by performing CMP processing on an insulating film that becomes the insulator 280 when the insulating film is formed, and the top surface of the insulator is formed to be flat. Further, silicon nitride can be deposited on the insulator 280 by, for example, a sputtering method, and the silicon nitride is subjected to CMP processing until the insulator 280 is reached.

[0465] The insulator 275 and the insulator 280 can each be deposited by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0466] The insulator 275 is preferably an insulator that has a function of suppressing the permeation of oxygen. For example, as the insulator 275, silicon nitride is preferably deposited by a PEALD method. Further, as the insulator 275, aluminum oxide is preferably deposited by a sputtering method, and silicon nitride is deposited thereon by a PEALD method. When the insulator 275 has the above-described structure, the improvement of the function of suppressing the diffusion of impurities such as water, hydrogen, and oxygen can be achieved.

[0467] Thus, the oxide semiconductor 230 and the conductor 242A can be covered by an insulator 275 that has the function of suppressing oxygen diffusion. As a result, oxygen can be prevented from diffusing directly from the insulator 280 and the like into the oxide semiconductor 230 and the conductor 242A in subsequent processes.

[0468] Furthermore, silicon oxide is preferably deposited using sputtering as the insulator 280. By depositing the insulating film that will become the insulator 280 using sputtering under an oxygen-containing atmosphere, an insulator 280 containing excess oxygen can be formed. By using a sputtering method that does not require the use of hydrogen-containing molecules as the deposition gas, the hydrogen concentration in the insulator 280 can be reduced. In addition, a heat treatment can be performed before depositing the insulating film. This heat treatment can also be performed under reduced pressure, and the insulating film can be deposited continuously without exposure to the atmosphere. By performing this treatment, moisture and hydrogen adsorbed on the surface of the insulator 275 can be removed, and the moisture concentration and hydrogen concentration in the oxide semiconductor 230 can be reduced. The heat treatment can be performed under the conditions described above.

[0469] Next, the conductor 242A, insulator 275, and insulator 280 are fabricated using photolithography to form openings reaching the oxide semiconductor 230 and insulator 222 (see reference). FIG. 22A to FIG. 22D Here, conductor 242A is divided to form conductor 242a and conductor 242b. The openings are formed in the region overlapping with the oxide semiconductor 230.

[0470] The above-mentioned methods can be appropriately used in photolithography. In order to process the opening of the insulator 280 into a fine size, it is preferable to use photolithography using short wavelength light such as EUV light or electron beams.

[0471] The above processing is preferably performed using dry etching. Dry etching allows for anisotropic etching, making it suitable for creating openings with high aspect ratios. Note that the conditions and apparatus for dry etching can be found in the description above.

[0472] In addition, in the formation FIG. 3C In the structure shown, it is preferable to perform an etching process to form conductors 242a1 and 242b1 after forming conductors 242a2 and 242b2. Furthermore, using the above structure allows for the simultaneous manufacturing of… FIG. 13A and FIG. 13BThe transistor 200 and the capacitor 460 are formed. At this time, when the conductive body 242al and the conductive body 242bl are formed by etching the conductive body 242A of the transistor 200, the capacitor 460 is not subjected to the etching treatment, whereby the structure in which the oxide semiconductor 452 is covered with the conductive body 242bl can be formed. Thus, the capacitor 460 including the conductive body 242bl, the insulator 454, and the conductive body 456 can be manufactured in parallel with the transistor 200.

[0473] In addition, after the conductive body 242A is processed, ashing treatment with oxygen plasma can be performed. By performing such oxygen plasma treatment, impurities which are generated in the etching treatment described above and diffuse into the oxide semiconductor 230 and the like can be removed. As the impurities, there are impurities which are components of the object to be processed due to the etching treatment described above and impurities which are components of a gas or the like used in the etching. For example, there are chlorine, fluorine, tantalum, silicon, hafnium, and the like. In particular, when chlorine gas is used in the processing of the conductive body 242A, the oxide semiconductor 230 is exposed to an atmosphere containing chlorine gas, and thus it is preferable to remove chlorine attached to the oxide semiconductor 230. By removing the impurities attached to the oxide semiconductor 230, the electrical characteristics and reliability of the transistor can be improved.

[0474] In addition, in order to remove impurities and the like attached to the surface of the oxide semiconductor 230 in the etching step described above, washing treatment can be performed. As the washing method, there are wet washing (which can be referred to as wet etching treatment) using a washing liquid or the like, plasma treatment using plasma, washing using heat treatment, and the like, and the washing methods can be combined as appropriate. Note that the groove portion described above is sometimes deeper by the washing treatment.

[0475] The wet washing can be performed using an aqueous solution in which one or more of oxalic acid, phosphoric acid, and hydrofluoric acid is diluted with carbonated water or pure water. Further, the wet washing can be performed using an aqueous solution in which ammonia water is diluted with carbonated water or pure water. Further, the wet washing can be performed using pure water or carbonated water or the like. Alternatively, the above-described aqueous solution, pure water, or carbonated water can be used for ultrasonic washing. Alternatively, the above-described washing methods can be combined as appropriate.

[0476] Note that in this specification and the like, an aqueous solution in which hydrofluoric acid is diluted with pure water is referred to as dilute hydrofluoric acid and an aqueous solution in which ammonia water is diluted with pure water is referred to as dilute ammonia water. Further, the concentration, temperature, and the like of the aqueous solution are adjusted as appropriate depending on the impurities to be removed, the structure of the semiconductor device to be washed, and the like. The ammonia concentration of dilute ammonia water is preferably set to be higher than or equal to 0.01 % and lower than or equal to 5 %, more preferably higher than or equal to 0.1 % and lower than or equal to 0.5 %. Further, the hydrogen fluoride concentration of dilute hydrofluoric acid is preferably set to be higher than or equal to 0.01 ppm and lower than or equal to 100 ppm, more preferably higher than or equal to 0.1 ppm and lower than or equal to 10 ppm.

[0477] Further, as the ultrasonic wave washing, a frequency of 200 kHz or higher is preferably used, and a frequency of 900 kHz or higher is more preferably used. With the use of such a frequency, damage to the oxide semiconductor 230 and the like can be reduced.

[0478] Further, the above-described washing treatment can be performed a plurality of times, and the washing liquid can be changed for each washing treatment. For example, a treatment using dilute hydrofluoric acid or dilute ammonia water can be performed as a first washing treatment, and a treatment using pure water or carbonic acid water can be performed as a second washing treatment.

[0479] As the above-described washing treatment, in this embodiment, wet washing is performed using dilute ammonia water. With this washing treatment, impurities attached to or diffused into the oxide semiconductor 230 can be removed. Further, the crystallinity of the oxide semiconductor 230 can be improved.

[0480] A heat treatment is preferably performed after the above-described etching or after the above-described washing. The temperature of the heat treatment is higher than or equal to 100 °C and lower than or equal to 650 °C, preferably higher than or equal to 250 °C and lower than or equal to 600 °C, more preferably higher than or equal to 300 °C and lower than or equal to 550 °C, still more preferably higher than or equal to 350 °C and lower than or equal to 400 °C. The heat treatment is performed in an atmosphere of a nitrogen gas, an inert gas, or a gas containing an oxidizing gas at 10 ppm or more, 1 % or more, or 10 % or more. The heat treatment is preferably performed in an atmosphere containing oxygen, for example, a treatment is preferably performed at a temperature of 350 °C for one hour in an atmosphere where the flow rate ratio of a nitrogen gas to an oxygen gas is 4: 1. Thus, oxygen is supplied to the oxide semiconductor 230, so that oxygen vacancies can be reduced. Further, by the heat treatment, the crystallinity of the oxide semiconductor 230 can be improved. Furthermore, hydrogen remaining in the oxide semiconductor 230 can be removed as H20 (dehydration) by reacting with the supplied oxygen. Thus, hydrogen remaining in the oxide semiconductor 230 can be prevented from recombining with oxygen vacancies to form V OH. Thus, the electric characteristics of the transistor provided with the oxide semiconductor 230 can be improved, and the reliability can be improved. In addition, the electric characteristics of the plurality of transistors formed over the same substrate can be made uniform. The above heat treatment can be performed under a reduced pressure. Alternatively, the heat treatment can be performed in an oxygen atmosphere, and then the heat treatment can be continuously performed in a nitrogen atmosphere without exposure to the air. The above heat treatment can be used as the heat treatment described in Embodiment 1. Thus, the crystalline region of the oxide semiconductor 230 is sometimes grown by the above heat treatment.

[0481] When the heat treatment is performed in a state where the conductive body 242a and the conductive body 242b are in contact with the oxide semiconductor 230, the sheet resistance of the region of the oxide semiconductor 230 overlapping with the conductive body 242a and the region of the oxide semiconductor 230 overlapping with the conductive body 242b is sometimes reduced. In addition, the carrier concentration is sometimes increased. Thus, the region of the oxide semiconductor 230 overlapping with the conductive body 242a and the region of the oxide semiconductor 230 overlapping with the conductive body 242b can be self-aligned and low-resistance.

[0482] Next, an insulating film 250A which will be the insulator 250 is deposited so as to fill the opening formed in the insulator 280 and the like (see FIG. 2B). FIG. 23A to FIG. 23D Here, the insulating film 250A is in contact with the insulator 280, the insulator 275, the conductive body 242a, the conductive body 242b, the insulator 222, and the oxide semiconductor 230.

[0483] The insulating film 250A can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. For example, the insulating film 250A is preferably deposited by an ALD method. As in the case of the above insulator 250, the insulating film 250A is preferably thin, and it is necessary to reduce the thickness unevenness. In this case, the ALD method is a deposition method in which a precursor and a reactant (e.g., an oxidizing agent or the like) are alternately introduced, and the thickness can be adjusted depending on the number of times of repeating the cycle, so that the thickness can be precisely adjusted. In addition, the insulating film 250A needs to be deposited on the bottom surface and the side surface of the above opening with high coverage. By using the ALD method, an atomic layer can be deposited layer by layer on the bottom surface and the side surface of the above opening, so that the insulating film 250A can be formed with high coverage in the opening.

[0484] In addition, when the insulating film 250A is deposited by the ALD method, ozone (O3), oxygen (O2), water (H2O), or the like can be used as an oxidizing agent. By using ozone (O3), oxygen (O2), or the like which does not contain hydrogen as an oxidizing agent, hydrogen diffused into the oxide semiconductor 230 can be reduced.

[0485] The insulator 250 can have the layered structure illustrated in FIG. 2 and the like. For example, as illustrated in FIG. 2, the insulator 250 can include the insulating film 250A, the insulating film 250B, and the insulating film 250C. FIG. 2AAs shown in FIG. 6A, the insulator 250 can have a stacked structure of the insulator 250a to the insulator 250d. In that case, as the insulator 250a, aluminum oxide can be deposited by a thermal ALD method, as the insulator 250b, silicon oxide can be deposited by a PEALD method, as the insulator 250c, hafnium oxide can be deposited by a thermal ALD method, and as the insulator 250d, silicon nitride can be deposited by a PEALD method.

[0486] Further, it is preferable to perform the microwave treatment in an oxygen-containing atmosphere after deposition of the insulating film 250A or after deposition of any of the insulators included in the insulating film 250A. Note that the microwave treatment refers to treatment using a device including a power source for generating high-density plasma with microwaves, for example. In this specification and the like, a microwave refers to an electromagnetic wave having a frequency of 300 MHz or more and 300 GHz or less.

[0487] The microwave treatment is preferably performed using a microwave treatment device including a power source for generating high-density plasma with microwaves, for example. Here, the frequency of the microwave treatment device is preferably 300 MHz or more and 300 GHz or less, further preferably 2.4 GHz or more and 2.5 GHz or less, for example, 2.45 GHz. By using high-density plasma, high-density oxygen radicals can be generated. Further, the power of the power source of the microwave treatment device for applying microwaves is preferably 1000 W or more and 10000 W or less, further preferably 2000 W or more and 5000 W or less. Furthermore, the microwave treatment device can include a power source for applying RF to the substrate side. Furthermore, by applying RF to the substrate side, oxygen ions generated by the high-density plasma can be efficiently introduced into the oxide semiconductor 230.

[0488] Further, the above microwave treatment is preferably performed under reduced pressure, and the pressure is preferably 10 Pa or more and 1000 Pa or less, further preferably 300 Pa or more and 700 Pa or less. Further, the treatment temperature is preferably 750 °C or lower, further preferably 500 °C or lower, for example, around 250 °C. Further, the heating treatment can be continuously performed without exposure to the outside air after the oxygen plasma treatment. The temperature of the heating treatment is preferably 100 °C or more and 750 °C or less, further preferably 300 °C or more and 500 °C or less, for example.

[0489] Alternatively, for example, the microwave processing described above can be performed using oxygen gas and argon gas. Here, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 0% and less than 100%. Preferably, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 0% and less than 50%. More preferably, the oxygen flow ratio (O2 / (O2+Ar)) is more than 10% and less than 40%. Even more preferably, the oxygen flow ratio (O2 / (O2+Ar)) is more than 10% and less than 30%. In this way, by performing microwave processing in an oxygen-containing atmosphere, the carrier concentration in the oxide semiconductor 230 can be reduced. In addition, by preventing excessive oxygen from being introduced into the processing chamber during microwave processing, an excessive decrease in the carrier concentration in the oxide semiconductor 230 can be prevented.

[0490] By performing microwave treatment in an oxygen-containing atmosphere, oxygen gas can be plasmaized using microwaves or high frequencies such as RF, and this oxygen plasma can then act on the region between conductors 242a and 242b of the oxide semiconductor 230. Through the action of plasma, microwaves, etc., the V in this region can be increased. O H separates into oxygen vacancies and hydrogen, and hydrogen is removed from this region. Here, in the use of FIG. 2A When using the structure shown, an insulating film (e.g., alumina) with the function of trapping or fixing hydrogen is preferably used as the insulator 250a. By adopting the above structure, the insulating film 250A can trap or fix the hydrogen generated by microwave treatment. In this way, the V contained in the channel forming region can be reduced. O H. This can reduce oxygen vacancies and V in the channel formation region. O H reduces carrier concentration. Furthermore, by supplying oxygen free radicals generated in the aforementioned oxygen plasma to the oxygen vacancies formed in the channel formation region, the oxygen vacancies in the channel formation region can be further reduced, thereby reducing carrier concentration.

[0491] The oxygen injected into the channel formation region can be in various forms, including oxygen atoms, oxygen molecules, oxygen ions, and oxygen free radicals (also known as O free radicals, which are atoms, molecules, or ions containing unpaired electrons). The oxygen injected into the channel formation region can be any one or more of the above forms, and oxygen free radicals are particularly preferred. In addition, since the film quality of the insulator 250 can be improved, the reliability of the transistor is enhanced.

[0492] Furthermore, microwave processing can remove impurities such as carbon from the oxide semiconductor 230. Removing carbon impurities from the oxide semiconductor 230 improves its crystallinity. This allows the oxide semiconductor 230 to be formed as CAAC-OS. In particular, when the oxide semiconductor 230 is deposited using the ALD method, carbon from the precursor is sometimes incorporated into the oxide semiconductor 230; therefore, microwave processing is preferred for carbon removal.

[0493] On the other hand, the oxide semiconductor 230 has a region that overlaps with either conductor 242a or conductor 242b. This region can be used as a source region or a drain region. Here, conductor 242a and conductor 242b are preferably used as shielding films to protect against the effects of microwaves, RF, or oxygen plasma during microwave processing in an oxygen-containing atmosphere. Thus, conductor 242a and conductor 242b preferably have the function of shielding electromagnetic waves of 300 MHz or higher and 300 GHz or lower, for example, 2.4 GHz or higher and 2.5 GHz or lower.

[0494] Conductors 242a and 242b shield against high-frequency radiation such as microwaves or RF, and oxygen plasma, so the aforementioned effects do not affect the regions of the oxide semiconductor 230 that overlap with either conductor 242a or conductor 242b. Therefore, Vo does not occur in the source and drain regions during microwave processing. O The decrease in H and the excessive supply of oxygen can prevent the decrease in carrier concentration.

[0495] As described above, oxygen vacancies and V can be selectively removed in the channel formation region of an oxide semiconductor. O H makes the channel formation region i-type or substantially i-type. Furthermore, it can suppress the supply of excessive oxygen to the regions used as source or drain regions, maintaining the conductivity (low resistance region state) before microwave processing. Thus, it can suppress variations in the electrical characteristics of the transistor and suppress non-uniformity of the transistor's electrical characteristics within the substrate surface.

[0496] Furthermore, by modifying the film quality of the insulator 250 through microwave treatment, the diffusion of hydrogen, water, impurities, etc., can be suppressed. This prevents hydrogen, water, impurities, etc., from diffusing through the insulator 250 into the oxide semiconductor 230 and the like due to subsequent processes such as deposition of the conductive film that will become the conductor 260, or post-processing such as heat treatment. Thus, by improving the film quality of the insulator 250, the reliability of the transistor can be improved.

[0497] When the insulator 250 adopts a stacked structure of insulators 250a to 250d, it is preferable to perform microwave treatment after depositing insulator 250b. Alternatively, microwave treatment can be performed again after depositing insulator 250c. Thus, microwave treatment in an oxygen-containing atmosphere can be performed multiple times (at least twice). Furthermore, sometimes the above-described microwave treatment can also be combined with the heat treatment shown in Embodiment 1. Therefore, sometimes the crystalline region of the oxide semiconductor 230 grows through the above-described microwave treatment.

[0498] Alternatively, heat treatment can be performed while maintaining a reduced pressure after microwave treatment. This treatment efficiently removes hydrogen from the oxide semiconductor 230 in the insulating film. Furthermore, the step of performing heat treatment while maintaining a reduced pressure after microwave treatment can be repeated multiple times. Repeated heat treatment further efficiently removes hydrogen from the oxide semiconductor 230 in the insulating film. Note that the heat treatment temperature is preferably 300°C or higher and 500°C or lower. Additionally, the above-described heat treatment can also be performed as shown in Embodiment 1. Thus, sometimes a crystalline region of the oxide semiconductor 230 grows through the above-described heat treatment.

[0499] Next, conductive film 260A, which will become conductor 260a, and conductive film 260B, which will become conductor 260b, are deposited sequentially (see reference). FIG. 24A to FIG. 24D The conductive films 260A and 260B can be deposited, for example, using sputtering, CVD, MBE, PLD, electroplating, or ALD. In this embodiment, titanium nitride is deposited as conductive film 260A using CVD, and tungsten is deposited as conductive film 260B using CVD. Alternatively, conductive films 260A and 260B can be deposited simultaneously with heating the substrate. The heating of the substrate can also be performed as shown in Embodiment 1. Thus, sometimes the crystalline region of the oxide semiconductor 230 grows through the heating of the substrate described above.

[0500] Next, CMP processing is used to polish the insulating film 250A, conductive film 260A, and conductive film 260B until the insulator 280 is exposed. That is, the portions of the insulating film 250A, conductive film 260A, and conductive film 260B exposed from the opening are removed. Thus, the insulator 250 and conductor 260 (conductor 260a and conductor 260b) are formed in the opening (see reference). FIG. 25A to FIG. 25D ).

[0501] Thus, the insulator 250 is disposed in contact with the insulator 280, insulator 275, conductor 242a, conductor 242b, oxide semiconductor 230, and insulator 222 in the aforementioned opening. Furthermore, the conductor 260 is disposed such that it is embedded in the aforementioned opening with the insulator 250 in between. This forms the transistor 200.

[0502] Next, an insulator 282 is formed on the insulator 250, the conductor 260, and the insulator 280 (see reference). FIG. 1A to FIG. 1D The insulator 282 can be deposited, for example, using sputtering, CVD, MBE, PLD, or ALD methods. Sputtering is preferred for depositing the insulator 282. Alternatively, during the deposition of the insulator 282, a first layer can be formed using ALD, and a second layer can be formed thereon using sputtering.

[0503] Furthermore, by depositing insulator 282 in an oxygen-containing atmosphere using sputtering, oxygen can be added to insulator 280 during deposition. This allows insulator 280 to contain excess oxygen. In this case, it is preferable to deposit insulator 282 while heating the substrate. By depositing insulator 282 in this way, an appropriate amount of oxygen can be supplied from insulator 280 through insulator 250 to oxide semiconductor 230. Additionally, by providing insulator 250a within insulator 250, excessive oxygen supply to insulator 250 can be prevented, thus avoiding over-oxidation of conductors 242a and 242b near insulator 250.

[0504] During alumina deposition, an aluminum target is used in an atmosphere containing oxygen gas. The amount of oxygen injected into the insulator 280 can be controlled by the magnitude of the bias power applied to the substrate via sputtering. For example, a lower bias power results in less oxygen injected into the insulator 280, and this oxygen content is easily saturated even when the thickness of the insulator 282 is small. Conversely, a higher bias power results in more oxygen injected into the insulator 280. By reducing the RF power, the amount of oxygen injected into the insulator 280 can be suppressed. Note that when applying substrate bias using an RF power supply, the RF frequency is preferably 10 MHz or higher. Typically, it is 13.56 MHz. The higher the RF frequency, the less damage to the substrate can be caused.

[0505] In addition, by depositing a second layer on the first layer formed by the ALD method using a sputtering method, the upper end of the insulator 250 and the top surface of the conductor 260 can be protected from the impact of ion collisions generated by sputtering deposition.

[0506] Furthermore, a heat treatment can be performed before depositing the insulator 282. This heat treatment can also be performed under reduced pressure, and the insulator 282 can be deposited continuously without exposure to the atmosphere. By performing this treatment, moisture and hydrogen adsorbed on the surface of the insulator 280 can be removed, and the moisture concentration and hydrogen concentration in the insulator 280 can be reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower. In this embodiment, the temperature of the heat treatment is set to 250°C.

[0507] Next, insulator 283 is formed on insulator 282 (see reference). Figures 1A-1D The insulator 283 can be deposited, for example, using sputtering, CVD, MBE, PLD, or ALD methods. Sputtering is preferred for depositing the insulator 283. By using sputtering, which does not require the use of hydrogen-containing molecules as the deposition gas, the hydrogen concentration in the insulator 283 can be reduced. In this embodiment, silicon nitride is deposited as the insulator 283 using sputtering.

[0508] Here, it is preferable to deposit insulators 282 and 283 continuously without exposure to the atmospheric environment. By depositing without exposure to the atmosphere, impurities or moisture from the atmospheric environment can be prevented from adhering to insulators 282 and 283, thus keeping the interface or vicinity of the interface between insulators 282 and 283 clean.

[0509] In this embodiment, silicon nitride is deposited as insulator 283, and aluminum oxide is deposited as insulator 282. Thus, by using silicon nitride, which has the function of suppressing hydrogen diffusion, as insulator 283, hydrogen diffusion from the upper layer of transistor 200 can be suppressed. Furthermore, by using aluminum oxide, which has the function of trapping or fixing hydrogen, as insulator 282, hydrogen in insulator 280 and the like can be trapped or fixed. Therefore, the hydrogen concentration in and around oxide semiconductor 230 can be reduced.

[0510] Next, openings leading to conductor 242a and conductor 242b are formed in insulators 275, 280, 282, and 283 (see reference). Figures 1A-1D When forming this opening, photolithography can be used. However, dry etching is preferably used to process the workpiece when forming this opening. Dry etching allows for anisotropic etching, making it suitable for forming openings with high aspect ratios. For example, reactive ion etching is preferred when performing anisotropic etching. For information on the conditions and apparatus for dry etching, please refer to the previous description. Note that in... Figure 1A In the above view, the opening has a square shape, but is not limited to this. For example, the opening can also have a circular shape, an ellipse or other near-circular shape, a polygonal shape such as a square, or a polygonal shape with arc-shaped corners when viewed from above.

[0511] Next, after forming the opening described above, a heat treatment can be performed. The temperature for the heat treatment can be 100°C or higher and 600°C or lower, preferably 250°C or higher and 550°C or lower, and more preferably 350°C or higher and 450°C or lower. Note that the heat treatment is preferably performed in an atmosphere of nitrogen or an inactive gas. In addition, since the heat treatment is performed with the conductors 242a and 242b exposed, it is preferable to perform the heat treatment in an atmosphere that does not contain oxidizing gases or oxygen gases. For example, it is preferable to perform the heat treatment at 400°C for 1 hour in a nitrogen atmosphere. Alternatively, the heat treatment can be performed under reduced pressure. Through the heat treatment described above, oxygen in the insulator 280 can be supplied to the oxide semiconductor 230 via the insulator 250. This reduces the oxygen vacancies in the channel formation region of the oxide semiconductor 230. Furthermore, the heat treatment described above can also be performed as the heat treatment shown in Embodiment 1. Thus, sometimes the crystalline region of the oxide semiconductor 230 grows through the heat treatment described above.

[0512] Here, since the side of the insulator 280 is exposed in the aforementioned opening, the oxygen in the insulator 280 can diffuse outward through the aforementioned heat treatment, thereby controlling the oxygen content in the insulator 280. On the other hand, since the insulator 280 is provided with oxygen-barrier insulators 282 and 283, oxygen does not diffuse outward from the top surface of the insulator 280. This prevents excessive oxygen from diffusing outward from the insulator 280 and forming oxygen vacancies within the insulator 280. Furthermore, the oxide semiconductor 230, conductors 242a and 242b are covered by the insulator 275. This prevents excessive oxygen from directly diffusing from the insulator 280 to the oxide semiconductor 230, conductors 242a and 242b during the aforementioned heat treatment.

[0513] Therefore, by further adjusting the oxygen content in the insulator 280 appropriately, a suitable amount of oxygen can be supplied to the oxide semiconductor 230. This reduces oxygen vacancies in the oxide semiconductor 230 and prevents excessive oxygen supply to it. Consequently, the electrical characteristics and reliability of the transistor 200 can be improved. Furthermore, the process of exposing the sidewalls of the insulator 280 also serves as the process of forming openings for embedding the conductors 240a and 240b, thus simplifying the semiconductor device manufacturing process.

[0514] Next, an insulating film that will become insulator 241 is deposited, and the insulating film is anisotropically etched to form insulator 241a in the opening reaching conductor 242a, and insulator 241b in the opening reaching conductor 242b (see reference). Figures 1A-1DThe insulating film that will become insulator 241 can be deposited using methods such as sputtering, CVD, MBE, PLD, or ALD. As the insulating film that will become insulator 241, an insulating film with the function of inhibiting oxygen permeation is preferred. For example, silicon nitride is preferably deposited using the PEALD method. Silicon nitride has high hydrogen barrier properties, so it is preferred.

[0515] Furthermore, anisotropic etching of the insulating film that will become insulator 241 can be performed, for example, by dry etching. By providing insulator 241 on the sidewall of the opening, the permeation of oxygen from the outside can be suppressed, and oxidation of the conductors 240a and 240b to be formed subsequently can be prevented. In addition, impurities such as water and hydrogen in the insulator 280 can be prevented from diffusing into conductors 240a and 240b. Note that sometimes, due to this anisotropic etching, a recess is formed on a portion of the top surface of conductors 242a and 242b.

[0516] Next, conductive films that will become conductors 240a and 240b are deposited. The conductive films that will become conductors 240a and 240b preferably employ a multilayer structure comprising a conductor that suppresses the permeation of impurities such as water and hydrogen. For example, it can be a multilayer of tantalum nitride, titanium nitride, tungsten, molybdenum, copper, etc. The conductive films that will become conductors 240a and 240b can be deposited using methods such as sputtering, CVD, MBE, PLD, or ALD.

[0517] Next, by performing CMP processing, a portion of the conductive film that will become conductors 240a and 240b is removed, exposing the top surface of insulator 283. As a result, the conductive film remains only at the opening, thereby forming conductors 240a and 240b with flat top surfaces (see reference). Figures 1A-1D Note that sometimes a portion of the top surface of insulator 283 is removed during this CMP process.

[0518] As described above, by providing a conductor 240a that contacts conductor 242a, conductor 240a, which can be used as one of the source and drain terminals of transistor 200, can be electrically connected to wiring. Furthermore, by providing a conductor 240b that contacts conductor 242b, conductor 240b, which can be used as the other of the source and drain terminals of transistor 200, can be electrically connected to wiring.

[0519] Alternatively, conductive films for wiring or for plugs can be formed on conductors 240a and 240b.

[0520] The semiconductor device shown in Figure 1 can be manufactured through the above-described process.

[0521] This embodiment can be appropriately combined with other embodiments. Furthermore, in this specification, where multiple structural examples are shown in one embodiment, these structural examples can be appropriately combined.

[0522] (Implementation Method 2)

[0523] In this embodiment, a semiconductor device 900 according to one aspect of the present invention is described. The semiconductor device 900 can be used as a storage device.

[0524] Figure 28 This is a block diagram illustrating a structural example of a semiconductor device 900. Figure 28 The semiconductor device 900 shown includes a driving circuit 910 and a memory array 920. The memory array 920 includes one or more memory cells 950. Figure 28 An example of a memory array 920 including multiple memory cells 950 configured in a matrix is ​​shown.

[0525] The storage cell 950 can use the transistor shown in Embodiment 1. By using the aforementioned transistor, the operating speed of the storage device can be improved. Furthermore, miniaturization and high integration of the storage device can be achieved. In addition, the capacity per unit area of ​​the storage device can be increased.

[0526] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and peripheral circuit 915. The peripheral circuit 915 includes peripheral circuit 911, control circuit 912, and voltage generation circuit 928.

[0527] In the semiconductor device 900, circuits, signals, and voltages can be appropriately selected or omitted as needed. Alternatively, other circuits or signals can be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are signals input from the outside, while signal RDA is a signal output to the outside. Signal CLK is the clock signal.

[0528] In addition, signals BW, CE, and GW are control signals. Signal CE is the chip enable signal, signal GW is the global write enable signal, and signal BW is the byte write enable signal. Signal ADDR is the address signal. Signal WDA is for writing data, and signal RDA is for reading data. Signals PON1 and PON2 are power gating control signals. Furthermore, signals PON1 and PON2 can also be generated in the control circuit 912.

[0529] The control circuit 912 is a logic circuit that controls the overall operation of the semiconductor device 900. For example, the control circuit 912 performs logical operations on signals CE, GW, and BW to determine the operating mode of the semiconductor device 900 (e.g., write operation, read operation). Alternatively, the control circuit 912 generates control signals for the peripheral circuit 911 to execute the aforementioned operating mode.

[0530] The voltage generation circuit 928 has the function of generating voltage. The signal WAKE has the function of controlling the input signal CLK to the voltage generation circuit 928. For example, when a signal of level H is applied as the signal WAKE, the signal CLK is input to the voltage generation circuit 928, and the voltage generation circuit 928 generates voltage.

[0531] The peripheral circuit 911 is used to write and read data from the memory cell 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0532] Row decoder 941 and column decoder 942 are used to decode the signal ADDR. Row decoder 941 is used to specify the row to be accessed, and column decoder 942 is used to specify the column to be accessed. Row driver 923 is used to select the row specified by row decoder 941. Column driver 924 has the following functions: writing data to memory cell 950; reading data from memory cell 950; and storing the read data.

[0533] Input circuit 925 has the function of holding signal WDA. The data held in input circuit 925 is output to column driver 924. The output data of input circuit 925 is the data written to memory cell 950 (Din). The data read from memory cell 950 by column driver 924 (Dout) is output to output circuit 926. Output circuit 926 has the function of holding Dout. In addition, output circuit 926 has the function of outputting Dout to the outside of semiconductor device 900. The data output from output circuit 926 is signal RDA.

[0534] PSW931 has a control function to supply V to the external circuit 915. DD The PSW932 has the function of controlling the supply of V to the line driver 923. HM The function of the semiconductor device 900. Here, the high power supply potential of the semiconductor device 900 is V.DD The low power supply potential is GND (ground potential). Additionally, V HM It is a high power supply potential used to make the word line high, which is higher than V. DD The PSW931 is turned on and off using signal PON1, and the PSW932 is turned on and off using signal PON2. Figure 28 In the middle, the peripheral circuit 915 is supplied with V DD The number of power domains can be 1, but it can also be multiple. In this case, a power switch can be set for each power domain.

[0535] Reference Figures 29A-29H This section describes structural examples of other memory cells that can be used in memory cell 950.

[0536] [NOSRAM]

[0537] Figure 29C An example circuit structure of a gain-cell type memory cell with two transistors and one capacitor is shown. Memory cell 953 includes transistor M2, transistor M3, and capacitor CB. In this specification and the like, memory devices that include a gain-cell type memory cell using transistor M2 are sometimes referred to as NOSRAM (Nonvolatile Oxide Semiconductor RAM).

[0538] Transistor M2's first terminal is connected to capacitor CB's first terminal; transistor M2's second terminal is connected to wiring WBL; and transistor M2's gate is connected to wiring WOL. Capacitor CB's second terminal is connected to wiring CAL. Transistor M3's first terminal is connected to wiring RBL; transistor M3's second terminal is connected to wiring SL; and transistor M3's gate is connected to capacitor CB's first terminal.

[0539] Wiring WBL is used as the write bit line, wiring RBL as the read bit line, and wiring WOL as the word line. Wiring CAL is used to apply a predetermined potential to the second terminal of capacitor CB. During data writing, data holding, and data reading, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to wiring CAL.

[0540] Data writing is performed by applying a high-level potential to wiring WOL, which turns on transistor M2 and connects wiring WBL to the first terminal of capacitor CB. Specifically, when transistor M2 is on, a potential corresponding to the information to be recorded is applied to wiring WBL to write that potential to the first terminal of capacitor CB and the gate of transistor M3. Then, a low-level potential is applied to wiring WOL, which turns on transistor M2, thereby maintaining the potential of the first terminal of capacitor CB and the potential of the gate of transistor M3.

[0541] Data is read out by applying a predetermined potential to the wiring SL. Since the current flowing between the source and drain of transistor M3 and the potential of the first terminal of transistor M3 are determined by the potential of the gate and the second terminal of transistor M3, the potential held by the first terminal of capacitor CB (or the gate of transistor M3) can be read by reading the potential of the wiring RBL connected to the first terminal of transistor M3. In other words, the information written to the memory cell can be read from the potential held by the first terminal of capacitor CB (or the gate of transistor M3).

[0542] For example, a structure that combines the wiring WBL and wiring RBL into a single wiring BIL can also be adopted. Figure 29D An example of the circuit structure of the memory cell in this case is shown. In memory cell 954, the wiring WBL and wiring RBL of memory cell 953 are combined into a single wiring BIL, and the second terminal of transistor M2 and the first terminal of transistor M3 are connected to the wiring BIL. That is, memory cell 954 operates by combining the write bit line and the read bit line into a single wiring BIL.

[0543] Figure 29E The memory cell 955 shown is an example where the capacitor CB and wiring CAL of memory cell 953 are omitted. Furthermore, Figure 29F The memory cell 956 shown is an example of omitting the capacitor CB and wiring CAL found in memory cell 954. This structure improves the integration density of the memory cells.

[0544] Furthermore, at least for transistor M2, the OS transistor described in Embodiment 1 is preferably used. For example, transistors M2 and M3, and capacitor CB, which are memory cells 953 and 954, can be used. Figure 13A or Figure 13B The transistors 200, 310, and 460 are shown. In particular, the OS transistors described in Embodiment 1 are preferably used as transistors M2 and M3. For example, transistors M2, M3, and capacitor CB, which are used as memory cells 953 and 954, can be... Figure 15A orFigure 15B Transistor 200a, transistor 200b, and capacitor 400 are shown. By using the OS transistor described in Embodiment 1, the operating speed of the storage device can be improved. Furthermore, the area occupied by the storage cells can be reduced.

[0545] Because the OS transistor has extremely low off-state current, transistor M2 can hold written data for an extended period, thereby reducing the refresh frequency of the memory cells. Furthermore, the memory cell refresh operation can be omitted. Additionally, due to the very low leakage current, multi-valued or analog data can be held in memory cells 953, 954, 955, and 956.

[0546] The memory cells 953, 954, 955, and 956, which use OS transistors as transistor M2, are a type of NOSRAM.

[0547] Si transistors can also be used as transistor M3. Si transistors can improve field-effect mobility and can be p-channel transistors, thus increasing the freedom of circuit design.

[0548] Furthermore, when the OS transistor is used as transistor M3, the memory cell can be constructed from a unipolar circuit.

[0549] also, Figure 29G A gain-cell type memory cell 957 with three transistors and one capacitor is shown. The memory cell 957 includes transistors M4 to M6 and capacitor CC.

[0550] Transistor M4's first terminal is connected to capacitor CC's first terminal; transistor M4's second terminal is connected to wiring BIL; and transistor M4's gate is connected to wiring WOL. Capacitor CC's second terminal is electrically connected to transistor M5's first terminal and wiring GNDL. Transistor M5's second terminal is connected to transistor M6's first terminal; transistor M5's gate is connected to capacitor CC's first terminal. Transistor M6's second terminal is connected to wiring BIL; and transistor M6's gate is connected to wiring RWL.

[0551] The BIL (Bite Line) is used as the bit line, the WOL (Write Word Line) is used as the write word line, and the RWL (Read Word Line) is used as the read word line. The GNDL (Read Word Line) is a low-level supply.

[0552] Data writing is performed by applying a high-level potential to the wiring WOL, which turns on transistor M4 to connect the wiring BIL to the first terminal of capacitor CC. Specifically, when transistor M4 is on, a potential corresponding to the information to be recorded is applied to the wiring BIL to write that potential to the first terminal of capacitor CC and the gate of transistor M5. Then, a low-level potential is applied to the wiring WOL to turn off transistor M4, thereby maintaining the potential of the first terminal of capacitor CC and the potential of the gate of transistor M5.

[0553] Data readout is performed by pre-charging the wiring BIL to a predetermined potential, then making the wiring BIL electrically floating and applying a high-level potential to the wiring RWL. By making the wiring RWL high, transistor M6 becomes conductive, and the wiring BIL and the second terminal of transistor M5 become electrically connected. At this time, the second terminal of transistor M5 is supplied with the potential of the wiring BIL, but the potential of the second terminal of transistor M5 and the potential of the wiring BIL vary depending on the potential held by the first terminal of capacitor CC (or the gate of transistor M5). Here, the potential held by the first terminal of capacitor CC (or the gate of transistor M5) can be read by reading the potential of the wiring BIL. In other words, the information written to the memory cell can be read from the potential held by the first terminal of capacitor CC (or the gate of transistor M5).

[0554] Note that it is preferable to use the OS transistor shown in Embodiment 1 as at least transistor M4. By using the OS transistor shown in Embodiment 1, the area occupied by the memory cell can be reduced.

[0555] Si transistors can also be used as transistors M5 and M6. As mentioned above, the field-effect mobility of Si transistors is sometimes higher than that of OS transistors, depending on factors such as the crystallization state of the silicon used in the semiconductor layer.

[0556] Furthermore, when OS transistors are used as transistors M5 and M6, the memory cell can be constructed from unipolar circuits.

[0557] [DOSRAM]

[0558] Figure 29A An example circuit structure of a DRAM-type memory cell is shown. In this specification, DRAM using OS transistors is referred to as DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). Memory cell 951 includes transistor M1 and capacitor CA.

[0559] Transistor M1 may also include a front gate (sometimes simply referred to as the gate) and a back gate. In this case, the back gate may be connected to a wiring supplied with a constant potential or signal, or it may be connected to the front gate.

[0560] The first terminal of transistor M1 is connected to the first terminal of capacitor CA, the second terminal of transistor M1 is connected to wiring BIL, and the gate of transistor M1 is connected to wiring WOL. The second terminal of capacitor CA is connected to wiring CAL.

[0561] The BIL (Bite Line) wiring is used as the bit line, and the WOL (Word Line) wiring is used as the word line. The CAL (Chip Line) wiring is used to apply a predetermined potential to the second terminal of the capacitor CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to ...

Claims

1. A semiconductor device, comprising: First oxide semiconductor; First and second insulators; as well as First to third conductors, The first oxide semiconductor is disposed on the substrate. The first conductor and the second conductor are disposed on the first oxide semiconductor. The first insulator is disposed on the first conductor and the second conductor and includes an opening overlapping the region between the first conductor and the second conductor. The second insulator is disposed within the opening, overlapping the first oxide semiconductor. The third conductor is disposed on the second insulator within the opening. When viewed in cross-section along the channel width, the height of the first oxide semiconductor is greater than the width of the first oxide semiconductor. Furthermore, the semiconductor device, when viewed from above, has two or more regions where the first oxide semiconductor and the third conductor overlap.

2. The semiconductor device according to claim 1, When viewed from above, the first oxide semiconductor has a circumferential shape with two ends aligned.

3. The semiconductor device according to claim 1, When viewed from above, the side of the opening of the first insulator is aligned or approximately aligned with the side of the first conductor and the side of the second conductor.

4. The semiconductor device according to claim 1, When viewed in cross-section along the channel width, the width of the first oxide semiconductor is greater than 5 nm and less than 50 nm. Furthermore, when viewed in cross-section along the channel width direction, the height of the first oxide semiconductor is more than twice and less than ten times the width of the first oxide semiconductor.

5. A semiconductor device, comprising: First oxide semiconductor; First to third insulators; as well as First to third conductors, The first oxide semiconductor is disposed on the substrate. The first conductor and the second conductor are disposed on the first oxide semiconductor. The first insulator is disposed on the first conductor and the second conductor and includes an opening overlapping the region between the first conductor and the second conductor. The second insulator is disposed within the opening, overlapping the first oxide semiconductor. The third conductor is disposed on the second insulator within the opening. The third insulator is disposed beneath the first oxide semiconductor and overlaps with the first oxide semiconductor when viewed from above. The thickness of the third insulator is greater than the thickness of the second insulator. When viewed in cross-section along the channel width, the height of the first oxide semiconductor is greater than the width of the first oxide semiconductor. Furthermore, the semiconductor device, when viewed from above, has two or more regions where the first oxide semiconductor and the third conductor overlap.

6. The semiconductor device according to claim 5, When viewed from above, the first oxide semiconductor has a circumferential shape with two ends aligned.

7. The semiconductor device according to claim 5, When viewed from above, the side of the opening of the first insulator is aligned or approximately aligned with the side of the first conductor and the side of the second conductor.

8. The semiconductor device according to claim 5, When viewed in cross-section along the channel width, the width of the first oxide semiconductor is greater than 5 nm and less than 50 nm. Furthermore, when viewed in cross-section along the channel width direction, the height of the first oxide semiconductor is more than twice and less than ten times the width of the first oxide semiconductor.

9. The semiconductor device according to claim 5, The bottom surface of the third conductor has a portion located below the bottom surface of the first oxide semiconductor.

10. A semiconductor device, comprising: First and second oxide semiconductors; First to third insulators; as well as First to fourth conductors, The first oxide semiconductor and the second oxide semiconductor are disposed on a substrate. The first conductor is disposed on the first oxide semiconductor. The second conductor is disposed on the first oxide semiconductor and the second oxide semiconductor. The first insulator is disposed on the first conductor and the second conductor and includes a first opening and a second opening. The first opening overlaps the region between the first conductor and the second conductor and reaches the first oxide semiconductor. The second opening overlaps with the second oxide semiconductor and reaches the second conductor. The second insulator is disposed overlapping the first oxide semiconductor within the first opening. The third conductor is disposed on the second insulator within the first opening. The third insulator is disposed overlapping the second conductor within the second opening. The fourth conductor is disposed on the third insulator within the second opening. When viewed in cross-section along the channel width, the height of the first oxide semiconductor is greater than the width of the first oxide semiconductor. Furthermore, the semiconductor device, when viewed from above, has two or more regions where the first oxide semiconductor and the third conductor overlap.

11. The semiconductor device according to claim 10, When viewed in cross-section along the channel width, the height of the second oxide semiconductor is greater than its width. Furthermore, the semiconductor device, when viewed from above, has two or more regions where the second oxide semiconductor and the fourth conductor overlap.

12. The semiconductor device of claim 10, further comprising: The first layer; and The second layer on the first layer, The first layer includes a first transistor containing silicon in the channel formation region. The second layer includes a second transistor and a capacitor. The first transistor is electrically connected to the second transistor and the capacitor. The second transistor includes the first oxide semiconductor, the first to third conductors, and the second insulator. The capacitor includes the second conductor, the fourth conductor, and the third insulator.

13. A semiconductor device, comprising: First oxide semiconductor; First to third insulators; as well as First to fourth conductors, The first oxide semiconductor is disposed on the substrate. The first conductor and the second conductor are disposed on the first oxide semiconductor. The first insulator is disposed on the first conductor and the second conductor and includes a first opening and a second opening. The first opening overlaps the region between the first conductor and the second conductor and reaches the first oxide semiconductor. The second opening overlaps with the first oxide semiconductor and reaches the second conductor. The second insulator is disposed overlapping the first oxide semiconductor within the first opening. The third conductor is disposed on the second insulator within the first opening. The third insulator is disposed overlapping the second conductor within the second opening. The fourth conductor is disposed on the third insulator within the second opening. When viewed in cross-section along the channel width, the height of the first oxide semiconductor is greater than the width of the first oxide semiconductor. Furthermore, the semiconductor device, when viewed from above, has two or more regions where the first oxide semiconductor overlaps with the third conductor and two or more regions where the first oxide semiconductor overlaps with the fourth conductor.

14. The semiconductor device of claim 13, further comprising: The first layer; and The second layer on the first layer, The first layer includes a first transistor containing silicon in the channel formation region. The second layer includes a second transistor and a capacitor. The first transistor is electrically connected to the second transistor and the capacitor. The second transistor includes the first oxide semiconductor, the first to third conductors, and the second insulator. The capacitor includes the second conductor, the fourth conductor, and the third insulator.

15. The semiconductor device according to any one of claims 1 to 14, The first oxide semiconductor contains indium. The first oxide semiconductor is formed perpendicular or substantially perpendicular to the surface of the substrate. When the first oxide semiconductor was observed in cross section using a transmission electron microscope, bright spots arranged in layers in a direction perpendicular to the surface of the substrate were confirmed.

16. The semiconductor device according to any one of claims 1 to 14, The first oxide semiconductor contains indium. The first oxide semiconductor is formed perpendicular or substantially perpendicular to the surface of the substrate. The first oxide semiconductor includes a first region, a second region in contact with the first region, and a third region in contact with the second region. When the first oxide semiconductor was observed in cross section using a transmission electron microscope, bright spots arranged in layers in a direction perpendicular to the surface of the substrate were identified in each of the first region, the second region, and the third region.

17. The semiconductor device according to claim 16, The second region contains zinc. The second region has crystals. The c-axis of the crystal is approximately parallel to the normal direction of the side surface of the first oxide semiconductor.

18. The semiconductor device according to claim 16, The indium content in the first region is higher than that in the second region. Furthermore, the indium content in the third region is higher than that in the second region.

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