Epitaxial method for improving thickness flat region of heavily-doped As substrate thin layer high-resistance silicon epitaxial wafer

Abstract

The invention discloses an epitaxial method for improving a thickness flat region of a heavily-doped As substrate thin-layer high-resistance silicon epitaxial wafer, and the method comprises the following steps: S1, preparing an As-doped substrate material, and putting the substrate material into an epitaxial furnace; s2, HCl is introduced into the epitaxial furnace cavity for etching; s3, PH3 and SiH2Cl2 are introduced into a cavity of the epitaxial furnace, and a highly-doped buffer layer grows under the conditions that the growth temperature is 1060-1090 DEG C and the epitaxial pressure is 10-50 torr; s4, PH3 and SiH2Cl2 are introduced into the epitaxial furnace cavity, and an epitaxial layer grows under the conditions that the growth temperature is 1070-1100 DEG C and the epitaxial pressure is 20-70 torr; the concentration of PH3 introduced in the step is smaller than the concentration of PH3 introduced in the step S3, the growth temperature is higher than the growth temperature in the step S3, and the epitaxial pressure is higher than the epitaxial pressure in the step S3. Through the step-by-step pressure reduction growth process, the proportion of the thickness flat region of the epitaxial layer is increased, and meanwhile the problem of cavity silicon deposition caused by long-time low-temperature low-pressure growth is solved.

Description

Technical Field

[0001] This invention relates to the field of silicon carbide epitaxy technology, and in particular to an epitaxy method for improving the thickness flat region of a thin, high-resistivity silicon epitaxial wafer on a heavily As-doped substrate. Background Technology

[0002] The growth of thin, high-resistivity epitaxial layers on heavily doped substrates is a core technology for high-end semiconductor devices such as power devices and photodetectors. It is widely used in high-voltage MOSFETs, TVS diodes, FRDs (fast recovery diodes), and broadcast devices. This structure meets the dual requirements of high breakdown voltage and low on-resistance for power devices. However, due to the heavily doped substrate, the current ambient-pressure epitaxial process involves high temperatures. As impurities in the substrate volatilize at these high temperatures and enter the epitaxial layer during epitaxy, resulting in a self-doping effect. This self-doping effect leads to a decrease in the resistivity of the epitaxial layer, poorer uniformity within the wafer, and a slower transition region. Furthermore, subsequent devices using this epitaxial wafer are also severely affected by epitaxial self-doping during high-temperature processes, significantly impacting the device's electrical performance. For example, on heavily doped As substrates, self-doping after epitaxy results in a flat region accounting for less than 60% of the thickness, greatly affecting the performance and yield of the device. Summary of the Invention

[0003] Purpose of the invention: To address the drawback of low thickness flat region ratio in heavily doped As substrates, this invention provides an epitaxial method for improving the thickness flat region of thin high-resistivity silicon epitaxial wafers on heavily doped As substrates. By first epitaxially forming a doping concentration barrier with a highly doped buffer layer, and then epitaxially forming a high-resistivity layer, this process condition can limit the influence of self-doping to between the substrate and the highly doped buffer layer, greatly reducing the impact on the high-resistivity layer.

[0004] Technical solution: To solve the above problems, the present invention employs an epitaxial method for improving the thickness flat region of a thin, high-resistivity silicon epitaxial wafer on a heavily As-doped substrate, comprising the following steps: S1. Prepare the As-doped substrate material and load the substrate material into the furnace; S2. HCl is introduced into the epitaxial furnace cavity for etching; S3. Introduce PH3 and SiH2Cl2 into the epitaxial furnace cavity and grow a highly doped buffer layer at a growth temperature of 1060-1090℃ and an epitaxial pressure of 10-50 Torr. S4. Introduce PH3 and SiH2Cl2 into the epitaxial furnace cavity and grow the epitaxial layer at a growth temperature of 1070-1100℃ and an epitaxial pressure of 20-70 Torr. The concentration of PH3 introduced in this step is less than that introduced in step S3, the growth temperature is higher than that in step S3, and the epitaxial pressure is higher than that in step S3.

[0005] Furthermore, the resistivity of the As-doped substrate material is 0.002 ohm·cm-0.004 ohm·cm.

[0006] Furthermore, the etching temperature in step S2 is 1190℃, and the etching time is 25-35s.

[0007] Furthermore, in step S2, the flow rate of HCl introduced is 20 slm.

[0008] Furthermore, in step S3, the concentration of PH3 introduced is 3000 ppm, and the flow rate of PH3 introduced is 190 sccm.

[0009] Furthermore, in step S3, the flow rate of SiH2Cl2 introduced is 450 sccm.

[0010] Furthermore, in step S4, the concentration of PH3 introduced is 30 ppm, and the flow rate of PH3 introduced is 10 sccm.

[0011] Furthermore, in step S4, the flow rate of SiH2Cl2 introduced is 450 sccm.

[0012] Furthermore, the thickness of the highly doped buffer layer grown in step S3 is 1-2 μm.

[0013] Furthermore, the epitaxial layer grown in step S4 has a thickness of 7-9 μm.

[0014] Beneficial effects: Compared with the prior art, the significant advantage of this invention is that through a stepwise depressurization growth process, a highly doped buffer layer is first epitaxially grown to form a doping concentration barrier. Based on the principle of impurity trapping, the impurity concentration at the substrate-epitaxy interface decreases exponentially with the increase of epitaxial layer thickness. This can limit the influence of self-doping to between the substrate and the highly doped buffer layer. Then, a high-resistivity layer is epitaxially grown. This process greatly reduces the influence of substrate self-doping on the high-resistivity layer, increases the proportion of flat areas in the epitaxial wafer, and solves the silicon deposition problem caused by long-term low-temperature and low-pressure growth. Attached Figure Description

[0015] Figure 1 This is a comparison chart of the extended resistance tests of various embodiments of the present invention; Figure 2 The images show a comparison of silicon deposition within the cavity in Examples 1 to 3. Detailed Implementation

[0016] Example 1

[0017] This embodiment provides an epitaxial method for improving the thickness of flat regions in thin, high-resistivity silicon epitaxial wafers on heavily As-doped substrates, comprising the following steps: S1. Prepare an As-doped substrate material with a resistivity of 0.002 ohm·cm and load the substrate material into an ASM E2000 epitaxial furnace.

[0018] S2. Etching is performed by introducing HCl into the ASM E2000 epitaxial furnace cavity. The HCl flow rate is 20 slm, the etching temperature is 1190℃, and the etching time is 25 s.

[0019] S3. A concentration of 3000 ppm PH3 and SiH2Cl2 is introduced into the ASM E2000 epitaxial furnace cavity. The PH3 flow rate is 190 sccm, and the SiH2Cl2 flow rate is 450 sccm. A 1 μm thick highly doped buffer layer is grown at a growth temperature of 1060℃ and an epitaxial pressure of 10 Torr. This step uses depressurized epitaxy to grow a highly doped buffer layer with a relatively high concentration of PH3 to better suppress the influence of substrate self-diffusion.

[0020] S4. A PH3 and SiH2Cl2 solution with a concentration of 30 ppm is introduced into the ASM E2000 epitaxial furnace cavity. The flow rate of PH3 is 10 sccm, and the flow rate of SiH2Cl2 is 450 sccm. A 7 μm thick epitaxial layer is grown at a growth temperature of 1070℃ and an epitaxial pressure of 20 Torr. Since lower pressure and temperature, and longer epitaxial time, lead to more severe silicon deposition within the cavity, affecting the temperature field and product surface quality, this step uses a slightly higher growth temperature and pressure than step S3. By appropriately increasing the epitaxial temperature and pressure, the silicon deposition problem is alleviated, while still using a lower pressure than conventional processes to improve the thickness and flatness of the epitaxial growth area.

[0021] In this embodiment, the HCl and SiH2Cl2 introduced are both 100% pure gases, and the two concentrations of PH3 are existing products that were directly purchased.

[0022] Example 2

[0023] This embodiment provides an epitaxial method for improving the thickness of flat regions in thin, high-resistivity silicon epitaxial wafers on heavily As-doped substrates, comprising the following steps: S1. Prepare an As-doped substrate material with a resistivity of 0.003 ohm·cm and load the substrate material into an ASM E2000 epitaxial furnace.

[0024] S2. Etching is performed by introducing HCl into the ASM E2000 epitaxial furnace cavity. The HCl flow rate is 20 slm, the etching temperature is 1190℃, and the etching time is 30 s.

[0025] S3. PH3 and SiH2Cl2 at a concentration of 3000 ppm are introduced into the ASM E2000 epitaxial furnace cavity. The flow rate of PH3 is 190 sccm, and the flow rate of SiH2Cl2 is 450 sccm. A highly doped buffer layer with a thickness of 1.5 μm is grown at a growth temperature of 1070℃ and an epitaxial pressure of 20 Torr.

[0026] S4. Introduce PH3 and SiH2Cl2 at a concentration of 30 ppm into the ASM E2000 epitaxial furnace chamber. The flow rate of PH3 is 10 sccm, and the flow rate of SiH2Cl2 is 450 sccm. Grow an epitaxial layer with a thickness of 8 μm at a growth temperature of 1080℃ and an epitaxial pressure of 40 Torr.

[0027] Example 3

[0028] This embodiment provides an epitaxial method for improving the thickness of flat regions in thin, high-resistivity silicon epitaxial wafers on heavily As-doped substrates, comprising the following steps: S1. Prepare an As-doped substrate material with a resistivity of 0.004 ohm·cm and load the substrate material into an ASM E2000 epitaxial furnace.

[0029] S2. Etching is performed by introducing HCl into the ASM E2000 epitaxial furnace cavity. The HCl flow rate is 20 slm, the etching temperature is 1190℃, and the etching time is 35 s.

[0030] S3. PH3 and SiH2Cl2 at a concentration of 3000 ppm are introduced into the ASM E2000 epitaxial furnace cavity. The flow rate of PH3 is 190 sccm, and the flow rate of SiH2Cl2 is 450 sccm. A highly doped buffer layer with a thickness of 2 μm is grown at a growth temperature of 1090℃ and an epitaxial pressure of 50 Torr.

[0031] S4. Introduce PH3 and SiH2Cl2 at a concentration of 30 ppm into the ASM E2000 epitaxial furnace. The flow rate of PH3 is 10 sccm, and the flow rate of SiH2Cl2 is 450 sccm. Grow an epitaxial layer with a thickness of 9 μm at a growth temperature of 1100℃ and an epitaxial pressure of 70 Torr.

[0032] Comparative Example 1

[0033] This embodiment describes an atmospheric pressure growth process, including the following steps: S1. Prepare an As-doped substrate material with a resistivity of 0.004 ohm·cm and load the substrate material into an ASM E2000 epitaxial furnace.

[0034] S2. Etching is performed by introducing HCl into the ASM E2000 epitaxial furnace cavity. The HCl flow rate is 20 slm, the etching temperature is 1190℃, and the etching time is 35 s.

[0035] S3. PH3 and SiH2Cl2 at a concentration of 30 ppm are introduced into the ASM E2000 epitaxial furnace cavity. The flow rate of PH3 is 10 sccm, and the flow rate of SiH2Cl2 is 450 sccm. An epitaxial layer with a thickness of 8 μm is grown at a growth temperature of 1130℃ and an epitaxial pressure of 760 Torr.

[0036] The extension resistance of the epitaxial wafers obtained in each embodiment was tested, and the results are as follows: Figure 1 As shown in the figure, the horizontal axis represents the test thickness, and the vertical axis represents the volume resistivity. At the horizontal axis of 0 μm (i.e., the surface of the epitaxial layer), the resistivity values ​​of the epitaxial wafers obtained in Examples 1 to 3 are all higher than those under atmospheric pressure process conditions, indicating that the epitaxial method of the present invention can effectively improve the surface resistivity of the epitaxial wafer. The steepness and gentleness of the curve between 0 and 10 μm on the horizontal axis represent the width of the flat area of ​​the product; the steeper the curve, the larger the flat area, and the better the product performance. From the curves in the figure, it can be seen that the effective flat area width of the epitaxial wafers obtained in Examples 1 to 3 is better than that of the atmospheric pressure process.

[0037] The epitaxial resistivity and the proportion of the thickness flat region of the epitaxial wafers obtained in each embodiment were tested, and the results are shown in the table below:

[0038] The silicon deposition within the epitaxial cavity of Examples 1 to 3 was observed, and the results are as follows: Figure 2 As shown in the figure, from left to right, they are Example 1 to Example 3. It can be seen from the figure that the silicon deposition phenomenon in Example 1 is more obvious, while there is no obvious silicon deposition phenomenon in Example 2 and Example 3.

[0039] Considering the proportion of flat areas in the epitaxial wafer thickness and the silicon deposition phenomenon, Example 1 has the lowest growth pressure and the largest proportion of flat areas in the resulting epitaxial wafer thickness, but its silicon deposition phenomenon is more obvious; Example 2 has a significantly improved proportion of flat areas in thickness and no obvious silicon deposition phenomenon; Example 3 has no obvious silicon deposition phenomenon, but the proportion of flat areas in thickness is not as good as that of Example 2; therefore, Example 2 can be regarded as the optimal process conditions.

Claims

1. An epitaxial method for improving the thickness flat region of a thin, high-resistivity silicon epitaxial wafer on a heavily As-doped substrate, characterized in that, Includes the following steps: S1. Prepare the As-doped substrate material and load the substrate material into the furnace; S2. HCl is introduced into the epitaxial furnace cavity for etching; S3. Introduce PH3 and SiH2Cl2 into the epitaxial furnace cavity and grow a highly doped buffer layer at a growth temperature of 1060-1090℃ and an epitaxial pressure of 10-50 Torr. S4. Introduce PH3 and SiH2Cl2 into the epitaxial furnace cavity and grow the epitaxial layer at a growth temperature of 1070-1100℃ and an epitaxial pressure of 20-70 Torr. The concentration of PH3 introduced in this step is less than that introduced in step S3, the growth temperature is higher than that in step S3, and the epitaxial pressure is higher than that in step S3.

2. The epitaxial method as described in claim 1, characterized in that, The resistivity of the As-doped substrate material is 0.002 ohm·cm to 0.004 ohm·cm.

3. The epitaxial method as described in claim 1, characterized in that, The etching temperature in step S2 is 1190℃, and the etching time is 25-35s.

4. The epitaxial method as described in claim 1, characterized in that, In step S2, the flow rate of HCl introduced is 20 slm.

5. The epitaxial method as described in claim 1, characterized in that, In step S3, the concentration of PH3 introduced is 3000 ppm, and the flow rate of PH3 introduced is 190 sccm.

6. The epitaxial method as described in claim 1, characterized in that, In step S3, the flow rate of SiH2Cl2 introduced is 450 sccm.

7. The epitaxial method as described in claim 1, characterized in that, In step S4, the concentration of PH3 is 30 ppm and the flow rate of PH3 is 10 sccm.

8. The epitaxial method as described in claim 1, characterized in that, In step S4, the flow rate of SiH2Cl2 introduced is 450 sccm.

9. The epitaxial method as described in claim 1, characterized in that, The thickness of the highly doped buffer layer grown in step S3 is 1-2 μm.

10. The epitaxial method as described in claim 1, characterized in that, The epitaxial layer grown in step S4 has a thickness of 7-9 μm.

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