Semiconductor epitaxial growth method and epitaxial structure
By combining low-energy, low-dose ion implantation with laser annealing, the semiconductor epitaxial growth method solves the problems of substrate damage and high dislocation density in traditional processes, achieving higher quality GaN epitaxial layers and device performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-12
- Publication Date
- 2026-03-24
AI Technical Summary
In the manufacturing process of GaN devices, traditional ion implantation processes result in uncontrollable substrate lattice damage, difficulty in precisely controlling the implantation dose, poor uniformity of nucleation point density, and high dislocation density in the epitaxial layer due to lattice mismatch and thermal expansion coefficient differences between the substrate and the GaN material layer, which affects device reliability and lifespan.
A low-energy, low-dose ion implantation process, combined with low-current implantation, and nucleation layer growth processes at different temperatures, including MOCVD and PEALD, are employed to form a high-density nucleation site and a uniform buffer layer, thereby reducing implantation damage and dislocation density.
It significantly improves the uniformity of ion implantation, reduces the substrate damage depth, increases the nucleation point density and crystal quality, enhances the performance and reliability of the device layer, and extends the device lifetime.
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Figure CN121728984A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor epitaxial growth method and epitaxial structure. Background Technology
[0002] Third-generation semiconductor materials, represented by gallium nitride (GaN), possess many excellent properties, such as wide bandgap, high voltage resistance, high temperature resistance, high electron saturation velocity, and radiation resistance. Furthermore, the interface of the AlGaN / GaN heterojunction structure can generate a high concentration of two-dimensional electron gas, enabling the fabrication of channel structures with extremely low on-resistance. These properties give GaN materials better performance parameters than first-generation semiconductor materials; for example, GaN devices can theoretically achieve switching speeds tens of times higher than silicon (Si)-based devices.
[0003] Despite the many excellent properties of GaN devices, some problems still exist in practical applications. During the ion implantation process on the substrate, when using traditional ion implantation techniques to implant argon ions (Ar... + ) or carbon ions (C + When implanted into the substrate, the implantation process can uncontrollably damage the substrate's lattice, and the implantation dosage is difficult to control precisely, resulting in poor uniformity of nucleation point density. Furthermore, during the growth of the epitaxial layer on the substrate, due to the significant lattice mismatch and difference in thermal expansion coefficients between the substrate and the GaN material layer, the nucleation islands formed using the traditional two-step growth method exhibit disordered orientation and poor morphology, leading to a high dislocation density in the grown epitaxial layer, which severely affects the reliability and lifespan of the device. Summary of the Invention
[0004] In view of the above-mentioned technical problems in the prior art, the purpose of this application is to provide a semiconductor epitaxial growth method and epitaxial structure, which can improve the uniformity of implanted ions during the ion implantation process of the substrate, and reduce the implantation damage of the substrate and the dislocation density of the device layer.
[0005] To achieve the above and other related objectives, in a first aspect, this application provides a semiconductor epitaxial growth method, comprising the following steps: Provide a substrate; The first element is implanted into the substrate, wherein the implantation energy of the first element does not exceed 15 keV and the implantation dose does not exceed 5 × 10⁻⁶. 11 cm -2 ; Anneal the substrate inoculated with the first element; A nucleation layer is formed on the annealed substrate; A buffer layer and a device layer are sequentially formed on the nucleation layer.
[0006] Optionally, the step of implanting a first element into the substrate is performed, wherein the first element is C. + or N + .
[0007] Optionally, in the step of implanting a first element into the substrate, the implantation energy of the first element is 5keV~15keV, and the implantation dose of the first element is 1×10⁻⁶. 11 cm -2 ~5×10 11 cm -2 .
[0008] Optionally, in the step of implanting the first element into the substrate, the first element is implanted into the substrate at an angle of not less than 3°, and the ion beam current is less than or equal to 20 μA.
[0009] Optionally, in the step of annealing the substrate implanted with the first element, the substrate is subjected to 20 to 40 pulsed laser annealing cycles under the conditions of a laser wavelength of 400 nm to 500 nm, a pulse energy of 10 mJ to 20 mJ, a pulse width of 20 ns to 30 ns, and a scanning speed of 20 mm / s to 30 mm / s.
[0010] Optionally, the nucleation layer includes a first nucleation layer and a second nucleation layer; the step of forming the nucleation layer on the annealed substrate includes: A first nucleation layer is formed on the substrate under a growth environment at a first temperature; Under the growth environment of the second temperature, a second nucleation layer is formed on the first nucleation layer; The second temperature is lower than the first temperature.
[0011] Optionally, in the step of forming the first nucleation layer on the substrate, the first temperature is controlled to be 1150°C to 1200°C, a first nitrogen source and a first aluminum source are introduced into the reaction chamber, and the first nucleation layer is grown on the substrate using the MOCVD process. The growth rate of the first nucleation layer is 0.5 μm / h, the thickness of the first nucleation layer is 30 nm to 50 nm, and the ratio of the molar flow rate of the nitrogen-containing reactant in the first nitrogen source to the molar flow rate of the aluminum-containing reactant in the first aluminum source is (200:1) to (300:1).
[0012] Optionally, in the step of forming a second nucleation layer on the first nucleation layer, the second temperature is controlled to be 400°C to 450°C, a second nitrogen source and a second aluminum source are introduced into the reaction chamber, and the second nucleation layer is formed on the first nucleation layer using the PEALD process.
[0013] Optionally, in the step of forming a second nucleation layer on the first nucleation layer using the PEALD process, each atomic layer deposition cycle consists of a second aluminum source pulse of 0.1 s, a rinsing and purging time of 2 s, a second nitrogen source pulse of 5 s, and a rinsing and purging time of 2 s, as one atomic layer deposition cycle; wherein the thickness of the second nucleation layer is 20 nm to 40 nm.
[0014] Secondly, this application provides a semiconductor epitaxial structure, which is prepared by the semiconductor epitaxial growth method described in this application, including a substrate and a nucleation layer, a buffer layer and a device layer sequentially formed on the substrate; The substrate is prepared by ion implantation and annealing processes. In the ion implantation process, the implantation energy of the implanted ions does not exceed 15 keV, and the implantation dose does not exceed 5 × 10⁻⁶. 11 cm -2 .
[0015] As described above, compared with the prior art, the semiconductor epitaxial growth method and epitaxial structure provided in this application have at least the following beneficial effects: In this method, the injection energy of the first element is controlled to not exceed 15 keV, and the injection dose is not exceeded 5 × 10⁻⁶. 11 cm -2 The implanted ion beam current does not exceed 20 μA. Employing a low-energy, low-dose ion implantation process combined with small beam current implantation effectively improves the uniformity of implanted ions during the ion implantation process, reduces the implantation damage depth to the substrate, and can reduce the substrate implantation damage depth by more than 50%, for example, by 70%. This significantly improves the amorphization damage to the substrate during the ion implantation process, increasing the nucleation point density and uniformity during subsequent nucleation layer growth, thereby improving the crystal quality of the device layer grown on it and contributing to improved device performance. The semiconductor epitaxial structure of this application is prepared using the above method and therefore also possesses the aforementioned beneficial effects. Attached Figure Description
[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1 The diagram shown is a schematic flowchart of a semiconductor epitaxial growth method provided in Embodiment 1 of this application.
[0018] Figure 2 Displayed as Figure 1 The diagram shows a schematic of a substrate structure in the semiconductor epitaxial growth method.
[0019] Figure 3 Displayed as Figure 1 The diagram shows a schematic of the semiconductor epitaxial growth method involving ion implantation into the substrate.
[0020] Figure 4 Displayed as Figure 1 The diagram shows a schematic of the structure for annealing the pad in a semiconductor epitaxial growth method.
[0021] Figure 5 Displayed as Figure 1 The diagram shows a schematic of a nucleation layer formed on a substrate in a semiconductor epitaxial growth method.
[0022] Figure 6 Displayed as Figure 1 The diagram shows a schematic of a buffer layer formed on the nucleation layer in a semiconductor epitaxial growth method.
[0023] Figure 7 Displayed as Figure 1 The diagram shows a schematic of a device layer formed on a buffer layer in a semiconductor epitaxial growth method.
[0024] Illustration of reference numerals in the attached diagram: 11. Substrate; 12. Nucleation layer; 121. First nucleation layer; 122. Second nucleation layer; 13. Buffer layer; 14. Device layer. Detailed Implementation
[0025] To make the technical objectives, technical solutions, and technical effects of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with embodiments. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0026] Therefore, the following detailed description of embodiments of this application is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0027] In the description of this application, it should be noted that the terms "center", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0028] In the description of this application, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly, for example, referring to both fixed connections and detachable connections. Furthermore, the descriptions using terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples" indicate that a specific feature, structure, material, or characteristic described in connection with an implementation or example is included in at least one implementation or example of this application. In this specification, illustrative expressions of the above terms do not necessarily refer to the same implementation or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.
[0029] Example 1 In view of the problems in the prior art, such as poor uniformity of implanted ions and significant damage to the substrate during ion implantation, as well as high dislocation density of device layers grown on the substrate, this embodiment provides a semiconductor epitaxial growth method that can effectively improve the uniformity of implanted ions during ion implantation, reduce implantation damage, and also reduce the dislocation density of device layers grown on the substrate.
[0030] Reference Figure 1 The semiconductor epitaxial growth method provided in this embodiment includes steps S1 to S5, specifically including: S1. Provide a substrate; S2. Inject the first element into the substrate; S3. Anneal the substrate inoculated with the first element; S4. A nucleation layer is formed on the annealed substrate; S5. A buffer layer and a device layer are formed sequentially on the nucleation layer.
[0031] Wherein, the injection energy of the first element does not exceed 15 keV, and the injection dose does not exceed 5 × 10⁻⁶. 11 cm -2 .
[0032] In the semiconductor epitaxial growth method of this embodiment, the implantation energy of the first element is controlled to not exceed 15 keV, and the implantation dose is not exceeded 5 × 10⁻⁶. 11 cm -2 By employing low-energy, low-dose ion implantation, the uniformity of implanted ions during the ion implantation process can be effectively improved, reducing the implantation damage depth to the substrate 11. This can reduce the implantation damage depth to the substrate 11 by more than 50%, for example, by 70%. This effectively improves the amorphization damage to the substrate 11 during the ion implantation process, and can increase the nucleation point density and uniformity during the subsequent growth of the nucleation layer 12, thereby improving the crystal quality of the device layer 14 grown on it and helping to improve device performance.
[0033] In step S1, refer to Figure 2 Provide any substrate 11, which can be a substrate suitable for growing nitride single crystals. The material of the substrate 11 can be, for example, sapphire, silicon carbide, silicon, gallium nitride or other suitable materials. Specifically, the substrate 11 can be, for example, a sapphire substrate.
[0034] In step S2, refer to Figure 3 Ion implantation is performed on substrate 11, and a first element can be implanted into substrate 11 using an ion implantation process. The first element can be carbon ions (C). + ), nitrogen ions (N + (or other suitable ions). Optionally, the substrate 11 is, for example, a silicon carbide substrate 11, with C as the first element. + Since C is an element contained in the silicon carbide substrate 11, it will not introduce new impurity particles, thus avoiding impurity contamination and ensuring the high quality of the epitaxial layer.
[0035] In an optional embodiment, the injection energy of the first element is 5keV to 15keV. Specifically, the injection energy of the first element can be, for example, 5keV, 8keV, 10keV, 12keV, 15keV, or any value between the above endpoints, or other suitable values.
[0036] In an optional embodiment, the injection dose of the first element is 1 × 10⁻⁶. 11 cm -2 ~5×10 11 cm -2 Specifically, the injection dose of the first element can be, for example, 1 × 10⁻⁶. 11 cm -2 2×10 11 cm -2 3×10 11 cm -2 4×10 11 cm -2 5×10 11cm -2 Or any value between the above endpoint values or other suitable settings.
[0037] In an optional embodiment, during the implantation of the first element into the substrate 11, the ion beam current is less than or equal to 20 μA. Specifically, during ion implantation, the ion beam current can be, for example, 5 μA, 10 μA, 15 μA, 20 μA, or any value between the above endpoints, or other suitable values.
[0038] In step S2, during the ion implantation process on the substrate 11, the first element is implanted into the substrate 11 at an angle of not less than 3°. Specifically, during the implantation of the first element, the angle of inclination can be, for example, 3°, 5°, 7°, or other suitable values. Preferably, in step S2, the first element is implanted into the substrate 11 at an angle of 7°.
[0039] In this embodiment, a low-energy, low-dose ion implantation process is used to implant the first element into the substrate 11, which can effectively reduce lattice damage to the substrate 11 and avoid introducing foreign impurities. Combined with low-current implantation of the first element, the uniformity of the implanted first element can be effectively improved, and the implantation damage depth to the substrate 11 can be significantly reduced by 70%. This effectively improves the amorphization damage problem of the substrate 11, thereby increasing the density and uniformity of nucleation points in the subsequent nucleation layer 12, thus improving the quality of nucleation and helping to improve the quality of the subsequently grown device layer 14, thereby improving device performance.
[0040] In step S3 of this embodiment, refer to Figure 4 After the ion implantation process of substrate 11 is completed, the substrate 11 can be annealed by pulsed laser annealing to enhance the adsorption of subsequent precursors.
[0041] In an optional embodiment, in step S3, which involves annealing the substrate 11 implanted with the first element, the substrate 11 implanted with the first element is subjected to 20 to 40 pulsed laser annealing cycles under the conditions of a laser wavelength of 400 nm to 500 nm, a pulse energy of 10 mJ to 20 mJ, a pulse width of 20 ns to 30 ns, and a scanning speed of 20 mm / s to 30 mm / s.
[0042] Specifically, in the step of annealing the substrate 11 implanted with the first element, for example, the substrate 11 implanted with the first element can be subjected to 20 pulsed laser annealing cycles under conditions of a laser wavelength of 400 nm, a pulse energy of 20 mJ, a pulse width of 30 ns, and a scanning speed of 20 mm / s. Alternatively, for example, the substrate 11 implanted with the first element can be subjected to 40 pulsed laser annealing cycles under conditions of a laser wavelength of 500 nm, a pulse energy of 10 mJ, a pulse width of 20 ns, and a scanning speed of 30 mm / s. Alternatively, the substrate 11 implanted with the first element can also be subjected to pulsed laser annealing under other suitable process parameters.
[0043] During the ion implantation process of substrate 11, the implanted ions form implantation pits on the surface of substrate 11, which facilitate nucleation induced by dangling bonds around the pits. The ion implantation process inevitably causes some lattice damage to substrate 11. The pulsed laser annealing process in step S3 of this embodiment is used to anneal substrate 11. By strictly controlling the process parameters of the pulsed laser annealing process, the depth of the heat-affected zone can be controlled below 100 nm, and the implanted ions can be activated to repair the lattice distortion in substrate 11 and form high-density dangling bonds, for example, the density of dangling bonds can be greater than 10. 15 cm -2 This enhances the adsorption of subsequent precursors and the consistency of induced nucleation island orientation, thereby improving the consistency of nucleation island orientation by more than 40%.
[0044] In an optional embodiment, before performing step S3, the following step may be included: cleaning the substrate 11. Further, a wet cleaning method may be used to clean the substrate 11. The step of cleaning the substrate 11 may include, for example, placing the substrate 11 in a container filled with a first cleaning solution and placing the container in a cleaning device for a first preset time; removing the cleaned substrate 11 from the cleaning device and placing it in a drying device for drying; immersing the dried substrate 11 in a second cleaning solution for a second preset time, and then removing the immersed substrate 11 and placing it in the drying device for drying. Specifically, the first cleaning solution may be, for example, an acetone solution, and the second cleaning solution may be, for example, a dilute hydrochloric acid solution.
[0045] In step S4, after pulsed laser annealing of the substrate 11 is completed, a nucleation layer 12 is formed on the annealed substrate 11 to provide a basis for crystal growth. The nucleation layer 12 has a three-dimensional island structure and can be made of AlN or other suitable semiconductor materials.
[0046] In an optional embodiment, refer to Figure 5The nucleation layer 12 includes a first nucleation layer 121 and a second nucleation layer 122. Step S4, forming the nucleation layer 12 on the annealed substrate 11, includes: forming the first nucleation layer 121 on the substrate 11 under a first temperature growth environment; and forming the second nucleation layer 122 on the first nucleation layer 121 under a second temperature growth environment; wherein the second temperature is lower than the first temperature. Further, the first nucleation layer 121 can be grown using metal-organic chemical vapor deposition (MOCVD), and the second nucleation layer 122 can be grown using plasma-enhanced atomic layer deposition (PEALD).
[0047] By growing the first nucleation layer 121 using MOCVD technology in a high-temperature environment, a high density of nucleation sites can be provided, and the extension of dislocations in the substrate 11 can be blocked. By growing the second nucleation layer 122 using PEALD technology in a low-temperature environment, atomic-level flat coverage can be achieved, which can effectively fill the grain boundary micropores of the first nucleation layer 121 grown in a high-temperature environment, thereby improving the dislocation blocking efficiency and the quality of the subsequently formed buffer layer 13.
[0048] In an optional embodiment, during the step of forming the first nucleation layer 121 on the substrate 11, the first temperature is controlled at 1150°C to 1200°C, a first nitrogen source and a first aluminum source are introduced into the reaction chamber, and the first nucleation layer 121 is grown on the substrate 11 using an MOCVD process. Specifically, the first temperature can be, for example, 1150°C, 1160°C, 1180°C, 1200°C, or any value between the above endpoints, or other suitable values.
[0049] Further, in the step of forming a first nucleation layer 121 on the substrate 11, the growth rate of the first nucleation layer 121 is 0.5 μm / h, the thickness of the first nucleation layer 121 is 30 nm to 50 nm, and the ratio of the molar flow rate of the nitrogen-containing reactant in the first nitrogen source to the molar flow rate of the aluminum-containing reactant in the first aluminum source is (200:1) to (300:1). Specifically, the thickness of the formed first nucleation layer 121 can be, for example, 30 nm, 40 nm, 50 nm, or any value between the above endpoints, or other suitable values. The molar flow rate ratio between the nitrogen-containing reactant in the first nitrogen source and the aluminum-containing reactant in the first aluminum source can be, for example, 200:1, 240:1, 270:1, 300:1, or other suitable ratios. The first aluminum source can be, for example, trimethylaluminum (TMA) or other suitable aluminum-containing materials, and the first nitrogen source can be, for example, NH2 or other suitable nitrogen-containing materials.
[0050] In an optional embodiment, during the step of forming the second nucleation layer 122 on the first nucleation layer 121, the second temperature is controlled at 400°C to 450°C, a second nitrogen source and a second aluminum source are introduced into the reaction chamber, and the second nucleation layer 122 is formed on the first nucleation layer 121 using the PEALD process. Specifically, the second temperature can be, for example, 400°C, 420°C, 430°C, 450°C, or other suitable values.
[0051] Furthermore, in the step of forming a second nucleation layer 122 on the first nucleation layer 121 using the PEALD process, each atomic layer deposition cycle consists of a second aluminum source pulse of 0.1s, a rinsing and purging time of 2s, a second nitrogen source pulse of 5s, and a rinsing and purging time of 2s, as one atomic layer deposition cycle; wherein, the thickness of the second nucleation layer 122 formed is 20nm~40nm.
[0052] Furthermore, the second aluminum source can be, for example, trimethylaluminum (TMA), and the second nitrogen source can be, for example, a mixture of nitrogen and hydrogen gas; nitrogen or other suitable inert gas can be used for purging for a purging time of 2 seconds, and nitrogen can be used as the carrier gas; the thickness of the second nucleation layer 122 can be, for example, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm or other suitable values.
[0053] Reference Figure 6 In step S5, a buffer layer 13 is formed on the second nucleation layer 122 to provide stress and lattice mismatch compensation and reduce dislocations. The lattice constant of the buffer layer 13 can be between the semiconductor material layer in contact with the substrate 11 and the device layer 14. The material of the buffer layer 13 can be GaN, AlGaN, or other suitable semiconductor materials. The buffer layer 13 can be, for example, an undoped semiconductor material layer, or it can be a semiconductor material layer doped with a second element, such as C, Mg, or other suitable impurities. In the step of forming the buffer layer 13, a chemical vapor deposition process or other suitable process can be used to grow and form the buffer layer 13 on the second nucleation layer 122.
[0054] Reference Figure 7 In step S5, device layer 14 is formed on buffer layer 13. The specific structural dimensions and material of device layer 14 can be set according to actual needs. Specifically, the device to be fabricated may be, for example, a high electron mobility transistor (HEMT), and device layer 14 may be an HEMT epitaxial layer; or the device to be fabricated may be, for example, a light-emitting diode (LED), and device layer 14 may be an LED epitaxial layer.
[0055] In an optional embodiment, device layer 14 is an LED epitaxial layer. The step of forming device layer 14 in step S5 may include, for example, forming a first semiconductor layer, an active layer, a first barrier layer, a low-temperature semiconductor layer, a second barrier layer, and a second semiconductor layer sequentially on buffer layer 13. The first semiconductor layer may be, for example, an N-type layer, the second semiconductor layer may be, for example, a P-type layer, and the low-temperature semiconductor layer may be, for example, a low-temperature P-type layer.
[0056] In this embodiment, by employing low-energy, low-dose ion implantation on the substrate 11, combined with low-current ion implantation, the uniformity of implanted ions during the ion implantation process can be effectively improved, the implantation damage depth to the substrate 11 can be reduced, and the amorphization damage to the substrate 11 during the ion implantation process can be mitigated. This can improve the nucleation point density and uniformity during the subsequent growth of the nucleation layer 12, thereby improving the crystal quality of the device layer 14 grown on it. By performing pulsed laser annealing on the ion-implanted substrate 11, the implanted ions can be activated, lattice distortion in the substrate 11 can be repaired, and high-density dangling bonds can be formed, enhancing the adsorption of the subsequent AlN precursor and the consistency of the induced nucleation island orientation. By first growing the first nucleation layer 121 using MOCVD at high temperature, high-density nucleation points can be provided, and dislocation extension of the substrate 11 can be blocked. By growing the second nucleation layer 122 using PEALD at low temperature, atomic-level flat coverage can be achieved, effectively filling the grain boundary micropores of the first nucleation layer 121, improving the dislocation blocking efficiency and the quality of the subsequently formed buffer layer 13. Therefore, the method of this embodiment for preparing semiconductor epitaxial structures effectively reduces damage to the substrate 11 and dislocation density in the device layer 14, thereby improving the reliability and lifespan of the device.
[0057] Example 2 This embodiment provides a semiconductor epitaxial structure, referring to... Figure 7 The device includes a substrate 11 and a nucleation layer 12, a buffer layer 13, and a device layer 14 sequentially formed on the substrate 11. The substrate 11 is prepared by ion implantation and annealing processes. In the ion implantation process of the substrate 11, the implantation energy of the implanted ions does not exceed 15 keV, and the implantation dose does not exceed 5 × 10⁻⁶. 11 cm -2 Optionally, the ions implanted into the substrate 11 can be, for example, a first element, such as C. + N + Or other suitable ions.
[0058] The semiconductor epitaxial structure of this embodiment is prepared using any of the semiconductor epitaxial growth methods in Embodiment 1. Therefore, the semiconductor epitaxial structure of this embodiment also has the beneficial effects of Embodiment 1.
[0059] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify, alter, or combine the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.
Claims
1. A semiconductor epitaxial growth method, characterized in that, Includes the following steps: Provide a substrate; The first element is implanted into the substrate, wherein the implantation energy of the first element does not exceed 15 keV and the implantation dose does not exceed 5 × 10⁻⁶. 11 cm -2 ; Anneal the substrate inoculated with the first element; A nucleation layer is formed on the annealed substrate; A buffer layer and a device layer are sequentially formed on the nucleation layer.
2. The semiconductor epitaxial growth method according to claim 1, characterized in that, In the step of implanting a first element into the substrate, the first element is C. + or N + .
3. The semiconductor epitaxial growth method according to claim 1, characterized in that, In the step of implanting the first element into the substrate, the implantation energy of the first element is 5keV~15keV, and the implantation dose of the first element is 1×10⁻⁶. 11 cm -2 ~5×10 11 cm -2 .
4. The semiconductor epitaxial growth method according to claim 1, characterized in that, In the step of implanting the first element into the substrate, the first element is implanted into the substrate at an angle of not less than 3° and the ion beam current is less than or equal to 20 μA.
5. The semiconductor epitaxial growth method according to claim 1, characterized in that, In the step of annealing the substrate implanted with the first element, the substrate is subjected to 20 to 40 pulsed laser annealing cycles under the conditions of a laser wavelength of 400 nm to 500 nm, a pulse energy of 10 mJ to 20 mJ, a pulse width of 20 ns to 30 ns, and a scanning speed of 20 mm / s to 30 mm / s.
6. The semiconductor epitaxial growth method according to claim 1, characterized in that, The nucleation layer includes a first nucleation layer and a second nucleation layer; the step of forming the nucleation layer on the annealed substrate includes: A first nucleation layer is formed on the substrate under a growth environment at a first temperature; Under the growth environment of the second temperature, a second nucleation layer is formed on the first nucleation layer; The second temperature is lower than the first temperature.
7. The semiconductor epitaxial growth method according to claim 6, characterized in that, In the step of forming the first nucleation layer on the substrate, the first temperature is controlled to be 1150°C~1200°C, a first nitrogen source and a first aluminum source are introduced into the reaction chamber, and the first nucleation layer is grown on the substrate using MOCVD process. The growth rate of the first nucleation layer is 0.5 μm / h, the thickness of the first nucleation layer is 30 nm to 50 nm, and the ratio of the molar flow rate of the nitrogen-containing reactant in the first nitrogen source to the molar flow rate of the aluminum-containing reactant in the first aluminum source is (200:1) to (300:1).
8. The semiconductor epitaxial growth method according to claim 6, characterized in that, In the step of forming a second nucleation layer on the first nucleation layer, the second temperature is controlled at 400°C to 450°C, a second nitrogen source and a second aluminum source are introduced into the reaction chamber, and the second nucleation layer is formed on the first nucleation layer using the PEALD process.
9. The semiconductor epitaxial growth method according to claim 8, characterized in that, In the step of forming a second nucleation layer on the first nucleation layer using the PEALD process, each atomic layer deposition cycle consists of a second aluminum source pulse of 0.1 s, a rinsing and purging time of 2 s, a second nitrogen source pulse of 5 s, and a rinsing and purging time of 2 s, as one atomic layer deposition cycle; wherein, the thickness of the second nucleation layer is 20 nm to 40 nm.
10. A semiconductor epitaxial structure, prepared by the semiconductor epitaxial growth method according to any one of claims 1 to 9, comprising a substrate and a nucleation layer, a buffer layer and a device layer sequentially formed on the substrate; in, The substrate is prepared by ion implantation and annealing processes. In the ion implantation process, the implantation energy of the implanted ions does not exceed 15 keV, and the implantation dose does not exceed 5 × 10⁻⁶. 11 cm -2 .