Seed substrate for epitaxial growth and method for manufacturing the same, and semiconductor substrate and method for manufacturing the same

Abstract

The purpose is to provide an epitaxial or green seed substrate for epitaxial growth use, which comprises a Group III nitride such as AlN, AlxGa1-xN (0<X<1) and GaN, has little crystal defects and high quality, and is inexpensive. The seed substrate for epitaxial growth use comprises a support substrate, a flattened layer provided on an upper surface of the support substrate and having a thickness of 0.5 to 3 μm, and a seed crystal layer provided on an upper surface of the flattened layer. The support substrate includes a core that comprises a polycrystalline ceramic of a Group III nitride and a sealing layer that seals the core and has a thickness of 0.05 to 1.5 μm. The seed crystal layer is provided by the thin film transfer of 0.1 to 1.5 μm of a surface layer comprising Si<111> single crystals and having an oxidation induced stacking faults (OSFs) of 10 / cm2 or less.

Description

Technical Field

[0001] The present invention relates to a seed substrate for epitaxial growth of high-quality III-nitride epitaxial layers and bulk epitaxial layers with few defects, such as aluminum nitride (AlN), aluminum gallium nitride (Al x Ga 1-x N (where 0 < x < 1), gallium nitride (GaN), and its manufacturing method. More specifically, it relates to a seed substrate for epitaxial growth of III-nitride epitaxial layers and bulk epitaxial layers with extremely few crystal defects, warpage, and voids, such as high-quality and inexpensive AlN, Al x Ga 1-x N (0 < X < 1), GaN-based III-nitride epitaxial layers and bulk epitaxial layers, and its manufacturing method.

Background Art

[0002] Crystal substrates of III-nitrides such as AlN-based and GaN-based have a wide bandgap and excellent high-frequency characteristics with short-wavelength luminescence and high breakdown voltage. Therefore, III-nitride substrates are expected to be applied to devices such as light-emitting diodes (LEDs), lasers, Schottky diodes, power devices, and high-frequency devices. For example, AlN-based crystal substrates have recently seen an increase in demand for substrates for deep ultraviolet (UVC; 200 - 280 nm) light-emitting diodes made of single crystals of AlN and / or Al x Ga 1-x N (0.5 < X < 1) for the purpose of removing bacteria and viruses, triggered by the recent spread of the coronavirus and the like. However, currently, these AlN and / or Al x Ga 1-xSingle crystal substrates with N(0.5 < X < 1) have many defects, are of low quality, and are expensive. Even when various devices are fabricated using these substrates, the expected characteristics cannot be obtained, which restricts the wide spread and expansion of applications of these substrates. On the other hand, with the start of 5G communication and the progress of the electrification of vehicles, GaN-based crystal substrates are required to have higher high-frequency characteristics and higher breakdown voltage performance. As a result, GaN-based crystal substrates with extremely few crystal defects and low-cost epitaxial and bulk substrates are also in great demand. However, currently, similar to AlN-based crystal substrates, GaN-based crystal substrates also have many crystal defects and are of low quality, yet they are expensive, which hinders their wide spread to devices and further improvement is desired.

[0003] For example, regarding AlN single crystal substrates, as described in Non-Patent Document 1 and Non-Patent Document 2, since AlN does not have a melting point, it is difficult to manufacture by the general melt method using single crystal silicon (Si), etc. Usually, it is manufactured by the sublimation method (modified Lely method) at 1700 - 2250 °C in a N₂ atmosphere using silicon carbide (SiC) or AlN as a seed crystal, or as disclosed in Patent Document 1 and Non-Patent Document 3, it is made by the hydride vapor phase epitaxy (HVPE) method on a sapphire substrate or an AlN substrate obtained by the sublimation method. Since the sublimation method of AlN single crystal requires high temperature for crystal growth, currently, due to device limitations, it is at most a small-diameter substrate with a diameter of φ2 - φ4 inches and is extremely expensive. The dislocation density of the obtained AlN single crystal is <10 5 cm -2 which is relatively small. However, on the other hand, the crystal is colored due to contamination by carbon and metal impurities derived from carbon materials such as crucibles and heat insulation materials, etc., and has the drawbacks of low resistivity and low ultraviolet transmittance. On the other hand, AlN single crystals made by the hydride vapor phase epitaxy (HVPE) method on a sapphire substrate are relatively inexpensive and have less coloring. However, due to the difference in lattice constants between AlN and sapphire, the dislocation density of the AlN crystal is high and the resistivity is low. Also, the AlN crystal obtained by HVPE film formation on an AlN substrate by the sublimation method has a relatively small dislocation density. However, due to contamination by coloring substances from the underlying AlN substrate, it is opaque to deep ultraviolet light emission and has a low resistivity. Moreover, conventionally, the expensive sublimation method AlN crystal is used directly as the underlying substrate that also serves as a seed crystal, which has the drawback of being extremely costly.

[0004] Regarding GaN substrates, bulk GaN substrates obtained by growing GaN crystals in a liquid such as liquid ammonia or Na flux have relatively few defects and are of high quality. However, since a high-temperature and high-pressure device is required, they are extremely expensive. Also, as with the above-mentioned AlN substrates obtained by the sublimation method, when used as a base substrate that also serves as a seed crystal as it is, the cost becomes extremely high. On the other hand, if heteroepitaxial growth is performed on a sapphire substrate or the like using the MOCVD method or hydride vapor phase growth methods (HVPE method, THVPE method) that grow crystals in the gas phase, high-quality and large-sized crystals are theoretically possible. However, in reality, since the lattice constants and thermal expansion coefficients between the generated GaN crystals and the underlying sapphire substrate are significantly different, a large number of crystal defects and cracks occur during manufacturing, and high-quality crystals cannot be obtained.

[0005] As one solution to these problems, Patent Document 2 discloses a so-called QST (trade name) substrate having a support substrate with an AlN ceramic core and a sealing layer that seals the AlN ceramic core with a multilayer film of SiO2 / P-Si / SiO2 / Si3N4, a planarization layer such as SiO2 provided on the upper surface of the support substrate, and further having a seed crystal layer obtained by thin film transfer of Si<111> as a seed crystal on the upper surface of the planarization layer.

[0006] However, in this method, a difference in thermal expansion coefficient is likely to occur between the multilayer films that seal the core, or between the sealing layer, the planarization layer, and the seed crystal layer. Also, thermal stress based on the difference in thermal expansion coefficient generates cracks, chips, or distortions between the sealing layer, the planarization layer, or the seed crystal layer, or between the layers formed in subsequent processes such as the epitaxial film formation process. As a result, it has been found that dirt due to impurity diffusion in the AlN ceramic core and various distortions are induced in the seed crystal, which also has an adverse effect on subsequent epitaxial growth, resulting in an epitaxial growth film with low characteristics and many crystal defects.

[0007] Therefore, especially for substrates that require few crystal defects and high characteristics, for example, AlN and / or Al for substrates of light-emitting diodes used in the extremely ultra-short wavelength deep ultraviolet region (UVC; 200 - 280 nm) x Ga 1-xIt is difficult to obtain a GaN crystal substrate suitable for N(0 < X < 1), or high frequency and high breakdown voltage accompanying 5G communication and the electrification of vehicles with few crystal defects, high quality, and low cost, and thus new solutions have been desired.

[0008] Therefore, the inventors have conducted various studies to solve the above problems, and as a result, have arrived at the present invention. That is, one of the important components of the present invention is to minimize the difference in thermal expansion coefficients between the multilayer films that seal the above core, or between the sealing layer, the planarization layer, and the seed crystal layer, and to optimize the film thicknesses between the sealing layer, the planarization layer, and the seed crystal layer in a well-balanced manner. Among them, the optimization of the composition and thickness of the sealing layer, and / or, if necessary, adding a stress adjustment layer to minimize the thermal stress and achieve lower stress.

[0009] On the other hand, although the role of the seed crystal has been understood, its nature has not been deeply studied. In particular, the causal relationship between the nature of the Si<111> seed crystal and the subsequent epitaxial film formation has not been fully studied. Therefore, the inventors have minimized the strain caused by the thermal stress difference occurring between the above layers and the contamination from the core, etc., by optimizing the composition of each layer and minimizing the thermal stress between each layer, and investigated the effect of the nature of the Si<111> seed crystal on epitaxial film formation.

[0010] As a result, in order to obtain a seed substrate for epitaxial growth of group III nitrides such as AlN, Al x Ga 1-x N(0 < X < 1), GaN with few defects, high characteristics, and low cost, it was discovered that, in addition to the above strain and contamination, the oxidation-induced stacking fault (OSF) described in Patent Document 3 among the natures of the Si<111> seed crystal has a great influence. That is, it was found that the fewer the OSF in the Si<111> seed crystal, the fewer the defects in the epitaxial film formation, and the better the subsequent device characteristics.

[0011] Conventionally, many crystal defects existed in the epitaxial film, so Si <111> It was generally believed that the amount of oxidation-induced stacking faults (OSFs) in the seed crystal had little effect on defects in epitaxial deposition. However, the inventors re-examined the situation under conditions that make defects in epitaxial deposition more apparent, and found that Si <111> We discovered a significant causal relationship between the characteristics of the seed crystal and defects during epitaxial deposition, and incorporated this as another important component of the present invention, thus completing the invention. [Prior art documents] [Patent Documents]

[0012] [Patent Document 1] Patent No. 6042545 [Patent Document 2] Patent No. 6626607 [Patent Document 3] Patent No. 2936916 [Non-patent literature]

[0013] [Non-Patent Document 1] Japanese Journal of Applied Physics; Vol.46,No.17,2007,pp.L389-L391 [Non-Patent Document 2] SEI Technical Review; No. 177, pp. 88-91 [Non-Patent Document 3] Fujikura Technical Report; No. 119, 2010, Vol. 2, pp. 33-38 [Non-Patent Document 4] LEDs Magazine Japan; December 2016, p30~p31 [Overview of the project] [Problems that the invention aims to solve]

[0014] This invention was made in view of the above circumstances, and provides AlN, Al, which are of high quality and inexpensive with few crystal defects. x Ga 1-xTo obtain a seed substrate for epitaxial growth of group III nitrides such as N (0 < X < 1) and GaN and bulk epitaxial growth. To achieve this purpose, in the seed substrate for epitaxial growth of the present invention, by optimizing the composition and each film thickness between each multilayer film that seals the core serving as the base substrate, or between the sealing layer, the planarization layer, and the Si<111> seed crystal layer, the difference in thermal expansion coefficient is minimized and the stress is reduced, and the number of oxidation-induced stacking defects (OSF) on the upper surface of the planarization layer is 10 per cm 2 The following 0.1 to 1.5 μm of Si<111> single crystal was transferred by thin film and used as the seed crystal layer. The number of oxidation-induced stacking defects (OSF) of the present invention (per cm 2 ) was measured by the evaluation method of Patent Document 3. Although it becomes difficult to measure the defect density as the thickness of the seed crystal layer becomes thinner, it is considered that the defect density does not change by thin film transfer.

[0015] In the present invention, it is important to minimize the difference in thermal expansion coefficient between each multilayer film, or between the sealing layer, the planarization layer, and the seed crystal layer as much as possible. For this purpose, it is essential to optimize the composition and film thickness between the sealing layer, the planarization layer, and the seed crystal layer in a well-balanced manner. In particular, optimizing the composition and thickness of the sealing layer, and / or adding a stress adjustment layer as needed to further reduce the stress, and the number of oxidation-induced stacking defects (OSF) on the upper surface of the planarization layer is 10 per cm 2 By transferring the following 0. I to 1.5 μm of Si<111> single crystal by thin film and using it as the seed crystal layer, the expected crystal defects can be reduced, and high characteristics and low cost can be achieved.

Means for Solving the Problems

[0016] To achieve the above object, the seed substrate for epitaxial growth according to an embodiment of the present invention includes a support substrate, a planarization layer with a thickness of 0.5 to 3 μm provided on the upper surface of the support substrate, and a seed crystal layer provided on the upper surface of the planarization layer. The support substrate includes a core of polycrystalline ceramics of group III nitrides and a sealing layer with a thickness of 0.05 to 1.5 μm that seals the core. The seed crystal layer has 10 oxidation-induced stacking defects (Oxidation induced Stacking Fault: OSF) per cm 2The following Si <111> It is created by thin-film transfer of the surface layer (0.1-1.5 μm) of a single crystal.

[0017] In this invention, the polycrystalline ceramic of group III nitride that forms the core is preferably AlN ceramic.

[0018] In the present invention, the sealing layer preferably includes at least a layer of Si3N4.

[0019] In this invention, the planarization layer is made of SiO2 and / or silicon oxynitride (Si x O y N z ) Or it would be better if it were made of AlAs.

[0020] In this invention, the Si forming the seed crystal layer <111> The electrical resistivity (at room temperature) should ideally be 1 kΩ·cm or higher.

[0021] In this invention, it is preferable to further provide a stress adjustment layer on the lowest surface of the support substrate.

[0022] In this invention, the sealing layer is preferably formed by the LPCVD method.

[0023] In this invention, the planarization layer is made of SiO2 and / or silicon oxynitride (Si) on one side or the entire upper surface of the support substrate. x O y N z Alternatively, AlAs may be deposited by plasma CVD, LPCVD, or low-pressure MOCVD.

[0024] In this invention, the seed crystal layer is made of Si with an OSF of 10 particles / cm² or less and an electrical resistivity (room temperature) of 1 kΩ·cm or more. <111> This can be achieved by ion-implanting hydrogen and / or He into a single crystal, followed by transferring a thin film of 0.1 to 1.5 μm using physical means at a temperature of 450°C or lower.

[0025] In this invention, the stress adjustment layer can be selected from SiO2, Si3N4, amorphous Si, polycrystalline Si, etc., individually or in combination thereof, having a coefficient of thermal expansion that can correct the warping after the planarization layer is provided. Here, considering the compatibility with electrostatic chucks of process equipment in the device manufacturing process, it is preferable to select polycrystalline Si produced by a method selected from at least sputtering, plasma CVD, and LPCVD for the bottom layer of the support substrate. Furthermore, to improve the affinity between the sealing layer and the stress adjustment layer, SiO2 and / or silicon oxynitride (Si) x O y N z It is preferable to interpose the polycrystalline Si layer between the polycrystalline Si layer and the support substrate. When using a polycrystalline Si film that serves as both a stress adjustment film and a chucking film for the electrostatic chuck, the polycrystalline Si can be deposited directly, or, as described above, amorphous Si can be deposited and then polycrystallized by heating or laser irradiation. The reason for placing the polycrystalline Si film as the bottom layer is that, considering the compatibility with the electrostatic chuck of the process equipment, the smaller the distance between the electrostatic chuck surface and the chuck-compatible film, and the lower the resistivity of the chuck-compatible film, the stronger the electrostatic adsorption force becomes.

[0026] Furthermore, the semiconductor substrate according to the embodiment of the present invention is characterized in that a III-V semiconductor thin film is deposited on the upper surface of any of the above-mentioned epitaxial growth seed substrates. The III-V semiconductor thin film is preferably a nitride semiconductor thin film containing Ga and / or Al.

[0027] Furthermore, the method for manufacturing an epitaxial growth seed substrate according to an embodiment of the present invention includes the steps of: preparing a core made of a polycrystalline ceramic core of a group III nitride; forming a sealing layer with a thickness of 0.05 μm to 1.5 μm so as to enclose the core to form a support substrate; forming a planarization layer with a thickness of 0.5 μm to 3.0 μm on the upper surface of the support substrate; and forming an oxidation-induced stacking fault (OSF) of 10 units / cm² on the upper surface of the planarization layer. 2The following Si <111> The method comprises the step of providing a seed crystal layer by thin-film transfer of the surface layer 0.1 to 1.5 μm of a single crystal.

[0028] In this invention, the sealing layer is preferably formed by the LPCVD method.

[0029] In this invention, the planarization layer is made of SiO2 and / or silicon oxynitride (Si) on one side or the entire upper surface of the support substrate. x O y N z Alternatively, AlAs may be deposited by plasma CVD, LPCVD, or low-pressure MOCVD.

[0030] In this invention, the OSF is 10 particles / cm2 or less and the electrical resistivity (room temperature) is 1 kΩ·cm or more. <111> A seed crystal layer can be formed by ion-implanting hydrogen and / or He into a single crystal, followed by transferring a thin film of 0.1 to 1.5 μm using physical means at a temperature of 450°C or lower.

[0031] In the present invention, it is preferable to further include the step of providing a stress adjustment layer on the lowest surface of the support substrate. This stress adjustment layer has a coefficient of thermal expansion that allows for further correction of the warping after the planarization layer has been provided, and is preferably made of polycrystalline Si produced by a method selected from at least the sputtering method and the LPCVD method.

[0032] Furthermore, a method for manufacturing a semiconductor substrate according to an embodiment of the present invention comprises the steps of manufacturing an epitaxial growth seed substrate by any of the above-described methods for manufacturing an epitaxial growth seed substrate, and forming a III-V semiconductor thin film on the upper surface of the epitaxial growth seed substrate. [Effects of the Invention]

[0033] According to the present invention, AlN and / or Al are used in substrates for light-emitting diodes used in the deep ultraviolet region (UVC; 200~280nm). x Ga 1-xFor N (0 < X < 1), or for epitaxial growth of III-nitride such as GaN crystal substrates suitable for high-frequency and high-voltage applications associated with 5G communication and the electrification of vehicles, etc., it is possible to provide high-quality, low-defect and low-cost seed substrates for epitaxial growth of III-nitride epi and bulk epi.

Brief Description of Drawings

[0034] [Figure 1] It is a figure showing the cross-sectional structure of the seed substrate 1. [Figure 2] It is a figure showing the procedure for manufacturing the seed substrate 1.

Embodiments for Carrying Out the Invention

[0035] Hereinafter, embodiments of the present invention will be described in detail, but the present invention is not limited thereto.

[0036] The cross-sectional structure of the seed substrate 1 for epitaxial growth of III-nitride according to this embodiment (hereinafter, may be simply referred to as "seed substrate") is shown in FIG. 1. The seed substrate 1 shown in FIG. 1 has a structure in which a planarization layer 4 and a seed crystal layer 2 of Si<111> are laminated on a support substrate 3. Further, if necessary, a stress adjustment layer 5 is provided on the surface (lower surface) of the support substrate 3 opposite to the surface on which the planarization layer 4 is laminated.

[0037] The support substrate 3 includes a core 31 serving as the core material of the support substrate 3 and a sealing layer 32 covering the core 31.

[0038] Core 31 is formed from polycrystalline ceramics of group III nitride. Specifically, AlN, Si3N4, GaN, or mixtures thereof can be used, but polycrystalline AlN ceramics are preferred because they have lattice constants and thermal expansion coefficients close to those of the target group III nitride crystal, high thermal conductivity, and low cost. From the perspective of device processing, it is best to select mirror-finished wafers with a thickness of 200 to 1000 μm that can be used on semiconductor lines. There are various methods for manufacturing AlN ceramics, but the so-called sheet molding / atmospheric pressure sintering method is common due to its productivity. In the sheet molding / atmospheric pressure sintering method, AlN powder is mixed with a sintering aid, an organic binder, a solvent, etc. to create a wafer-shaped green sheet, which is then degreased, sintered in an N2 atmosphere, and polished to produce the product. Sintering aids can be selected from Y2O3, Al2O3, CaO, etc., but Y2O3 is usually preferred because it exhibits the highest thermal conductivity in the substrate after sintering.

[0039] If AlN ceramic is used as core 31 as is, metal impurities in the raw materials AlN and Y2O3 powder, as well as carbon, oxygen, and other impurities from the insulating material, furnace material, container, etc. during sintering, become sources of contamination, adversely affecting the target single crystal with crystal defects, discoloration, and other problems.

[0040] Therefore, a sealing layer 32 is provided to enclose and seal the polycrystalline ceramic core 31. Specifically, when sealing the core 31 with the sealing layer 32, the composition and thickness of each layer constituting the sealing layer 32 must be carefully considered so that thermal stress is kept as low as possible and thermal conductivity is kept as high as possible. In the present invention, from the standpoint of manufacturing cost, it is preferable to optimize the total thickness of the sealing layer 32 within the range of 0.05 to 1.5 μm.

[0041] The composition of the sealing layer 32 can be appropriately selected considering the coefficient of thermal expansion and thermal conductivity, but in order to further enhance its ability to prevent impurity diffusion, it is preferable to cover and seal the entire layer with a film made of at least silicon nitride (Si3N4).

[0042] If necessary, this sealing layer 32 may be provided with a p-Si layer for the electrostatic chuck, for example, if an electrostatic chuck is to be used. This p-Si layer may be formed between the AlN ceramics and the Si3N4 layer, or it may be provided together with the stress adjustment layer 5 described later, or as a layer below it. In that case, if the adhesion between the p-Si and the AlN core and Si3N4 is insufficient, SiO2 or silicon oxynitride (Si3N4) with high adhesive performance may be used, taking into account the affinity and thermal expansion coefficient between each layer. x O y N z It is advisable to interpose a membrane such as the following.

[0043] For seed substrates used for epitaxial growth of Group III nitrides such as GaN for high-frequency applications, especially ultra-high frequencies such as gigabits and millimeter waves, the above-mentioned Si is used to avoid high-frequency losses in devices fabricated using epitaxial layers grown on such seed substrates. <111> It is preferable that the electrical resistivity (at room temperature) of the seed crystal layer 2 is 1 kΩ·cm or more. <111> In the seed crystal layer 2, high-frequency losses due to gigabit and millimeter waves become large, causing the device to overheat, consume a lot of power, and fail to perform as intended.

[0044] When providing a p-Si film for the electrostatic chuck, it is preferable to use a p-Si with higher resistance, within the range that provides the necessary adsorption force. The p-Si should be deposited as far away as possible from the seed crystal layer 2 on which the epitaxial film is deposited, below the core 31, or below the stress adjustment layer 5, or it should be deposited as a multilayer film simultaneously with the stress adjustment layer 5. High-resistance p-Si has low high-frequency loss, and when placed below the support substrate 3, it is close to the electrostatic chuck, so sufficient electrostatic force is generated even with high resistance. For this reason, sufficient substrate adsorption is possible even without doping. To further reduce high-frequency loss, it is preferable to remove the p-Si layer by back grinding of the substrate at the end of device fabrication. When providing the stress adjustment layer 5, it is preferable to maintain the resistance of the p-Si as high as possible, but this does not limit the doping of the minimum amount of boron (B) or phosphorus (P) necessary to generate the required electrostatic force.

[0045] In the sealing layer 32, if the thickness of each layer becomes too thick, the stress between layers due to the difference in thermal expansion coefficients increases, causing delamination between layers. Therefore, even if films of various compositions are selected and combined, it is undesirable for the thickness of the sealing layer 32 to exceed 1.5 μm. On the other hand, from the viewpoint of the function of sealing impurities, a thickness of 0.05 μm or less is insufficient to prevent the diffusion of impurities. For the reasons above, it is preferable that the thickness of the sealing layer 32 be in the range of 0.05 to 1.5 μm. The method for depositing the sealing layer can be selected from conventional film deposition methods such as MOCVD, atmospheric pressure CVD, LPCVD, and sputtering, but the LPCVD method is particularly preferred in terms of film quality, film coverage, and impurity diffusion prevention ability.

[0046] A planarization layer 4 of 0.5 to 3 μm thickness is laminated on the sealing layer 32 on at least the upper surface of the support substrate 3. This planarization layer 4 is made of SiO2, Al2O3, Si3N4, SiC, or silicon oxynitride (Si x O y N z The material is selected from ordinary ceramic film materials such as ) and Si, GaAs, AlAs, etc., which are often used as sacrificial layers in etching, etc., but SiO2 and / or silicon oxynitride (Si) are selected because they are easy to grind and polish during planarization and easy to separate when obtaining a solid substrate. x O y N z ) or AlAs is preferable.

[0047] The planarization layer 4 is usually laminated on only one side of the sealing layer 32 for cost reasons, but if the warping is large, it can be deposited to cover the entire sealing layer 32. The thickness of the planarization layer 4 needs to be sufficient to fill voids and irregularities in the core 31 and sealing layer 32, and to provide sufficient smoothness for the seed crystal to be transferred. However, a planarization layer 4 that is too thick is undesirable as it can cause warping and cracking of the seed substrate 1. Therefore, it is preferable to provide it at least on the upper surface with a thickness of 0.5 to 3 μm. This is because if it is less than 0.5 μm, it will hardly be able to fill the voids and irregularities in the AlN ceramic core 31 and sealing layer 32, and if it is 3 μm or more, warping due to the planarization layer 4 is likely to occur.

[0048] From the viewpoints of the required film quality and film formation efficiency, the method for forming the planarization layer 4 is preferably a plasma CVD method, an LPCVD method, a low-pressure MOCVD method, or the like. The laminated SiO2 and / or silicon oxynitride (Si x O y N z ), or AlAs may be subjected to heat treatment for the purpose of annealing or CMP polishing for smoothness depending on the film situation, and is prepared for the thin film transfer of the seed crystal layer 2 described later.

[0049] The seed crystal is a substrate having a crystal structure similar to group III nitrides such as AlN, Al x Ga 1-x N (0 < X < 1), GaN, etc. are selected. Therefore, Si<111>, SiC, SCAM, AlN, AlGaN, sapphire, etc. are conceivable, but Si<111> is preferable in terms of ease of increasing the diameter, availability of commercial products, low cost, etc. Among them, among Si<111> crystals, a Si<111> single crystal with an oxidation-induced stacking fault (OSF) of 10 or less per cm 2 is particularly suitable as described above.

[0050] This is because when the OSF of the Si<111> seed crystal, which serves as the seed for the epitaxial film formation in the next step, is 10 or less per cm 2 , the epitaxially grown crystal also follows the seed crystal, has few defects, and ultimately the device using it also has high characteristics and good yield, resulting in low cost. On the other hand, when the OSF exceeds 10 per cm 2 , the defects in the epitaxially grown crystal also increase rapidly, the device characteristics deteriorate, and inevitably the yield also deteriorates, resulting in high cost.

[0051] Also, when using the epi and bulk substrates obtained by epitaxial film formation on the seed substrate 1 for high-frequency devices, especially for high-frequency devices after 5G, it is preferable to select a Si<111> seed crystal having an electrical resistivity (room temperature) of 1 kΩ·cm or more. This is because when the electrical resistivity (room temperature) of the Si<111> seed crystal is less than kΩ·cm, high-frequency loss occurs due to its resistance, the power consumption increases, and heat is generated, deteriorating the characteristics of the device.

[0052] Si <111> The seed crystal is implanted using ion implantation limited to hydrogen and / or helium (He) ions, which have little effect on the electrical resistance of the single crystal substrate, followed by the implantation of Si <111> The ion-implanted surface of the seed crystal is bonded to the upper surface of the planarization layer 4, and a thin film of 0.1 to 1.5 μm is peeled and transferred to the planarization layer 4 using physical means such as fingernails at a temperature of 450°C or lower to form the seed crystal layer 2. Unlike heavy elements such as boron (B), light elements such as hydrogen and He are suitable for ion implantation into seed crystals because they cause less damage to the seed crystal during ion implantation and do not reduce electrical resistance. Furthermore, peeling and transfer at a low temperature of 450°C or lower eliminates the Si problem that is unavoidable with the thermal peeling and transfer at high temperatures of 700°C or higher in the conventional smart cut method. <111> It can prevent heat damage to the seed crystal.

[0053] The transfer thickness of seed crystal layer 2 should be 0.1 to 1.5 μm. In ion implantation, the damage layer alone is nearly 0.1 μm thick, and if it is less than 0.1 μm, a good seed crystal cannot be obtained. Also, if the transfer thickness is 1.5 μm or more, the ion implanter requires high-power ion energy, resulting in a huge ion implanter, which is not economical and requires enormous investment. Note that if the thickness of seed crystal layer 2 is thin (for example, less than 1.0 μm), it may be difficult to directly measure the defect density, but since the defect density is not expected to change due to thin-film transfer, the defect density of OSF in seed crystal layer 2 is Si <111> Similar to seed crystals, 10 crystals / cm² 2 It is presumed that the following applies.

[0054] To describe the implementation method in more detail, hydrogen and / or He are ion-implanted into the seed crystal to a depth of 0.2 to 3.5 μm, and then the upper surface of the planarization layer 4 is joined to the ion-implanted surface of the seed crystal. After that, the seed crystal is peeled off at a temperature of 450°C or lower using physical methods such as gas pressure or fingernails. This is because at high temperatures above 450°C, impurity diffusion and stress and thermal damage due to thermal stress are likely to occur in the seed crystal of the thin film that has been transferred.

[0055] Subsequently, the upper surface of the transferred thin film is lightly etched with CMP polishing and / or chemicals to remove the unavoidable ion implantation damage layer, thereby obtaining a seed single crystal thin film (seed crystal layer 2) with a thickness of 0.1 to 1.5 μm. If higher uniformity is required for ion implantation, a film of SiO2 or the like may be deposited on the ion implantation surface of the seed substrate before ion implantation, if necessary.

[0056] In the present invention, a stress adjustment layer 5 may be added to the bottom surface of the support substrate 3 as needed. The stress adjustment layer 5 is made of a film material and thickness selected to have a coefficient of thermal expansion that can correct the warping of the seed substrate 1 caused by the formation of the planarization layer 4. For example, the stress adjustment layer 5 can be selected from SiO2, Si3N4, amorphous Si, polycrystalline Si, etc., either individually or in combination thereof. Here, considering the compatibility with electrostatic chucks in the process equipment during the device manufacturing process, it is preferable to select polycrystalline Si produced by a method selected from at least sputtering, plasma CVD, and LPCVD for the bottom layer of the support substrate. Usually, it is preferable to deposit polycrystalline Si (p-Si) as the stress adjustment layer 5, also to accommodate electrostatic chucks. Furthermore, from the viewpoint of correcting warping and affinity with the sealing layer 32, SiO2 and / or silicon oxynitride (Si) may be deposited between the polycrystalline Si and the sealing layer. x O y N z ) etc. may be interposed. When a polycrystalline Si film that also serves as a chucking film for the electrostatic chuck is used as the stress adjustment layer 5, the polycrystalline Si may be deposited directly, or amorphous Si may be deposited and then polycrystallized by heating or laser irradiation. By providing the polycrystalline Si film as the bottom layer, the distance between the electrostatic chuck surface and the chuck-compatible film can be shortened and the resistivity of the film can be reduced, thereby increasing the electrostatic adsorption force.

[0057] Next, with reference to Figure 2, the procedure for manufacturing the group III nitride-based epitaxial growth seed substrate 1 according to this embodiment will be described. Note that if a suitable method for forming each layer has already been described in conjunction with the configuration of each part of the seed substrate 1, the redundant explanation here will be omitted.

[0058] First, a core 31 made of nitride ceramics is prepared (S01 in Figure 2). Next, a sealing layer 32 with a thickness of 0.05 μm to 1.5 μm is deposited around the core 31 to form a support substrate 3 (S02 in Figure 2). At this time, the sealing layer 32 is preferably deposited by the LPCVD method. Next, a planarization layer 4 with a thickness of 0.5 μm to 3.0 μm is deposited on the upper surface of the support substrate 3 (S03 in Figure 2). In addition, a stress adjustment layer 5 is deposited on the lower surface of the support substrate 3 as needed (S04 in Figure 2). Note that the planarization layer 4 and the stress adjustment layer 5 may be deposited simultaneously.

[0059] In addition, separate from S01 to S04, there is a seed crystal, Si, which is used for exfoliating and transferring the seed crystal layer 2. <111> A single crystal substrate 20 is prepared (S11 in Figure 2). Next, ion implantation is performed from one side (ion implantation surface) of the single crystal substrate 20 to form a delamination position (embrittle layer) 21 within the single crystal substrate 20 (S12 in Figure 2).

[0060] Next, the ion-implanted surface of the single-crystal substrate 20 is joined to the planarization layer 4 formed on the support substrate 3 to form a bonded substrate (S21 in Figure 2). Then, the single-crystal substrate 20 is separated at the peeling position 21 of the single-crystal substrate 20 in the bonded substrate (S22 in Figure 2). In this way, Si is formed on the planarization layer 4 on the support substrate 3. <111> A single crystal film of the separated Si is transferred as a thin film as seed crystal layer 2. <111> The remaining portion of the single crystal substrate 20 can be repeatedly used to transfer a seed crystal layer as a thin film when fabricating another group III nitride composite substrate by polishing the surface again to create an ion implantation surface.

[0061] The structure and manufacturing method of the epitaxial growth seed substrate 1 have been described above. This invention is based on the synergistic effect of two essential components: 1) minimizing thermal stress by optimizing the composition and film thickness between each layer, particularly the sealing layer, and 2) growing high-quality epitaxial film crystals using high-quality seed crystals. Secondarily, 3) further stress reduction with a stress adjustment layer as needed, and 4) ion implantation limited to light elements such as hydrogen and / or He, and thin film transfer by physical means such as fingernails at 450°C or below are also effective. This invention makes it possible to economically obtain epitaxial substrates and solid substrates with extremely low warping, voids, crystal defects, etc., and extremely low high-frequency loss in devices.

[0062] The substrate of the present invention significantly improves the characteristics of devices such as light-emitting diodes used in the deep ultraviolet region (UVC; 200-280 nm), high-frequency devices for 5G communication and electric vehicles, and high-voltage devices, and also significantly improves the manufacturing yield of devices. [Examples]

[0063] The present invention will be described in more detail below with reference to examples and comparative examples, but the present invention is not limited to these examples.

[0064] [Example 1] (Preparation of the support substrate) A support substrate 3 was prepared, having a structure in which a polycrystalline ceramic core 31 was covered with a sealing layer 32. A commercially available AlN substrate was used for the polycrystalline ceramic core 31. This AlN substrate was prepared by mixing 100 parts by weight of AlN powder and 5 parts by weight of Y2O3 as a sintering aid with an organic binder and solvent to create a green sheet, which was then degreased and sintered at 1900°C under an N2 atmosphere. A double-sided polished AlN substrate with a diameter of φ8 inches and a thickness of t725 μm was used. The sealing layer 32 was formed by covering the entire AlN ceramic core 31 with a 0.1 μm thick silicon oxynitride layer using the LPCVD method, and then sealing the entire structure with a 0.4 μm thick Si3N4 layer using another LPCVD apparatus. The total thickness of the sealing layer 32 was 0.5 μm. For the purpose of further planarization, a 6 μm thick SiO2 layer was laminated on only one side of the upper layer using the plasma CVD method (ICP-CVD apparatus). Afterward, the SiO2 was planarized to a thickness of 2 μm (Ra=0.2 nm) by CMP polishing after firing at 1000°C, in preparation for thin-film transfer of the seed crystal.

[0065] (Preparing the seed crystal) In the evaluation of Patent Document 3, the number of oxidation-induced stacking faults (OSFs) was 8 per cm². 2 A silicon carbide (Si) 8 inch in diameter and 725 μm thick with an electrical resistivity (room temperature) of 1.5 kΩ·cm. <111> A single crystal substrate was prepared as a seed crystal substrate. Hydrogen was added to this Si substrate at 100 keV to a depth of 0.6 μm, with a dose of 8 × 10⁻¹⁶. 17 cm -2 Ion implantation was performed under the following conditions.

[0066] The ion-implanted Si is placed in the planarization layer 4 (2 μm thick) of the support substrate 3 that was prepared earlier. <111> The surface layer (0.6 μm) of a single crystal was transferred as a thin film. Si during ion implantation and transfer. <111> The damaged areas of the single crystal are lightly polished with CMP, and Si <111> The single crystal layer was made 0.4 μm thick and used as seed crystal layer 2. The resulting seed substrate 1 was free of cracks, delamination, and warping when the film thickness was balanced to the thermal stresses between each layer of the sealing layer 32, as well as between the sealing layer 32, the planarization layer 4, and seed crystal layer 2.

[0067] Note that the remaining Si after thin film transfer <111> The single-crystal substrate could be repeatedly used as a seed crystal by repeatedly performing ion implantation, making it extremely economical.

[0068] This implementation provides a support substrate 3 having an AlN ceramic core 31 and a sealing layer 32, with a 2 μm thick planarization layer 4 and a 0.4 μm thick Si <111> A seed substrate 1 with a single-crystal seed crystal layer 2 was obtained. The following simple evaluation was performed on the properties of this seed substrate 1 as a seed substrate for GaN epitaxial growth.

[0069] The above seed substrate 1 was placed in the reactor of the MOCVD apparatus and epitaxial growth was performed. In this process, the epitaxial layer was formed by depositing AlN and AlGaN sequentially from the seed substrate 1 side toward the growth direction, followed by epitaxial growth of GaN. The structure of the epitaxial layer is not limited to this; for example, AlGaN may not be deposited, or AlN may be deposited after AlGaN deposition. In this evaluation, an AlN layer of 100 nm and an AlGaN layer of 150 nm were deposited. The total thickness of the epitaxial layer was 5 μm. During epitaxial growth, TMAl (trimethylaluminum) can be used as the Al source, TMGa (trimethylgallium) as the Ga source, and NH3 as the N source, but the process is not limited to these. The carrier gas can be N2 and H2, or either of them, and the process temperature is preferably around 900 to 1200°C.

[0070] Subsequently, to evaluate the dislocation density, etch pits were induced using the molten alkali (KOH) etching method, and the etch pit density (EPD) was measured. In addition, X-ray rocking curve (XRC) measurements were performed to evaluate the crystallinity.

[0071] As a result, EPD is 0.2 × 10 4 cm -2It showed an extremely low dislocation density. Furthermore, the full width at half maximum (FWHM) measured by XRC on the GaN(0002) surface of the substrate (hereinafter simply referred to as "FWHM of 0002XRC") was 135 arcsec, indicating that a high-quality GaN single crystal was obtained. These results show that the seed substrate 1 of this embodiment has excellent properties as a seed substrate for epitaxial growth. When an epitaxial substrate with an epitaxial layer formed on this seed substrate 1 was used for a 30 GHz / 20 Gbps high-frequency device, the surface temperature of the device was 43°C, and no significant temperature rise due to high-frequency loss was observed.

[0072] [Comparative Example 1] Oxidation-induced stacking faults (OSFs) are present at 16 per cm². 2 A single crystal silicon carbide (8 inch diameter) with an electrical resistivity (room temperature) of 0.2 kΩ·cm. <111> Seed substrate 1 was prepared under the same conditions as in Example 1, except that a single crystal substrate was used as the seed crystal substrate and a 1.3 μm thick seed crystal layer 2 was transferred as a thin film. A 5 μm thick GaN film was deposited on this seed substrate 1 using the MOCVD method, similar to Example 1. As a result, the EPD was 15 × 10⁻⁶. 4 cm -2 It showed an extremely high dislocation density. Furthermore, the FWHM of 0002XRC was 930 arcsec, resulting in a GaN single crystal with poorer crystallinity compared to Example 1. In addition, when this epitaxial substrate was used for a 30 GHz / 20 Gbps high-frequency device, the device surface temperature reached a high temperature of 125°C due to high-frequency losses, making long-term use impossible.

[0073] [Example 2] (Preparation of the support substrate) A support substrate 3 was prepared, having a structure in which a polycrystalline ceramic core 31 was covered with a sealing layer 32. The same commercially available AlN substrate as in Example 1 was used for the polycrystalline ceramic core 31. The sealing layer 32 was first formed by encasing the entire AlN ceramic core 31 in a 0.3 μm thick SiO2 layer using the LPCVD method, and then sealing the entire surface with a 0.8 μm thick Si3N4 layer using another LPCVD apparatus. The total thickness of the sealing layer 32 was 1.1 μm. For the purpose of further planarization, a 5 μm layer of silicon oxynitride was laminated only on the upper layer of the sealing layer 32 using the LPCVD method. Subsequently, the silicon oxynitride layer was polished to a thickness of 2.5 μm by CMP polishing. At this stage, the entire substrate warped significantly to about 30 μm. To correct this warping, a stress adjustment layer 5 was further deposited on the bottom surface using plasma CVD, consisting of silicon oxide to a thickness of 5 μm and undoped polycrystalline Si to a thickness of 0.2 μm, which also served as an electrostatic chuck adsorption layer. As a result, the warping was eliminated, and sufficient adsorption and desorption to the electrostatic chuck was achieved.

[0074] (Preparing the seed crystal) In the evaluation of Patent Document 3, the number of oxidation-induced stacking faults (OSFs) was 0 per cm². 2 A single crystal silicon (Si) with a diameter of 8 inches and a thickness of 725 μm has an electrical resistivity (room temperature) of 2.3 kΩ·cm. <111> A substrate was prepared as a seed crystal substrate. Hydrogen was added to this Si substrate at 130 keV to a depth of 1.4 μm with a dose of 9.5 × 10⁻¹⁶ 17 cm -2 Ion implantation was performed under the following conditions.

[0075] The ion-implanted Si is placed in the planarization layer 32 (thickness 2.5 μm) of the support substrate 3 that was prepared in advance. <111> The surface layer (1.4 μm) of a single crystal was transferred as a thin film. Si during ion implantation and transfer. <111> The damaged areas of the single crystal are lightly polished with CMP, and Si <111> The single crystal layer was set to a thickness of 1 μm and used as seed crystal layer 2. The resulting seed substrate 1 was free of cracks, delamination, and warping when the film thickness was adjusted so that the thermal stresses were balanced between each layer of the sealing layer 32 and between the sealing layer 32, the planarization layer 4, and the seed crystal layer 2.

[0076] Note that the remaining Si after thin film transfer <111> The single-crystal substrate could be repeatedly used as a seed crystal by performing ion implantation many times, similar to Example 1, making it extremely economical.

[0077] This implementation provides a support substrate 3 having an AlN ceramic core 31 and a sealing layer 32, with a 2.5 μm thick planarization layer 4 and a 1 μm thick Si <111> A seed substrate 1 with a single-crystal seed crystal layer 2 was obtained. The properties of this seed substrate 1 as a seed substrate for epitaxial growth of AlN were evaluated in the following simple evaluation.

[0078] A 600 μm thick AlN single crystal was deposited on this seed substrate 1 using the THVPE method with AlCl3 and NH3 as raw materials. This deposited AlN single crystal was cut with a wire saw and polished to create a smooth φ8 inch substrate. The cut AlN single crystal substrate was colorless, and the transmittance of light at a wavelength of 220 nm was approximately 80% at a film thickness of 100 μm. Next, this substrate was used as a seed substrate for epitaxial growth of AlN and the following simplified evaluation was performed.

[0079] A 2 μm thick AlN film was deposited on the above AlN substrate using the MOCVD method. Similar to the evaluation in Example 1, etch pits were generated by molten alkali (KOH) etching to evaluate the dislocation density, and EPD measurements were performed. In addition, X-ray rocking curve (XRC) measurements were performed to evaluate the crystallinity.

[0080] As a result, EPD is 0.5 × 10 4 cm -2 It exhibited an extremely low dislocation density. Furthermore, the FWHM of 0002XRC was 110 arcsec, resulting in a high-quality AlN single crystal. This AlN single crystal was an excellent substrate for LEDs in the deep ultraviolet region, possessing extremely few defects, high device characteristics, and being inexpensive.

[0081] [Example 3] Seed substrate 1 for epitaxial growth was obtained under the same conditions as in Example 1, except that the planarization layer 4 of Example 1 was a two-layer structure of SiO2 / AlAs with a total thickness of 2.5 μm, consisting of a 2 μm thick AlAs lower layer and a 0.5 μm thick SiO2 upper layer.

[0082] Note that the remaining Si after thin film transfer <111> The single-crystal substrate could be repeatedly used as a seed crystal by repeatedly performing ion implantation, making it extremely economical.

[0083] This implementation provides a support substrate 3 having an AlN ceramic core 31 and a sealing layer 32, a planarization layer 4 made of SiO2 / AlAs with a total thickness of 2.5 μm, and a 0.4 μm thick Si layer on top of it. <111> A seed substrate 1 with a single-crystal seed crystal layer 2 was obtained. This seed substrate 1 was used as a seed substrate for epitaxial growth of GaN, and a thick GaN film was epitaxially grown.

[0084] After depositing a 30 μm thick GaN film on the above-mentioned substrate 1 by MOCVD, the SiO2 / AlAs planarization layer 4 was dissolved in an HF aqueous solution to obtain a solid GaN substrate with a thickness of approximately 30 μm.

[0085] To evaluate the dislocation density of this GaN substrate, etch pits were induced by molten alkali (KOH) etching, similar to the evaluation in Example 1, and EPD measurements were performed. In addition, X-ray rocking curve (XRC) measurements were performed to evaluate the crystallinity.

[0086] As a result, EPD is 0.05 × 10 4 cm -2 It showed an extremely low dislocation density. Furthermore, the FWHM of 0002XRC was 101 arcsec, indicating that a high-quality GaN single crystal was obtained. These values ​​show that seed substrate 1 of this embodiment is an excellent seed substrate for epitaxial growth to obtain a solid substrate. When a solid GaN substrate obtained by epitaxial growth using this seed substrate 1 was used for a 30 GHz / 20 Gbps high-frequency device, the surface temperature of the device was 38°C, indicating that it was an excellent substrate with low heat generation due to high-frequency loss. [Explanation of Symbols]

[0087] Type 1 board 2 Seed crystal layer 3. Support substrate 4 Planarization layer 5. Stress adjustment layer Single crystal substrates of 20 types of crystals 21 Peeling position

Claims

1. Support substrate and A planarization layer of 0.5 to 3 μm is provided on the upper surface of the support substrate, A seed crystal layer provided on the upper surface of the flattened layer and An epitaxial growth seed substrate comprising the seed crystal layer for epitaxial growth of a group III nitride using the seed crystal layer as a seed crystal, The aforementioned support substrate is A core of polycrystalline ceramics made of group III nitride, The core includes a sealing layer of 0.05 to 1.5 μm thickness that seals the core, The aforementioned seed crystal layer has 10 oxidation-induced stacking faults per cm². ２ The following is provided by thin-film transfer of a 0.1 to 1.5 μm surface layer of a Si<111> single crystal: The lowest surface of the support substrate is provided with a stress adjustment layer having a thermal expansion coefficient and thickness that can correct the warping of the epitaxial growth seed substrate caused by forming the planarization layer. A seed substrate for epitaxial growth characterized by the following features.

2. Support substrate and A planarization layer of 0.5 to 3 μm is provided on the upper surface of the support substrate, A seed crystal layer provided on the upper surface of the flattened layer and An epitaxial growth seed substrate comprising the seed crystal layer for epitaxial growth of a group III nitride using the seed crystal layer as a seed crystal, The aforementioned support substrate is A core of polycrystalline ceramics made of group III nitride, The core includes a sealing layer of 0.05 to 1.5 μm thickness that seals the core, The aforementioned seed crystal layer has 10 oxidation-induced stacking faults per cm². ２ The following are the characteristics of a Si<111> single crystal with a thickness of 0.1 to 1.5 μm: The lowest surface of the support substrate is provided with a stress adjustment layer having a thermal expansion coefficient and thickness that can correct the warping of the epitaxial growth seed substrate caused by forming the planarization layer. A seed substrate for epitaxial growth characterized by the following features.

3. The epitaxial growth seed substrate according to claim 1 or 2, characterized in that the polycrystalline ceramic of a group III nitride forming the core is an AlN ceramic.

4. The sealing layer comprises at least Si ３ N ４ An epitaxial growth seed substrate according to any one of claims 1 to 3, characterized by including a layer.

5. The planarization layer is SiO ２ , silicon oxynitride (Si ｘ O ｙ N ｚ The epitaxial growth seed substrate according to any one of claims 1 to 4, characterized in that it comprises either ), or SiO2 / AlAs in which SiO2 is laminated on AlAs.

6. The seed substrate for epitaxial growth according to any one of claims 1 to 5, characterized in that the electrical resistivity (at room temperature) of the Si<111> forming the seed crystal layer is 1 kΩ·cm or more.

7. The stress adjustment layer is provided as polycrystalline Si directly below the lower surface of the support substrate with SiO ２ and / or silicon oxynitride (Si ｘ O ｙ N ｚ interposed therebetween. The seed substrate for epitaxial growth according to any one of claims 1 to 6, characterized in that it is provided as polycrystalline Si with SiO and / or silicon oxynitride (SiON) interposed therebetween directly below the lower surface of the support substrate.

8. A semiconductor substrate characterized in that a group III-V semiconductor thin film is deposited on the upper surface of an epitaxial growth seed substrate according to any one of claims 1 to 7.

9. The semiconductor substrate according to claim 8, characterized in that the III-V semiconductor thin film is a nitride semiconductor thin film containing Ga and / or Al.

10. A step of preparing a core made of a polycrystalline ceramic core of a group III nitride, The steps include forming a sealing layer with a thickness of 0.05 μm or more and 1.5 μm or less so as to enclose the core and using it as a support substrate, The steps include forming a planarization layer with a thickness of 0.5 μm or more and 3.0 μm or less on the upper surface of the support substrate, The step of providing a stress adjustment layer on the lowest surface of the support substrate, After the step of providing the stress adjustment layer, 10 oxidation-induced stacking faults / cm² are formed on the upper surface of the planarization layer. ２ The method comprises the step of providing a seed crystal layer by thin-film transfer of the following Si<111> single crystal surface layer of 0.1 to 1.5 μm, A method for manufacturing an epitaxial growth seed substrate for epitaxially growing a group III nitride using the aforementioned seed crystal layer as a seed crystal, A method for manufacturing an epitaxial growth seed substrate made of polycrystalline Si, wherein the stress adjustment layer has a coefficient of thermal expansion and thickness that allows for further correction of its warping after the planarization layer is provided, and is prepared by a method selected from at least sputtering, plasma CVD, and LPCVD.

11. The method for manufacturing an epitaxial growth seed substrate according to claim 10, characterized in that the sealing layer is formed by the LPCVD method.

12. The planarization layer has SiO2 on only one side of the upper surface of the support substrate. ２ , silicon oxynitride (Si ｘ O ｙ N ｚ A method for manufacturing an epitaxial growth seed substrate according to claim 10 or 11, characterized in that either ), or SiO2 / AlAs, in which SiO2 is laminated on AlAs, is deposited by plasma CVD, LPCVD, or low-pressure MOCVD.

13. In the step of providing the seed crystal layer, the oxidation-induced stacking faults are 10 / cm². ２ The method for producing an epitaxial growth seed substrate according to any one of claims 10 to 12, characterized in that, after ion implanting hydrogen and / or He into a Si<111> single crystal having an electrical resistivity (at room temperature) of 1 kΩ·cm or more, a seed crystal layer is provided by transferring a thin film of 0.1 to 1.5 μm by physical means at 450°C or lower.

14. A step of manufacturing an epitaxial growth seed substrate by a method for manufacturing an epitaxial growth seed substrate according to any one of claims 10 to 13, The steps include: forming a III-V semiconductor thin film on the upper surface of the epitaxial growth seed substrate; A method for manufacturing a semiconductor substrate, comprising the features described above.

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