Selective waveguide ion implantation for tuning the local refractive index of photonics
Selective ion implantation in discrete sections of optical device films within photonic integrated circuits adjusts refractive index, addressing the challenge of propagation losses and bend radius issues, thereby improving circuit performance.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- APPLIED MATERIALS INC
- Filing Date
- 2024-06-11
- Publication Date
- 2026-04-28
AI Technical Summary
High refractive index contrast waveguides in photonic integrated circuits experience competing factors of tight optical confinement leading to high bend radius and propagation losses, necessitating a method to adjust local refractive index while minimizing these losses.
Selective ion implantation is applied to specific sections of an optical device film on a base layer, patterning it into discrete sections with gaps, and performing ion injection only on selected sections to adjust the refractive index, while leaving others unaffected.
This approach allows for flexible refractive index tuning of selected regions, reducing propagation losses and enhancing the performance of photonic integrated circuits by optimizing bend radii and signal routing efficiency.
Smart Images
Figure 2026513571000001_ABST
Abstract
Description
Technical Field
[0001] Cross - reference to related applications
[0001] This application claims the benefit of priority to U.S. Patent Application No. 18 / 208,685, filed on June 12, 2023. The content of each application is hereby incorporated by reference in its entirety.
[0002]
[0002] This disclosure relates to photonic integrated circuit (PIC) processing, and more specifically, to selective waveguide ion implantation for adjusting the local refractive index of a PIC.
Background Art
[0003]
[0003] It has become more common to use waveguides created within a medium that houses other circuit components to route optical signals within optoelectronic devices. These devices are known as photonic integrated circuits (PICs), and passive waveguides are used to route optical signals between active elements on such circuits. In such circuits, waveguides are also typically used to route optical signals to and from other circuits, usually via fiber ports.
[0004]
[0004] As the density of such PICs increases, the need for turns along the path of the waveguide also increases. To avoid radiative losses of optical signals at the bends, waveguides with a high refractive index contrast medium are used. High refractive index waveguides tightly confine optical modes laterally due to a large refractive index discontinuity between the waveguide core and the surrounding medium (e.g., dielectric / air). However, due to the tight optical confinement, the bend radius and propagation loss are two competing factors that such high refractive index contrast waveguides experience.
[0005]
[0005] Therefore, there is a need for a method to adjust the local refractive index contrast of a waveguide while minimizing propagation losses.
Summary of the Invention
[0006]
[0005] This summary is provided to introduce, in a simplified form, selected from the concepts detailed in the following "Modes for Carrying Out the Invention". This summary is not intended to confirm any important or essential features of the subject matter of the claimed invention, nor is it intended to help determine the scope of the subject matter of the claimed invention.
[0007]
[0006] In one embodiment, the method may include depositing an optical device film on a base layer, patterning the optical device film into a plurality of sections, and performing an injection into the first section in order to adjust the refractive index of the first section of the plurality of sections of the optical device film.
[0008]
[0007] In another embodiment, a method for local waveguide tuning may include depositing an optical device film on a base layer and patterning the optical device film into a plurality of sections, wherein adjacent sections of the plurality of sections are separated by gaps. The method may further include performing an injection into a first section of the plurality of sections of the optical device film to adjust the refractive index of the first section, while a second section of the plurality of sections is not affected by the injection.
[0009]
[0008] In yet another embodiment, a method for local waveguide tuning may include depositing an optical device film on a base layer and patterning the optical device film into a plurality of sections, where adjacent sections of the plurality of sections are separated by gaps. The method may further include injecting into the curved waveguide section to adjust the refractive index of the curved waveguide section of the plurality of sections of the optical device film, while the straight waveguide section of the plurality of sections is not affected by the injection.
[0010]
[0009] The accompanying drawings illustrate exemplary approaches of the present disclosure, including practical applications of the principles of the present disclosure, as follows: [Brief explanation of the drawing]
[0011] [Figure 1] The image shows a side cross-sectional view of a device according to an embodiment of the present disclosure, which includes a base layer and an optical device film on the base layer. [Figure 2] This shows a side cross-sectional view of the device after patterning of the optical device film according to an embodiment of the present disclosure. [Figure 3] This shows a side cross-sectional view of a device undergoing ion implantation into a portion of an optical device film, according to an embodiment of this disclosure. [Figure 4] This shows a side cross-sectional view of a device following ion implantation into a portion of an optical device film, according to an embodiment of the present disclosure. [Figure 5] This is a graph showing various refractive index adjustments according to the embodiments of this disclosure. [Figure 6] This is a schematic diagram of a system for forming a device according to an embodiment of the present disclosure. [Modes for carrying out the invention]
[0012]
[0016] The drawings are not necessarily to scale. The drawings are for illustrative purposes only and are not intended to depict any specific parameter of the disclosure. The drawings are intended to illustrate exemplary embodiments of the disclosure and should therefore not be considered limiting. In the drawings, similar numbers represent similar elements.
[0013]
[0017] Furthermore, certain elements in some drawings may be omitted or not shown to scale in order to clarify the explanation. Sectional views may be in the form of "slice" or "close-up" sectional views, and certain background lines visible in "true" sectional views may be omitted in order to clarify the explanation. Additionally, some reference numbers may be omitted in some drawings for clarity.
[0014]
[0018] Herein, the integrated circuits (ICs), systems, and methods relating to this disclosure will be described more comprehensively with reference to the accompanying drawings illustrating various embodiments. The ICs, systems, and methods may be embodied in many different forms and should not be construed as being limited to the embodiments described herein. Rather, these embodiments are provided to ensure that this disclosure is comprehensive and complete and to fully convey the scope of the methods to those skilled in the art.
[0015]
[0019] To address the shortcomings of the prior art, embodiments herein provide ion implantation for enabling a flexible silicon nitride (e.g., Si3N4) photonic platform, which allows for desired RI (refractive index) tuning for a selected region.
[0016]
[0020] Figure 1 shows an exemplary photonic IC or device 100 (hereinafter, "device") in one stage of processing. Device 100 may include a base layer 102 formed on a substrate 101 and an optical device film 104 (hereinafter, "film") formed on the upper surface 106 of the base layer 102. In some embodiments, the base layer 102 may be SiO2, the substrate 101 may be Si, and the film 104 may be silicon nitride (Si3N4), and each layer may be formed using any variety of deposition processes. The material of film 104 may be selected to suit one type of application, for example, an application having a low refractive index for low propagation loss. While this may generally be beneficial, it is desirable that specific parts of film 104 can be tuned in a more efficient way.
[0017]
[0021] Next, as shown in Figure 2, the film 104 can be patterned (e.g., etched) by selectively removing one or more sections of the film 104 from the upper surface 106 of the base layer 102. Although only the first section 108 and the second section 110 are shown, it will be understood that the film 104 can be patterned into a greater number of discrete sections, each separated from the others by gaps 112. In the illustrated embodiment, the first section 108 may be a curved waveguide, and the second section 110 may be a straight waveguide. Optical ICs often require the inclusion of both straight waveguides and curved waveguides that curve along the surface of the substrate in order to properly connect various components. In this embodiment, the curved waveguide may include a core that is bent as a curve and a metal cladding surrounding the core, the metal cladding may be formed from a conductive metallic material. The external shape of the metal cladding may be the same as that of the core, but is not limited to this disclosure.
[0018]
[0022] Although not shown in detail, it should be understood that one or more lithography and etching steps may be used to form the first section 108 and the second section 110. Since the first section 108 and the second section 110 are formed from the film 104, the first section 108 and the second section 110 may be made of the same material and may have the same thickness relative to the top surface 106 of the base layer 102. In other embodiments, the film 104 may have multiple sections of different materials, and therefore the first section 108 and the second section 110 are made of different materials.
[0019]
[0023] Next, as shown in Figure 3, a blocking mask 114 may be formed over the second section 110, and as part of the ion implantation process 118, ionic species are introduced into the first section 108. The blocking mask 114 prevents the ionic species from colliding with the second section 110. Although not limited, the ionic species may be silicon (Si), argon (Ar), fluorine (F), nitrogen (N), etc. In some embodiments, the ion implantation process 118 may be performed while the device 100 is at a high temperature, for example, above 100°C. However, it will be understood that the ion implantation process 118 may also be performed at room temperature or at low temperatures (for example, below 0°C). The ion implantation process 118 may include one or more implantation steps performed using one or more ionic species at various temperatures, implantation energies, etc.
[0020]
[0024] As shown in Figure 4, following the ion implantation process 118, the RI of the first section 108 may be changed, i.e., increased or decreased. That is, the first section 108 may have a first RI, and the second section 110 may have a second RI different from the first RI. Furthermore, in some embodiments, the RI may vary across the first section 108 and / or the second section 110. Figure 5 shows possible adjustments to the RI of the first section 108 as a result of the ion implantation process 118. As demonstrated, RI adjustments depend on the ion species, implantation temperature, implantation energy, etc. Although only room temperature (RT) and high temperature (HOT) implantations are shown, it will be understood that one or more low-temperature implantations may be performed additionally or alternatively. Furthermore, although only Si, Ar, F, and N have been identified, other ion species may be considered in alternative embodiments.
[0021]
[0025] FIG. 6 shows a schematic diagram of a processing apparatus 200 useful for performing the processes described herein. An example of a beamline ion implantation processing apparatus is the Varian VIISTA (registered trademark) Trident available from Applied Materials Inc., Santa Clara, Calif. The processing apparatus 200 may include an ion source 201 for generating ions. For example, the ion source 201 may provide ion implantation such as the ion implantation process 118 shown in FIG. 3. The ion source 201 is operable to perform the ion implantation process 118 at an implantation temperature exceeding 500° C.
[0022]
[0026] The processing apparatus 200 may also include a series of beamline components. Examples of beamline components may include an extraction electrode 203, a magnetic mass analyzer 211, a plurality of lenses 213, and a beam homogenizer 217. The processing apparatus 200 may further include a platen 219 for supporting the substrate 202 to be processed. The substrate 202 may be the same as the base layer 102 described above. The substrate 202 may be moved in one or more dimensions (e.g., translation, rotation, tilt, etc.) by a platform component, sometimes referred to as a “roplat” (not shown). It is also contemplated that the platen 219 may be configured to perform the heated ion implantation process 118 described herein.
[0023]
[0027] During operation, ions of a desired species (e.g., dopant ions) are generated and extracted from the ion source 201. Thereafter, the extracted ions 235 may move in a beam-like state along the beamline components and be implanted into the substrate 202. Similar to a series of optical lenses that manipulate light rays, the beamline components manipulate the extracted ions 235 along the ion beam. In this way, the extracted ions 235 are manipulated by the beamline components while being directed towards the substrate 202. It is contemplated that the apparatus 200 may provide improved mass selection for implanting desired ions while reducing the probability of unwanted ions (impurities) being implanted into the substrate 202.
[0024]
[0028] In some embodiments, the processing apparatus 200 can be controlled by a processor-based system controller such as controller 230. For example, controller 230 can be configured to control beamline components and processing parameters related to a beamline ion implantation process. Controller 230 can include a programmable central processing unit (CPU) 232 operable with memory 234 and a mass storage device, an input control unit, and a display unit (not shown) such as a power supply, a clock, a cache, and input / output (I / O) circuits connected to various components of the processing apparatus 200 to facilitate control of substrate processing. Controller 230 also includes hardware for monitoring substrate processing through sensors within the processing apparatus 200, which hardware includes sensors for monitoring substrate position and sensors configured to receive feedback from the processing apparatus 200 and control a heating device connected to the processing apparatus 200. Other sensors for measuring system parameters such as substrate temperature can also provide information to controller 230.
[0025]
[0029] To facilitate control of the above-described processing apparatus 200, CPU 232 can be one of any form of general-purpose computer processor usable in an industrial setting, such as a programmable logic controller (PLC), for controlling various chambers and sub-processors. Memory 234 is connected to CPU 232, and memory 234 can be non-transitory and can be one or more of readily available memories such as random access memory (RAM), read only memory (ROM), floppy disk drive, hard disk, or any other form of local or remote digital storage. Support circuitry 236 can be connected to CPU 232 to support the processor in a conventional manner. The implantation and other processes are generally stored in memory 234 as typically software routines. Additionally, the software routines can be stored and / or executed by a second CPU (not shown) located remotely from the hardware controlled by CPU 232.
[0026]
[0030] Memory 234 is a computer-readable storage medium containing instructions that, when executed by the CPU 232, facilitates the operation of the device 200. The instructions in memory 234 take the form of a program product, such as a program that implements the method of the present disclosure. The program code may be adapted to any one of many different programming languages. In one embodiment, the present disclosure may be implemented as a program product stored on a computer-readable storage medium for use with a computer system. One or more programs in the program product define the function of the embodiment, including the method described herein. Exemplary computer-readable storage mediums include, but are not limited to, (i) a non-writable storage medium on which information is permanently stored (e.g., a read-only memory device in a computer, such as a CD-ROM disk readable by a CD-ROM drive, flash memory, ROM chip, or any type of solid-state non-volatile semiconductor memory), and (ii) a writable storage medium on which modifiable information is stored (e.g., a floppy disk in a diskette drive or hard disk drive, or any type of solid-state random-access semiconductor memory). Such computer-readable storage media are embodiments of the disclosure when carrying computer-readable instructions that direct the functionality of the methods described herein.
[0027]
[0031] Please understand that the various layers, structures, and regions shown in the attached drawings are schematic diagrams. For ease of explanation, one or more types of layers, structures, and regions commonly used to form semiconductor devices or structures may not be explicitly shown in the given drawings. This does not mean that any layers, structures, and / or regions not explicitly shown are excluded from actual semiconductor structures.
[0028]
[0032] For convenience and clarity, terms such as “top,” “bottom,” “up,” “down,” “vertical,” “horizontal,” “lateral,” and “vertical” are understood to describe the relative arrangement and orientation of components and their parts, as shown in the diagram. Such terms include the specifically mentioned words, their derivatives, and words of similar importance.
[0029]
[0033] As used herein, elements or actions described in the singular form and followed by the word "a" or "an" should be understood to include multiple elements or actions until such exclusion is explicitly stated. Furthermore, references to "one embodiment" in this disclosure are not intended to be limiting. Additional embodiments may incorporate the described features.
[0030]
[0034] Furthermore, the terms “substantial” or “substantially,” in addition to “approximate” or “approximately,” may be used interchangeably in some embodiments and may be described using any relative scale acceptable to those skilled in the art. For example, these terms may serve as a comparison to a reference parameter to indicate a deviation that is achievable for the intended function. The amount of deviation from such a reference parameter may be, but not limited to, less than 1%, less than 3%, less than 5%, less than 10%, less than 15%, less than 20%, etc.
[0031]
[0035] Furthermore, those skilled in the art will understand that when it is stated that an element such as a layer, region, or substrate is formed, deposited, or placed "on," "over," or "atop" another element, the element may be placed directly on top of the other element, or intervening elements may be present. In contrast, when it is stated that one element is "directly on, directly over, or directly atop" another element, no intervening elements are present.
[0032]
[0036] As used herein, “deposition” and / or “deposition” may include any currently known or later developed techniques suitable for the material to be deposited, including, but not limited to, chemical vapor deposition (CVD), low-pressure CVD (LPCVD), and plasma CVD (PECVD). Additional techniques may include semi-atmosphere CVD (SACVD) and high-density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited-reaction-process CVD (LRPCVD), metal-organic CVD (MOCVD), and sputtering deposition. Additional techniques may include ion beam deposition, electron beam deposition, laser-assisted deposition, thermal oxidation, thermal nitriding, spin-on methods, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, and evaporation.
[0033]
[0037] While this document has described certain embodiments of the Disclosure, the Disclosure is broad in scope as the art permits, and this Specified Publication may be read similarly; therefore, the Disclosure is not limited to the descriptions herein. Accordingly, the above descriptions should not be interpreted restrictively. Rather, they are merely illustrative of specific embodiments. Those skilled in the art will anticipate other modifications within the scope of the claims and ideas appended herein.
Claims
1. It is a method, Depositing an optical device film on a base layer, Patterning the optical device film into multiple sections, To adjust the refractive index of the first section among the plurality of sections of the optical device film, injection is performed into the first section. Methods that include...
2. The method according to claim 1, further comprising forming a mask on a second section of the plurality of sections of the optical device film to protect the second section while injection is being performed into the first section.
3. The method according to claim 1, wherein the first section of the plurality of sections is a curved waveguide, and the second section of the plurality of sections is a straight waveguide.
4. The method according to claim 1, wherein the injection into the first section includes supplying ions to the first section at a temperature exceeding 100°C.
5. The method according to claim 1, wherein the injection into the first section comprises supplying silicon ions to the first section.
6. The method according to claim 1, wherein the injection into the first section comprises supplying at least one ionic species selected from fluorine, argon, and nitrogen into the first section.
7. The method according to claim 1, wherein depositing the optical device film on the base layer includes depositing a silicon nitride film directly above the upper surface of the base layer.
8. The method according to claim 7, wherein patterning the optical device film into the plurality of sections includes selectively removing one or more sections of the optical device film with respect to the upper surface of the base layer.
9. A method for local waveguide adjustment, Depositing an optical device film on a base layer, wherein the base layer is formed on a substrate, and depositing an optical device film. Patterning the optical device film into multiple sections, wherein adjacent sections among the multiple sections are separated by gaps, Without performing injection into the second section of the plurality of sections of the optical device film, injection is performed into the first section in order to adjust the refractive index of the first section of the plurality of sections of the optical device film. Methods that include...
10. The method according to claim 9, further comprising forming a mask on the second section of the plurality of sections of the optical device film to block the second section while injection is being performed into the first section.
11. The method according to claim 9, wherein the first section of the plurality of sections is a curved waveguide, and the second section of the plurality of sections is a straight waveguide.
12. The method according to claim 9, wherein the injection into the first section includes supplying ions to the first section at a temperature above 20°C.
13. The method according to claim 9, wherein the injection into the first section comprises supplying at least one ionic species selected from silicon, fluorine, argon, and nitrogen into the first section.
14. The method according to claim 9, wherein depositing the optical device film on the base layer includes depositing a silicon nitride film directly above the upper surface of the base layer.
15. The method according to claim 14, wherein patterning the optical device film into the plurality of sections includes selectively removing one or more sections of the optical device film with respect to the upper surface of the base layer.
16. A method for local waveguide refractive index adjustment, Depositing an optical device film on a base layer, wherein the base layer is formed on a substrate, and depositing an optical device film. The optical device film is patterned within a curved waveguide section and a straight waveguide section separated by a gap, To adjust the refractive index of the curved waveguide section of the optical device film, an injection is performed into the curved waveguide section, wherein the straight waveguide section is not affected by the injection. Methods that include...
17. The method according to claim 16, further comprising forming a mask on the straight waveguide section of the optical device film while the injection is being performed into the curved waveguide section, thereby blocking the straight waveguide section.
18. The method according to claim 16, wherein the injection into the bending waveguide section includes supplying ions to the bending waveguide section at a temperature exceeding 100°C.
19. The method according to claim 16, wherein the injection into the bending waveguide section includes supplying at least one ionic species selected from silicon, fluorine, argon, and nitrogen into the bending waveguide section.
20. The method according to claim 16, wherein depositing the optical device film on the base layer includes depositing a silicon nitride film directly above the upper surface of the base layer, and patterning the optical device film includes selectively etching one or more sections of the optical device film with respect to the upper surface of the base layer.