Self-adaptive silicon-based single photon avalanche photoelectric detection system with high counting rate

Abstract

The invention provides a self-adaptive high-counting-rate silicon-based single-photon avalanche photoelectric detection system which comprises a silicon-based single-photon avalanche photodiode, an analog-to-digital conversion module, a counting module, a current detection module, an active quenching and active recovery module, a passive quenching and active recovery module and a quenching mode self-adaptive module. An avalanche signal can be counted through a counting module to generate a first gating condition, an avalanche current is extracted through a current detection module to generate a second gating condition, and a gating signal is generated based on the two gating conditions through a quenching mode self-adaptive module, so that self-adaptive switching between an active quenching active recovery mode and a passive quenching active recovery mode is realized; and the performance limitation in the prior art is effectively broken through. An active quenching and active recovery mode can be maintained in a weak light scene, and high detection sensitivity is guaranteed; the passive quenching and active recovery mode can be switched in a strong light scene, avalanche termination is quickly realized, the quenching time is greatly shortened, the high counting rate is guaranteed, and stable detection in a full light intensity range is realized.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuit technology, specifically relating to an adaptive high count rate silicon-based single-photon avalanche photodetector system. Background Technology

[0002] Single-photon detection technology, as a core supporting technology in quantum information processing and high-precision sensing, plays an irreplaceable role in key scenarios such as quantum communication, lidar, and biofluorescence imaging. Silicon-based avalanche photodiodes (Si APDs), operating in Geiger mode, can achieve high-sensitivity detection of single photons and are the core devices in this field. Their maximum count rate directly determines the overall performance ceiling of the detection system. In quantum key distribution scenarios, a high count rate can significantly shorten the key generation cycle and improve the secure transmission efficiency of the communication link; in lidar systems, a high count rate can increase the sampling frequency of the target point cloud and enhance the ability to capture high-speed dynamic targets; in biofluorescence imaging, a high count rate can improve temporal resolution and achieve precise tracking of the trajectories of biomolecules. Therefore, the maximum count rate has become a core indicator for measuring the practical application level of single-photon detectors.

[0003] To overcome the count rate bottleneck of Si APDs, existing technologies mainly focus on optimizing the quenching mechanism, resulting in two major technical paths: active quenching and passive quenching. The active quenching and active recovery mode uses a downstream logic circuit composed of comparators, flip-flops, and logic gates to control two high-speed cascaded MOS transistors, enabling rapid termination of the avalanche process and device state recovery. However, its performance has inherent limitations: the response delay of the logic chip results in a physical lower limit to the detector's dead time. Forcibly reducing the pulse width of the active quenching and active recovery signals to shorten the dead time can lead to incomplete quenching and incomplete recovery, resulting in increased dark count rate and decreased detection efficiency. It is difficult to further break through the upper limit of the count rate from a hardware circuit coordination perspective.

[0004] Passive quenching mode achieves avalanche suppression by connecting a quenching resistor in series with the APD, eliminating the need for complex logic circuits and theoretically offering a faster response speed. To address the insufficient adaptability caused by fixed passive quenching resistors, Zheng Jiyuan's team proposed using special functional materials to fabricate adaptive resistance passive quenching resistors, dynamically adjusting the resistance value according to the photocurrent through the material's inherent properties. However, this approach relies on scarce functional material fabrication processes, resulting in high material acquisition difficulty and cost. Furthermore, it requires customized adaptation for different APD models, exhibiting poor versatility and failing to meet the needs of large-scale applications.

[0005] When the incident light intensity increases, leading to an increase in avalanche current, the logic control mechanism of the active quenching circuit cannot match the rapid quenching requirements under high current due to response delay and bandwidth limitations, making the count rate bottleneck increasingly prominent; while traditional passive quenching, although responding quickly, lacks dynamic adaptation capabilities.

[0006] In other words, the technical shortcomings of existing silicon-based single-photon avalanche photodetectors (Si APDs) can be summarized as follows:

[0007] I. Due to the response delay of the logic chip, the dead time in the active quenching and active recovery mode has an inherent lower limit, making it difficult to break through the count rate bottleneck.

[0008] Second, traditional passive quenching modes rely on special materials to prepare adaptive quenching resistors, which have poor versatility and high cost.

[0009] Third, the active quenching and active recovery modes and the passive quenching mode cannot be dynamically switched with light intensity. The passive mode has insufficient sensitivity in low light and the active mode has a lag in response in strong light.

[0010] Therefore, there is an urgent need to develop an optimized quenching mechanism that balances high versatility and wide light intensity adaptability in order to overcome the dual limitations of existing technologies in improving count rate. Summary of the Invention

[0011] This invention addresses the aforementioned problems by providing an adaptive high-count-rate silicon-based single-photon avalanche photodetector system. By constructing an adaptive quenching mechanism, it achieves intelligent mode switching in low-light to high-light scenarios, balancing high detection sensitivity, wide light intensity adaptability, and high versatility, thereby improving the detector's maximum count rate and stability. To achieve the above-mentioned objectives, this invention employs the following technical solution:

[0012] This invention provides an adaptive high-count-rate silicon-based single-photon avalanche photodetector system, characterized by the following technical features: a silicon-based single-photon avalanche photodiode for detecting photons and acquiring avalanche signals; an analog-to-digital conversion module for converting the avalanche signals into digital signals, including counting signals; a counting module for counting the number of the counting signals per unit time and generating a first gating condition based on the counting result and a predetermined counting threshold; and a current detection module for detecting the avalanche current of the silicon-based single-photon avalanche photodiode to obtain a corresponding voltage, and generating a first gating condition based on the voltage and a predetermined gating threshold. The system includes: a voltage threshold generating a second gating condition; an active quenching and active recovery module for actively quenching and actively recovering the silicon-based single-photon avalanche photodiode; a passive quenching and active recovery module for passively quenching and actively recovering the silicon-based single-photon avalanche photodiode; and a quenching mode adaptive module that generates a gating signal based on the first and second gating conditions, and controls one of the active quenching and active recovery modules and the passive quenching and active recovery module to operate while the other is disabled, thereby enabling the system to enter either an active quenching and active recovery mode or a passive quenching and active recovery mode.

[0013] The adaptive high-count-rate silicon-based single-photon avalanche photodetector system provided by this invention may also have the following technical features: the system initially operates in the active quenching and active recovery mode. When the counting result is lower than or equal to the counting threshold and the voltage corresponding to the avalanche current is lower than or equal to the voltage threshold, the quenching mode adaptive module causes the system to operate in the active quenching and active recovery mode. When the counting result is higher than the counting threshold and / or the voltage corresponding to the avalanche current is higher than the voltage threshold, the quenching mode adaptive module causes the system to operate in the passive quenching and active recovery mode.

[0014] The adaptive high-count-rate silicon-based single-photon avalanche photodetector system provided by this invention may also have the following technical features: The analog-to-digital conversion module includes: a capacitor C1 and a sampling resistor R3, connected to the silicon-based single-photon avalanche photodiode, for generating a negative pulse avalanche signal; a high-speed comparator CMP1, for comparing the avalanche signal with a predetermined comparison threshold to determine whether an avalanche has occurred, and outputting a corresponding level; and a pulse width shaping chip U4, for generating the pulse-width adjustable counting signal based on the output of the high-speed comparator CMP1. The counting module includes at least: a core processing chip U7, for counting the number of the counting signals per unit time, and generating a first gating condition based on the counting result. The current detection module includes: a sampling resistor R1, connected to the silicon-based single-photon avalanche photodiode; a current acquisition operational amplifier A1, for sampling the avalanche current on the sampling resistor R1 and converting it into a voltage signal; and a high-speed comparator CMP2, for comparing the voltage signal with the voltage threshold, and generating a second gating condition based on the comparison result. The quenching mode adaptive module includes: a high-speed logic OR chip U8, used to perform a logic OR operation on the first gating condition and the second gating condition to obtain the gating signal; a high-speed logic AND chip U9, used to connect or disconnect the active quenching active recovery module based on the gating signal; and a high-speed electronic switch K1, used to connect or disconnect the passive quenching active recovery module based on the gating signal.

[0015] The adaptive high-count-rate silicon-based single-photon avalanche photodetector system provided by this invention also has the following technical features: the core processing chip U7 is further used to output active network signals and passive network signals based on the gating signal; the high-speed logic AND chip U9 connects or disconnects the active quenching and active recovery module and the silicon-based single-photon avalanche photodiode based on the active network signal; the pulse width shaping chip U4 generates an inverted signal of the counting signal as a negative pulse signal; the counting module further includes a clock output buffer U1, which transmits the counting signal to the core processing chip and the passive quenching and active recovery module or blocks the signal based on the passive network signal; the quenching mode adaptive module further includes a clock output buffer U2, which transmits the negative pulse signal to the active quenching and active recovery module and the passive quenching and active recovery module or blocks the signal based on the passive network signal.

[0016] The adaptive high-count-rate silicon-based single-photon avalanche photodetector system provided by this invention also has the following technical features: In the analog-to-digital conversion module, the high-speed comparator CMP has a non-inverting input terminal, an inverting input terminal, and an output terminal Q#; the pulse width shaping chip U4 has an input terminal IN, an output terminal Q, and an output terminal Q#. One end of the sampling resistor R3 is grounded, and the other end of the sampling resistor R3 is connected to one end of the capacitor C1 and the non-inverting input terminal of the high-speed comparator CMP1. The output terminal Q# of the high-speed comparator CMP1 is connected to the input terminal IN of the pulse width shaping chip U4. The other end of the capacitor C1 serves as a signal coupling terminal and is connected to the cathode of the silicon-based single-photon avalanche photodiode. The output terminal Q of the pulse width shaping chip U4 is connected to the clock input terminal of the clock output buffer U1, and the output terminal Q# of the pulse width shaping chip U4 is connected to the clock input terminal of the clock output buffer U2.

[0017] The adaptive high count rate silicon-based single-photon avalanche photodetector system provided by the present invention may also have the following technical features: in the counting module, the clock output buffer U1 has a clock input terminal ICLK, an enable terminal AOE, an output terminal Q1 and an output terminal Q2, and the core processing chip U7 is an FPGA, which has a gating condition output terminal, a gating signal input terminal, an active network terminal, a passive network terminal and an output terminal. The clock input terminal ICLK of the clock output buffer U1 is connected to the output terminal Q of the pulse width shaping chip U4. The enable terminal AOE of the clock output buffer U1 is connected to the passive network terminal of the core processing chip U7. The output terminal Q1 of the clock output buffer U1 is connected to the output terminal of the core processing chip U7. The output terminal Q2 of the clock output buffer U1 is connected to the passive quenching active recovery module. The gating condition output terminal of the core processing chip U7 is connected to the input terminal of the high-speed logic OR chip. The gating signal input terminal of the core processing chip U7 is connected to the output terminal of the high-speed logic OR chip. The active network terminal of the core processing chip U7 is connected to the input terminal INB of the high-speed logic AND chip U9. The passive network terminal of the core processing chip U7 is connected to the enable terminal AOE of the clock fan-out buffer U1 and the enable terminal BOE of the clock fan-out buffer U2, respectively.

[0018] The adaptive high count rate silicon-based single-photon avalanche photodetector system provided by this invention may also have the following technical features: in the current detection module, the current acquisition operational amplifier A1 has a non-inverting input terminal, an inverting input terminal, and an output terminal; the high-speed comparator CMP2 has an input terminal and an output terminal; one end of the sampling resistor R1 is connected to the high-voltage power supply terminal and the non-inverting input terminal of the current acquisition operational amplifier A1; the other end of the sampling resistor R1 is connected to the inverting input terminal of the current acquisition operational amplifier A1, the other end of the capacitor C1, and the cathode of the silicon-based single-photon avalanche photodiode; and the output terminal of the current acquisition operational amplifier A1 is connected to the input terminal of the high-speed comparator CMP2.

[0019] The adaptive high count rate silicon-based single-photon avalanche photodetector system provided by the present invention may also have the following technical features: in the quenching mode adaptive module, the high-speed logic and chip U9 has a first input terminal, a second input terminal, and an output terminal; the high-speed electronic switch K1 has a common terminal Z, a selection control terminal S, an output terminal Y0, and an output terminal Y1; the high-speed logic and chip U9 has an input terminal INA, an input terminal INB, and an output terminal OUT; and the clock fan-out buffer U2 has a clock input terminal ICLK, an enable terminal BOE, an output terminal Q3, and an output terminal Q4. The first input terminal of the high-speed logic OR chip U8 is connected to the gating condition output terminal of the core processing chip U7. The second input terminal of the high-speed logic OR chip U8 is connected to the output terminal of the high-speed comparator CMP2. The output terminal of the high-speed logic OR chip U8 is connected to the selection control terminal S of the high-speed electronic switch K1 and the gating signal input terminal of the core processing chip U7. The common terminal Z of the high-speed electronic switch K1 is directly connected to the anode of the silicon-based single-photon avalanche photodiode. The output terminal Y0 of the high-speed electronic switch K1 is grounded. The output terminal Y1 of the high-speed electronic switch K1 is connected to the passive quenching active recovery module. The output terminal Q3 of the clock fan-out buffer U2 is connected to the input terminal INA of the high-speed logic AND chip U9. The output terminal of the high-speed logic AND chip U9 is connected to the active quenching active recovery module.

[0020] The adaptive high count rate silicon-based single-photon avalanche photodetector system provided by the present invention may also have the following technical features, wherein the active quenching and active recovery module includes transistor D5, MOSFET D6, MOSFET D7, resistor R9, resistor R10 and pulse width shaping chip U3, wherein the pulse width shaping chip U3 has an input terminal IN, an output terminal Q and an output terminal Q#. The input terminal IN of the pulse width shaping chip U3 is connected to the output terminal OUT of the high-speed logic AND chip U9. The output terminal Q of the pulse width shaping chip U3 is connected to the base of the transistor D5. The collector of the transistor D5 is connected to one end of the resistor R9, the source of the MOSFET D7, and the output terminal Y0 of the high-speed electronic switch K1. The emitter of the transistor D5 is grounded, and the other end of the resistor R9 is grounded. The drain of the MOSFET D7 is connected to the power supply. The gate of the MOSFET D7 is connected to one end of the resistor R10 and the drain of the MOSFET D6. The other end of the resistor R10 is connected to the power supply. The source of the MOSFET D6 is grounded, and the gate of the MOSFET D6 is connected to the output terminal OUT of the high-speed logic AND chip U9 and the input terminal IN of the pulse width shaping chip U3.

[0021] The adaptive high count rate silicon-based single-photon avalanche photodetector system provided by the present invention may also have the following technical features, wherein the passive quenching and active recovery module includes Darlington transistor D1, Darlington transistor D2, diode D3, diode D4, quenching resistor Rq, resistor R5, resistor R6, resistor R7 and resistor R8. One end of the quenching resistor Rq is connected to the output terminal Y1 of the high-speed electronic switch K1, the cathode of the diode D4, and the collector of the Darlington transistor D2. The other end of the quenching resistor Rq is connected to the cathode of the diode D3 and the collector of the Darlington transistor D1. The anode of the diode D3 is connected to one end of the resistor R7 and one end of the resistor R8. The other end of the resistor R7 is connected to the output terminal Q4 of the clock fan-out buffer U2. The other end of the resistor R8 is grounded. The base of the Darlington transistor D1 is connected to one end of the resistor R8. The emitter of the Darlington transistor D1 is grounded. The anode of the diode D4 is connected to one end of the resistor R5. The other end of the resistor R5 is connected to the output terminal Q2 of the clock fan-out buffer U1. One end of the resistor R6 is connected to one end of the resistor R5 and the base of the Darlington transistor D2. The other end of the resistor R6 is grounded. The emitter of the Darlington transistor D2 is grounded.

[0022] The role and effect of invention

[0023] The adaptive high-count-rate silicon-based single-photon avalanche photodetector system provided by this invention, comprising a silicon-based single-photon avalanche photodiode, an analog-to-digital converter, a counting module, a current detection module, an active quenching and active recovery module, a passive quenching and active recovery module, and a quenching mode adaptive module, enables adaptive switching between active quenching and active recovery modes. This effectively overcomes the performance limitations of existing technologies. In low-light conditions, the active quenching and active recovery mode can be maintained to ensure high detection sensitivity; while in high-light conditions, it can switch to the passive quenching and active recovery mode to quickly terminate avalanches, thereby significantly shortening the quenching time and ensuring a high count rate. Combining the two modes and adaptive switching, stable detection across the entire light intensity range is achieved. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the adaptive high count rate silicon-based single-photon avalanche photodetector system in an embodiment of the present invention;

[0025] Figure 2 This is a schematic diagram of the interaction between modules in the adaptive high count rate silicon-based single-photon avalanche photodetector system in an embodiment of the present invention;

[0026] Figure 3 This is a circuit connection diagram of the adaptive high count rate silicon-based single-photon avalanche photodetector system in an embodiment of the present invention;

[0027] Figure 4 This is a circuit connection diagram of the current detection module, analog-to-digital conversion module, and counting module in an embodiment of the present invention;

[0028] Figure 5 This is a circuit connection diagram of the active quenching and active recovery module in an embodiment of the present invention;

[0029] Figure 6 This is a circuit connection diagram of the passive quenching and active recovery module in an embodiment of the present invention.

[0030] Figure label:

[0031] Adaptive high count rate silicon-based single-photon avalanche photodetector system 10;

[0032] Silicon-based single-photon avalanche photodiode (Si APD) 11;

[0033] Analog-to-digital conversion module 12;

[0034] High-speed comparator CMP1; pulse width shaping chip U4; capacitor C1; sampling resistor R3;

[0035] Counting module 13;

[0036] Clock output buffer U1; Core processing chip U7;

[0037] Current detection module 14;

[0038] Current acquisition operational amplifier A1; high-speed comparator CMP2; sampling resistor R1;

[0039] Quenching mode adaptive module 15;

[0040] Clock fanout buffer U2; High-speed logic OR chip U8; High-speed logic AND chip U9; High-speed electronic switch K1;

[0041] Active quenching and active recovery module 16;

[0042] Transistor D5; MOSFET D6; MOSFET D7; Resistor R9; Resistor R10; Pulse width shaping chip U3;

[0043] Passive quenching and active recovery module 17;

[0044] Darlington transistor D1; Darlington transistor D2; Diode D3; Diode D4; Quenching resistor Rq; Resistor R5; Resistor R6; Resistor R7; Resistor R8. Detailed Implementation

[0045] To make the technical means, creative features, objectives and effects of the present invention easy to understand, the adaptive high count rate silicon-based single-photon avalanche photodetector system of the present invention will be specifically described below with reference to embodiments and accompanying drawings.

[0046] Example

[0047] Figure 1 This is a schematic diagram of the adaptive high count rate silicon-based single-photon avalanche photodetector system in this embodiment. The diagram shows the overall system architecture and module connection relationships. Figure 2 This is a schematic diagram of the interaction between the modules in the adaptive high count rate silicon-based single-photon avalanche photodetector system in this embodiment.

[0048] like Figure 1 and Figure 2 As shown, the adaptive high count rate silicon-based single-photon avalanche photodetector system 10 (hereinafter referred to as the detector system 10) includes: a silicon-based single-photon avalanche photodiode (Si APD) 11, an analog-to-digital conversion module 12, a counting module 13, a current detection module 14, a quenching mode adaptive circuit module 15, an active quenching and active recovery module 16, and a passive quenching and active recovery module 17.

[0049] The Si APD11 is the core detection device, used to detect photons and generate corresponding avalanche signals. The Si APD11 operates in Geiger mode, meeting the sensitivity requirements for single-photon-triggered avalanches, and it has a cathode and an anode.

[0050] The analog-to-digital converter module 12 is used to convert the avalanche signal of the Si APD 11 into a digital signal that can be used for counting and triggering, including a counting signal.

[0051] The counting module 13 is used to count the number of counting signals per unit time and generate a first gating condition (gating condition A) based on the counting result and a predetermined counting threshold.

[0052] The current detection module 14 is used to extract the avalanche current of the Si APD 11 to obtain the corresponding voltage, and generate a second gating condition (gating condition B) based on the voltage and a predetermined voltage threshold.

[0053] The counting threshold and the current threshold both correspond to the predetermined incident light intensity.

[0054] The quenching mode adaptive module 15 is the core control module, which is used to generate a gating signal based on gating condition A and gating condition B, and control one of the active quenching active recovery module 16 and the passive quenching active recovery module 17 to work and the other to be disabled according to the gating signal, thereby controlling the detection system 10 to enter the active quenching active recovery mode or the passive quenching active recovery mode.

[0055] Preferably, the detection system 10 initially operates in active quenching and active recovery mode. When the statistical result is lower than or equal to the counting threshold and the voltage corresponding to the avalanche current is lower than or equal to the voltage threshold, that is, in a scenario with weak incident light, the quenching mode adaptive module 15 enables the detection system 10 to operate in active quenching and active recovery mode; when the statistical result is higher than the counting threshold or the voltage corresponding to the avalanche current is higher than the voltage threshold, that is, in a scenario with strong incident light, the quenching mode adaptive module 15 enables the detection system 10 to operate in passive quenching and active recovery mode.

[0056] The active quenching and active recovery module 16 is used to realize the active quenching and active recovery of Si APD 11.

[0057] The passive quenching and active recovery module 17 is used to realize the passive quenching and active recovery of Si APD 11.

[0058] Optionally, the modules described above can be electrically connected sequentially. Alternatively, the modules can be connected to the same central control module to achieve collaborative operation. The following will exemplarily illustrate one specific implementation of the system described above.

[0059] Figure 3 This is a schematic diagram of the circuit connection of the adaptive high count rate silicon-based single-photon avalanche photodetector system in this embodiment. Figure 3 As shown, in this embodiment, each of the above modules is a circuit module and they are electrically connected in sequence.

[0060] Figure 4 This is a circuit connection diagram of the current detection module, analog-to-digital conversion module, and counting module in this embodiment.

[0061] like Figures 1 to 4 As shown, in this embodiment, the analog-to-digital conversion module 12 includes a high-speed comparator CMP1, a pulse width shaping chip U4, a capacitor C1, and a sampling resistor R3. The high-speed comparator CMP1 has a positive input terminal, a negative output terminal, a positive output terminal Q, and an inverting output terminal Q#. The pulse width shaping chip U4 has an input terminal IN, a positive output terminal Q, and an inverting output terminal Q#.

[0062] In this embodiment, the high-speed comparator is a single-supply voltage comparator device using silicon-germanium (SiGe) technology. Under the conditions of a single power supply of 3.3V to 5.2V and an input overdrive voltage of about 200mV, the propagation delay from any input terminal to the output terminal is no more than 300ps, and it can correctly compare input pulse signals with a minimum pulse width of no more than 200ps.

[0063] In this circuit, one end of the sampling resistor R3 is grounded, and the other end is connected to one end of capacitor C1 and the positive input terminal of high-speed comparator CMP1. The negative input terminal of high-speed comparator CMP1 is left unused, the positive output terminal Q of high-speed comparator CMP1 is left unused, and the inverting output terminal Q# is connected to the input terminal IN of pulse width shaping chip U4. The other end of capacitor C1 serves as the signal coupling terminal of analog-to-digital converter module 12 and is connected to the cathode of Si APD 11.

[0064] like Figures 1 to 4 As shown, in this embodiment, the counting module 13 includes a clock fan-out buffer U1 and a core processing chip U7. The clock fan-out buffer U1 has a clock input terminal ICLK, an enable terminal AOE (used to control the second output terminal Q2), output terminals Q1 and Q2. The core processing chip U7 is an FPGA, which has a gating condition output terminal, a gating signal input terminal, an active network terminal, a passive network terminal, and an output terminal. The gating condition output terminal outputs the state of gating condition A, the active network terminal outputs the active network signal, and the passive network terminal outputs the passive network signal.

[0065] Among them, the clock input terminal ICLK of the clock fanout buffer U1 is connected to the positive output terminal Q of the pulse width shaping chip U4, the enable terminal AOE is connected to the passive network terminal of the core processing chip U7, the output terminal Q1 is connected to the output terminal of the core processing chip U7, and the output terminal Q2 is connected to the passive quenching active recovery module 17.

[0066] like Figures 1 to 4 As shown, in this embodiment, the current detection module 14 includes a current acquisition operational amplifier A1, a high-speed comparator CMP2, and a sampling resistor R1. The current acquisition operational amplifier A1 has a non-inverting input terminal, an inverting input terminal, and an output terminal. The high-speed comparator CMP2 has an input terminal and an output terminal.

[0067] One end of the sampling resistor R1 is connected to the high-voltage power supply terminal HV and the non-inverting input terminal of the current acquisition operational amplifier A1. The other end of the sampling resistor R1 is connected to the inverting input terminal of the current acquisition operational amplifier A1, the other end of the capacitor C1, and the cathode of the Si APD 11. The output terminal of the current acquisition operational amplifier A1 is connected to the input terminal of the high-speed comparator CMP2.

[0068] like Figures 1 to 4 As shown, in this embodiment, the quenching mode adaptive module 15 includes a high-speed logic OR chip U8, a high-speed electronic switch K1, a high-speed logic AND chip U9, and a clock fan-out buffer U2. The high-speed logic OR chip U8 has a first input terminal, a second input terminal, and an output terminal. The high-speed electronic switch K1 has a common terminal Z, a selection control terminal S, an output terminal Y0, and an output terminal Y1. The high-speed logic AND chip U9 has an input terminal INA, an input terminal INB, and an output terminal OUT. The clock fan-out buffer U2 has a clock input terminal ICLK, an enable terminal BOE, an output terminal Q3, and an output terminal Q4.

[0069] In this embodiment, the high-speed electronic switch is a single-pole double-throw analog electronic switch device. Under the conditions of VCC = 3.0V to 5.5V and load capacitance CL ≤ 50pF, the propagation delay between its common terminal and any input / output terminal is no greater than 1ns.

[0070] The high-speed logic OR chip is a single-channel two-input OR gate logic chip. Under the conditions of VCC = 3.3V and load capacitance CL ≈ 15pF, the maximum propagation delay from any input terminal to the output terminal is no greater than 3.6ns.

[0071] The high-speed logic AND chip is a single-channel two-input AND gate logic chip. Under the conditions of VCC=5.0V and load capacitance CL≈15pF, the typical propagation delay from any input terminal to the output terminal is about 3.5ns, and the maximum is no more than 10ns.

[0072] The high-speed logic OR chip U8 has its first input connected to the gating condition output of the core processing chip U7, used to input gating condition A. Its second input is connected to the output of the high-speed comparator CMP2, used to input gating condition B. The output is used to output a gating signal, and is connected to the selection control terminal S of the high-speed electronic switch K1 and the gating signal input of the core processing chip U7, respectively. The common terminal Z of the high-speed electronic switch K1 is directly connected to the anode of the Si APD 11. Its output Y0 is grounded, and its output Y1 is connected to the passive quenching active recovery module 17. The clock input ICLK of the clock fan-out buffer U2 is connected to the output Q# of the pulse width shaping chip U4, and its output Q3 is connected to the input INA of the high-speed logic AND chip U9. The output of the high-speed logic AND chip U9 is connected to the active quenching active recovery module 16.

[0073] In addition, the active network terminal of the core processing chip U7 is connected to the input terminal INB of the high-speed logic and chip U9; the passive network terminal of the core processing chip U7 is connected to the enable terminal AOE of the clock fan-out buffer U1 and the enable terminal BOE of the clock fan-out buffer U2.

[0074] Figure 5 This is a schematic diagram of the circuit connection of the active quenching and active recovery module in this embodiment.

[0075] like Figure 5 As shown, in this embodiment, the active quenching and active recovery module 16 includes transistors D5, D6, and D7, resistors R9 and R10, and a pulse width shaping chip U3. The pulse width shaping chip U3 has an input terminal IN, an output terminal Q, and an output terminal Q#.

[0076] In this circuit, the input terminal IN of the pulse width shaping chip U3 is connected to the output terminal OUT of the high-speed logic AND chip U9, and the output terminal Q is connected to the base of transistor D5. The collector of transistor D5 is connected to one end of resistor R9, the source of MOSFET D7, and the output terminal Y0 of high-speed electronic switch K1, while the emitter of transistor D5 is grounded. The other end of resistor R9 is grounded. The drain of MOSFET D7 is connected to a 24V power supply, and its gate is connected to one end of resistor R10 and the drain of MOSFET D6. The other end of resistor R10 is connected to a 12V power supply. The source of MOSFET D6 is grounded, and its gate is connected to the output terminal OUT of the high-speed logic AND chip U9 and the input terminal IN of the pulse width shaping chip U3.

[0077] Figure 6 This is a circuit connection diagram of the passive quenching and active recovery module in this embodiment.

[0078] like Figure 6As shown, in this embodiment, the passive quenching and active recovery module 17 includes Darlington transistor D1, Darlington transistor D2, diode D3, diode D4, quenching resistor Rq, resistor R5, resistor R6, resistor R7, and resistor R8.

[0079] In this circuit, one end of the quenching resistor Rq is connected to the output terminal Y1 of the high-speed electronic switch K1, the cathode of diode D4, and the collector of Darlington transistor D2. The other end of the quenching resistor Rq is connected to the cathode of diode D3 and the collector of Darlington transistor D1. The anode of diode D3 is connected to one end of resistor R7 and one end of resistor R8. The other end of resistor R7 serves as the QB terminal of this module and is connected to the output terminal Q4 of clock fan-out buffer U2. The other end of resistor R8 is grounded. The base of Darlington transistor D1 is connected to one end of resistor R8, and its emitter is grounded. The anode of diode D4 is connected to one end of resistor R5. The other end of resistor R5 serves as the QA terminal of this module and is connected to the output terminal Q2 of clock fan-out buffer U1. One end of resistor R6 is connected to one end of resistor R5 and the base of Darlington transistor D2, and the other end of resistor R6 is grounded. The emitter of Darlington transistor D2 is grounded.

[0080] When in use, the Si APD 11 detects photons and generates corresponding avalanche signals.

[0081] The analog-to-digital conversion module 12 extracts avalanche current from the cathode of the Si APD 11 and couples it to the sampling resistor R3 via capacitor C1 to generate a negative pulse avalanche signal. The high-speed comparator CMP1 uses a predetermined comparison threshold of "a negative value slightly higher than the minimum value of the negative pulse" to compare the negative pulse avalanche signal with the comparison threshold to determine whether an avalanche has occurred. When no avalanche has occurred, its positive output terminal Q outputs a high level; when an avalanche has occurred, its inverting output terminal Q# outputs a positive pulse. The high and low levels output by the high-speed comparator CMP1 trigger the pulse width shaping chip U4. The pulse width shaping chip U4 generates a pulse width adjustable counting signal and a negative pulse signal (the inverted signal of the counting signal, i.e., its output differential pair signal). The counting signal is sent to the counting module 13 and the passive quenching active recovery module 17 (QA terminal). The negative pulse signal is transmitted to the active quenching active recovery module 16 and the passive quenching active recovery module 17 (QB terminal) through the output terminals Q3 and Q4 of the clock fan-out buffer U2, respectively.

[0082] The comparison threshold is a negative voltage, which is higher than the minimum value of the negative pulse voltage but lower than 0V; preferably, the comparison threshold is 10% to 50% higher than the minimum value of the negative pulse voltage and is negative.

[0083] In the counting module 13, the counting signal is transmitted to the core processing chip U7 via the output terminal Q1 of the clock fan-out buffer U1. The core processing chip U7 counts the count value within a unit time (e.g., 1 second). When the count value is higher than the preset counting threshold, a gating condition A=1 is generated. When the count value is lower than or equal to the counting threshold, a gating condition A=0 is generated.

[0084] In the current detection module 14, the current acquisition operational amplifier A1 acquires the avalanche current on the sampling resistor R1 and converts it into an amplitude-adapted voltage signal. The high-speed comparator CMP2 compares the voltage signal with a preset voltage threshold. When the voltage signal is higher than the voltage threshold, a gating condition B=1 is generated. When the voltage signal is lower than or equal to the voltage threshold, a gating condition B=0 is generated.

[0085] In the quenching mode adaptive module 15, gating conditions A and B are input to the high-speed logic OR chip U8, and a gating signal is generated through a logic OR operation (i.e., gating signal = A / B). The core processing chip U7 synchronously outputs passive network signals and active network signals to coordinate the switching of the control mode.

[0086] Specifically, when the turn signal = 0, active = 1, passive = 0, the output terminal Q2 (i.e., QA terminal) of the clock output buffer U1 is disabled, and the output terminal Q4 (i.e., QB terminal) of the clock output buffer U2 is disabled; the high-speed logic and chip U9 transmits the inverted signal of the counting signal to the active quenching active recovery module 16, the common terminal Z of the high-speed electronic switch K1 (which is connected to the anode of Si APD11) and the output terminal Y0 are turned on, the passive quenching active recovery module 17 is disconnected from Si APD11, that is, the passive quenching active recovery module 17 is disabled, the detection system 10 enters the active quenching active recovery mode, and transmits the negative pulse signal (the inverted signal of the counting signal) to the active quenching active recovery module 16.

[0087] When the select signal = 1, active = 0, passive = 1, the output terminal Q2 (i.e. QA terminal) of clock output buffer U1 is enabled, and the output terminal Q4 (i.e. QB terminal) of clock output buffer U2 is enabled; the high-speed logic AND chip U9 blocks the signal transmission to the active quenching active recovery module 16, the common terminal Z of high-speed electronic switch K1 is connected to the output terminal Y1, the detection system 10 enters the passive quenching active recovery mode, the high-speed logic AND chip U9 is turned off, blocking the signal transmission, that is, the active quenching active recovery module 16 is disabled.

[0088] In active quenching and active recovery mode, the input terminal INA of the high-speed logic AND chip U9 of the active quenching and active recovery module 16 is connected to a negative pulse signal, and then a logical AND operation is performed between the negative pulse signal and the active network signal. When the active network signal is 1, the negative pulse signal is input to the two high-speed cascaded MOSFETs (i.e., D6 and D7) and the pulse width shaping chip U3. The two high-speed cascaded MOSFETs use the negative pulse signal as the turn-off signal of the front-stage MOSFET D6 and the turn-on signal of the rear-stage MOSFET D7. At the falling edge of the negative pulse, the preceding MOSFET D6 is turned off and the following MOSFET D7 is turned on to generate an active quenching signal. The active quenching signal raises the anode potential of Si APD 11, causing Si APD 11 to exit Geiger mode. At the rising edge of the negative pulse, the pulse width shaping chip U3 is triggered to output a positive pulse, which turns on the transistor D5 and pulls the anode potential of Si APD 11 to ground. This restores the bias voltage across Si APD 11 to above the avalanche breakdown voltage, and the detection system 100 returns to the detection state.

[0089] In passive quenching active recovery mode, a negative pulse signal is connected to one end (QB end) of resistor R7 of passive quenching active recovery module 17. During the detection phase, the output terminal Q4 of clock output buffer U2 (to the QB network) outputs a high level, causing Darlington transistor D1 to conduct and ground; the output terminal Q2 of clock output buffer U1 (to the QA network) outputs a low level, causing Darlington transistor D2 to turn off. The anode of Si APD 11 is grounded through quenching resistor Rq and the conducting Darlington transistor D1. Since the equivalent resistance of Si APD 11 is much greater than the resistance of quenching resistor Rq, most of the high voltage HV is applied across Si APD 11 and is higher than its avalanche breakdown voltage, causing Si APD 11 to enter Geiger mode. During the avalanche phase, after photons incident on the Si APD 11 trigger an avalanche, the equivalent resistance of the Si APD 11 is much smaller than the resistance of the quenching resistor Rq. Most of the high voltage HV is transferred to both ends of the quenching resistor Rq, and the high voltage across the Si APD 11 drops below its avalanche breakdown voltage, terminating the avalanche process and achieving passive quenching, causing the Si APD 11 to exit Geiger mode. During the recovery phase, the avalanche signal from the Si APD 11 cathode is processed by the analog-to-digital converter module 12 to generate a counting signal, triggering the QA and QB networks to output a low level. Darlington transistor D2 is turned on, and Darlington transistor D1 is turned off. The anode potential of the Si APD 11 is instantaneously pulled to ground by the turned-on Darlington transistor D2. Subsequently, the Si APD 11 regains a high voltage higher than the avalanche breakdown voltage, re-enters Geiger mode, and returns to the detection state.

[0090] The detection system 10 initially operates in active quenching and active recovery mode.

[0091] In low-light scenarios (when the incident light is weak), the counting module 13 determines that the counting result is lower than the counting threshold and outputs the gating condition A=0. The current detection module 14 determines that the voltage corresponding to the avalanche current is lower than the voltage threshold and outputs the gating condition B=0. The quenching mode adaptive module 15 obtains the gating signal = 0 through a logical OR operation based on the gating conditions A and B. The core processing chip U7 outputs the network signal active=1 and passive=0 based on the gating signal. The detection system 10 enters the active quenching and active recovery mode. The active quenching and active recovery module 16 realizes the active quenching and active recovery of Si APD 11. The active quenching signal is output through the cascaded MOS transistor to terminate the avalanche, and the anode potential of Si APD 11 is pulled down through the conducting transistor D5. The detection system 10 returns to the detection state.

[0092] In strong light scenarios (such as single-pulse multi-photon or single-photon high-density incident scenarios), the counting module 13 determines that the counting result is higher than the counting threshold and outputs the gating condition A=1, and / or the current detection module 14 determines that the voltage corresponding to the avalanche current is higher than the voltage threshold and outputs the gating condition B=1. That is, when either the gating condition A or the gating condition B is 1, the quenching mode adaptive module 15 outputs the gating signal = 1 according to the gating condition A and the gating condition B. The core processing chip U7 outputs the network signal active=0 and passive=1 according to the gating signal. The detection system 10 enters the passive quenching and active recovery mode. The passive quenching and active recovery module 17 realizes the passive quenching and active recovery of Si APD 11. After the avalanche occurs, the passive quenching is achieved by voltage division through the quenching resistor Rq, and the anode potential of Si APD 11 is pulled down by the conducting Darlington transistor D2. The detection system 10 returns to the detection state.

[0093] If the incident light intensity subsequently decreases, similarly, the gating signal changes from 1 to 0, the high-speed electronic switch K1 disconnects from the passive quenching active recovery module 17 and switches to ground connection. At the same time, the active network is set to 1 and the passive network is set to 0, and the detection system 10 switches from passive quenching active recovery mode to active quenching active recovery mode.

[0094] The role and effect of the embodiments

[0095] The adaptive high-count-rate silicon-based single-photon avalanche photodetector system provided in this embodiment, due to its silicon-based single-photon avalanche photodiode, analog-to-digital conversion module, counting module, current detection module, active quenching and active recovery module, passive quenching and active recovery module, and quenching mode adaptive module, can generate a first gating condition by counting avalanche signals through the counting module, generate a second gating condition by extracting avalanche current through the current detection module, and generate a gating signal based on the first and second gating conditions through the quenching mode adaptive module. This achieves adaptive switching between active quenching and active recovery modes and passive quenching and active recovery modes, effectively overcoming the performance limitations of existing technologies. In low-light scenarios, the active quenching and active recovery mode can be maintained to ensure high detection sensitivity; while in high-light scenarios, it can switch to the passive quenching and active recovery mode to quickly terminate avalanches, thereby significantly shortening the quenching time and ensuring a high count rate. Combining the two modes and adaptive switching, stable detection across the entire light intensity range can be achieved.

[0096] Compared with existing technologies, this approach solves two main problems. First, it addresses the inherent lower limit of dead time in traditional active quenching circuits due to logic chip response delays, and the inability to meet the high-current rapid quenching requirements under strong light. In strong light scenarios, it switches to a passive quenching and active recovery mode. In this mode, there is no need for active circuits such as comparators and logic gates. Instead, avalanche termination is achieved through rapid voltage division by the quenching resistor, resulting in no response delay and significantly shortening the quenching time. Second, it avoids the drawbacks of adaptive quenching schemes that rely on special functional materials, such as difficulty in material acquisition, high cost, and the need for customized adaptation. The detection system can be built using conventional analog integrated circuits (high-speed comparators, logic chips, electronic switches, etc.), which are highly versatile and can be easily adapted to different models of Si APDs.

[0097] In summary, the detection system of this embodiment effectively solves the problems of bottlenecks in count rate improvement (limitation of active mode dead zone), insufficient versatility (special material scheme), and poor light intensity adaptability (single quenching mode) of traditional detectors by dynamically and adaptively adjusting the quenching method, and significantly improves the maximum count rate and detection stability of silicon-based single-photon avalanche photodetector system.

[0098] The above embodiments are merely illustrative of specific implementations of the present invention, and the present invention is not limited to the scope of the description of the above embodiments. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are only for illustrating the principles of the present invention. Various changes and modifications can be made to the present invention without departing from the spirit and scope thereof, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. An adaptive high-count-rate silicon-based single-photon avalanche photodetector system, characterized in that, include: Silicon-based single-photon avalanche photodiodes are used to detect photons and acquire avalanche signals. An analog-to-digital converter module is used to convert the avalanche signal into a digital signal, which includes a counting signal; The counting module is used to count the number of the counting signals per unit time and generate a first gating condition based on the counting result and a predetermined counting threshold. The current detection module is used to detect the avalanche current of the silicon-based single-photon avalanche photodiode to obtain the corresponding voltage, and generate a second gating condition based on the voltage and a predetermined voltage threshold. An active quenching and active recovery module is used to realize the active quenching and active recovery of the silicon-based single-photon avalanche photodiode; The passive quenching and active recovery module is used to realize the passive quenching and active recovery of the silicon-based single-photon avalanche photodiode. as well as The quenching mode adaptive module generates a gating signal based on the first gating condition and the second gating condition, and controls one of the active quenching active recovery module and the passive quenching active recovery module to work and the other to be disabled based on the gating signal, thereby enabling the system to enter the active quenching active recovery mode or the passive quenching active recovery mode.

2. The adaptive high count rate silicon-based single-photon avalanche photodetector system according to claim 1, characterized in that: in, The system initially operates in the active quenching and active recovery mode. When the counting result is lower than or equal to the counting threshold and the voltage corresponding to the avalanche current is lower than or equal to the voltage threshold, the quenching mode adaptive module enables the system to operate in the active quenching and active recovery mode. When the counting result is higher than the counting threshold and / or the voltage corresponding to the avalanche current is higher than the voltage threshold, the quenching mode adaptive module enables the system to operate in the passive quenching active recovery mode.

3. The adaptive high count rate silicon-based single-photon avalanche photodetector system according to claim 2, Its features are: in, The analog-to-digital conversion module includes: Capacitor C1 and sampling resistor R3 are connected to the silicon-based single-photon avalanche photodiode to generate a negative pulse avalanche signal; A high-speed comparator CMP1 is used to compare the avalanche signal with a predetermined comparison threshold to determine whether an avalanche has occurred, and output a corresponding level; and The pulse width shaping chip U4 generates the pulse width-adjustable counting signal based on the output of the high-speed comparator CMP1. The counting module includes at least: The core processing chip U7 is used to count the number of the counting signals per unit time and generate the first gating condition based on the counting results. The current detection module includes: The sampling resistor R1 is connected to the silicon-based single-photon avalanche photodiode. Current acquisition operational amplifier A1 is used to sample the avalanche current on the sampling resistor R1 and convert it into a voltage signal; and The high-speed comparator CMP2 is used to compare the voltage signal with the voltage threshold and generate the second gating condition based on the comparison result. The adaptive quenching mode module includes: A high-speed logic OR chip U8 is used to perform a logic OR operation on the first gating condition and the second gating condition to obtain the gating signal; High-speed logic and chip U9 are used to connect or disconnect the active quenching and active recovery module based on the strobe signal; and A high-speed electronic switch K1 is used to connect or disconnect the passive quenching active recovery module based on the gating signal.

4. The adaptive high count rate silicon-based single-photon avalanche photodetector system according to claim 3, characterized in that: in, The core processing chip U7 is also used to output active network signals and passive network signals based on the gating signal. The high-speed logic and chip U9 connects or disconnects the active quenching and active recovery module and the silicon-based single-photon avalanche photodiode based on the active network signal. The pulse width shaping chip U4 also generates an inverted signal of the counting signal as a negative pulse signal. The counting module also includes a clock output buffer U1, which transmits the counting signal to the core processing chip and the passive quenching active recovery module, or blocks the signal, based on the passive network signal. The quenching mode adaptive module also includes a clock output buffer U2, which transmits the negative pulse signal to the active quenching active recovery module and the passive quenching active recovery module respectively based on the passive network signal, or blocks the signal.

5. The adaptive high count rate silicon-based single-photon avalanche photodetector system according to claim 4, characterized in that: in, In the analog-to-digital conversion module, the high-speed comparator CMP has a non-inverting input terminal, an inverting input terminal, and an output terminal Q#, and the pulse width shaping chip U4 has an input terminal IN, an output terminal Q, and an output terminal Q#. One end of the sampling resistor R3 is grounded, and the other end of the sampling resistor R3 is connected to one end of the capacitor C1 and the non-inverting input of the high-speed comparator CMP1. The output Q# of the high-speed comparator CMP1 is connected to the input IN of the pulse width shaping chip U4. The other end of the capacitor C1 is connected as a signal coupling terminal to the cathode of the silicon-based single-photon avalanche photodiode. The output Q of the pulse width shaping chip U4 is connected to the clock input of the clock output buffer U1, and the output Q# of the pulse width shaping chip U4 is connected to the clock input of the clock output buffer U2.

6. The adaptive high count rate silicon-based single-photon avalanche photodetector system according to claim 4, characterized in that: in, In the counting module, the clock output buffer U1 has a clock input terminal ICLK, an enable terminal AOE, an output terminal Q1, and an output terminal Q2. The core processing chip U7 is an FPGA, which has a gating condition output terminal, a gating signal input terminal, an active network terminal, a passive network terminal, and an output terminal. The clock input terminal ICLK of the clock output buffer U1 is connected to the output terminal Q of the pulse width shaping chip U4. The enable terminal AOE of the clock output buffer U1 is connected to the passive network terminal of the core processing chip U7. The output terminal Q1 of the clock output buffer U1 is connected to the output terminal of the core processing chip U7. The output terminal Q2 of the clock output buffer U1 is connected to the passive quenching active recovery module. The gating condition output terminal of the core processing chip U7 is connected to the input terminal of the high-speed logic OR chip, the gating signal input terminal of the core processing chip U7 is connected to the output terminal of the high-speed logic OR chip, the active network terminal of the core processing chip U7 is connected to the input terminal INB of the high-speed logic OR chip U9, and the passive network terminal of the core processing chip U7 is connected to the enable terminal AOE of the clock fan-out buffer U1 and the enable terminal BOE of the clock fan-out buffer U2, respectively.

7. The adaptive high count rate silicon-based single-photon avalanche photodetector system according to claim 4, characterized in that: in, In the current detection module, the current acquisition operational amplifier A1 has a non-inverting input terminal, an inverting input terminal, and an output terminal, and the high-speed comparator CMP2 has an input terminal and an output terminal. One end of the sampling resistor R1 is connected to the high-voltage power supply terminal and the non-inverting input terminal of the current acquisition operational amplifier A1, respectively. The other end of the sampling resistor R1 is connected to the inverting input terminal of the current acquisition operational amplifier A1, the other end of the capacitor C1, and the cathode of the silicon-based single-photon avalanche photodiode, respectively. The output terminal of the current acquisition operational amplifier A1 is connected to the input terminal of the high-speed comparator CMP2.

8. The adaptive high count rate silicon-based single-photon avalanche photodetector system according to claim 7, characterized in that: in, In the adaptive quenching mode module, the high-speed logic and control chip U9 has a first input terminal, a second input terminal, and an output terminal; the high-speed electronic switch K1 has a common terminal Z, a selection control terminal S, an output terminal Y0, and an output terminal Y1; the high-speed logic and control chip U9 has an input terminal INA, an input terminal INB, and an output terminal OUT; and the clock fan-out buffer U2 has a clock input terminal ICLK, an enable terminal BOE, an output terminal Q3, and an output terminal Q4. The first input terminal of the high-speed logic OR chip U8 is connected to the gating condition output terminal of the core processing chip U7. The second input terminal of the high-speed logic OR chip U8 is connected to the output terminal of the high-speed comparator CMP2. The output terminal of the high-speed logic OR chip U8 is connected to the selection control terminal S of the high-speed electronic switch K1 and the gating signal input terminal of the core processing chip U7. The common terminal Z of the high-speed electronic switch K1 is directly connected to the anode of the silicon-based single-photon avalanche photodiode. The output terminal Y0 of the high-speed electronic switch K1 is grounded. The output terminal Y1 of the high-speed electronic switch K1 is connected to the passive quenching active recovery module. The output terminal Q3 of the clock fan-out buffer U2 is connected to the input terminal INA of the high-speed logic AND chip U9. The output terminal of the high-speed logic AND chip U9 is connected to the active quenching active recovery module.

9. The adaptive high count rate silicon-based single-photon avalanche photodetector system according to claim 8, characterized in that: in, The active quenching and active recovery module includes transistor D5, MOSFET D6, MOSFET D7, resistor R9, resistor R10, and pulse width shaping chip U3. The pulse width shaping chip U3 has an input terminal IN, an output terminal Q, and an output terminal Q#. The input terminal IN of the pulse width shaping chip U3 is connected to the output terminal OUT of the high-speed logic AND chip U9. The output terminal Q of the pulse width shaping chip U3 is connected to the base of the transistor D5. The collector of the transistor D5 is connected to one end of the resistor R9, the source of the MOSFET D7, and the output terminal Y0 of the high-speed electronic switch K1. The emitter of the transistor D5 is grounded, and the other end of the resistor R9 is grounded. The drain of the MOSFET D7 is connected to the power supply. The gate of the MOSFET D7 is connected to one end of the resistor R10 and the drain of the MOSFET D6. The other end of the resistor R10 is connected to the power supply. The source of the MOSFET D6 is grounded, and the gate of the MOSFET D6 is connected to the output terminal OUT of the high-speed logic AND chip U9 and the input terminal IN of the pulse width shaping chip U3.

10. The adaptive high count rate silicon-based single-photon avalanche photodetector system according to claim 8, characterized in that: in, The passive quenching and active recovery module includes Darlington transistors D1 and D2, diodes D3 and D4, quenching resistors Rq, R5, R6, R7, and R8. One end of the quenching resistor Rq is connected to the output terminal Y1 of the high-speed electronic switch K1, the cathode of the diode D4, and the collector of the Darlington transistor D2. The other end of the quenching resistor Rq is connected to the cathode of the diode D3 and the collector of the Darlington transistor D1. The anode of the diode D3 is connected to one end of the resistor R7 and one end of the resistor R8. The other end of the resistor R7 is connected to the output terminal Q4 of the clock fan-out buffer U2. The other end of the resistor R8 is grounded. The base of the Darlington transistor D1 is connected to one end of the resistor R8. The emitter of the Darlington transistor D1 is grounded. The anode of the diode D4 is connected to one end of the resistor R5. The other end of the resistor R5 is connected to the output terminal Q2 of the clock fan-out buffer U1. One end of the resistor R6 is connected to one end of the resistor R5 and the base of the Darlington transistor D2. The other end of the resistor R6 is grounded. The emitter of the Darlington transistor D2 is grounded.

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