Chip packaging box electrical characteristic test method

Abstract

The invention discloses a method for testing electrical characteristics of a chip packaging box. The method comprises the following steps: providing a box to be tested; adjacent signal channels in the packaging box are connected through bonding wires to form a signal channel test unit or an integral test module; connecting a test system and acquiring a first insertion loss parameter; and calculating a fourth insertion loss parameter of each signal channel by combining the second insertion loss parameter of the bonding wire and the third insertion loss parameter of the connecting cable. According to the method, the high-frequency defects are accurately diagnosed, the performance bottleneck is positioned, the industrial pain points that a traditional method cannot evaluate the high-frequency characteristics and cannot distinguish whether the problem is from a chip or a packaging box are thoroughly solved, and the design optimization efficiency and the product quality control level of the packaging box are greatly improved.

Description

Technical Field

[0001] This invention belongs to the field of electronic device testing technology, specifically relating to a method for testing the electrical characteristics of a chip package. Background Technology

[0002] In quantum computers, the chip package plays a crucial role in signal transmission, electromagnetic wave shielding, and mechanical support. To achieve the expected performance of the entire quantum computer system, it is essential to first evaluate the reflection and transmission characteristics of the chip package, i.e., the S-parameters. However, traditional methods for evaluating reflection and transmission characteristics are limited in their ability to measure the package's connection methods. Specifically, traditional methods use a multimeter to measure the DC resistance of the quantum chip package to determine the continuity of the circuitry within the package. The quantum chip is then assembled into the package for testing. However, in practical applications, this testing method cannot definitively determine whether the problem lies with the chip, the package, or the bonding wires after obtaining the test results, making it impossible to pinpoint the root cause and thus hindering the evaluation of the package's performance.

[0003] In related technologies, the quantum chip is packaged in another slot inside a box and connected to the signal line by wire bonding. Then it is connected to test instruments and equipment to test the effect of wire bonding on the quantum chip. However, the performance of the packaging box still cannot be evaluated. Summary of the Invention

[0004] The purpose of this invention is to propose a method for testing the electrical characteristics of chip packages to solve the problems in the prior art.

[0005] Therefore, the present invention provides a method for testing the electrical characteristics of a chip package, comprising: Provide a test box; The adjacent signal channels of the test box are connected sequentially by bonding wires, and two adjacent signal channels constitute a signal channel test unit. Each of the signal channel test units is connected to the test system via a connecting cable and tested sequentially. The first insertion loss parameter of the current signal channel test unit is obtained sequentially based on the test signal. The second insertion loss parameter of the bonding wire and the third insertion loss parameter of the connecting cable are obtained respectively. Based on the first insertion loss parameter, the second insertion loss parameter, and the third insertion loss parameter corresponding to each of the signal channel test units, a fourth insertion loss parameter is obtained for each signal channel in each of the signal channel test units.

[0006] In one embodiment, each of the signal channel test units is connected to the test system via a connecting cable to determine whether resonance occurs. If resonance occurs, the connection point between the connecting cable and the signal channel is adjusted.

[0007] In one embodiment, determining whether resonance occurs includes: If the first insertion loss parameter displayed by the test system shows a dip or a rapid drop at a frequency point, it indicates that resonance exists; otherwise, resonance does not exist.

[0008] In one embodiment, the test system is calibrated before each signal channel unit is connected to the test system via a test cable. The calibration includes: Set the test power and number of test points for the test system; Connect the calibration piece to the test system; Press the test system calibration button to perform calibration.

[0009] In one embodiment, the test system includes a vector network analyzer and a test cable. During calibration, one end of the calibration device is connected to the vector network analyzer, and the other end of the calibration device is connected to the test cable.

[0010] In one embodiment, obtaining the third insertion loss parameter of the connecting cable includes: Connect the connecting cable to the calibrated test system and read the third insertion loss parameter displayed in the test system.

[0011] In one embodiment, obtaining the second insertion loss parameter of the bonding wire includes: A simulation model with the same geometric parameters as the test box is established, and the second insertion loss parameter of the bonding wire is calculated through the simulation model.

[0012] In one embodiment, obtaining a fourth insertion loss parameter for each signal channel in each signal channel test unit, based on the first insertion loss parameter, the second insertion loss parameter, and the third insertion loss parameter corresponding to each signal channel test unit, includes: Fourth insertion loss parameter = First insertion loss parameter / 2 - Second insertion loss parameter - Third insertion loss parameter.

[0013] A method for testing the electrical characteristics of a chip package is also provided, including: Provide a test box; Adjacent signal channels of the test box are connected by bonding wires, and two signal channels constitute a signal channel test unit. Each of the signal channel test units is connected sequentially via a connecting cable to form a signal channel test module. The two ends of the signal channel test unit module are connected to the test system via connecting cables and tested. The first insertion loss parameter of the signal channel test module is obtained based on the test signal. The second insertion loss parameter of the bonding wire and the third insertion loss parameter of the connecting cable are obtained respectively. Based on the first insertion loss parameter, the second insertion loss parameter, and the third insertion loss parameter of the signal channel test module, and the number of signal channels in the signal channel test module, a fourth insertion loss parameter is obtained for each signal channel.

[0014] In one embodiment, obtaining a fourth insertion loss parameter for each signal channel in each signal channel test unit, based on the first insertion loss parameter, the second insertion loss parameter, and the third insertion loss parameter corresponding to each signal channel test unit, includes: The fourth insertion loss parameter = (first insertion loss parameter - (N-1) second insertion loss parameter - third insertion loss parameter) / N, where N is the number of signal channels.

[0015] Beneficial effects: 1. This invention constructs a complete high-frequency test loop using a vector network analyzer, chip packaging, and cables. It sequentially or directly tests all signal channels within the packaging and obtains the corresponding total test results. The impact of insertion loss caused by bonding wires or cables is removed from the total measurement results, allowing for more accurate extraction of single-channel insertion loss of the packaging itself at high frequencies. This enables accurate diagnosis of high-frequency defects and location of performance bottlenecks, completely solving the industry pain point that traditional methods cannot assess high-frequency characteristics and cannot distinguish whether the problem originates from the chip or the packaging. This greatly improves the efficiency of packaging design optimization and the level of product quality control.

[0016] 2. This invention integrates a vector network analyzer, test cables, and connecting cable system into a single test system to achieve complete link performance characterization of quantum chip packaging boxes under high-frequency signals. It can effectively evaluate the overall electrical characteristics, including the gold fingers, internal transmission lines, and connectors, providing direct and reliable experimental data support for the design verification, fault diagnosis, and performance optimization of the packaging box. This overcomes the limitation of traditional DC testing, which cannot reflect high-frequency performance.

[0017] 3. By calibrating the vector network analyzer and test cables, this invention effectively eliminates the inherent errors of the test system itself, thereby ensuring the accuracy and reliability of the parameter data measured on the package link, and providing a real and reliable benchmark for quantitatively evaluating the high-frequency electrical characteristics of the package. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart illustrating a method for testing the electrical characteristics of a chip package according to the present invention.

[0020] Figure 2 This is a schematic diagram of the chip package electrical characteristic testing system provided by the present invention.

[0021] Figure 3 This is a schematic diagram of the internal wiring of the chip package provided by the present invention.

[0022] Figure 4 This is a schematic diagram showing the gold fingers connected by bonding wires in the chip package provided by the present invention.

[0023] Figure 5 This is a flowchart illustrating another method for testing the electrical characteristics of a chip package provided by the present invention.

[0024] In the diagram: 1. Vector network analyzer; 2. Test cable; 3. Connecting cable; 4. Package box; 5. Bonding wire; 6. Gold fingers. Detailed Implementation

[0025] The invention will be more readily understood by referring to the following detailed description of preferred embodiments and included examples. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. In case of conflict, the definitions in this specification shall prevail.

[0026] This invention provides a method for testing the electrical characteristics of chip packaging boxes, which solves the problem in the prior art where, when problems occur during the use of the packaging box, it is impossible to directly determine whether the cause is the chip, the packaging box, or the bonding between the two. Furthermore, it is impossible to directly evaluate the performance of the packaging box, which in turn affects the prediction of the performance of quantum computers and seriously hinders the development and use of quantum computers.

[0027] The technical concept of this invention is to construct a complete high-frequency test loop by using a vector network analyzer, chip packaging box, and cables, to test all signal channels in the packaging box sequentially or directly and obtain the corresponding total test results. The influence of external factors, such as insertion loss caused by bonding wires or cables, is removed from the total measurement results to accurately extract the single-channel insertion loss of the packaging box itself at high frequency, thereby more accurately characterizing the performance of the packaging box.

[0028] like Figure 1-4 As shown, the present invention provides a method for testing the electrical characteristics of a chip package, comprising: Provide a test box, i.e., a packaging box 4; like Figure 4 As shown, adjacent signal channels within the package 4 are sequentially connected by bonding wires 5, with each pair of adjacent signal channels forming a signal channel test unit. Specifically, each signal channel corresponds to a gold finger 6, and the gold fingers 6 are interconnected via bonding wires 5. When connecting adjacent signal channels within the package 4 by bonding wires 5, select the channel to be tested, remove the cover of the package 4, locate the corresponding package connector and gold finger number, and use a bonding machine to connect the gold fingers 6 of adjacent channels via bonding wires 5. It should be noted that each gold finger 6 corresponds to one signal channel, as shown in the figure. After bonding, the connection of the bonding wires 5 is checked under a microscope for magnification to ensure it is secure, serving as a test piece.

[0029] like Figure 2 As shown, each signal channel test unit is connected to the test system via connecting cable 3, and tested sequentially. The first insertion loss parameter of the current signal channel test unit is obtained based on the test signal. Specifically, the port of the vector network analyzer 1 is connected to the signal channel test unit of the package box 4, and then the connection test is performed. After the test is completed, the parameter data is recorded; this parameter data is the S-parameter. It should be noted that the first insertion loss parameter needs to be obtained under signal conduction conditions, and signal conduction is indicated by the |S-parameter| displayed on the vector network analyzer 1. 21 The parameters showed continuous and stable changes with frequency, and no obvious abnormal test values ​​were observed.

[0030] The second insertion loss parameter of the bonding wire 5 and the third insertion loss parameter of the connecting cable 3 are obtained respectively. Based on the first, second, and third insertion loss parameters corresponding to each signal channel test unit, the fourth insertion loss parameter for each signal channel in each signal channel test unit is obtained. It should be noted that the second and third insertion loss parameters are the insertion losses of the package 4 itself. By excluding the insertion loss data of the package 4, that is, the insertion loss data of the bonding wire 5 and the insertion loss of the connecting cable 3, the single-channel insertion loss of the package 4 itself can be accurately extracted, which can truly reflect the real performance indicators of the entire package 4 and realize the direct evaluation of the high-frequency electrical characteristics of the package 4 itself.

[0031] In one embodiment, the test system is calibrated before each signal channel unit is connected to the test system via test cable 2. The calibration includes: Set the test power and number of test points for the test system; The calibration component is connected to the test system, which includes a vector network analyzer 1 and a test cable 2. During calibration, one end of the calibration component is connected to the vector network analyzer 1, and the other end of the calibration component is connected to the test cable 2.

[0032] Press the test system calibration button to perform calibration.

[0033] Specifically, before testing package 4, it is necessary to avoid the influence of external interference (insertion loss) from the vector network analyzer 1 on the error of package 4 detection. Set the test power of the vector network analyzer 1 to -10dBm, and set the test frequency starting point according to the test bandwidth of package 4 and the test frequency range of the calibration component. The number of test points should be 401 or 801. The number of test points refers to the number of frequency points at which the vector network analyzer 1 collects data when measuring within a specified frequency range, such as -10dBm. After setting the above parameters, connect one end of the calibration component to the vector network analyzer 1, and connect the other end of the test cable 2 to the calibration component. After connection, the connector green light will illuminate. Press the calibration button on the vector network analyzer 11, select electronic calibration, 2-port calibration, and complete the calibration. To verify successful calibration, connect both ends of the test cable 2 and check if the displayed value of the vector network analyzer 11 is 0. If it is 0, the calibration is successful; if not, readjust and recalibrate. Simultaneously... In one embodiment, when connecting test cable 2 and connecting cable 3, if the cable connectors at the cable joints are the same, such as both being male or both being female, an adapter can be used to connect one of them to achieve normal connection between test cable 2 and connecting cable 3.

[0034] In one embodiment, obtaining the third insertion loss parameter of the connecting cable 3 includes: Connect the connecting cable 3 to the calibrated test system and read the third insertion loss parameter displayed in the test system. Alternatively, connect the connecting cable 3 to both ends of the calibrated test cable 2 and test the S-parameters of the connecting cable 3 to obtain the third insertion loss parameter of the connecting cable 3.

[0035] In one embodiment, obtaining the second insertion loss parameter of the bonding wire 5 includes: establishing a simulation model with the same geometric parameters as the test box, and calculating the second insertion loss parameter of the bonding wire 5 through the simulation model. Since insertion loss is essentially the loss of electromagnetic wave energy during transmission, the simulation software can input an electromagnetic wave signal with known power and Gaussian frequency band into one port of the model. The software will calculate how this electromagnetic wave propagates, reflects, and radiates in the three-dimensional model, and then calculate the received power at another port of the model. The insertion loss can be directly calculated, and since this calculation method is based on the fundamental physical laws of electromagnetic fields, it has high reliability.

[0036] In one embodiment, each signal channel test unit is connected to the test system via connecting cable 3 to determine if resonance occurs. If resonance occurs, the connection point between connecting cable 3 and the signal channel is adjusted. Specifically, before testing the insertion loss of the signal channel, it is necessary to ensure that there is no resonance. Before testing, the connecting cable 3 connected to the package 4 is slightly shaken to check for resonance. If the vector network analyzer 1 displays |S 21 The parameter exhibits a noticeable dip at a certain frequency point, or |S 21 If a rapid drop occurs, resonance is present. This indicates a misconnection between the connector of surface-mount cable 3 and the interior of the enclosure 4. Adjustment is needed to stabilize the connection. If no resonance occurs during shaking, continue testing the enclosure 4 as described above. In summary, by slightly shaking the cable and observing the S-parameter curve for resonance, potential defects such as unreliable mechanical connections and cold solder joints in connectors and solder joints can be sensitively detected.

[0037] In one embodiment, obtaining the fourth insertion loss parameter for each signal channel in each signal channel test unit based on the first insertion loss parameter, the second insertion loss parameter, and the third insertion loss parameter corresponding to each signal channel test unit includes: The fourth insertion loss parameter = (first insertion loss parameter / 2) - (second insertion loss parameter) - (third insertion loss parameter). The fourth insertion loss parameter is the single-channel insertion loss within package 4, accurately reflecting the performance of package 4.

[0038] like Figure 5 As shown, on the other hand, a method for testing the electrical characteristics of a chip package is also provided, including: Provide a test box; The adjacent signal channels of the test box are connected by bonding wire 5, and the two signal channels constitute a signal channel test unit. Each signal channel test unit is connected sequentially via a connecting cable to form a signal channel test module. The two ends of the signal channel test unit module are connected to the test system via connecting cable 3 and tested. The first insertion loss parameter of the signal channel test module is obtained based on the test signal. Obtain the second insertion loss parameter of the bonding wire 5 and the third insertion loss parameter of the connecting cable 3 respectively; Based on the first, second, and third insertion loss parameters of the signal channel test module, and the number of signal channels in the signal channel test module, a fourth insertion loss parameter for each signal channel is obtained.

[0039] Specifically, in this embodiment, signal channel one is connected to one port of the vector network analyzer 1, signal channel N is connected to another port of the vector network analyzer 1, and the remaining signal channels are connected sequentially using bonding wires 5. For example, signal channel two is connected to signal channel three, signal channel four is connected to signal channel N, and so on. After connection, a test is performed. If the signal channel is connected, it indicates that all bonding wires 5 and connecting lines are conducting well, and the test data is recorded. If the signal is not conducting, the connection of the bonding wires 5 and the connection of the cables need to be checked. After checking and confirming normal conduction, the test is repeated.

[0040] In one embodiment, obtaining the fourth insertion loss parameter for each signal channel in each signal channel test unit based on the first insertion loss parameter, the second insertion loss parameter, and the third insertion loss parameter corresponding to each signal channel test unit includes: The fourth insertion loss parameter = (first insertion loss parameter - (N-1) second insertion loss parameter - third insertion loss parameter) / N, where N is the number of signal channels. This method has higher testing efficiency and can quickly verify the connection status of all bond wires 5. The second insertion loss parameter represents the insertion loss value of a single bond wire, but in the entire test path, there are actually N-1 bond wires, so the total bond wire insertion loss value should be the insertion loss of a single bond wire * (N-1). For example, if there are 5 signal channels, the connection method should be: signal channel 1 - bond wire - signal channel 2 - bond wire - signal channel 3 - bond wire - signal channel 4 - bond wire - signal channel 5, that is, adjacent signal channels are connected by one bond wire.

[0041] Compared to traditional package 4 testing methods, the above method covers testing of the signal channel, i.e., the gold fingers 6. Furthermore, the gold fingers 6 are connected using bonding wires 5, forming a complete test of the entire package 4 link, which more accurately reflects the high-frequency performance of the entire link. Moreover, after eliminating insertion losses outside the package 4 itself, the performance of the package 4 can be evaluated. When a problem occurs in a certain signal channel, the root cause can be identified, accelerating the technological iteration of the package 4.

[0042] In some embodiments, the electrical characteristic testing method of the package structure that also includes connectors and gold fingers can be used as an alternative or optimization of the present invention.

[0043] Finally, it should be noted that the above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for testing the electrical characteristics of a chip package, characterized in that, include: Provide a test box; The adjacent signal channels of the test box are connected sequentially by bonding wires, and two adjacent signal channels constitute a signal channel test unit. Each of the signal channel test units is connected to the test system via a connecting cable and tested sequentially. The first insertion loss parameter of the current signal channel test unit is obtained sequentially based on the test signal. The second insertion loss parameter of the bonding wire and the third insertion loss parameter of the connecting cable are obtained respectively. Based on the first insertion loss parameter, the second insertion loss parameter, and the third insertion loss parameter corresponding to each of the signal channel test units, a fourth insertion loss parameter is obtained for each signal channel in each of the signal channel test units.

2. The test method according to claim 1, characterized in that, Each of the signal channel test units is connected to the test system via a connecting cable to determine whether resonance occurs. If resonance occurs, the connection point between the connecting cable and the signal channel is adjusted.

3. The test method according to claim 2, characterized in that, Determining whether resonance occurs includes: If the first insertion loss parameter displayed by the test system shows a dip or a rapid drop at a frequency point, it indicates that resonance exists; otherwise, resonance does not exist.

4. The test method according to claim 1, characterized in that, Before connecting each of the signal channel units to the test system via test cables, the test system is calibrated, and the calibration includes: Set the test power and number of test points for the test system; Connect the calibration piece to the test system; Press the test system calibration button to perform calibration.

5. The test method according to claim 4, characterized in that, The testing system includes a vector network analyzer and test cables. During calibration, one end of the calibration device is connected to the vector network analyzer, and the other end of the calibration device is connected to the test cables.

6. The test method according to claim 4, characterized in that, Obtaining the third insertion loss parameter of the connecting cable includes: Connect the connecting cable to the calibrated test system and read the third insertion loss parameter displayed in the test system.

7. The test method according to claim 1, characterized in that, Obtaining the second insertion loss parameter of the bonding wire includes: A simulation model with the same geometric parameters as the test box is established, and the second insertion loss parameter of the bonding wire is calculated through the simulation model.

8. The test method according to claim 1, characterized in that, Based on the first insertion loss parameter, the second insertion loss parameter, and the third insertion loss parameter corresponding to each of the signal channel test units, the fourth insertion loss parameter for each signal channel in each of the signal channel test units is obtained as follows: Fourth insertion loss parameter = First insertion loss parameter / 2 - Second insertion loss parameter - Third insertion loss parameter.

9. A method for testing the electrical characteristics of a chip package, characterized in that, include: Provide a test box; Adjacent signal channels of the test box are connected by bonding wires, and two signal channels constitute a signal channel test unit. Each of the signal channel test units is connected sequentially via a connecting cable to form a signal channel test module. The two ends of the signal channel test unit module are connected to the test system via connecting cables and tested. The first insertion loss parameter of the signal channel test module is obtained based on the test signal. The second insertion loss parameter of the bonding wire and the third insertion loss parameter of the connecting cable are obtained respectively. Based on the first insertion loss parameter, the second insertion loss parameter, and the third insertion loss parameter of the signal channel test module, and the number of signal channels in the signal channel test module, a fourth insertion loss parameter is obtained for each signal channel.

10. The test method according to claim 9, characterized in that, Based on the first insertion loss parameter, the second insertion loss parameter, and the third insertion loss parameter corresponding to each of the signal channel test units, the fourth insertion loss parameter for each signal channel in each of the signal channel test units is obtained as follows: The fourth insertion loss parameter = (first insertion loss parameter - (N-1) second insertion loss parameter - third insertion loss parameter) / N, where N is the number of signal channels.

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