Time discriminator, precharge delay gate, time-to-digital converter and digital phase-locked loop

Abstract

This invention relates to the field of integrated circuits, specifically a time discriminator, a precharge delay gate, a time-to-digital converter, and a digital phase-locked loop (PLL). The time discriminator outputs a corresponding flag signal after the first of two input signals that successively transition from low to high has completed its transition. It includes an SR flip-flop and a signal shielding circuit. The signal shielding circuit immediately cuts off the transmission path between the other input signal and the SR flip-flop when either input signal becomes high. The delay gate circuit adds a precharge transistor to the traditional delay circuit, significantly reducing the delay time. The time-to-digital converter is based on the improved design of the above two circuits. The coarse quantization circuit uses a Flash-type TDC, and the fine quantization circuit uses a Vernier-type TDC. Signal transmission and quantization result sharing between the two are achieved through an inter-stage transmission circuit. This invention solves the problems of complex circuit structure and control logic, high power consumption, and large area commonly found in high-precision TDCs.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to a time discriminator, a precharge delay gate, a time-to-digital converter, and a digital phase-locked loop. Background Technology

[0002] The Time-to-Digital Converter (TDC), a key module in an all-digital phase-locked loop (ADPLL), is widely used in clock recovery, frequency synthesis, and time interval measurement. Its core function is to convert the time interval (delay difference) between two signals into digital code; the conversion accuracy and power consumption directly affect the performance of the entire system.

[0003] Traditional time-delay converter (TDC) structures mainly include Flash, Vernier, and Pipeline types. Flash-type TDCs are simple in structure and have fast conversion speeds, but their resolution is limited by the accuracy of the basic delay unit, making it difficult to achieve picosecond-level high resolution. Vernier-type TDCs can achieve high resolution through two chains with different delays, but they have high circuit complexity, high power consumption, and are sensitive to process variations. In addition, the basic delay units commonly used in traditional TDCs (such as inverter chains) are greatly affected by variations in process technology, voltage, and temperature (PVT), making it difficult to achieve stable and accurate picosecond-level delays in deep submicron processes.

[0004] In terms of timing decisions, traditional arbiters typically employ bistable flip-flops or comparator structures, resulting in complex circuitry and high power consumption. Especially in high-precision time-discretion (TDC) systems, the parallel use of multiple arbiters further exacerbates power consumption and area overhead.

[0005] Therefore, existing high-precision TDC technologies often fail to achieve a balance between resolution, power consumption, area, and resistance to process variations, making it difficult to simultaneously achieve high resolution, low power consumption, and low complexity. Especially in power-sensitive applications such as the Internet of Things and mobile communications, developing a TDC circuit that can achieve both picosecond-level resolution and low power consumption has significant practical implications and market value. Summary of the Invention

[0006] To address the common problems of complex circuit structure and control logic, high power consumption, and large area in high-precision time-to-digital converters (TDCs), this invention provides a time discriminator, a pre-charge delay gate, a time-to-digital converter, and a digital phase-locked loop.

[0007] The technical solution provided by this invention is as follows:

[0008] A timing discriminator is used to output a corresponding flag signal after the first of two input signals A and B, which successively flip from low to high, has completed its flip. The actual discriminator consists of four PMOS transistors PM4~PM7, six NMOS transistors NM3~NM8, and an SR flip-flop. The circuit connections are as follows: the gates of NM5 and PM4 are connected and serve as the input port IN1 for one signal; the gates of NM6 and PM5 are connected and serve as the input port IN2 for the other signal. The sources of PM4, PM5, PM6, and PM7 are connected to VDD; the drains of PM4 and NM5 are connected to the gates of PM6, NM4, and NM7; the drains of PM5 and NM6 are connected to the gates of PM7, NM3, and NM8; the drain of NM3 is connected to the source of NM5; the drain of NM4 is connected to the source of NM6; and the sources of NM3, NM4, NM7, and NM8 are grounded. The drains of PM6 and NM7 are connected to the R terminal of the SR flip-flop; the drains of PM7 and NM8 are connected to the S terminal of the SR flip-flop. The positive output terminal Q and the inverted output terminal QN of the SR flip-flop are used to output the flag signal.

[0009] As a further improvement of the present invention, the output logic of the flag signal in the time discriminator is as follows:

[0010] (1) When the input signal A at the IN1 port flips before the input signal B at the IN2 port, then Q=1 and QN=0; and the output time of this flag signal is the flip time of the input signal A from low level to high level.

[0011] (2) When the input signal B at the IN2 port flips before the input signal A at the IN1 port, then Q=0 and QN=1; and the output time of this flag signal is the flip time of the input signal B from low level to high level.

[0012] As a further improvement of the present invention, the SR flip-flop is composed of two NAND gates, NAND1 and NAND2. One input of NAND1 is used as the R input, and the other input is connected to the output of NAND2. One input of NAND2 is used as the S input, and the other input is connected to the output of NAND1. The output of NAND1 is used as the Q input; the output of NAND2 is used as the QN input.

[0013] This invention further provides a precharge delay gate for delaying an input signal for a specified duration. It consists of three PMOS transistors PM1-PM3 and two NMOS transistors NM1-NM2. The circuit connections are as follows: the sources of PM1-PM3 are connected to VDD; the drain and gate of PM3 are connected to the gates of PM1, PM3, and NM1, serving as the input port IN of the original signal; the drains of PM1 and NM1 are connected to the gates of PM2 and NM2; the sources of NM1 and NM2 are grounded; and the drains of PM2 and NM2 are connected, serving as the output port OUT of the delayed signal.

[0014] As a further improvement of the present invention, the precharge delay gate shortens the charging stroke of the circuit by using the precharge tube MP3, thereby ensuring that the shortest controllable delay of the input signal is no more than 10ps.

[0015] The present invention also includes a time-to-digital converter for identifying the delay difference between the input signal Vin and the reference signal Vref and generating a corresponding digital code. The time-to-digital converter includes: a coarse quantization circuit, a first encoder, an inter-stage transfer circuit, a fine quantization circuit, and a second encoder.

[0016] The coarse quantization circuit includes: n As mentioned above, the pre-charge delay issue, and n +1 time discriminator as described above. Each pre-charge delay gate is connected in series to form a first delay chain for gradient-delaying of the input signal Vin. Each pre-charge delay gate in the first delay chain delays the input signal according to a preset minimum controllable delay ΔT; and then outputs sequentially. n The path delay lengths are ΔT, 2ΔT, ..., n The coarse input signal Vin of ΔT <1> ~Vin< n One input of each time discriminator is connected to the reference signal Vref, and the other input is connected to Vin and Vin' respectively. <1> ~Vin< n >

[0017] The first encoder is used to acquire the signal of the positive output terminal Q of each time discriminator in the coarse quantization circuit, and generate the value of the high-order part of the digital code according to the preset encoding logic based on the resolution of the coarse quantization circuit.

[0018] The interstage transmission circuit includes a time residual transmission gate and a delay matching circuit. The time residual transmission gate is used to acquire the output signals of the QN / Q terminals of each time discriminator in the coarse quantization circuit, as well as Vin and Vin's output signals. <1> ~Vin< n Then, the positions of two adjacent precharge delay gates that cause the output signal at the QN / Q input of the time discriminator to be inverted are identified, and the output signal Vin of the first precharge delay gate is set to the second precharge delay gate. The selection is routed to the rear. The delay matching circuit is used to delay the reference signal and output Vref0. The signal delay generated by the delay matching circuit is equal to the delay from Vin to Vin.The delay error generated during signal processing, excluding the first delay chain.

[0019] The fine quantization circuit includes 2 m The aforementioned pre-charge delay gate, and m +1 time discriminator as described above. m A series of pre-charge delay gates are connected in series to form a second delay chain; each pre-charge delay gate in the second delay chain is used to adjust Vin according to a preset delay ΔU. Gradient delay processing is performed; then the outputs are processed sequentially. m The path delay lengths are ΔU, 2ΔU, ..., m The fine input signal Vin of ΔU m +1>~Vin< n + m >. The remainder m A series of pre-charge delay gates are connected in series to form a third delay chain; each pre-charge delay gate in the third delay chain is used to perform gradient delay processing on Vref0 according to a preset delay ΔK; and then outputs sequentially. m The path delay lengths are ΔK, 2ΔK, ..., m The fine reference signal Vref of ΔK n +1>~Vref< n + m >. One input of each time discriminator is connected sequentially to Vref0 and Vref< n +1>~Vref< n + m >; The other input terminal is connected to Vin in sequence. Vin< n +1>~Vin< n + m >

[0020] The second encoder is used to acquire the signal of the positive phase output terminal Q of each time discriminator in the fine quantization circuit, and generate the value of the low-order part of the digital code according to the preset encoding logic based on the resolution of the fine quantization circuit.

[0021] As a further improvement of the present invention, the resolution of the coarse quantization circuit is equal to the shortest controllable delay ΔT of the precharge delay gate in the first delay chain.

[0022] Parameters related to the number of precharge delay gates and time discriminators in the coarse quantization circuit n Satisfy the following formula:

[0023] ;

[0024] In the above formula, D This represents the dynamic range of the time delay difference between the input signal and the reference signal. Mod {•} represents the modulo operation; Trunc {•} represents the rounding operation.

[0025] As a further improvement of the present invention, the resolution of the fine quantization circuit is equal to the difference between the preset delay ΔU of the precharge delay gate in the second delay chain and the preset delay ΔK of the precharge delay gate in the third delay chain.

[0026] Parameters related to the number of precharge delay gates and time discriminators in the fine quantization circuit m Satisfy the following formula:

[0027] .

[0028] As a further improvement of the present invention, the time residual transmission gate is... n Each buffer is buffer1 to buffern. n A transmission gate TG1~TGn and a n This is constructed using a dynamic OR gate (DOR) with input 1 and output 2. It is used in the coarse quantization circuit. n The pre-charge delay gates are denoted as PD1~PDn in sequence; n With one time discriminator denoted as TD0 to TDn+1, the connection relationship of the time residual transmission gate circuit is as follows: the inputs of buffer1 to buffern are connected to the outputs of PD1 to PDn respectively; the outputs of buffer1 to buffern are connected to the inputs of TG1 to TGn respectively; the non-inverting control terminals of TG1 to TGn are connected to the QN terminals of TD0 to TDn+1 respectively, and the inverting control terminals are connected to the Q terminals of TD0 to TDn+1 respectively; the outputs of TG1 to TGn are connected to the DOR... n The input terminals are connected in sequence; the output terminal of DOR is used to output the selected Vin. .

[0029] The present invention also includes a digital phase-locked loop that employs the time-to-digital converter as described above.

[0030] The present invention has the following beneficial effects:

[0031] This invention designs a novel delay gate circuit, which adds a pre-charge transistor to the traditional delay circuit, enabling pre-charging of the input terminal. Compared with voltage-controlled delay circuits, this circuit can effectively reduce the charging and discharging stroke of the delay gate, thereby reducing the delay duration without sacrificing other conditions. Compared with ordinary voltage-controlled delay gates, its advantage lies in achieving low picosecond delays without requiring a large-size MOSFET.

[0032] This invention designs a novel time discriminator that introduces a signal shielding circuit into the SR flip-flop. This circuit immediately cuts off the signal transmission path between the other input and the SR flip-flop when either input signal goes high. This mechanism not only ensures high reliability of the decision result, avoids metastability issues, and eliminates dead zones, but also significantly reduces dynamic power consumption by blocking the flipping and propagation of invalid signals. Compared to traditional structures, it reduces the number of transistors by nearly half, making the circuit simpler, while maintaining similar accuracy. Furthermore, its signal shielding characteristics can significantly reduce power consumption through special circuit connections.

[0033] Based on the improved predictive delay gate and time discriminator, this invention further designs a novel two-step time-to-digital converter (TD-SCDMA). It introduces a Flash-type TDC in the coarse quantization circuit and a Vernier-type TDC in the fine quantization circuit, and uses an inter-stage transmission circuit to transmit signals and share quantization results between the two. The introduction of the new predictive delay gate and time discriminator helps improve accuracy, significantly reduces the complexity of the circuit structure and control, shrinks the in-plane area, and lowers power consumption; resulting in superior performance. Attached Figure Description

[0034] Figure 1 This is a circuit diagram of the precharge delay gate provided in Embodiment 1 of the present invention.

[0035] Figure 2 This is a circuit diagram of the time discriminator provided in Embodiment 1 of the present invention.

[0036] Figure 3 This is an architecture diagram of the time-to-digital converter provided in Embodiment 2 of the present invention.

[0037] Figure 4 This is a circuit diagram of the time residual transmission gate section in the time-to-digital converter of Embodiment 2 of the present invention.

[0038] Figure 5 To test the delay effect of the pre-charge delay gate of this invention compared with that of a conventional pressure-controlled delay gate in the experiment.

[0039] Figure 6 The diagram shows the signal delay effect of the 7-stage delay chain using the pre-charge delay gate of this invention in the test experiment.

[0040] Figure 7 The signal flow graph is used to test the inter-signal delay time difference quantization of the time converter of this invention in the experiment. Detailed Implementation

[0041] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0043] Example 1

[0044] Existing time-to-digital converter (TDC) circuits mainly include delay chains composed of delay circuits and front-and-back decision circuit chains composed of various flip-flops (such as D flip-flops, SR flip-flops, and flip-flops based on sensitive amplifiers). Their strategy for quantizing the delay difference between the input signal Vin and the reference signal Vref is as follows: first, the input signal is gradient-delayed through the delay chain; then, each delayed signal and the reference signal are input to the flip-flops in the front-and-back decision circuit chains, respectively. When the outputs of any two flip-flops are out of phase, it indicates that the delay difference between the input signal and the reference signal lies precisely between the delay lengths corresponding to these two delay circuits. Based on the above quantization principle, it is clear that the shortest controllable delay ΔT achievable by the delay circuit and the dead-time width of the front-and-back decision circuits (implemented through various flip-flops) are key factors limiting the resolution improvement of time-to-digital converters.

[0045] In this circuit, the trigger or decision circuit primarily distinguishes between two signals by comparing their high and low levels. However, this comparison often involves a response time. The dead zone width refers to the minimum time difference between two signals that the trigger or decision circuit can effectively distinguish. If the minimum time difference between any two signals is less than the dead zone width of a trigger, the subsequent signal arrives before the trigger can respond to the earlier signal; therefore, it cannot correctly determine the order of the two signals. Conversely, if the minimum time difference between any two signals is less than the dead zone width of a trigger, it can respond to the earlier signal and output the corresponding order decision result.

[0046] Based on this analysis, to improve the resolution of the time-to-digital converter (TDC), this embodiment first provides an improved before-and-after decision device, referred to in this embodiment as a "time discriminator." This device outputs a corresponding flag signal after the earlier of two input signals A and B, which successively transition from low to high level, completes its transition. Next, an improved pre-charge delay gate is provided. Compared to existing delay circuits, the core feature of this pre-charge delay gate is its ability to effectively reduce the circuit's shortest controllable delay ΔT. For example, in practical applications, the minimum ΔT of a conventional delay circuit under this TDC load can reach 12 ps, while the ΔT of the pre-charge delay circuit in this embodiment can be as low as 10 ps, ​​with the potential to further reduce it.

[0047] Finally, based on the improved time discriminator and predictive delay gate, this embodiment further provides a two-step time-to-digital converter (TDC). The coarse quantization section of this TDC adopts a Flash-type TDC structure, while the fine quantization section adopts a Vernier-type TDC structure. This two-step TDC provided in this embodiment significantly improves quantization accuracy while also featuring a simpler circuit structure, smaller circuit area, and higher integration. Its control logic is more concise, improving quantization efficiency and reducing power consumption, resulting in more balanced performance and significant advantages.

[0048] Specifically, the pre-charge delay gate provided in this embodiment is composed of three PMOS transistors PM1~PM3 and two NMOS transistors NM1~NM2, which can achieve a specified delay of the input signal down to the level of 10 picoseconds. Figure 1 As shown, the circuit connection relationship of the precharge delay gate is as follows:

[0049] The sources of PM1~PM3 are connected to VDD; the drain and gate of PM3 are connected to the gates of PM1, PM3, and NM1, serving as the input port IN of the original signal; the drains of PM1 and NM1 are connected to the gates of PM2 and NM2; the sources of NM1 and NM2 are grounded; the drains of PM2 and NM2 are connected, serving as the output port OUT of the delayed signal. PM1, PM2, NM1, and NM2 constitute a conventional delay gate circuit, while PM3 uses a diode connection and acts as a pre-charge transistor. This pre-charges the node before the input signal arrives at the IN terminal, changing its original charging range from 0~0.9V to 0.15~0.9V, thus achieving a 10-picosecond delay by reducing its charging capacity.

[0050] Combination Figure 1 After analyzing the circuit principle of the pre-charge delay gate designed in this embodiment, it can be found that when the signal input to the IN port is low, PM1 is turned on and NM1 is turned off. At this time, PM3, which is connected by a diode, is also turned on. PM3 will inject current into the IN port from VDD through PM3, which is "pre-charging". When the input signal of the IN port changes from low to high, due to the pre-charging function of PM3, the starting voltage of the input signal is no longer 0V. This means that when the signal source boosts the voltage of the IN port, it only needs to continue charging on the basis of the pre-charged voltage (150mV) until the target level is reached. This means that the charge required for the charging process is significantly reduced. The reduction in charge directly leads to a significant reduction in charging time (i.e., delay), thereby achieving an extremely short delay at the picosecond level.

[0051] That is, the precharge delay gate designed in this embodiment can shorten the charging stroke of the circuit through the precharge tube MP3, thereby making its shortest controllable delay for the input signal no more than 10ps.

[0052] like Figure 2 As shown, the time discriminator provided in this embodiment consists of four PMOS transistors PM4~PM7, six NMOS transistors NM3~NM8, and one SR flip-flop. As a single device, the time discriminator has two input ports, IN1 and IN2, used to receive two input signals with a phase difference to be compared; it also has two inverted output ports, Q and QN, used to output a flag signal indicating the sequential order of the input signals at IN1 and IN2.

[0053] In practical applications, an SR flip-flop can be constructed using two NAND gates, NAND1 and NAND2. One input of NAND1 serves as the R input, and the other input is connected to the output of NAND2. One input of NAND2 serves as the S input, and the other input is connected to the output of NAND1. The output of NAND1 serves as the Q input, and the output of NAND2 serves as the QN input.

[0054] The circuit connections between the components in the time discriminator are as follows: the gates of NM5 and PM4 are connected and serve as input port IN1 for one signal; the gates of NM6 and PM5 are connected and serve as input port IN2 for another signal. The sources of PM4, PM5, PM6, and PM7 are connected to VDD; the drains of PM4 and NM5 are connected to the gates of PM6, NM4, and NM7; the drains of PM5 and NM6 are connected to the gates of PM7, NM3, and NM8; the drain of NM3 is connected to the source of NM5; the drain of NM4 is connected to the source of NM6; the sources of NM3, NM4, NM7, and NM8 are grounded. The drains of PM6 and NM7 are connected to the R terminal of the SR flip-flop; the drains of PM7 and NM8 are connected to the S terminal of the SR flip-flop. The positive output Q and the inverted output QN of the SR flip-flop are used to output the flag signal.

[0055] Specifically, in the time discriminator with the above circuit structure provided in this embodiment, the output logic of the flag signal is as follows:

[0056] (1) When the input signal A at the IN1 port flips before the input signal B at the IN2 port, then Q=1 and QN=0; and the output time of this flag signal is the flip time of the input signal A from low level to high level.

[0057] (2) When the input signal B at the IN2 port flips before the input signal A at the IN1 port, then Q=0 and QN=1; and the output time of this flag signal is the flip time of the input signal B from low level to high level.

[0058] In the novel time discriminator designed in this embodiment, PM4~PM7 and NM3~NM8 constitute a mirror-symmetric signal shielding circuit. The signal shielding circuit has two functions: First, it forms a signal transmission channel that transmits the two input signals A and B to be decided to the R and S terminals of the SR flip-flop, respectively. After outputting the A or B signal to the SR flip-flop through the corresponding channel, the SR flip-flop will complete the "comparison" of the signals and generate the decision result (i.e., output the corresponding flag signal).

[0059] On the other hand, unlike traditional flip-flops that directly compare the two input signals, the signal shielding circuit in this embodiment can immediately shut off the transmission channel of the other signal when either A or B is transmitted to the R or S terminal first. This prevents it from being transmitted to the SR flip-flop. As mentioned earlier, the reason why traditional SR flip-flops have a large dead zone is that the circuit's response characteristics mean that if the delay difference between a later signal and an earlier signal is less than the dead zone, the later signal, although arriving later, will still affect the output of the SR flip-flop, causing it to lose its ability to determine the order of arrival. However, the signal shielding circuit of this invention can immediately block the signal transmission channel between the other signal and the SR flip-flop when the earlier signal flips to a high level, preventing it from ever reaching the SR flip-flop. In this state, no matter how short the delay difference between the later signal and the earlier signal is, it cannot reach the SR flip-flop and therefore cannot interfere with the output of the SR flip-flop. To some extent, the signal truncation mechanism implemented by the signal shielding circuit in this embodiment can "substantially" eliminate the signal dead zone problem in the front and rear decision circuits based on triggers; or, to put it another way, the mechanism can "significantly" narrow the dead zone width of the front and rear decision circuits.

[0060] In detail, the working principle of the signal shielding circuit in the novel time discriminator provided in this embodiment is as follows:

[0061] like Figure 2 As shown, assuming that signal A arrives first among two input signals A and B, when the current signal transitions from low to high, NM5 turns on and PM4 turns off. This causes node 1, which was originally charged to a high level, to discharge from a high level to a low level, and turns off NM4 in the discharge path on the right (B terminal). Therefore, the output signal at the Q terminal of the SR flip-flop is high, and the output signal at the QN terminal is low. Conversely, when signal B arrives first, when the current signal transitions from low to high, NM6 turns on and PM5 turns off. This causes node 2, which was originally charged to a high level, to discharge from a high level to a low level, and turns off NM3 in the discharge path on the left (A terminal). Therefore, the output signal at the Q terminal of the SR flip-flop is low, and the output signal at the QN terminal is high.

[0062] Therefore, when there is a time difference between two input signals (A and B), the signal that arrives first will immediately activate its corresponding discharge path, pulling the critical internal node low. This action triggers the SR flip-flop to latch the current result (e.g., if IN1 is leading, the output Q=1). Furthermore, the change in the node's level directly turns off the NMOS transistor (such as NM3 or NM4) on the other discharge path. When the lagging signal arrives, its discharge path has been physically cut off by the preceding signal, preventing the formation of an effective discharge loop. Therefore, its state change cannot propagate to the SR flip-flop and is thus completely "shielded." This mechanism not only ensures high reliability of the decision result and avoids metastability issues but also significantly reduces the circuit's dynamic power consumption by blocking the flipping and propagation of invalid signals.

[0063] Example 2

[0064] Based on the precharge delay gate with a lower minimum controllable delay ΔT and the time discriminator with a narrower dead zone width provided in Embodiment 1, this embodiment further provides a time-to-digital converter, which is used to identify the delay difference between the input signal Vin and the reference signal Vref and generate the corresponding digital code.

[0065] like Figure 3 As shown, the time-to-digital converter provided in this embodiment includes: a coarse quantization circuit, a first encoder, an inter-stage transmission circuit, a fine quantization circuit, and a second encoder.

[0066] The coarse quantization circuit includes components made of... n As in Example 1, a pre-charge delay gate, and n +1 time discriminator as shown in Example 1. Each pre-charge delay gate is connected in series to form a first delay chain for gradient-delaying of the input signal Vin. Each pre-charge delay gate in the first delay chain is used to delay the input signal according to a preset minimum controllable delay ΔT; and then outputs sequentially. n The path delay lengths are ΔT, 2ΔT, ..., n The coarse input signal Vin of ΔT <1> ~Vin< n One input of each time discriminator is connected to the reference signal Vref, and the other input is connected to Vin and Vin' respectively. <1> ~Vin< n >

[0067] The first encoder is used to acquire the signal of the positive output terminal Q of each time discriminator in the coarse quantization circuit, and generate the value of the high-order part of the digital code according to the preset encoding logic based on the resolution of the coarse quantization circuit.

[0068] The interstage transmission circuit includes a time residual transmission gate and a delay matching circuit. The time residual transmission gate is used to acquire the output signals of the QN / Q terminals of each time discriminator in the coarse quantization circuit, as well as Vin and Vin's output signals. <1> ~Vin< n Then, the positions of two adjacent precharge delay gates that cause the output signal at the QN / Q input of the time discriminator to be inverted are identified, and the output signal Vin of the first precharge delay gate is set to the second precharge delay gate. The selection is routed to the rear. The delay matching circuit is used to delay the reference signal and output Vref0. The signal delay generated by the delay matching circuit is equal to the delay from Vin to Vin. The delay error generated during signal processing, excluding the first delay chain.

[0069] In a typical scheme provided in this embodiment, the time residual transmission gate can be adopted as follows: Figure 4 The circuit shown is composed of... n Each buffer is buffer1 to buffern. n A transmission gate TG1~TGn and a n It is composed of a dynamic OR gate circuit with input 1 and output DOR.

[0070] In the coarse quantization circuit n The pre-charge delay gates are denoted as PD1~PDn in sequence; n If the +1 time discriminators are denoted as TD0 to TDn+1 respectively, then the connection relationship of the time residual transmission gate circuit is as follows:

[0071] The input terminals of buffer1 to buffern are connected to the output terminals of PD1 to PDn, respectively; the output terminals of buffer1 to buffern are connected to the input terminals of TG1 to TGn, respectively; the non-inverting control terminals of TG1 to TGn are connected to the QN terminals of TD0 to TDn+1, respectively, and the inverting control terminals are connected to the Q terminals of TD0 to TDn+1, respectively; the output terminals of TG1 to TGn are connected to the DOR, respectively. n The input terminals are connected in sequence; the output terminal of DOR is used to output the selected Vin. .

[0072] Correspondingly, the delay matching circuit can be any type of delay circuit with adjustable delay length, such as a voltage-controlled delay circuit.

[0073] The fine quantization circuit includes 2 m A precharge delay gate as shown in Example 1, and m +1 time discriminator as shown in Example 1. m A series of pre-charge delay gates are connected in series to form a second delay chain; each pre-charge delay gate in the second delay chain is used to adjust Vin according to a preset delay ΔU. Gradient delay processing is performed; then the outputs are processed sequentially. m The path delay lengths are ΔU, 2ΔU, ..., m The fine input signal Vin of ΔU m +1>~Vin< n + m >. The remainder m A series of pre-charge delay gates are connected in series to form a third delay chain; each pre-charge delay gate in the third delay chain is used to perform gradient delay processing on Vref0 according to a preset delay ΔK; and then outputs sequentially. m The path delay lengths are ΔK, 2ΔK, ..., m The fine reference signal Vref of ΔK n +1>~Vref< n + m >. One input of each time discriminator is connected sequentially to Vref0 and Vref< n +1>~Vref< n + m >; The other input terminal is connected to Vin in sequence. Vin< n +1>~Vin< n + m >

[0074] The second encoder is used to acquire the signal of the positive phase output terminal Q of each time discriminator in the fine quantization circuit, and generate the value of the low-order part of the digital code according to the preset encoding logic based on the resolution of the fine quantization circuit.

[0075] Specifically, the quantization logic of the time-to-digital converter provided in this embodiment includes three processes: coarse quantization, matching and positioning, and fine quantization. The specific steps are as follows:

[0076] (a) Coarse Quantification Stage

[0077] If the dynamic range of the delay difference between two input signals that need to be quantized is L, then the arrival time of the reference signal is t+L, while the arrival time of the input signal is (t+0)~(t+L), the specific value of which is unknown and needs to be quantized.

[0078] In this embodiment, the shortest controllable delay of a single pre-charge delay gate in the coarse quantization circuit is ΔT. Therefore, n prediction delay gates can be used to form an n-stage delay chain, sequentially shifting the arrival time of the input signal from its original value by ΔT, 2ΔT, ..., nΔT. Then, a time discriminator compares these gradient-delayed input signals with the reference signal.

[0079] In this case, assuming the value of L is between pΔT and (p+1)ΔT, it means that the input signal after the p-th stage delay gate and the p+1-th stage delay is exactly earlier than the reference signal and later than the reference signal, causing the outputs of the corresponding two adjacent time discriminators to flip.

[0080] (II) Matching and Positioning Stage

[0081] The coarse quantization circuit in this embodiment performs the aforementioned signal delay operation and signal time-domain discrimination operation. The discrimination result is then reflected in the flag signal output by each stage of the time discriminator. This flag signal can be output to the first encoder to generate the high-order bits of the digital code of the flag quantization result, and can also be input to the inter-stage transmission circuit to help the time residual transmission gate locate the position where the output flip occurs on the time discriminator chain, thereby finding the input signal Vin after a pΔT delay from the output of the corresponding pre-charge delay gate on the corresponding first delay chain. This Vin It is the closest signal to the reference signal that the coarse quantization circuit can generate. The time residual transmission gate is located at Vin. This information is then transmitted to the fine-tuning circuit. The fine-tuning circuit, using circuitry capable of generating lower delay differences, fine-tunes the delay lengths of the reference and input signals, gradually adjusting them to a level where the signal delay is negligible.

[0082] Furthermore, it should be emphasized that in the interstage transmission circuit, Vin, after being delayed by the first delay chain, is transmitted from the coarse quantization circuit to the fine quantization circuit. Compared to the original input signal Vin, there should be a delay of pΔT. However, in actual circuits, the circuitry used for signal transmission may require components such as buffers, and Vin... This results in a non-negligible delay error besides pΔT, which affects the final quantization accuracy of the circuit. To address this issue, this embodiment further introduces a delay matching circuit in the inter-stage transmission circuit. Its function is to pre-analyze the Vin output of the time residual transmission gate to the fine quantization circuit. It includes delay errors other than pΔT. The original reference signal is also subjected to the same level of delay processing, thereby eliminating the error components contained in the delay difference between the reference and input signals, achieving error compensation.

[0083] (III) Detailed Quantification Stage

[0084] As mentioned earlier, the ΔT of a single delay gate has become a bottleneck limiting the resolution of coarse quantization circuits. In Flash-type TDC structures, it is impossible to perform shorter delay processing for reference or input signals. To address this issue, engineers can use Vernier-type TDC structures as fine quantization circuits in practical applications.

[0085] The working logic of this fine quantization circuit is as follows: Considering the relative difference in delay between two signals, a precharge delay gate with a minimum delay of ΔT can be used to simultaneously delay both the input and reference signals by a value greater than ΔT, ensuring a difference in their delays. If this difference is less than ΔT, it is equivalent to delaying only one of them by a value less than ΔT. For example, if the ΔT of a precharge delay gate is 10ps, it can be used to delay the reference signal by 11ps and the input signal by 12ps. Comparing the two, this is equivalent to delaying the input signal by only 1ps. This more complex structure (requiring two delay chains) effectively overcomes the accuracy limitation of a single precharge delay gate when processing signal delays, allowing for a lower resolution. Correspondingly, the dead zone width of the time discriminator also needs to be narrowed accordingly. The improved time discriminator in this embodiment happens to have an extremely narrow dead zone width, thus meeting this requirement of the fine quantization circuit.

[0086] Finally, the essence of the detailed quantification stage is to focus on Vin. Based on and according to ΔT / m The gradient change (less than ΔT) is finely adjusted step by step in a manner similar to that of the coarse quantization stage to gradually fine-tune the delay difference between the input signal and the reference signal. Then, the input signal with the delay that best approximates the reference signal is found between pΔT and (p+1)ΔT, and the corresponding decision result is output by the time discriminator in the fine quantization circuit.

[0087] It is worth emphasizing that, in practical applications, the number of precharge delay gates and time discriminators in the coarse quantization circuit can be flexibly set according to the shortest controllable delay ΔT of the precharge delay gates and the dynamic range of the delay difference between the input signal and the reference signal of the quantization task. The number of precharge delay gates and time discriminators in the coarse quantization circuit can be flexibly set according to ΔT and the required resolution (i.e., the minimum delay length corresponding to a unit 1 in the digital code, which is equal to "|ΔU-ΔK|" in the fine quantization circuit).

[0088] Specifically, in this embodiment, the resolution of the coarse quantization circuit is equal to the shortest controllable delay ΔT of the precharge delay gates in the first delay chain. The parameters in the coarse quantization circuit related to the number of precharge delay gates and time discriminators... n Satisfy the following formula:

[0089] ;

[0090] In the above formula, D This represents the dynamic range of the time delay difference between the input signal and the reference signal. Mod {•} represents the modulo operation; Trunc {•} represents the rounding operation.

[0091] For example, when the dynamic range D is 61-69ps and ΔT is 10ps, then n=7; when the dynamic range D is 70ps and ΔT is 10ps, then n=7; when the dynamic range D is 71-79ps and ΔT is 10ps, then n=8.

[0092] The resolution of the fine quantization circuit is equal to the difference between the preset delay ΔU of the precharge delay gate in the second delay chain and the preset delay ΔK of the precharge delay gate in the third delay chain. The parameters in the fine quantization circuit related to the number of precharge delay gates and time discriminators are as follows: m Satisfy the following formula:

[0093] .

[0094] For example, if ΔT is 10 ps and the required resolution is 1 ps, then m = 10; if ΔT is 10 ps and the required resolution is 1.5 ps, then m = 7; if ΔT is 10 ps and the required resolution is 2 ps, then m = 5.

[0095] As previously described, the optimized precharge delay gate and time discriminator help improve the resolution of the time-to-digital converter provided in this embodiment. Furthermore, the precharge delay gate, with its lower minimum controllable delay ΔT, can also help reduce circuit power consumption and area, and improve quantization efficiency.

[0096] Based on the operating logic of the two-step time-to-digital converter provided in this embodiment as described above, the following further explains why applying the precharge delay gate with a lower minimum controllable delay ΔT provided in Embodiment 1 can significantly improve the circuit's power consumption, area, and other performance characteristics:

[0097] In the two-step time-to-digital converter architecture of this embodiment, the coarse quantization circuit adopts a Flash-type TDC structure, which uses quantization logic with single-sided signal delay and comparison of signals on both sides. Therefore, for each additional delay and comparison stage, the coarse quantization circuit only adds one pre-charge delay gate. The fine quantization circuit, however, adopts a Vernier-type TDC structure, which uses double-sided signal delay and comparison of signals on both sides. Therefore, for each additional delay and comparison stage, the fine quantization circuit adds two pre-charge delay gates. Under the same quantization accuracy conditions, reducing the length of the delay chain and the number of time discriminators in the fine quantization circuit can more effectively reduce the circuit area and power consumption, and shorten the quantization period.

[0098] For example, suppose we use delay gates with delay lengths of 10ps and 15ps to quantize two signals with a dynamic range of 60ps, achieving a final quantization accuracy of 1ps. When building the circuit using 10ps delay gates, the coarse quantization circuit requires a 6-stage first delay chain, and the fine quantization circuit requires 10 stages of second and third delay chains, totaling 26 (6 + 2 × 10) delay gates. However, when building the circuit using 15ps delay gates, the coarse quantization circuit requires a 4-stage first delay chain, and the fine quantization circuit requires 15 stages of second and third delay chains, totaling 34 (4 + 2 × 15) delay gates. Furthermore, in terms of the number of time discriminators, the former requires 18 (6 + 1 + 10 + 1) and the latter requires 21 (4 + 1 + 15 + 1). Clearly, the shorter the minimum delay of the delay gates, the more effective it is to reduce the number of delay gates and time discriminators when building a time-to-digital converter with the same level of precision, thereby reducing circuit area and power consumption.

[0099] Example 3

[0100] Building upon the time-to-digital converter in Embodiment 1, this embodiment further provides a digital phase-locked loop (PLL) employing the time-to-digital converter as described in Embodiment 2. This higher-performance time-to-digital converter will help improve the PLL's high-precision identification and analog-to-digital conversion of signal delay differences (i.e., phase differences), while further reducing the on-chip area and power consumption of the circuit, thereby enhancing the practical value of the related circuits and their chip products.

[0101] Performance testing

[0102] To verify the performance of the time discriminator, precharge delay gate, time-to-digital converter, etc. provided by this invention, technicians simulated and tested the relevant circuit schemes on a 28nm CMOS process.

[0103] 1. Latency performance comparison

[0104] This experiment first tested the delay effect of the pre-charge delay gate provided by this invention and the ordinary voltage-controlled delay gate on the same signal. The obtained signal is as follows: Figure 5 As shown in the figure. The TM curve is the delayed input signal, curve 1 is the delay curve of a conventional voltage-controlled delay gate, and curve 2 is the delay curve of the novel pre-charge delay gate of this invention.

[0105] Analysis of the data in the figure clearly shows that when the tube parameters in the two delay gates are the same, the pre-charge delay gate of the present invention achieves a significant reduction in delay time by pre-charging the input node (about 150mV).

[0106] This experiment further tested the delay effect of a delay chain composed of seven pre-charge delay gates of this invention connected end-to-end, and the obtained signal is as follows: Figure 6 As shown in the figure, the data analysis reveals that the delay effect of the signal after being delayed by each stage of pre-charge delay gates is consistent.

[0107] 2. Quantitative effect simulation

[0108] This experiment tested the effect of using the time-to-digital converter of this invention for input signal delay length quantization. In the experiment, the coarse quantization circuit of the time-to-digital converter of this invention consists of seven stages of pre-charge delay gates with a resolution of 10 s. The fine quantization circuit includes two seven-stage pre-charge delay gates with different speeds, and the delay difference between each stage of the two delay chains is 1.5 ps. That is, the resolution of the fine quantization circuit is 1.5 ps. During the test phase, the input signal led the reference signal by 66 ps. After quantization by the time-to-digital converter of this invention, the resulting signal flow graph is as follows: Figure 7 As shown.

[0109] The output during the experiment was a 6-bit digital code, with the order of the coarse quantization (Flash-TDC) 3-bit result first, followed by the fine quantization (Vernier-TDC) 3-bit result, i.e., B2, B1, B0, BB2, BB1, BB0. According to the signal diagram, the 6-bit code is 110100. Therefore, using a coarse quantization resolution of 10 ps and a fine quantization resolution of 1.5 ps, the quantization result is T = 6 × 10 + 4 × 1.5 = 66 ps, consistent with the delay difference between the input and reference signals.

[0110] 3. Map Design

[0111] In the layout of the time-to-digital converter of this invention, designed using a 28nm process, the layout area is 0.00367 mm². 2 The power consumption is 207.7uW, both of which are significantly improved compared to conventional products.

[0112] The above-described embodiments are merely one implementation of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept, and these all fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. A time discriminator, characterized in that, It is used to output the corresponding flag signal after the first of two input signals A and B, which successively flip from low level to high level, has completed its flip; it is composed of 4 PMOS transistors PM4~PM7, 6 NMOS transistors NM3~NM8 and one SR flip-flop; The gates of NM5 and PM4 are connected and serve as the input port IN1 of one signal; the gates of NM6 and PM5 are connected and serve as the input port IN2 of another signal; the sources of PM4, PM5, PM6 and PM7 are connected to VDD; the drains of PM4 and NM5 are connected to the gates of PM6, NM4 and NM7; the drains of PM5 and NM6 are connected to the gates of PM7, NM3 and NM8; the drain of NM3 is connected to the source of NM5; the drain of NM4 is connected to the source of NM6; the sources of NM3, NM4, NM7 and NM8 are grounded; the drains of PM6 and NM7 are connected to the R terminal of the SR flip-flop; the drains of PM7 and NM8 are connected to the S terminal of the SR flip-flop; the positive output terminal Q and the inverted output terminal QN of the SR flip-flop are used to output the flag signal.

2. The time discriminator according to claim 1, characterized in that: The output logic of the flag signal is as follows: When the input signal A at port IN1 flips before the input signal B at port IN2, then Q=1 and QN=0; and the output time of this flag signal is the flip time of input signal A from low level to high level. When the input signal B at port IN2 flips before the input signal A at port IN1, then Q=0 and QN=1; and the output time of this flag signal is the flip time of the input signal B from low level to high level.

3. The time discriminator according to claim 2, characterized in that: The SR flip-flop consists of two NAND gates, NAND1 and NAND2; one input of NAND1 is used as the R input, and the other input is connected to the output of NAND2; one input of NAND2 is used as the S input, and the other input is connected to the output of NAND1; the output of NAND1 is used as the Q input; and the output of NAND2 is used as the QN input.

4. A pre-charge delay gate, used to delay an input signal for a specified duration, characterized in that: It consists of three PMOS transistors PM1~PM3 and two NMOS transistors NM1~NM2; The sources of PM1~PM3 are connected to VDD; the drain and gate of PM3 are connected to the gates of PM1, PM3, and NM1, and serve as the input port IN of the original signal; the drains of PM1 and NM1 are connected to the gates of PM2 and NM2; the sources of NM1 and NM2 are grounded; the drains of PM2 and NM2 are connected and serve as the output port OUT of the delayed signal. PM3 uses a diode connection and acts as a pre-charge diode. The pre-charge diode PM3 shortens the charging path of the circuit, thereby ensuring that its shortest controllable delay to the input signal is no more than 10ps.

5. A time-to-digital converter, used to identify the delay difference between an input signal Vin and a reference signal Vref and generate a corresponding digital code, characterized in that, It includes: Coarse quantization circuit, which includes a coarse quantization circuit consisting of ... n A precharge delay gate as described in claim 4, and n +1 time discriminator as described in any one of claims 1-3; each precharge delay gate is connected in series to form a first delay chain for gradient-delaying the input signal; each precharge delay gate in the first delay chain is used to delay the input signal according to a preset minimum controllable delay ΔT; and then outputs sequentially. n The path delay lengths are successively ΔT, 2ΔT, ..., n The coarse input signal Vin of △T <1> ~Vin< n >; One input of each time discriminator is connected to the reference signal Vref, and the other input is connected to Vin, Vin, and Vin respectively. <1> ~Vin< n >; The first encoder is used to acquire the signal of the positive output terminal Q of each time discriminator in the coarse quantization circuit, and generate the value of the high-order part of the digital code according to the preset encoding logic based on the resolution of the coarse quantization circuit. The interstage transmission circuit includes a time residual transmission gate and a delay matching circuit; the time residual transmission gate is used to acquire the signals output from the QN / Q terminals of each time discriminator in the coarse quantization circuit, as well as Vin and Vin. <1> ~Vin< n Then, the positions of two adjacent precharge delay gates that cause the output signal at the QN / Q input of the time discriminator to be inverted are identified, and the output signal Vin of the first precharge delay gate is set to the second precharge delay gate. The selection is directed to the rear; the delay matching circuit is used to delay the reference signal and output Vref0, and the signal delay generated by the delay matching circuit is equal to the delay from Vin to Vin. The delay error generated during signal processing, excluding the first delay chain; Fine quantization circuit, which includes 2 m A precharge delay gate as described in claim 4, and m +1 time discriminator as described in any one of claims 1-3; wherein m A pre-charge delay gate is connected in series to form a second delay chain; Each pre-charge delay gate in the second delay chain is used to adjust Vin according to a preset delay ΔU. Gradient delay processing is performed; then the outputs are processed sequentially. m The path delay lengths are ΔU, 2ΔU, ..., m The fine input signal Vin of △U m +1>~Vin< n + m >; the remaining m A series of pre-charge delay gates are connected in series to form a third delay chain; Each pre-charge delay gate in the third delay chain is used to perform gradient delay processing on Vref0 according to a preset delay ΔK; and then outputs sequentially. m The road delay lengths are ΔK, 2ΔK, ..., m The fine reference signal Vref of △K n +1>~Vref< n + m >; One input terminal of each time discriminator is connected sequentially to Vref0, Vref< n +1>~Vref< n + m >; The other input terminal is connected to Vin in sequence. 、Wine< n +1>~I'm coming< n + m >; The second encoder is used to acquire the signal of the positive phase output terminal Q of each time discriminator in the fine quantization circuit, and generate the value of the low-order part of the digital code according to the preset encoding logic based on the resolution of the fine quantization circuit.

6. The time-to-digital converter according to claim 5, characterized in that: The resolution of the coarse quantization circuit is equal to the shortest controllable delay ΔT of the precharge delay gate in the first delay chain; The parameters related to the number of precharge delay gates and time discriminators in the coarse quantization circuit n Satisfy the following formula: ； In the above formula, D This represents the dynamic range of the time delay difference between the input signal and the reference signal. Mod {·} represents the modulo operation; Trunc {·} represents the rounding operation.

7. The time-to-digital converter according to claim 6, characterized in that: The resolution of the fine quantization circuit is equal to the difference between the preset delay ΔU of the precharge delay gate in the second delay chain and the preset delay ΔK of the precharge delay gate in the third delay chain. The parameters related to the number of precharge delay gates and time discriminators in the fine-tuning circuit m Satisfy the following formula: 。 8. The time-to-digital converter according to claim 5, characterized in that: The time residual transmission gate is composed of n Each buffer is buffer1 to buffern. n A transmission gate TG1~TGn and a n It is composed of a dynamic OR gate circuit with 1 input and 1 output (DOR). In the coarse quantization circuit n The pre-charge delay gates are denoted as PD1~PDn in sequence; n If the +1 time discriminators are denoted as TD0 to TDn+1 respectively, then the connection relationship of the time residual transmission gate circuit is as follows: The inputs of buffer1 to buffer1 are connected to the outputs of PD1 to PDn, respectively; the outputs of buffer1 to buffer1 are connected to the inputs of TG1 to TGn, respectively; the non-inverting control terminals of TG1 to TGn are connected to the QN terminals of TD0 to TDn+1, respectively, and the inverting control terminals are connected to the Q terminals of TD0 to TDn+1, respectively; the outputs of TG1 to TGn are connected to the DOR, respectively. n The input terminals are connected in sequence; the output terminal of DOR is used to output the selected Vin. 。 9. A digital phase-locked loop, characterized in that, It employs a time-to-digital converter as described in any one of claims 6-8.

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