Timing generation control circuit applied to multi-channel micro-current detection and system on chip

Abstract

The application provides a timing generation control circuit applied to multi-channel micro-current detection, a system on chip, and a specific timing generation control circuit structure composed of a three-phase clock generation circuit, a first delay chain, a 2N-phase clock generation circuit, and an N-channel integral sampling control signal generation circuit connected in sequence, and a three-phase non-overlapping clock generation circuit connected with the three-phase clock generation circuit. The specific timing generation control circuit structure can systematically generate a large number of control signals following strict timing, so as to accurately, synchronously and non-conflictingly time-division multiplex control the integrator, the differential circuit and the shared multiplexer and analog-to-digital converter in the N current detection channels. Further, a high-density integrated, low inter-channel crosstalk and high energy efficiency current detection system on chip is obtained, which can realize accurate detection of multiple biological macromolecules in multi-channel parallel mode, significantly improve the detection speed, and ensure the detection accuracy.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a timing generation and control circuit and a system-on-a-chip for multi-channel microcurrent detection. Background Technology

[0002] In the field of biomolecular detection technology, System-on-Chip (SoC) integrated circuits enable nanoscale dynamic analysis of biomolecules (such as DNA and proteins) through multi-channel microcurrent detection technology. This system can precisely capture the weak picoampere (pA) or nanoampere (nA) currents generated when biomolecules pass through nanopores, converting the physicochemical properties of biomolecules into high-precision, parallel-readable electrical signals; providing a revolutionary detection method for basic life science research, precision medicine, public health monitoring, and environmental bioanalysis.

[0003] The current detection principle of the aforementioned System-on-Chip (SoC) is as follows: An operational amplifier and a feedback capacitor form the core current integration circuit. By measuring the voltage change across the capacitor within a fixed integration time, the average value of the pA to nA current generated when biomolecules pass through the nanopore is obtained. For noise reduction, to overcome the interference of low-frequency noise from the operational amplifier, the system can employ correlated double sampling technology. This involves sampling the voltage at the beginning and end of the integration period and taking the difference, thereby effectively canceling low-frequency noise and offset voltage, significantly improving the signal-to-noise ratio. In terms of system implementation, multiple integration and sampling channels can be integrated onto a chip using CMOS or similar processes. Combined with a timing generation and control circuit, parallel measurement of the current in multiple nanopore channels can be achieved.

[0004] In particular, in the design of the aforementioned integrated circuit system-on-a-chip (SoC), since multi-channel measurements involve a large number of control signals, and these signals must adhere to strict timing relationships, this high-precision timing control mechanism is a key technical guarantee for achieving the expected performance of multi-channel nanopore current parallel measurement. Therefore, the timing generation and control circuit in the aforementioned integrated circuit system-on-a-chip (SoC) has stringent timing accuracy requirements. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a timing generation and control circuit and on-chip system for multi-channel microcurrent detection, which has high-precision timing control capability and can ensure the accuracy of multi-channel parallel measurement.

[0006] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0007] A timing generation and control circuit for multi-channel microcurrent detection includes: a three-phase clock generation circuit, a first delay chain, a 2N-phase clock generation circuit, and an N-channel integral sampling control signal generation circuit connected in sequence; it also includes a three-phase non-overlapping clock generation circuit connected to the three-phase clock generation circuit.

[0008] The period is T MCLK After the clock signal MCLK is input into the three-phase clock generation circuit, the generation period is 3T. MCLK Three periodic square wave signals with different phases 0、 1 and 2, and its corresponding complementary level signal 0b , 1b and 2b The complementary level signal 0b , 1b and 2b The three-phase non-overlapping clock generation circuit generates three sets of non-overlapping timing signals to control the same analog-to-digital converter shared by N channels; the periodic square wave signal 0 generates a period of T after passing through the first delay chain. GCLK Two complementary square wave signals, GCLK and GCLKb, are used to drive the 2N-phase clock generation circuit to generate a clock with a period of 2N. T GCLK 2N periodic square wave signals T0, T1 to T2 with different phases 2N-1 and its corresponding complementary level signal T 0b T 1b To T 2N-1b The signal is input to the N-channel integral sampling control signal generation circuit, so that it generates four sets of periodic square wave signals for each channel, which are used to control the reset phase and integral phase of the integrator of each channel, as well as the reset phase and amplification phase of the differential circuit; where N is a positive integer.

[0009] Optionally, the N-channel integral sampling control signal generation circuit generates four sets of periodic square wave signals for each channel, with the first set being a periodic square wave signal. RSTn , RSTnb , RSTDLYn and RSTDLYnb The second group of periodic square wave signals INTn and INTnb The third group of periodic square wave signals sSDn , sSDnb , sSDDLYn , sSDDLYnb and the fourth group of periodic square wave signals aSDn and aSDnb The first and second sets of periodic square wave signals are used to control the reset phase and integration phase of the integrator, respectively; the third and fourth sets of periodic square wave signals are used to control the reset phase and amplification phase of the differential circuit, respectively.

[0010] Optionally, the three-phase clock generation circuit includes three D flip-flops and several inverters;

[0011] The clock signal ports CLK of the three D flip-flops are connected sequentially; the output port Q of the first D flip-flop is connected to the data input port D of the second D flip-flop through an even number of inverters, and the output port Q of the third D flip-flop is connected to the data input port D of the first D flip-flop through an even number of inverters; the reset ports RST of the second and third D flip-flops are connected to the set port SET of the first D flip-flop; the output ports Q of the three D flip-flops output three periodic square wave signals with different phases. 0、 1 and 2. Its inverting output port Qb outputs corresponding complementary level signals respectively. 0b , 1b and 2b .

[0012] Optionally, the first delay chain includes a delay chain body and two output paths; the delay chain body is composed of several cascaded inverters, and its input is connected to the periodic square wave signal in the three-phase clock generation circuit. The output terminal is connected to the 0 output terminal, and its output terminal is connected to the two output paths; the first output path is composed of two cascaded inverters and is used to output the square wave signal GCLKb; the second output path is composed of a CMOS transmission gate and an inverter connected in sequence and is used to output the square wave signal GCLK.

[0013] Optionally, the 2N-phase clock generation circuit includes 2N D flip-flops and several inverters; the clock signal ports CLK of the 2N D flip-flops are connected sequentially; the output port Q of the previous D flip-flop is connected to the data input port D of the next D flip-flop through an even number of inverters, and the output port Q of the 2Nth D flip-flop is connected to the data input port D of the first D flip-flop through an even number of inverters; the reset ports RST of the second to the 2Nth D flip-flops are connected to the set port SET of the first D flip-flop; the output ports Q of the 2N D flip-flops respectively output 2N periodic square wave signals T0, T1 to T2 with different phases. 2N-1 Its inverting output port Qb outputs corresponding complementary level signals T. 0b T 1b To T 2N-1b .

[0014] Optionally, the N-channel integral sampling control signal generation circuit includes an integrator reset and integral control signal generation circuit corresponding to the nth channel; where n∈{0,1,2,...,N-1};

[0015] The integrator reset and integration control signal generation circuit of the nth channel includes an OR gate logic, a first two equal-length delay chain, a non-overlapping two-phase signal generation circuit, a second two equal-length delay chain, a third two equal-length delay chain, and a second delay chain connected in sequence. The circuit structures of the first two equal-length delay chains, the second two equal-length delay chains, and the third two equal-length delay chains are the same, wherein the first chain is composed of two cascaded inverters, and the second chain is composed of a CMOS transmission gate and an inverter connected in sequence. The circuit structure of the second delay chain is the same as that of the first delay chain.

[0016] The signal T input to the nth channel integrator reset and integration control signal generation circuit n T (n+1)mod2N To T (n+m-1)mod2N After the OR operation of the aforementioned OR gate logic, a value with a width of m is generated. T GCLK The period is 2N T GCLK A periodic square wave is input to the first two equal-length delay chains, and the first chain outputs a signal. RSTXn Second output signal RSTXbn The signal RSTXn and the signal RSTXbn After passing through the non-overlapping two-phase signal generation circuit, a non-overlapping signal is generated. RSTn and INTn The signal RSTn The first output signal in the second two equal-length delay chains RSTn Second output signal RSTnb The signal INTn The first output signal in the third two-way equal-length delay chain INTn Second output signal INTnb The signal RSTn The output signal is passed through the second delay chain. RSTDLYn and RSTDLYnb ; where mod is the modulo operation.

[0017] Optionally, the N-channel integral sampling control signal generation circuit further includes an nth-channel differential circuit sampling and amplification control signal generation circuit corresponding to the nth channel; the nth-channel differential circuit sampling and amplification control signal generation circuit has the same circuit structure as the nth-channel integrator reset and integral control signal generation circuit.

[0018] The signal T input to the sampling and amplification control signal generation circuit of the nth channel differential circuit (n+N-1)mod 2N and T (n+2N-1)mod 2N The non-overlapping signal is generated by sequentially passing through an OR gate logic, the first two equal-length delay chains, and the non-overlapping two-phase signal generation circuit. aSDn and aSDnb The signal aSDn The first output signal in the second two equal-length delay chains aSDnb Second output signal aSDn The signal aSDnb The first output signal in the third two-way equal-length delay chain sSDnb Second output signal sSDn The signal sSDn The output signal is passed through the second delay chain. sSDDLYn and sSDDLYnb .

[0019] Another technical solution provided by this invention is:

[0020] A system-on-chip for multi-channel microcurrent detection includes the aforementioned timing generation and control circuit, N-channel sampling circuit, and multiplexing circuit; each channel sampling circuit includes an integrator and a differential circuit connected in sequence.

[0021] The N-channel integral sampling control signal generation circuit in the timing generation control circuit is connected to the integrator and differential circuit of each channel in the N-channel sampling circuit; the output of the differential circuit of each channel is connected to the input of the multiplexing circuit.

[0022] Optionally, the N-channel integral sampling control signal generation circuit generates the fourth set of periodic square wave signals from the four sets of periodic square wave signals generated by each channel. aSDn and aSDnb It is also output to the control terminal of the multiplexing circuit as its selection control signal.

[0023] Optionally, it also includes an analog-to-digital converter; the control terminal of the analog-to-digital converter is connected to the output terminal of the three-phase non-overlapping clock generation circuit, and its input terminal is connected to the output terminal of the multiplexing circuit.

[0024] The beneficial effects of this invention are as follows: The timing generation control circuit and on-chip system provided by this invention for multi-channel microcurrent detection, through a specific timing generation control circuit structure consisting of a three-phase clock generation circuit, a first delay chain, a 2N-phase clock generation circuit, and an N-channel integral sampling control signal generation circuit connected in sequence; and a three-phase non-overlapping clock generation circuit connected to the three-phase clock generation circuit, can perform precise, synchronous, and conflict-free time-division multiplexing control on the N-channel integral sampling control signal generation circuit, systematically generating a large number of control signals that follow strict timing, and precisely controlling the integrators, differential circuits, and the shared multiplexer circuit and analog-to-digital converter of each channel; thereby obtaining a high-density integrated, low-channel crosstalk, and high-energy-efficiency current detection on-chip system, which can realize the precise detection of multiple biomolecules in parallel through multiple channels, significantly improving the detection speed and ensuring detection accuracy. Attached Figure Description

[0025] Figure 1 A schematic diagram of the overall structure of a timing generation control circuit for multi-channel microcurrent detection provided in an embodiment of the present invention;

[0026] Figure 2A schematic diagram of the circuit structure of a three-phase clock generation circuit in a timing generation control circuit for multi-channel microcurrent detection provided in an embodiment of the present invention;

[0027] Figure 3 This is a timing diagram of the signals generated by the three-phase clock generation circuit in an embodiment of the present invention;

[0028] Figure 4 A schematic diagram of the circuit structure of the first delay chain in a timing generation control circuit for multi-channel microcurrent detection provided in an embodiment of the present invention;

[0029] Figure 5 A schematic diagram of the circuit structure of a 2N-phase clock generation circuit in a timing generation control circuit for multi-channel microcurrent detection provided in an embodiment of the present invention;

[0030] Figure 6 A timing relationship diagram of the signal generated by the 2N-phase clock generation circuit in a timing generation control circuit for multi-channel microcurrent detection provided in an embodiment of the present invention;

[0031] Figure 7 A schematic diagram of the circuit structure of the nth channel integrator reset and integration control signal generation circuit in a timing generation control circuit for multi-channel microcurrent detection provided in an embodiment of the present invention;

[0032] Figure 8 A timing relationship diagram of the nth channel integrator reset and integration control signal generation circuit in a timing generation control circuit for multi-channel microcurrent detection provided in an embodiment of the present invention;

[0033] Figure 9 A schematic diagram of the circuit structure for generating the sampling and amplification control signal of the nth channel differential circuit in a timing generation control circuit for multi-channel microcurrent detection, provided in an embodiment of the present invention;

[0034] Figure 10 A timing relationship diagram of the signal generated by the sampling and amplification control signal generation circuit of the nth channel differential circuit in a timing generation control circuit applied to multi-channel microcurrent detection, provided in an embodiment of the present invention;

[0035] Figure 11 This is a schematic diagram of the circuit connection between an n-channel sampling circuit and a multiplexer circuit in an on-chip system for multi-channel microcurrent detection, provided as an embodiment of the present invention.

[0036] Figure 12 A schematic diagram of the timing relationship of multi-channel correlated double sampling in an on-chip system for multi-channel microcurrent detection provided in an embodiment of the present invention;

[0037] Figure 13 This is an exemplary circuit diagram for synchronizing the control and output results of an analog-to-digital converter in an on-chip system for multi-channel microcurrent detection, as provided in an embodiment of the present invention. Detailed Implementation

[0038] To explain in detail the technical principles, specific implementable solutions, possible application scenarios, and achievable objectives and effects of the present invention, exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. It is understood that the embodiments described herein and the embodiments shown in the accompanying drawings are only used to more clearly illustrate the technical solutions of the present invention, and are therefore only examples intended to explain the present invention, and should not be construed as limiting the present invention. It should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0039] Explanation of technical terms involved in this invention:

[0040] MCLK: The main clock signal for the timing generation control circuit, with a period of T. MCLK Typically 150ns, it is the core signal for timing generation and control circuits to perform multi-channel parallel control and operation; it is periodically generated by peripheral circuits (such as FPGAs).

[0041] N and n: N represents the number of current detection channels, meaning there are a total of N current detection channels, i.e., the number of current detection channels ∈ {1, 2, 3, ..., N}; n is the position index of sequence N, with a value range of 0 ≤ n ≤ N-1, meaning it starts counting from n=0, and n∈{0,1,2, ..., N-1}. For example, when N=68, it means there are a total of 68 current detection channels; when n=0, it indicates pointing to the 1st current detection channel.

[0042] Please see Figure 1 The embodiments of the present invention provide a timing generation control circuit for multi-channel microcurrent detection.

[0043] like Figure 1 As shown in the figure, this embodiment provides a timing generation and control circuit for multi-channel micro-current detection, including a three-phase clock generation circuit, a first delay chain, a 2N-phase clock generation circuit, and an N-channel integral sampling control signal generation circuit connected in sequence; it also includes a three-phase non-overlapping clock generation circuit connected to the three-phase clock generation circuit. The N-channel integral sampling control signal generation circuit includes N integral sampling control signal generation circuits corresponding one-to-one with N independent current detection channels, used to generate control signals for each channel respectively. N is a positive integer, preferably in the range of 64-256.

[0044] In this embodiment, the working principle of the timing generation control circuit is as follows:

[0045] The period is T MCLK The clock signal MCLK is input to the three-phase clock generation circuit of the timing generation control circuit; the generation period of the three-phase clock generation circuit is T. GCLK =3T MCLK Three periodic square wave signals with different phases 0、 1 and 2, and their respective complementary level signals. 0b , 1b and 2b The complementary level signal 0b , 1b and 2b Three sets of non-overlapping timing signals are generated using a three-phase non-overlapping clock generation circuit: s , sb , sDLY , sbDLY ; a , ab , aDLY , abDLY ; h , hb , hDLY , hbDLY These three sets of signals are used to control the same analog-to-digital converter shared by N channels. The periodic square wave signal... 0 generates a cycle of T through the first delay chain. GCLK Two complementary periodic square wave signals, GCLK and GCLKb, are used to drive the 2N-phase clock generation circuit to generate a clock with a period of 2N. T GCLK 2N periodic square wave signals T0, T1, ... to T with different phases 2N-1 and their respective complementary level signals T 0b T 1b ...to T 2N-1bThe 2N signals are processed by the N-channel integral sampling control signal generation circuit, which generates four sets of periodic square wave signals for each channel, respectively controlling the reset phase of the integrator for each channel. RSTn , RSTnb , RSTDLYn , RSTDLYnb ) and integral phase ( INTn , INTnb ), and the reset phase of the differential circuit ( sSDn , sSDnb , sSDDLYn , sSDDLYnb ) and amplified phase ( aSDn , aSDnb ).

[0046] Among them, signals with the subscript "b" are level complementary signals; signals with the subscript "DLY" are delayed versions of signals. The sign is a multiplication sign, indicating a multiplication operation.

[0047] The timing generation control circuit provided in this embodiment constructs a two-layer hierarchical timing circuit structure consisting of coarse-grained channel scheduling (three-phase clock) and fine-grained operation scheduling (2N-phase clock). Utilizing a unified clock source, it generates control signals at different time scales, ensuring that the N current detection channels share core resources (analog-to-digital converters, ADCs) in an orderly and conflict-free manner, while also guaranteeing the accurate execution of precise operations within each channel. This achieves precise, synchronous, and conflict-free time-division multiplexing control of the N channel integration sampling circuits, ultimately achieving the core technical effects of high-density integration, low inter-channel crosstalk, and high energy efficiency.

[0048] Please see Figure 2 Another embodiment of the present invention refines and expands the three-phase clock generation circuit based on the above embodiment.

[0049] In this embodiment, the three-phase clock generation circuit, as shown... Figure 2 As shown, a loop structure is formed by three D flip-flops and several inverters, driven by the clock signal MCLK.

[0050] The clock signal ports CLK of the three D flip-flops are connected sequentially. The clock signal port CLK of the first D flip-flop is then connected to the clock signal MCLK output port of the system's peripheral circuit (such as an FPGA). All three D flip-flops are driven by the clock signal MCLK. An even number of inverters are connected between the output port Q of the first D flip-flop and the data input port D of the second D flip-flop, between the output port Q of the second D flip-flop and the data input port D of the third D flip-flop, and between the output port Q of the third D flip-flop and the data input port D of the first D flip-flop. Figure 2 The example shown has two inverters connected. The output ports Q of the three D flip-flops output three periodic square wave signals with different phases. 0、 1 and 2. Its inverting output port Qb outputs corresponding complementary level signals respectively. 0b , 1b and 2b The reset signal RST is connected to the set port SET of the first D flip-flop, and the reset ports RST (full name RESET) of the second and third D flip-flops are connected to the set port SET of the first D flip-flop. Here, after a reset is triggered by the reset signal RST, as follows... Figure 3 As shown, the outputs of the three D flip-flops are 1, 0, and 0, respectively.

[0051] The three-phase clock generation circuit described in this embodiment has the following structural features:

[0052] (1) Ring topology: Three D flip-flops are connected end to end to form a loop. This allows the circuit to automatically generate a preset sequence without relying on external complex counting logic.

[0053] (2) Determined self-starting and initial state: By using the differentiated connection of the reset signal RST, it is ensured that the circuit always starts working from a determined initial state (1,0,0), avoiding the "invalid state" trap problem that may occur in the ring counter and ensuring the reliable start of the circuit.

[0054] (3) Built-in delay adjustment: By setting an even number of inverters between every two D flip-flops, the propagation delay between D flip-flops is increased to meet the hold time requirements of D flip-flops and eliminate timing errors caused by insufficient hold time. Its working principle is as follows: When the rising edge of the clock signal MCLK arrives, the outputs of all D flip-flops will be updated almost simultaneously; without inverters, the new output of the previous stage will immediately reach the data input port D of the next stage; if this change occurs within the hold time window of the next stage D flip-flop, it may destroy the correct sampling of data, resulting in timing errors; by setting the inverter insertion delay, the change of the new output of the previous stage will arrive at the next stage later than the delay time T_hold, thereby ensuring the correctness of the timing. In particular, the setting of an even number of inverters between every two D flip-flops in this embodiment can ensure that the signal polarity remains unchanged, and the next stage D flip-flop still receives the logic value of the output of the previous stage.

[0055] (4) Simple and direct output: Three-phase clock signal output by the three-phase clock generation circuit 0、 1 and 2 and its inverted signal 0b , 1b and 2b It comes directly from the output ports Q and Qb of three D flip-flops, requiring no additional decoding logic and featuring a simple circuit structure.

[0056] Based on the above structural features, the three-phase clock generation circuit provided in this embodiment can achieve the following technical effects:

[0057] (1) It can generate a strictly single-step cycle three-phase clock: after reset, the state is (1, 0, 0), and under the drive of the clock signal MCLK, it changes to 010->001->100 in sequence, and so on; the three phases generated are delayed by one MCLK cycle in sequence, and there is only one high-level clock signal in each cycle. This is the ideal waveform for realizing time-division multiplexing control, which can effectively avoid conflicts between channels.

[0058] (2) High reliability and determinism: The deterministic initial state (100) and simple ring shift structure ensure that the state transition path is unique and deterministic; the built-in delay adjustment eliminates the risk of hold-time violation, enabling the circuit to operate stably at higher MCLK frequencies.

[0059] (3) Simplified design, reduced power consumption and area: Compared with the existing scheme that uses a general-purpose counter (such as a binary counter) plus a 3-8 decoder to generate a three-phase clock, the three-phase clock generation circuit structure in this embodiment is extremely simple; it directly implements the state machine through hardware wiring, eliminating the need for complex combinational logic (decoder). This means fewer logic gates, lower power consumption and smaller chip area.

[0060] In summary, the three-phase clock generation circuit provided in this embodiment cleverly utilizes a ring flip-flop structure and a differentiated reset strategy to reliably generate a strictly non-overlapping three-phase clock reference that is crucial for multiple channels with minimal hardware resources. At the same time, the timing is optimized through built-in delay, laying a solid foundation for the stable and high-speed operation of the entire timing generation and control circuit.

[0061] Please see Figure 4 Another embodiment of the present invention, based on any of the above embodiments, further refines and expands the first delay chain, namely the signal generation circuits of GCLK and GCLKb.

[0062] In this embodiment, the first delay chain, such as Figure 4 As shown, it includes a delay chain body and two output paths. The delay chain body is composed of several cascaded inverters, and its input is connected to the periodic square wave signal in the three-phase clock generation circuit. The output terminal is connected to the two output paths. The first output path consists of two cascaded inverters and is used to output the square wave signal GCLKb. The second output path consists of a CMOS transmission gate and an inverter connected in sequence and is used to output the square wave signal GCLK. The two output paths have the same length (i.e., the propagation delay time is equal), but their output logic values ​​are opposite. Therefore, the levels of signals GCLK and GCLKb are precisely complementary.

[0063] In some specific implementations, such as Figure 1 As shown, since the first delay chain only affects the signal of the three-phase clock generation circuit... The 0 output terminal forms a load; in order to balance its signal 1 and signal The load at the output terminal is preferably the signal of the three-phase clock generation circuit. 1 and signal Add an inverter to each of the two output terminals as its output load.

[0064] In this embodiment, the first delay chain, through a delay-matched dual-path design, transmits the input signal... The conversion of 0 into a pair of precisely aligned true complementary clock signals GCLK and GCLKb significantly improves the quality of the clock signal and the timing reliability of subsequent circuits. For the latter, it effectively prevents logic races and short-circuit currents during clock transitions, thereby improving the stability and reliability of the entire system. Furthermore, since complementary clock signals are generated using matching techniques within the same circuit module (i.e., the first delay chain), the skew between the complementary clock signals can also be effectively controlled.

[0065] Please see Figure 5 and Figure 6 Another embodiment of the present invention refines and expands the 2N-phase clock generation circuit based on any of the above embodiments.

[0066] In this embodiment, as Figure 5 As shown, the 2N-phase clock generation circuit consists of 2N D flip-flops and several inverters forming a loop, driven by signals GCLK and GCLKb.

[0067] The clock signal ports CLK of 2N D flip-flops are connected sequentially. The clock signal port CLK of the first D flip-flop is then connected to the clock signal output port MCLK of the system's peripheral circuit (such as an FPGA). In the 2N sequentially connected D flip-flops, the output port Q of the preceding D flip-flop is connected to the data input port D of the following D flip-flop through an even number of inverters. The output port Q of the last (i.e., the 2Nth) D flip-flop is then connected back to the data input port D of the first D flip-flop through an even number of inverters, thus forming a loop structure. The output ports Q of the 2N D flip-flops output 2N periodic square wave signals T0, T1… to T… with different phases. 2N-1 Its inverting output port Qb outputs corresponding complementary level signals T. 0b T 1b …to T 2N-1b .like Figure 6 As shown, 2N periodic square wave signals T0, T1... to T... with different phases are generated. 2N-1 The period is 2N T GCLK The duty cycle is 1 / (2N); the phase Tn+1 (0≤n<2N-2) is delayed by T relative to Tn. GCLK Where n is the (N-1)th channel out of N channels, n∈{0,1,2,...,N-1}. The reset signal RST is connected to the set port SET of the first D flip-flop, and the reset ports RST (full name RESET) of the second to 2Nth D flip-flops are connected to the set port SET of the first D flip-flop. Here, after a reset is triggered by the reset signal RST, as follows... Figure 6 As shown, the outputs of the 2N D flip-flops are 1, 0, ... 0.

[0068] The 2N-phase clock generation circuit provided in this embodiment has the following structural features:

[0069] (1) Twisted ring topology: Connect 2N D flip-flops end to end to form a twisted ring topology.

[0070] (2) Differential clock drive: The D flip-flop is driven by precise complementary clock signals GCLK and GCLKb, which can reduce clock skew and ensure timing accuracy.

[0071] (3) Determined self-starting and initialization state: By using the differentiated connection of the reset signal RST, it is ensured that the circuit always starts working from a determined initial state (1,0,0,...,0), avoiding the problem of "invalid state" and ensuring reliable circuit startup.

[0072] (4) Simple and direct output: 2N phase signals T0 to T 2N-1 , and its complementary signal T 0b To T 2N-1b The outputs come directly from the output ports Q and Qb of each flip-flop, requiring no additional decoding logic, resulting in a simple structure.

[0073] Based on the above structural features, the 2N-phase clock generation circuit provided in this embodiment can achieve the following technical effects:

[0074] (1) Generate 2N equally spaced, low-duty-cycle precision clock phases:

[0075] Equal intervals: Each phase Tn+1 is delayed by one period T precisely compared to Tn. GCLK This forms 2N phases that are evenly distributed along the time axis;

[0076] Low duty cycle: The duty cycle of each phase signal is 1 / (2N), which is a "pulse" with a very short high-level duration. This narrow pulse can be used to precisely control the conduction timing of analog switches (in the N-channel integral sampling control signal generation circuit), so that it can generate signals that can accurately control the reset, integration, sample-and-hold operations in the correlated double sampling.

[0077] (2) High reliability and determinism: There are no invalid state cycles in the ring topology. Combined with the deterministic initial reset, the absolute reliability of the circuit operation is ensured and it will not "get stuck".

[0078] (3) High hardware efficiency: Only 2N D flip-flops are used to generate 2N different phases, with high encoding efficiency (only one bit changes in each state), which saves more area and power consumption than the scheme of binary counter plus decoder in phase.

[0079] In summary, the 2N-phase clock generation circuit provided in this embodiment, utilizing a twisted ring structure and differential clock, can efficiently and reliably generate a set of 2N-phase clocks with strictly equal time intervals and extremely low duty cycles with minimal hardware, providing key signals for precise timing control of multi-current detection channel systems.

[0080] Please see Figure 7 and Figure 8 Another embodiment of the present invention, based on any of the above embodiments, further refines and expands the N-channel integral sampling control signal generation circuit therein.

[0081] In this embodiment, the N-channel integral sampling control signal generation circuit includes n+1 channel integrator reset and integral control signal generation circuits corresponding one-to-one with the N channels, where n∈{0,1,2,...,N-1}. The signals generated by the channel integrator reset and integral control signal generation circuits are specifically used to control the integrators in the channels.

[0082] like Figure 7 As shown, the integrator reset and integration control signal generation circuit corresponding to the nth channel includes, in sequence, an OR gate logic, a first two-way equal-length delay chain, a non-overlapping two-phase signal generation circuit, a second two-way equal-length delay chain, a third two-way equal-length delay chain, and a second delay chain. The circuit structures of the first two-way equal-length delay chains, the second two-way equal-length delay chains, and the third two-way equal-length delay chains are identical. The first path in each chain consists of two cascaded inverters, and the second path in each chain consists of a CMOS transmission gate and an inverter connected in sequence. The circuit structure of the second delay chain is identical to that of the first delay chain.

[0083] The reset time of the integrator reset and integration control signal generation circuit of the nth channel is determined by the settling time and measurement accuracy of the corresponding nth channel integrator in the reset phase, denoted as m. T GCLK Where m is a positive integer. After the nth channel integrator reset and integration control signal generation circuit triggers the reset, the signal input to the nth channel integrator reset and integration control signal generation circuit is T. n T (n+1)mod2N To T (n+m-1)mod2N Where mod is the modulo operation; after being ORed by the OR gate logic, they generate a value with a width of m. T GCLK The period is 2N T GCLK A periodic square wave is generated and input to the first two equal-length delay chains, from which the first chain outputs a signal. RSTXn Second output signal RSTXbn These two signals are complementary in level; the signals RSTXn and the signal RSTXbn After passing through the non-overlapping two-phase signal generation circuit, non-overlapping signals are generated. RSTn and INTn The signal RSTn The first output signal in the second two equal-length delay chains RSTn Second output signal RSTnb The signal INTn The first output signal in the third two-way equal-length delay chain INTn Second output signal INTnb Among them, signals RSTnb and INTnb They are RSTn and INTn The signal is a level complementary signal; RSTn The output signal is also passed through the second delay chain. RSTDLYn and RSTDLYnb Among them, signals RSTn The delayed version of the signal is generated through the second delay chain. RSTDLYn and its level complementary signal RSTDLYnb .

[0084] In this embodiment, the N-channel integral sampling control signal generation circuit generates two sets of periodic square wave signals for each channel by resetting and integrating the N-channel integrator control signal generation circuit: the first set of periodic square wave signals... RSTn , RSTnb , RSTDLYn and RSTDLYnb This is used to control the reset phase of the integrator in the corresponding channel; where the signal... RSTDLYn and RSTDLYnb Used for bottom-plate sampling in the integrator. The second set of periodic square wave signals. INTn and INTnb This is used to control the integrating phase of the integrator in the corresponding channel, where the signal... INTn The width determines the integration time, which is approximately (2N-m). T GCLK .Signal RSTXn , RSTXbn , RSTn , RSTbn , INTn and INTnb Relative time relationships such as Figure 8 As shown. It can be seen that the signal... RSTXn and RSTXbn There is a temporal overlap between the rising and falling edges, but the signal... RSTn and INTn There is no overlap between the rising and falling edges; both are logic 1.

[0085] The N-channel integral sampling control signal generation circuit provided in this embodiment has the following structural features:

[0086] (1) It is composed of N circuit modules with identical structures in parallel. Each module independently generates control signals for the integrator in the corresponding channel. The structure is clear and easy to expand.

[0087] (2) Each circuit module first combines the continuous narrow pulses of the 2N-phase clock from the 2N-phase clock generation circuit into a single pulse with a width of m. T GCLKA controllable wide-pulse square wave is generated. Here, by changing the number of pulses *m* at the input OR gate, the width of the controllable wide-pulse square wave can be adjusted, thereby controlling the reset and integration phases of the integrator. Then, a precise timing chain (first two equal-length delay chains + non-overlapping two-phase signal generation circuit) is used to shape the wide pulse timing. Finally, a large number of delay chains (second two equal-length delay chains + third two equal-length delay chains + second delay chain) are used to generate high-quality timing signals. Non-overlapping control ensures that the reset and integration signals are not effective simultaneously, preventing signal conflicts that could lead to short circuits. The use of equal-length delay chains throughout to generate complementary signals ensures precise alignment of signal edges, making the on and off times of the control signals extremely accurate.

[0088] In summary, the N-channel integral sampling control signal generation circuit provided in this embodiment is a high-precision control signal generator structure that supports multi-module parallelism and timing-driven operation. It can convert 2N-phase clock signals into multi-channel control signals with flexible width, strict non-overlapping and edge alignment, and has extremely high timing integrity and reliability. It can realize reliable and high-performance timing control of multi-channel integrators.

[0089] Please see Figure 9 and Figure 10 Another embodiment of the present invention further refines and expands the N-channel integral sampling control signal generation circuit based on the previous embodiment.

[0090] In this embodiment, the N-channel integral sampling control signal generation circuit further includes n+1 channel differential circuit sampling and amplification control signal generation circuits corresponding one-to-one with the N channels, where n∈{0,1,2,...,N-1}. The signals generated by the channel differential circuit sampling and amplification control signal generation circuits are specifically used to control the differential circuits in the channels. Here, the differential circuit is a single-ended to differential circuit.

[0091] like Figure 9 As shown, the circuit structure of the differential circuit sampling and amplification control signal generation circuit corresponding to the nth channel is the same as that of the integrator reset and integration control signal generation circuit for the nth channel. The specific circuit structure will not be described in detail here; please refer to the description in the previous embodiment for more information.

[0092] Combination Figure 9 The working principle of the sampling and amplification control signal generation circuit of the nth channel differential circuit is as follows: the signal T input to the sampling and amplification control signal generation circuit of the nth channel differential circuit is... (n+N-1)mod 2N and T (n+2N-1)mod 2N The non-overlapping signal is generated by sequentially passing through an OR gate logic, the first two equal-length delay chains, and the non-overlapping two-phase signal generation circuit. aSDn and aSDnb The signal aSDn The first output signal in the second two equal-length delay chains aSDnb Second output signal aSDn The signal aSDnb The first output signal in the third two-way equal-length delay chain sSDnb Second output signal sSDn The signal sSDn The output signal is passed through the second delay chain. sSDDLYn and sSDDLYnb .

[0093] In this embodiment, the N-channel integral sampling control signal generation circuit will generate two sets of periodic square wave signals for each channel by sampling and amplifying the control signal generation circuit through N-channel differential circuits: a third set of periodic square wave signals. sSDn , sSDnb , sSDDLYn , sSDDLYnb Used to control the reset phase (also known as the sampling phase) of the differential circuit; the fourth group of periodic square wave signals. aSDn and aSDnb This is used to control the amplification phase of the differential circuit. (Signal) INTn , sSDn and aSDn Relative time relationships such as Figure 10 As shown. It can be seen that the signal... aSDn The signal width is T GCLK ;Signal sSDn and aSDn There is no overlap between the rising and falling edges; both are logic 1.

[0094] The N-channel differential circuit sampling and amplification control signal generation circuit provided in this embodiment has the same structure and working principle as the N-channel integrator reset and integration control signal generation circuit described in the previous embodiment. Therefore, the N-channel integral sampling control signal generation circuit provided in this embodiment has the same structural characteristics as the N-channel integrator reset and integration control signal generation circuit described in the previous embodiment. It can achieve the same technical effect for controlling differential circuits, that is, it can realize reliable and high-performance timing control of multi-channel differential circuits.

[0095] Embodiments of the present invention also provide a system-on-chip for multi-channel microcurrent detection.

[0096] Please see Figure 11 , Figure 12 and Figure 13 This embodiment provides an on-chip system for multi-channel microcurrent detection, including the timing generation and control circuit, N-channel sampling circuit, and multiplexing circuit described in any of the above embodiments.

[0097] The N-channel integral sampling control signal generation circuit in the timing generation control circuit is connected to the integrator and differential circuit of each channel in the N-channel sampling circuit. For example... Figure 11 As shown, each channel sampling circuit includes an integrator and a differential circuit connected in sequence; the output of the differential circuit of each channel is connected to the input of the multiplexing circuit. The multiplexing circuit is composed of two transmission gates connected in parallel to the output of the differential circuit in each channel, and its input includes differential signal outputs V corresponding to N channels respectively. opn and V onn The last 'n' corresponds to the nth channel; its input consists of only two differential signals V. op and V on .

[0098] In some specific implementations, the integrator output of each channel is a single-ended signal output, and the differential circuit is a single-ended to differential circuit. The output of the integrator is converted into a differential signal by the single-ended to differential circuit, and then selected by the multiplexing circuit.

[0099] In this embodiment, the timing of multi-channel correlated double sampling is as follows: Figure 12 As shown, the integrator completes each current integration cycle (2N-m). T GCLK Samples were taken twice, at T... (n+N-1)mod 2N and T (n+2N-1)mod 2NThat is, during and at the end of the integration. Therefore, by taking the difference between two samples and calculating the slope, we can not only obtain the average current, but also eliminate low-frequency noise.

[0100] In some other specific implementations, the N-channel integral sampling control signal generation circuit in the timing generation control circuit generates the fourth set of periodic square wave signals from the four sets of periodic square wave signals generated by each channel. aSDn and aSDnb It is also output to the control terminal of the multiplexing circuit as its selection control signal.

[0101] Optionally, the multiplexing circuit is a CMOS multiplexer.

[0102] In some other embodiments, the system-on-a-chip further includes an analog-to-digital converter; the control terminal of the analog-to-digital converter is connected to the output terminal of the three-phase non-overlapping clock generation circuit in the timing generation control circuit, and its input terminal is connected to the output terminal of the multiplexing circuit.

[0103] Optionally, the analog-to-digital converter is specifically implemented as a K-bit pipelined analog-to-digital converter, using a CMOS switched-capacitor structure.

[0104] As a specific example, such as Figure 13 As shown, the process of synchronizing control and output results through a K-bit pipelined analog-to-digital converter is as follows:

[0105] The output differential signal V of the CMOS multiplexer op and V on After being converted into K-bit digital signals D0, D1... to D by a K-bit pipelined analog-to-digital converter. K-1 Where K is a positive integer between 16 and 24. The three sets of signals generated by the three-phase non-overlapping clock generation circuit in the timing generation control circuit are: s , sb , sDLY , sbDLY ; a , ab , aDLY , abDLY ; h , hb , hDLY , hbDLY The output is sent to a K-bit pipelined analog-to-digital converter (ADC) to control the ADC's operation in the sampling (S), amplification (A), and hold (H) phases. To synchronize the output results, the ADC's output signals D0, D1, ... to D... K-1 And T N-1 T 2N-1 Each passes through a signal aDLY, The driver's register outputs a synchronization signal: D s0 D s1 ...to D sK-1 And T sN-1 T s2N-1 When T sN-1 When it is 1, it indicates that the current output D is... s0 D s1 ...to D sK-1 This is the value of the first sample from channel 0 (at this point, n=0, i.e., the first channel), the signal. aDLY, The output D of the next cycle s The value is the first sampled value of channel 1 (at this point, n=1, i.e., the second channel), and so on, until the first sampled value of channel N-1. Signal aDLY, In the next cycle, T s2N-1 A value of 1 indicates that the current output D is 1. s The value is the second sampled value of channel 0; in the next cycle, the second sampled value of channel 1 is output, and so on, until the second sample of channel N-1. Then the cycle repeats.

[0106] In particular, the on-chip system provided in this embodiment uses a multiplexer circuit and an analog-to-digital converter to process control signals for N channels, which greatly reduces the total chip area and hardware cost (the analog-to-digital converter is usually a module with a large area and power consumption in the chip).

[0107] The system-on-a-chip provided in this embodiment, based on the specific timing generation and control circuit provided in any of the above embodiments, through the circuit design of "time-division multiplexing" and "fine control", ensures that N detection channels can share core resources (analog-to-digital converters) in an orderly and conflict-free manner; and also ensures that the precision detection operations inside each detection channel are executed accurately; thereby achieving high-precision synchronous control of multi-channel integration and sampling, and achieving an excellent balance between chip area, power consumption and performance.

[0108] Although preferred embodiments of the invention have been described, those skilled in the art, upon understanding the basic inventive concept, can make other changes and modifications to the embodiments. Therefore, the appended claims are intended to cover the preferred embodiments and all equivalent modifications falling within the scope of protection defined by the claims and their equivalents. Clearly, those skilled in the art can make various alterations and variations to the invention without departing from its spirit and scope. If such modifications and variations fall within the scope of protection defined by the claims and their equivalents, the invention also intends to include them.

[0109] It should be noted that any reference signs placed between parentheses in the claims should not be construed as limiting the claims. The word "comprising" does not exclude the presence of components or steps not listed in the claims. The word "a" or "an" preceding a component does not exclude the presence of a plurality of such components. The invention can be implemented by means of hardware comprising several different components and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by the same item of hardware.

[0110] In this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "multiple" means two or more, unless otherwise explicitly specified. The term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone.

[0111] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0112] In this specification, the use of terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refers to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of the present invention. The illustrative expressions of the above terms in this specification should not be construed as necessarily referring to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0113] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent modifications made based on the content of the present invention specification and drawings, or direct or indirect applications in related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A timing generation and control circuit for multi-channel microcurrent detection, characterized in that, include: The circuit consists of a three-phase clock generation circuit, a first delay chain, a 2N-phase clock generation circuit, and an N-channel integral sampling control signal generation circuit connected in sequence; it also includes a three-phase non-overlapping clock generation circuit connected to the three-phase clock generation circuit. The period is T MCLK After the clock signal MCLK is input into the three-phase clock generation circuit, the generation period is 3T. MCLK Three periodic square wave signals with different phases 0、 1 and 2, and its corresponding complementary level signal 0b , 1b and 2b The complementary level signal 0b , 1b and 2b The three-phase non-overlapping clock generation circuit generates three sets of non-overlapping timing signals to control the same analog-to-digital converter shared by N channels; the periodic square wave signal 0 generates a period of T after passing through the first delay chain. GCLK Two complementary square wave signals, GCLK and GCLKb, are used to drive the 2N-phase clock generation circuit to generate a clock with a period of 2N*T. GCLK 2N periodic square wave signals T0, T1 to T2 with different phases 2N-1 and its corresponding complementary level signal T 0b T 1b To T 2N-1b The signal is input to the N-channel integral sampling control signal generation circuit, so that it generates four sets of periodic square wave signals for each channel, which are used to control the reset phase and integral phase of the integrator of each channel, as well as the reset phase and amplification phase of the differential circuit; where N is a positive integer. The 2N-phase clock generation circuit includes 2N D flip-flops and several inverters; the clock signal ports CLK of the 2N D flip-flops are connected sequentially; the output port Q of the previous D flip-flop is connected to the data input port D of the next D flip-flop through an even number of inverters, and the output port Q of the 2Nth D flip-flop is connected to the data input port D of the first D flip-flop through an even number of inverters; the reset ports RST of the second to the 2Nth D flip-flops are connected to the set port SET of the first D flip-flop; the output ports Q of the 2N D flip-flops respectively output 2N periodic square wave signals T0, T1 to T2 with different phases. 2N-1 Its inverting output port Qb outputs corresponding complementary level signals T. 0b T 1b To T 2N-1b .

2. The timing generation and control circuit for multi-channel microcurrent detection as described in claim 1, characterized in that, The N-channel integral sampling control signal generation circuit generates four sets of periodic square wave signals for each channel, including the first set of periodic square wave signals. RSTn , RSTnb , RSTDLYn and RSTDLYnb The second group of periodic square wave signals INTn and INTnb The third group of periodic square wave signals sSDn , sSDnb , sSDDLYn , sSDDLYnb and the fourth group of periodic square wave signals aSDn and aSDnb The first and second sets of periodic square wave signals are used to control the reset phase and integration phase of the integrator, respectively; the third and fourth sets of periodic square wave signals are used to control the reset phase and amplification phase of the differential circuit, respectively.

3. The timing generation and control circuit for multi-channel microcurrent detection as described in claim 1, characterized in that, The three-phase clock generation circuit includes three D flip-flops and several inverters; The clock signal ports CLK of the three D flip-flops are connected in sequence; the output port Q of the first D flip-flop is connected to the data input port D of the second D flip-flop through an even number of inverters, and the output port Q of the third D flip-flop is connected to the data input port D of the first D flip-flop through an even number of inverters; the reset ports RST of the second and third D flip-flops are connected to the set port SET of the first D flip-flop. The output ports Q of the three D flip-flops each output three periodic square wave signals with different phases. 0、 1 and 2. Its inverting output port Qb outputs corresponding complementary level signals respectively. 0b , 1b and 2b .

4. The timing generation and control circuit for multi-channel microcurrent detection as described in claim 1, characterized in that, The first delay chain includes a delay chain body and two output paths; the delay chain body is composed of several cascaded inverters, and its input is connected to the periodic square wave signal in the three-phase clock generation circuit. The output terminal is connected to the 0 output terminal, and its output terminal is connected to the two output paths; the first output path is composed of two cascaded inverters and is used to output the square wave signal GCLKb; the second output path is composed of a CMOS transmission gate and an inverter connected in sequence and is used to output the square wave signal GCLK.

5. The timing generation and control circuit for multi-channel microcurrent detection as described in claim 2, characterized in that, The N-channel integral sampling control signal generation circuit includes a circuit for resetting the integrator and generating the integral control signal corresponding to the nth channel; where n∈{0,1,2,...,N-1}. The integrator reset and integration control signal generation circuit of the nth channel includes an OR gate logic, a first two equal-length delay chain, a non-overlapping two-phase signal generation circuit, a second two equal-length delay chain, a third two equal-length delay chain, and a second delay chain connected in sequence. The circuit structures of the first two equal-length delay chains, the second two equal-length delay chains, and the third two equal-length delay chains are the same, wherein the first chain is composed of two cascaded inverters, and the second chain is composed of a CMOS transmission gate and an inverter connected in sequence. The circuit structure of the second delay chain is the same as that of the first delay chain. The signal T input to the nth channel integrator reset and integration control signal generation circuit n T (n+1)mod2N To T (n+m-1)mod2N After the OR operation of the aforementioned OR gate logic, a value with a width of m*T is generated. GCLK The period is 2N*T GCLK A periodic square wave is input to the first two equal-length delay chains, and the first chain outputs a signal. RSTXn Second output signal RSTXbn The signal RSTXn and the signal RSTXbn After passing through the non-overlapping two-phase signal generation circuit, a non-overlapping signal is generated. RSTn and INTn The signal RSTn The first output signal in the second two equal-length delay chains RSTn Second output signal RSTnb The signal INTn The first output signal in the third two-way equal-length delay chain INTn Second output signal INTnb The signal RSTn The output signal is passed through the second delay chain. RSTDLYn and RSTDLYnb Where m is a positive integer and mod is the modulo operation.

6. The timing generation and control circuit for multi-channel microcurrent detection as described in claim 5, characterized in that, The N-channel integral sampling control signal generation circuit also includes a differential circuit sampling and amplification control signal generation circuit corresponding to the nth channel; the differential circuit sampling and amplification control signal generation circuit of the nth channel has the same circuit structure as the integrator reset and integral control signal generation circuit of the nth channel. The signal T input to the sampling and amplification control signal generation circuit of the nth channel differential circuit (n+N-1)mod 2N and T (n+2N-1)mod 2N The non-overlapping signal is generated by sequentially passing through an OR gate logic, the first two equal-length delay chains, and the non-overlapping two-phase signal generation circuit. aSDn and aSDnb The signal aSDn The first output signal in the second two equal-length delay chains aSDnb Second output signal aSDn The signal aSDnb The first output signal in the third two-way equal-length delay chain sSDnb Second output signal sSDn The signal sSDn The output signal is passed through the second delay chain. sSDDLYn and sSDDLYnb .

7. A system-on-chip for multi-channel microcurrent detection, characterized in that, It includes the timing generation control circuit, the N-channel sampling circuit, and the multiplexing circuit as described in any one of claims 1 to 6; each channel sampling circuit includes an integrator and a differential circuit connected in sequence; The N-channel integral sampling control signal generation circuit in the timing generation control circuit is connected to the integrator and differential circuit of each channel in the N-channel sampling circuit; the output of the differential circuit of each channel is connected to the input of the multiplexing circuit.

8. The on-chip system for multi-channel microcurrent detection as described in claim 7, characterized in that, The N-channel integral sampling control signal generation circuit generates the fourth set of four periodic square wave signals for each channel. aSDn and aSDnb It is also output to the control terminal of the multiplexing circuit as its selection control signal.

9. The on-chip system for multi-channel microcurrent detection as described in claim 8, characterized in that, It also includes an analog-to-digital converter; the control terminal of the analog-to-digital converter is connected to the output terminal of the three-phase non-overlapping clock generation circuit, and its input terminal is connected to the output terminal of the multiplexing circuit.

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