PCIe retimer with low latency mode for reduced power

Abstract

An illustrative retimer includes an upstream interface having an upstream receiver configured to convert a downlink signal to a stream of downlink symbols; a downstream interface having a downstream transmitter configured to provide a transmit signal representing a stream of downlink symbols; core circuitry having a downstream path and a downstream bypass path; and a controller. The downstream path is configured to transmit the downlink stream of symbols from the upstream receiver to the downstream transmitter via the receive clock domain component, the core clock domain component, and the transmit clock domain component. The downstream bypass path is configured to transmit the downlink stream of symbols from the upstream receiver to the downstream transmitter without any core clock domain component. The controller is configured to disable a clock signal for a transmit clock domain component of the downstream path when the downstream bypass path is enabled.

Description

Background Technology

[0001] The Peripheral Component Interconnect High Speed ​​(“PCIe”) specification is one of several standards for general-purpose input / output interconnects. This type of interconnect is frequently used as an expansion bus to accept expansion cards or other interchangeable components to enhance the resources and functionality of computers and other electronic systems. The PCI Special Interest Group (PCI Special Interest Group) is an industry alliance that updates the PCIe specification every few years to double the data rate while maintaining backward compatibility as much as possible. The PCIe 7.0 specification, finalized in 2025, will support 8 × 10⁻⁶ data rates per lane. 9 Each PAM4 symbol, in a 16-channel configuration, delivers a net raw symbol rate of 128 GT / s in each direction. The net bit rate of a 16-channel PCIe link will reach up to 242 Gbps. This bit rate makes PCIe attractive for systems designed for machine learning, artificial intelligence, real-time image processing, gaming, high-bandwidth data storage, and even computer-centric networks.

[0002] Because it was originally a parallel bus, PCIe has strict latency limitations to favor load-memory interconnect protocols. This latency limitation inevitably restricts the range of a given PCIe link, especially at high symbol rates where noise or other signal integrity issues may necessitate relatively frequent retransmissions. Retimers can address such signal integrity issues and improve consistency, significantly reducing average transaction latency (although this increases minimum latency).

[0003] Depending on the signal integrity issues presented in a given link, it is possible to bypass certain functions of the retimer and thus reduce the latency associated with it. As an example, a PCIe retimer can operate to remove skew between channels of a link, thereby improving the alignment between symbol streams arriving at the endpoints of the link. This anti-skew operation requires some form of symbol stream buffering, which inevitably introduces latency. If the channel skew is determined to be negligible or at least within acceptable tolerances, this function can be bypassed to avoid the associated buffering latency. For this purpose, some retimers can support a "low latency" mode, which the root complex can invoke to at least bypass the anti-skew function. It can be expected that such retimers can exit the low latency mode immediately. The undesirable level of power consumption in the ready state of this low latency mode may be quite comparable to the power consumption in the normal operating mode of the retimer. Summary of the Invention

[0004] Therefore, this paper discloses a method for reducing power consumption in the low-latency mode of a recharge timer and a recharge timer suitable for using such a method. An illustrative recharge timer includes: an upstream interface having an upstream receiver configured to convert a downlink signal into a downlink symbol stream; a downstream interface having a downstream transmitter configured to provide a transmit signal representing the downlink symbol stream; a core circuit system having a downstream path and a downstream bypass path; and a controller. The downstream path is configured to transmit the downlink symbol stream from the upstream receiver to the downstream transmitter via a receive clock domain component, a core clock domain component, and a transmit clock domain component. The downstream bypass path is configured to transmit the downlink symbol stream from the upstream receiver to the downstream transmitter without any core clock domain component. The controller is configured to disable the clock signal for the transmit clock domain component of the downstream path when the downstream bypass path is enabled.

[0005] An illustrative method for reducing the power consumption of a retimer in a low-latency mode includes: converting a downlink signal into a downlink symbol stream using an upstream receiver; providing a transmit signal representing the downlink symbol stream using a downstream transmitter; transmitting the downlink symbol stream from the upstream receiver to the downstream transmitter using a downstream path having a receive clock domain component, a core clock domain component, and a transmit clock domain component; enabling a downstream bypass path from the upstream receiver to the downstream transmitter in response to an ordered set for enabling the low-latency mode, the downstream bypass path operating without any clock domain component; and disabling the clock signal for the transmit clock domain component of the downstream path after enabling the downstream bypass path.

[0006] The aforementioned retimer and method can be implemented as the core of semiconductor intellectual property to generate a retimer circuit system for performing the method.

[0007] Each of the foregoing embodiments can be implemented individually or in combination, and can be implemented in any suitable combination with any one or more of the following features: 1. The transmit clock domain component is one of a scrambler and a transmit buffer. 2. The core clock domain component is one of a channel anti-skew module, an ordered set decoder, and an ordered set modifier. 3. The receive clock domain component is one of a descrambler and a receive buffer. 4. The downstream path includes multiple channels, and the controller is configured to disable the clock signal for all channels except one channel in the core clock domain component when the downstream bypass path is enabled. 5. The controller is further configured to disable the clock signal for the core clock domain component of the downstream path when the downstream bypass path is enabled. 6. The controller is further configured to disable the clock signal for the receive clock domain component of the downstream path when the downstream bypass path is enabled. 7. A correlation module is coupled to the downstream bypass path and configured to detect the ordered set for re-enabling the downstream path. 8. The retimer further includes a management interface configured to receive a command for re-enabling the downstream path. 9. The downstream interface has a downstream receiver configured to convert the received signal into an uplink symbol stream. 10. The upstream interface has an upstream transmitter configured to provide an uplink signal representing the uplink symbol stream. 11. The core circuitry has an upstream path configured to transmit the uplink symbol stream from the downstream receiver to the upstream transmitter, the upstream path having a receive clock domain component, a core clock domain component, and a transmit clock domain component; and an upstream bypass path configured to transmit the downlink symbol stream from the downstream receiver to the upstream transmitter without any core clock domain component. 12. The controller is configured to disable the core clock domain component of the upstream path when the upstream bypass path is disabled. Attached Figure Description

[0008] Figure 1 An illustrative computer is shown.

[0009] Figure 2 This is a block diagram illustrating the retimer.

[0010] Figure 3 The state transition diagram is for illustrating the training state machine of the link. Detailed Implementation

[0011] Note that the specific embodiments given in the accompanying drawings and the following description do not limit this disclosure. Rather, they provide a basis for those skilled in the art to identify alternatives, equivalents, and modifications included within the scope of the claims.

[0012] The disclosed retimer and low-latency method for reducing power are best understood in an explanatory context. Therefore, Figure 1An illustrative computer system 102 is shown, having a central processing unit 104 coupled to other components such as system memory 108, video display interface 110, non-volatile information storage device 112, user input / output interface 114, network interface 116, and expansion bus bridge 118 via a system bus 106. The computer system 102 can represent a server, workstation, desktop computer, laptop computer, or virtually any form of scalable computer equipment. System memory 108 and / or information storage device 112 provide software to the central processing unit 104, thereby configuring the computer system 102 to interact with the user and / or perform desired functions. As an example, the computer system 102 can be used as a high-bandwidth, network-accessible storage device. As another example, the computer system 102 can interact with other computer systems as part of a computer cluster implementing machine learning, artificial intelligence, real-time image processing, gaming, numerical simulation, or other types of highly parallel processing tasks.

[0013] To this end, computer system 102 can control a set of high-bandwidth resources via one or more expansion bus bridges 118. In at least some of the contemplated embodiments, the bridges 118 serve as part of a PCIe Root Complex, providing access to a set of PCIe endpoints 130, 132, and 138 via switch 120. To achieve greater range between the switch and the endpoints, each endpoint 130, 132, and 138 can be coupled to switch 120 via a corresponding retimer 131, 133, and 139. As further described herein, the retimers can be configured to implement a low-latency mode with reduced power consumption.

[0014] Figure 2An illustrative monolithic transceiver chip 200 is shown. Chip 200 includes a serializer module 204 and a deserializer module 205, an additional serializer module 206 and a deserializer module 207, and core logic 210-237. Serializer module 204 and deserializer module 205 have contacts 201 for transmitting and receiving high-rate symbol streams in each of eight channels in the downlink (e.g., to endpoint 130). Additional serializer module 206 and deserializer module 207 have contacts 202 for transmitting high-rate symbol streams to and from the uplink (e.g., to switch 120). Core logic 210-237 implements a channel communication protocol while transmitting symbol streams between the uplink and downlink. It also includes various support modules, such as a power and clock module 240 with contact 241, a controller module 242, a digital input / output module 244 with contact 245 for control signals, and a JTAG module 246 with contact 247 for built-in self-test. Although eight channels are shown here, the actual number of channels may vary depending on the specifications of the relevant standards.

[0015] Deserializer modules 205 and 207 implement the receiving function of chip 200, implement decision feedback equalization (“DFE”) or any other suitable equalization technique, including those employing discrete-time finite impulse response (“FIR”) filters with adjustable tap coefficients, such as linear equalization and partial response equalization. Deserializer module 205 converts the uplink signal into a parallel uplink symbol stream, and similarly, deserializer module 207 converts the downlink signal into a parallel downlink symbol stream. The core logic includes components 230-237 for coupling the uplink symbol stream from deserializer 205 to the upstream path of serializer 206, and corresponding components for coupling the downlink symbol stream to the downstream path of serializer 204. Serializers 204 and 206 implement the transmitting function of chip 200 with optional pre-equalization to combat signal attenuation. Serializer 204 includes a transmitter to provide a transmit signal representing a downlink symbol stream, and serializer 206 similarly includes a transmitter to provide a transmit signal representing an uplink symbol stream. Serializer 204 and deserializer 205 can together form a downstream interface, while serializer 206 and serializer 207 can together form an upstream interface of retimer chip 200.

[0016] As part of the receiving process, deserializer modules 205 and 207 derive the symbol clock from the uplink and downlink signals. (The symbol clock is derived for each channel, but for clarity, in...) Figure 2 Only a single symbol clock from each deserializer module is shown and described. Deserializer 205 recovers the downstream interface receive clock signal CLK from the uplink signal. RDFurthermore, the deserializer 207 recovers the upstream interface receive clock signal CLK from the downlink signal. RU As part of the transmission process, serializer modules 204 and 206 generate symbol clocks for the transmitted signal. Serializer module 204 generates the downstream interface transmit clock signal CLK. TD Furthermore, the serializer module 206 generates the upstream interface transmit clock CLK. TU Downstream and upstream paths can respectively include components operating in multiple clock domains. A downstream path may include a component receiving a clock signal CLK from an upstream interface(s). RU One or more components operating in the driven receive clock domain 210, under the core clock signal CLK provided by the power and clock module 241. C One or more components operating in the core clock domain 212 of the driver, and the clock signal CLK transmitted by the downstream interface. TD One or more components operating in the driven transmit clock domain 214. The upstream path can similarly include receiving the clock signal CLK via the downstream interface. RD The components operating in the receive clock domain 216, the components operating in the core clock domain 212, and the components transmitting the clock signal CLK from the upstream interface. TU The component that operates in the driven transmit clock domain 218.

[0017] Examples of components that can operate in the receive clock domain 216 include a descrambler 230, which applies a predetermined exclusive-OR mask to the uplink symbol stream to recover the unscrambled symbol stream. (Such reversible masking operations can improve performance by flattening the spectrum of the symbol stream traversing the channel.) Another illustrative component is a flexible buffer 231, which allows for drift between clock frequencies in different domains.

[0018] Examples of components that can operate in the core clock domain 212 include a lane deskew 232 that reduces or eliminates skew between channels of the uplink symbol stream. Other illustrative components include an ordered set (OS) decoder 233 and an ordered set modifier 234. The OS decoder 233 extracts and decodes command and control parameters contained in fields between data frames. The link state machine (LSM) module 235 accepts commands from the OS decoders in the upstream and downstream paths and, if necessary, invokes the appropriate OS modifier 234 to respond to or update the ordered set before forwarding.

[0019] Examples of components that can operate in the transmit clock domain 218 include transmit buffer 236 to facilitate transitions between clock domains, and as another example, scrambler module 237 can apply a predetermined XOR mask to flatten the spectral content of data frames in the symbol stream.

[0020] While the aforementioned core components can be used to enhance link performance, some links may not require them. This is, for example, the case when the uplink and downlink clock signals are strictly aligned. In such cases, the core circuitry of the retimer provides an upstream bypass path 220 and a multiplexer 221, which selects between the upstream path and the upstream bypass path to feed the uplink symbol stream to the serializer 206. Similarly, a downstream bypass path 222 can be provided with a multiplexer 223, which selects between the downstream path and the downstream bypass path to feed the downlink symbol stream to the serializer 204. These bypass paths can eliminate the latency associated with the upstream and downstream path components and can be invoked by an ordered set in the downlink symbol stream, which provides vendor-defined commands that enable or disable the bypass paths for selectively providing a low-latency mode of operation.

[0021] The power and clock module 240 regulates power and distributes it to other components of the chip 200, and generates the core clock signal CLK. C Alternatively, the core clock signal CLK can be derived from the reference clock signal received via contact 241. C The power and clock module 240 distributes the core clock signal to at least the core clock domain 212, and may further distribute the core clock signal to a reference clock for other components of the chip 200.

[0022] Controller module 242 may include a programmable microcontroller and non-volatile memory with firmware configuring the operation of the programmable microcontroller. Controller module 242 can configure and coordinate the operation of other components, particularly when their operation is constrained by configuration parameters initialized during a startup or reset process. In addition, controller module 242 can provide a set of clock enable signals 250. Each clock enable signal is coupled to a gate to block the associated clock signal when deactivated and to pass the associated clock signal when activated.

[0023] The digital I / O module 244 can implement a management bus interface, enabling monitoring and modification of the operation of the control module and even the entire chip. The digital I / O module 244 can support one or more suitable management bus protocols, such as I... 2C, MDIO, and SPI enable an external host to read from and write to the configuration registers in controller module 242. Digital I / O module 244 can further support enable signal inputs and one or more of fault, status, error, or interrupt signals outputs. JTAG module 246 can be reserved for use by automated test equipment in built-in self-test according to the JTAG specification.

[0024] Here we note that when a bypass path is enabled, there is an opportunity to reduce power consumption by disabling unused components in the upstream and downstream paths. Therefore, when the LSM module 235 instructs it appropriately, the controller module 242 provides a clock enable signal, enabling the controller to selectively enable and disable components in the upstream and downstream paths. Such a clock enable signal can alternatively be generated directly by the LSM module 235.

[0025] In the first conceptual embodiment, the LSM module 235 and / or the controller module 242 disable the transmit clock domain clock signal CLK when entering low-latency mode via an enabled bypass path (or shortly thereafter). TU and CLK TD Receive clock domain clock signal CLK RU and CLK RD and the core clock signal CLK C It can remain enabled. The continuous operation of the associated receive clock domain and core clock domain components enables the LSM module 235 to monitor ordered sets in the uplink and downlink symbol streams to obtain commands to exit low-latency mode. When such an exit command is received, the LSM module 235 and / or controller module 242 re-enable the transmit domain clock signal CLK. TU and CLK TD This causes multiplexers 221 and 223 to deselect the bypass path and reselect the upstream and downstream paths, respectively.

[0026] In a first variation of the first conceptual embodiment, components can be reordered to advance the OS decoder 233, for example, by placing it before the channel anti-skew module 232. For all components following decoder 233 in each of the upstream and downstream paths, their clock signals can be disabled until a low-latency mode exit command is detected.

[0027] In a second variation of the first conceptual embodiment, it is assumed that any command to exit low-latency mode will be received from the upstream interface. In this case, in addition to disabling the transmit domain clock signal CLK... TU and CLK TDIn addition, the LSM module and / or controller module can further disable the clocks to other upstream path components 230-234, 236-237. When a single downlink symbol stream channel is sufficient to receive the exit command, the clock signal can be disabled for all downlink symbol channels except for one, thereby significantly reducing power consumption.

[0028] In a second conceptual embodiment, controller module 242 deactivates all clock enable signals 250 after enabling the bypass path. This minimizes power consumption in low-latency mode but may prevent LSM module 235 from monitoring the symbol stream used for exit commands. Alternatively (in this and other conceptual embodiments), chip 200 can be forcibly reset or exited from low-latency mode by providing an appropriate value to the controller configuration register via the management bus.

[0029] In a variant of the second transistor concept embodiment, disabling all clock enable signals causes gate 225 to receive the upstream interface clock signal CLK. RU The signal is passed to pattern-matched filter 224 (also known as the correlation module), enabling the filter to monitor the downlink symbol stream to indicate the mode of the exit command from the low-latency time mode. (The ordered set is not scrambled, so pattern detection does not require descrambling.) As previously stated, gate 226 prevents the upstream interface of the receive clock domain 210 from receiving the clock signal CLK from the downstream path. RU The pattern matching filter 224 is sufficient for operation on a single channel of the downstream symbol stream. Upon detecting an exit command, filter 224 can cause controller module 242 to activate all clock enable signals and switch multiplexers 221 and 223 from the bypass path to the original upstream and downstream paths, respectively.

[0030] Figure 3 This is a state transition diagram for the illustrative link training state machine. States 300-309 correspond to the states of the Link Training and State Machine (LTSSM) shown and described in Section 4.2 of PCIExpress Base Specification Revision 6.1. The referenced specification is incorporated herein by reference in its entirety. For the first conceptual embodiment, state 320 is modified and states 326-328 are added. For the second conceptual embodiment, state 330 is added. For a variant of the second conceptual embodiment, state 340 is added. The LSM module can independently implement state machines for uplink and downlink.

[0031] State 300 is the initial startup state of the LSM module and can be returned to in the event of a reset or link failure. State 300 represents a detection state used by the LSM module to detect when the upstream and downstream link channels each terminate at a remote end (i.e., each connected to a port that can send signals to at least one channel of the upstream interface of the repeater and at least one channel of the downstream interface of the repeater). The lack of such termination can manifest as high impedance on the output signal conductor.

[0032] State 301 is the hot reset state. The LSM module enters this state if the controller module triggers it, or if the OD decoder indicates that a hot reset command has been received. After a 2ms timeout, the LSM module enters detection state 300.

[0033] State 302 is the polling state, which the LSM module enters from state 300 after determining which channels have terminated. In the polling state, the upstream and downstream interfaces transmit training ordered sets and respond to the training ordered sets they receive. The receiver locks (clocks synchronize) using symbols and blocks transmitted by the uplink and downlink links, adjusting channel polarity and equalizer settings as needed. The interfaces exchange capacity information to negotiate the data rate. If enough training ordered sets have been exchanged before timeout, the LSM module transitions to state 303. Otherwise, it returns to state 300.

[0034] State 303 is the configuration state, where a negotiation sequence is implemented to determine the channel width and channel number of the link. If the link is disabled by the controller or command OS, the LSM module transitions to state 304. If the controller or ordered set command puts the link into loopback mode, the LSM module transitions to state 305. If the negotiation sequence completes before timeout, the LSM module transitions to state 306. Otherwise, the LSM module transitions to state 320.

[0035] State 304 is a disabled state, during which the interface maintains the link in Electrically Idle mode. When an Electrically Idle exit command is detected, the LSM module will transition from this state to state 300.

[0036] State 305 is the loopback test mode, which the controller can use to perform link tests. During loopback test mode, the interface initiating the loopback request is the leading end, and the transmission will be echoed by the remote end in symbol mode. When the LSM module exits this state, it will return to detection state 300.

[0037] State 306 is referred to as the L0 state, which represents the normal operating state of the link used for transmitting and receiving data and control packets. The LSM module can exit the L0 state upon the occurrence of an event or upon detecting a command OS. The L0 state may have a sub-state L0p, in which some channels of the link are placed into idle mode while the remaining channels remain active. L0p is intended as a first power-saving state. When a transition is encountered (e.g., a request to use a different data rate or a switch to low-latency mode), the LSM module transitions from the L0 state to the recovery state 320.

[0038] State 307 is the power-saving state L0s that the LSM module enters from state 306 when it detects an electrical idle command set. The channel remains in the electrical idle state until an electrical idle exit command is detected. Before returning to box 306, the LSM module exchanges a fast training sequence across links to re-establish synchronization. If the fast training sequence fails to complete successfully, the LSM module transitions to recovery state 320.

[0039] State 308 is power-saving state L1, which provides better power savings at the cost of additional recovery delay. This state can be selected by the controller or by an ordered set of commands, as an alternative to state L0s. Once exiting this state, the LSM module transitions to recovery state 320.

[0040] State 309 is power-saving state L2, in which most of the interface is powered down to actively conserve power. When power is restored or a wake-up event is detected in other ways, the LSM module will transition to detection state 300.

[0041] In recovery state 320, before optionally returning to state 306, the LSM module acknowledges or re-establishes synchronization, and may optionally update the leveling settings and renegotiate the data rate. The LSM can also transition from this state to other states if prompted by the controller or command OS. For example, the controller may initiate a transition to loopback state 305, hot reset state 301, or disabled state 304.

[0042] Recovery state 320 can be enhanced to facilitate the transition to a low-latency state. If a command OS to enter a low-latency state is detected in state 306, the LSM can transition to recovery state 320 before enabling upstream and downstream bypass paths. In this mode, no data symbols will be in transition during the handover, symbol stream synchronization locks can be re-established, and data rate and equalization settings can be renegotiated before exiting recovery state 320.

[0043] States 326-328 are first conceptual embodiments of a low-latency mode (LL1) with reduced power. State 326 is the normal operating mode L0 with a bypass path enabled in the low-latency state. LL1 As previously mentioned, the clocks of selected components in the upstream and downstream paths can be disabled. The LSM module continues to monitor the ordered set and can transition to the substate L0p. LL1 Some of these channels are placed in idle mode, while the rest remain active.

[0044] State 327 is similar to power-saving state 307, but a bypass path is enabled. The channel remains electrically idle until startup exit as previously discussed in conjunction with state 307. The LSM module can return from state 327 to state 326 or resume state 320.

[0045] State 328 is similar to power-saving state 308, but a bypass path is enabled. Upon startup exit, the LSM module returns to recovery state 320.

[0046] Since the corresponding state of state 309 is equivalent to state 309, the LSM module can transition from state 326 to state 309. All paths, including bypass paths, are de-energized to actively conserve power.

[0047] States 330-328 are a second conceptual embodiment of the low-latency mode (LL2) with reduced power. This is the normal operating mode L0 with the bypass path enabled in the low-latency state. LL2 The clocks of the upstream and downstream path components are disabled, preventing the LSM module from monitoring the ordered set. Exiting this state occurs via a reset of the retimer chip 200 or, for example, via sideband communication on the management bus.

[0048] State 340 is a variant of the second conceptual embodiment that can be used for a low-latency mode (LL3) with reduced power. This is the normal operation mode L0 with a bypass path enabled in the low-latency state. LL3 The upstream and downstream components are clocked, but the pattern-matched filter enables monitoring of the selected OS mode that allows the LSM module to return to recovery state 320. The LSM can also support substate L0p. LL3 Some of these channels are placed in idle mode, but in at least some embodiments, the transition will occur via recovery state 320.

[0049] Re-timers and other interfaces that employ serializer and deserializer modules have become so complex that it is impractical for electronics designers to design them from scratch. Instead, electronics designers rely on predefined modular units of integrated circuit layout design, arranging and assembling them as needed to achieve the various functions of the desired device. Each modular unit has a defined interface and behavior that has been validated by its creator. While creating each modular unit can be time-consuming and costly, the availability of modular units for reuse and further development significantly reduces product cycle time and results in better products. Predefined units can be organized hierarchically, where a given unit contains one or more lower-level units, which in turn are contained within higher-level units. Many organizations have libraries of such predefined modular units for sale or licensing, including, for example, embedded processors, memories, interfaces for different bus standards, power converters, frequency multipliers, sensor transducer interfaces, etc. Predefined modular units are also referred to as cells, blocks, cores, and macros; these terms have different meanings and variations (“IP core”, “soft macro”), but are often used interchangeably.

[0050] Modular cells can be expressed in different ways, such as as Hardware Description Language (HDL) files or as fully routed designs that can be directly printed to create a range of manufacturing process masks. Fully routed designs are typically process-specific, meaning additional design work is often required to migrate the modular cells to different processes or manufacturers. Modular cells in HDL form require subsequent synthesis, placement, and routing steps to implement, but they are process-independent, meaning different manufacturers can apply their preferred automated synthesis, placement, and routing processes to implement the cells using a wide range of manufacturing processes. Due to their higher-level representation, HDL cells are more accommodating to the use of modified and variable design parameters, while fully routed cells offer better predictability in terms of area requirements, reliability, and performance. While there are no fixed rules, digital modular designs are more commonly specified in HDL form, while analog and mixed-signal cells are more often specified in lower-level physical descriptions. In either case, such semiconductor IP cores can be stored in a design database located on a non-volatile information storage medium, such as a hard disk, flash drive, or any known cloud-based abstraction of non-volatile information storage in hardware. Once the equipment has been fully designed, commercially available software can convert the core semiconductor intellectual property and other integrated circuit components into semiconductor mask patterns, which are then stored on a non-transient information storage medium. These patterns can then be transferred to various processing units on the appropriate assembly line in an integrated circuit manufacturing plant.

[0051] Once the foregoing disclosure is fully understood, numerous alternatives, equivalents, and modifications will become apparent to those skilled in the art. The order of modules and operations described in the upstream and downstream paths may be altered, with certain operations being reordered, pipelined, and / or performed in parallel. Where applicable, the claims are intended to be construed as encompassing all such alternatives, equivalents, and modifications.

Claims

1. A re-timer, comprising: An upstream interface having an upstream receiver configured to convert downlink signals into a downlink symbol stream; A downstream interface having a downstream transmitter configured to provide a transmission signal representing the downlink symbol stream; The core circuit system has: A downstream path, configured to transmit the downlink symbol stream from the upstream receiver to the downstream transmitter, the downstream path having a receive clock domain component, a core clock domain component, and a transmit clock domain component; as well as A downstream bypass path is configured to transmit the downlink symbol stream from the upstream receiver to the downstream transmitter without any core clock domain components. A controller configured to disable the clock signal for the transmit clock domain component of the downstream path when the downstream bypass path is enabled.

2. The re-timer as described in claim 1, wherein, The transmit clock domain component is one of a scrambler and a transmit buffer.

3. The re-timer as described in claim 1, wherein, The controller is further configured to disable the clock signal for the core clock domain component of the downstream path when the downstream bypass path is enabled.

4. The re-timer as described in claim 3, wherein, The core clock domain component is one of the channel anti-skew module, ordered set decoder, and ordered set modifier.

5. The re-timer as described in claim 3, wherein, The controller is further configured to disable the clock signal for the receive clock domain component of the downstream path when the downstream bypass path is enabled.

6. The re-timer as described in claim 5, wherein, The receive clock domain component is one of a descrambler and a receive buffer.

7. The re-timer as described in claim 1, wherein, The downstream path includes multiple channels, and the controller is configured to disable the clock signals of all channels except one in the core clock domain component when the downstream bypass path is enabled.

8. The retimer of claim 1, further comprising a correlation module coupled to the downstream bypass path and configured to detect an ordered set for reactivating the downstream path.

9. The retimer of claim 1, wherein the retimer further includes a management interface configured to receive a command for reactivating the downstream path.

10. The re-timer as described in claim 1, in, The downstream interface has a downstream receiver configured to convert the received signal into an uplink symbol stream. The upstream interface includes an upstream transmitter configured to provide uplink signals representing the uplink symbol stream. The core circuit system has the following features: An upstream path, configured to transmit the uplink symbol stream from the downstream receiver to the upstream transmitter, the upstream path having a receive clock domain component, a core clock domain component, and a transmit clock domain component; and An upstream bypass path is configured to transmit the downlink symbol stream from the downstream receiver to the upstream transmitter without any core clock domain components. The controller is configured to disable the core clock domain component of the upstream path when the upstream bypass path is disabled.

11. A method for reducing the power consumption of a retimer in a low-latency mode, the method comprising: The upstream receiver is used to convert the downlink signal into a downlink symbol stream; The downstream transmitter provides the transmission signal representing the downlink symbol stream; The downlink symbol stream is transmitted from the upstream receiver to the downstream transmitter using a downstream path that has a receive clock domain component, a core clock domain component, and a transmit clock domain component. In response to an ordered set for enabling a low-latency mode, a downstream bypass path from the upstream receiver to the downstream transmitter is enabled, the downstream bypass path operating without any clock domain components. as well as After enabling the downstream bypass path, disable the clock signal of the transmit clock domain component used for the downstream path.

12. The method of claim 11, wherein, The transmit clock domain component is one of a scrambler and a transmit buffer.

13. The method of claim 11, further comprising disabling clock signals for the core clock domain component of the downstream path after enabling the downstream bypass path.

14. The method of claim 13, wherein, The core clock domain component is one of the channel anti-skew module, ordered set decoder, and ordered set modifier.

15. The method of claim 13, further comprising disabling the clock signal for the receive clock domain component of the downstream path after enabling the downstream bypass path.

16. The method of claim 15, wherein, The receive clock domain component is one of a descrambler and a receive buffer.

17. The method of claim 11, wherein, The downstream path includes multiple channels, and the method further includes disabling the clock signals of all channels in the core clock domain component except for one channel after enabling the downstream bypass path.

18. The method of claim 11, further comprising monitoring the downlink symbol stream with a correlation module coupled to the downstream bypass path, the correlation module being configured to detect an ordered set for reactivating the downstream path.

19. A non-transient information storage medium having a semiconductor intellectual property core for generating a timer circuit system, comprising: An upstream interface having an upstream receiver configured to convert downlink signals into a downlink symbol stream; A downstream interface having a downstream transmitter configured to provide a transmission signal representing the downlink symbol stream; The core circuit system has: A downstream path, configured to transmit the downlink symbol stream from the upstream receiver to the downstream transmitter, the downstream path having a receive clock domain component, a core clock domain component, and a transmit clock domain component; as well as A downstream bypass path, configured to transmit the downlink symbol stream from the upstream receiver to the downstream transmitter without any core clock domain components; A controller configured to disable the clock signal for the transmit clock domain component of the downstream path when the downstream bypass path is enabled.

20. The non-transient information storage medium as described in claim 19, wherein, The downstream path includes multiple channels, and the controller is configured to disable clock signals for all channels except one in the core clock domain component when the downstream bypass path is enabled.

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