Instruction speculation execution method, device and storage medium of vector processor

Abstract

This application discloses a method, apparatus, and storage medium for instruction speculative execution in a vector processor. The method includes: responding to a vector configuration instruction identified at the front end of a vector processor pipeline; querying a vector prediction configuration table based on the instruction information of the vector configuration instruction to determine predicted vector configuration parameters; updating the speculative vector state at the back end of the vector processor pipeline based on the predicted vector configuration parameters; performing speculative processing on vector instructions following the vector configuration instruction based on the speculative vector state; determining the actual vector configuration parameters when the actual execution result of the vector configuration instruction is obtained; comparing the actual vector configuration parameters with the predicted vector configuration parameters; if they match, confirming the validity of the speculative processing and updating the confidence information in the vector prediction configuration table; if they do not match, performing a flushing operation on the vector processor pipeline and updating the vector prediction configuration table using the actual vector configuration parameters. This application can improve the processing efficiency of a vector processor pipeline.

Description

Technical Field

[0001] This disclosure relates to the field of vector processor technology, and in particular to a method, apparatus and storage medium for instruction speculative execution of a vector processor. Background Technology

[0002] With the increasing demand for high-performance computing, the RISC-V architecture of vector processors has been widely used in modern processor design due to its open-source flexibility and powerful vector scalability. Its core advantage lies in its support for variable-length vector operations, dynamically setting parameters such as vector length and register grouping multiples through vector configuration instructions, flexibly adapting to different data processing scales and register resources. However, current vector processors typically employ strongly serial execution logic when processing such vector configuration instructions. This means that subsequent vector arithmetic instructions must strictly wait for the configuration instruction to complete its actual calculations and confirm its parameters before determining its own execution width and register layout. Therefore, improving the processing efficiency of vector processor pipelines is a crucial issue. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide an instruction speculative execution method, apparatus, and storage medium for a vector processor, aiming to improve the processing efficiency of a vector processor pipeline. A first aspect provides an instruction speculative execution method for a vector processor, comprising: responding to a vector configuration instruction identified at the front end of a vector processor pipeline; querying a vector prediction configuration table based on instruction information of the vector configuration instruction to determine predicted vector configuration parameters, the predicted vector configuration parameters including: vector length and register grouping multiple; updating the speculative vector state at the back end of the vector processor pipeline based on the predicted vector configuration parameters; performing speculative processing on vector instructions following the vector configuration instruction based on the speculative vector state before obtaining the actual execution result of the vector configuration instruction, the speculative processing including: register renaming and issuing; when the actual execution result of the vector configuration instruction is obtained, determining the actual vector configuration parameters; comparing the actual vector configuration parameters with the predicted vector configuration parameters; when the comparison results are consistent, confirming the validity of the speculative processing and updating the confidence information in the vector prediction configuration table; when the comparison results are inconsistent, performing a flushing operation on the vector processor pipeline and updating the vector prediction configuration table using the actual vector configuration parameters.

[0004] The instruction speculative execution method of the vector processor described above breaks the strong serial dependency between vector configuration instructions and subsequent vector arithmetic instructions in the RISC-V architecture by introducing a prediction mechanism based on historical information at the pipeline front end. Before the configuration instruction completes its actual calculation, the speculative parameters drive subsequent instructions to complete register renaming and issuing in advance, thereby reducing the execution latency of vector configuration instructions and eliminating pipeline bubbles caused by waiting for configuration results. Especially in scenarios with intensive vector loop calculations, this method can improve the instruction throughput and overall computational efficiency of the vector processor.

[0005] Optionally, querying the vector prediction configuration table based on the instruction information of the vector configuration instruction includes: using the program counter of the vector configuration instruction or the hash value of the program counter as an index to query the vector prediction configuration table.

[0006] Optionally, the vector prediction configuration table includes multiple configuration items, including one or more of the following: historical vector configuration parameters, valid bits used to indicate whether an entry is valid, confidence counter, and program counter identifier.

[0007] Optionally, determining the predicted vector configuration parameters includes: querying the vector prediction configuration table based on the program counter of the vector configuration instruction; obtaining a first historical configuration parameter corresponding to the cyclic computation scenario; or, obtaining a second historical configuration parameter corresponding to the non-cyclic computation scenario; wherein the first historical configuration parameter is used to characterize the vector configuration parameter of the vector configuration instruction in the cyclic computation scenario, and the second historical configuration parameter is used to characterize the vector configuration parameter corresponding to at least one vector configuration instruction recently executed by the vector processor; and determining the predicted vector configuration parameters based on the first historical configuration parameter or the second historical configuration parameter.

[0008] Optionally, register renaming is configured to determine the number of physical registers required for vector instructions following the vector configuration instruction based on the predicted register grouping multiple, and to allocate physical registers.

[0009] Optionally, when the comparison results are inconsistent, after performing a flushing operation on the vector processor pipeline, the method further includes controlling the vector processor pipeline to start fetching instructions again from the instruction following the vector configuration instruction.

[0010] Optionally, update the confidence information in the vector prediction configuration table, including: increasing the value of the confidence counter; updating the vector prediction configuration table using actual vector configuration parameters, including: overwriting the original prediction vector configuration parameters in the vector prediction configuration table with actual vector configuration parameters; and / or, decreasing the value of the confidence counter.

[0011] Secondly, a vector processor instruction speculation execution apparatus is provided, comprising: a storage unit for storing a vector prediction configuration table, the vector prediction configuration table recording historical configuration information; a speculation control logic unit connected to the storage unit, configured to, in response to a vector configuration instruction identified at the front end of the vector processor pipeline, query the vector prediction configuration table in the storage unit based on the instruction information of the vector configuration instruction to determine the predicted vector configuration parameters; further configured to update the speculative vector state at the back end of the vector processor pipeline based on the predicted vector configuration parameters, so as to perform speculation processing on vector instructions following the vector configuration instruction based on the speculative vector state before obtaining the actual execution result of the vector configuration instruction, the speculation processing including: register renaming and issuance; and a verification and recovery logic unit connected to the storage unit and the vector processor pipeline, configured to, when obtaining the actual execution result of the vector configuration instruction, determine the actual vector configuration parameters and compare the actual vector configuration parameters with the predicted vector configuration parameters; when the comparison results are consistent, confirm the validity of the speculation processing and update the confidence information in the vector prediction configuration table; when the comparison results are inconsistent, perform a flushing operation on the vector processor pipeline and update the vector prediction configuration table using the actual vector configuration parameters.

[0012] Thirdly, a vector processor instruction speculation execution apparatus is provided, comprising: a query unit, configured to query a vector prediction configuration table based on instruction information of a vector configuration instruction identified at the front end of a vector processor pipeline, and determine predicted vector configuration parameters in response to a vector configuration instruction identified at the front end of the vector processor pipeline; an update unit, configured to update the speculative vector state of the back end of the vector processor pipeline based on the predicted vector configuration parameters; a speculation unit, configured to perform speculation processing on vector instructions following the vector configuration instruction based on the speculative vector state before obtaining the actual execution result of the vector configuration instruction, the speculation processing including register renaming and issuance; an acquisition unit, configured to determine the actual vector configuration parameters when the actual execution result of the vector configuration instruction is obtained; and a comparison unit, configured to compare the actual vector configuration parameters with the predicted vector configuration parameters, confirm the validity of the speculation processing when the comparison results are consistent, and update the confidence information in the vector prediction configuration table; and perform a flushing operation on the vector processor pipeline and update the vector prediction configuration table using the actual vector configuration parameters when the comparison results are inconsistent.

[0013] Fourthly, a computer-readable storage medium is provided, including instructions that, when executed by a processor, implement the instruction speculative execution method of a vector processor as described in the first aspect. Attached Figure Description

[0014] The accompanying drawings used in the description of the embodiments of this disclosure are briefly introduced below:

[0015] Figure 1The diagram shows a flowchart illustrating an instruction speculative execution method for a vector processor provided in some embodiments of this application;

[0016] Figure 2 This paper shows a structural block diagram of an instruction speculative execution apparatus for a vector processor provided in some embodiments of this application;

[0017] Figure 3 The diagram shows a schematic representation of the structure of an instruction speculative execution device for a vector processor provided in some embodiments of this application. Detailed Implementation

[0018] To more clearly illustrate the technical solutions in the embodiments of this disclosure, examples of implementation methods of this disclosure will be described below with reference to the accompanying drawings. The accompanying drawings described below are merely some embodiments of this disclosure. For those skilled in the art, other drawings and other implementation methods can be obtained based on these drawings without creative effort. Adjustments and improvements made without departing from the concept of this disclosure are all within the protection scope of this disclosure.

[0019] To keep the drawings simple, each figure only schematically shows the parts relevant to the embodiment, and they do not represent the actual structure of the product. In addition, for the sake of clarity and ease of understanding, some figures only schematically show parts of components with the same structure or function, and there may actually be more or fewer components with the same structure or function.

[0020] In this disclosure, unless otherwise expressly specified and limited, ordinal numbers, such as “first”, “second”, etc., are used only to distinguish and describe related objects, and should not be construed as indicating or implying the relative importance or order between related objects; furthermore, they do not represent the quantity of related objects. “Multiple” includes two or more, and other quantifiers are similar. “ / ” is used to describe the relationship between related objects, indicating an “or” relationship between them. “And / or” is used to describe the relationship between related objects, including any combination relationship between them, such as “a and / or b” including: “a alone”, “b alone”, or “a and b”. “One or more” or “at least one” of multiple objects refers to any object or any combination of multiple objects, such as “one or more of a1, a2, a3” or “at least one of a1, a2, a3” including: “a1 alone”, “a2 alone”, “a3 alone”, “a1 and a2”, “a1 and a3”, “a2 and a3”, or “a1, a2 and a3”.

[0021] In the current RISC-V vector processor microarchitecture, to support flexible data parallel processing, vector extensions introduce two key dynamic configuration parameters: vector length and register grouping multiple. The vector length determines the number of data elements operated on by a single instruction, while the register grouping multiple allows multiple consecutive vector registers to be combined into a larger logical register to increase operational bandwidth. There is a strong timing dependency between the processor and vector configuration instructions (such as `vsetvl`). The execution logic is typically designed so that when the front end of the pipeline encounters a vector configuration instruction, it must be sent to the back end execution unit for actual computation. Only after the exact vector length and register grouping multiple are calculated and the system state is updated can subsequent vector arithmetic instructions be allowed to enter the register renaming and issue phase. In actual program execution flow, especially when dealing with dense vector loop code, the drawbacks of this mechanism become increasingly apparent. Because the allocation of physical registers for subsequent vector instructions directly depends on the register grouping multiple set by the configuration instruction (for example, a register grouping multiple of LMUL=2 means that each instruction requires 2 physical registers), the hardware cannot know how many resources subsequent instructions will require until the configuration instruction is committed, causing the pipeline to be forced to pause. This architecture design, which heavily relies on configuration results, creates "bubbles" in the pipeline for several clock cycles each time a configuration instruction is executed, causing back-end execution units to be idle and waiting. As the complexity of computational tasks increases, frequent pipeline pauses significantly reduce instruction throughput. Furthermore, although in actual programs, especially within loops, the values ​​of vector length and register grouping multiple often exhibit high locality and repetition, existing conservative designs fail to utilize this characteristic and still mechanically execute the instruction fetch-wait-execute serial process. Once a high-frequency configuration switch is encountered, the processor's performance will degrade significantly due to continuous waiting delays. In view of this, this application provides an instruction speculative execution method, apparatus and storage medium for a vector processor. By introducing a vector configuration prediction mechanism, the vector length and register grouping multiple are predicted during the instruction fetch stage, and register renaming and instruction issuance are allowed in advance based on the predicted values. This achieves pipeline decoupling of configuration instructions and arithmetic instructions, and significantly improves the computational efficiency and throughput of the vector processor while eliminating pipeline bubbles.

[0022] The following description is in conjunction with the accompanying drawings:

[0023] Please refer to Figure 1 This document illustrates a flowchart of an instruction speculative execution method for a vector processor, provided in some embodiments of this application. The instruction speculative execution method for a vector processor includes:

[0024] S110: In response to a vector configuration instruction identified at the front end of the vector processor pipeline, the vector prediction configuration table is queried based on the instruction information of the vector configuration instruction to determine the predicted vector configuration parameters, which include: vector length and register grouping multiple;

[0025] S120: Update the speculative vector state of the back end of the vector processor pipeline based on the predicted vector configuration parameters;

[0026] S130: Before obtaining the actual execution result of the vector configuration instruction, perform speculative processing on the vector instructions following the vector configuration instruction based on the speculative vector state. The speculative processing includes register renaming and issuance.

[0027] S140: When the actual execution result of the vector configuration instruction is obtained, the actual vector configuration parameters are determined;

[0028] S150: Compare the actual vector configuration parameters with the predicted vector configuration parameters;

[0029] S160: When the comparison results are consistent, confirm that the speculation process is effective and update the confidence information in the vector prediction configuration table;

[0030] S170: When the comparison results are inconsistent, perform a flushing operation on the vector processor pipeline and update the vector prediction configuration table using the actual vector configuration parameters.

[0031] During processor pipeline operation, when the front end of a vector processor, such as the fetch and decode stages, detects a vector configuration instruction (e.g., `vsetvl`) in the current instruction stream, the system does not immediately pause subsequent operations to wait for the instruction's execution result, as is done in the traditional approach. Instead, it uses the instruction information of the vector configuration instruction, such as the instruction's program counter address or its associated identifier, as an index to query a pre-established vector prediction configuration table. The vector prediction configuration table can be a storage structure used to record historical configuration patterns. By querying this table, historical records corresponding to the instruction information can be retrieved, thereby determining the predicted vector configuration parameters. The predicted vector configuration parameters may include the predicted vector length and the predicted register grouping multiple, representing the most likely configuration value inferred by the system based on past experience. After obtaining the predicted value, the speculative vector state at the back end of the vector processor pipeline can be updated based on these predicted vector configuration parameters. Speculative vector state refers to the time difference between the processor's assumption of a valid context and the actual execution result of the vector configuration instruction. Before the actual execution result of the vector configuration instruction is obtained from the execution unit, the processor uses this speculative vector state to speculate on subsequent vector instructions following the configuration instruction. In a vector processor, the register renaming stage is responsible for mapping logical registers to physical registers. Since the register grouping multiple directly determines how many physical registers a single logical vector register needs to occupy, the renaming unit can only correctly allocate resources after the register grouping multiple is determined. In this embodiment, by using the predicted register grouping multiple, the renaming unit can allocate physical registers for subsequent instructions without waiting and issue these instructions to the corresponding execution queues for execution, thereby achieving parallelization of the calculation of the configuration instruction and the preparation of subsequent instructions. After the vector configuration instruction completes the actual arithmetic and logical operations in the functional unit, the system can determine the actual vector configuration parameters. At this point, to verify whether the previous speculation is correct, the actually calculated parameters can be compared one by one with the previously used predicted vector configuration parameters. Based on the comparison results, if the results are consistent, it indicates that the previous prediction was accurate, and the register renaming and issue operations performed based on the predicted state are safe. The validity of the prediction processing can be confirmed, allowing the execution results of subsequent instructions to be committed. Simultaneously, the confidence information in the vector prediction configuration table can be updated, for example, by increasing the weight of the entry or marking it as more reliable, so that the predicted value can be used more confidently the next time the same instruction is encountered. Conversely, if the comparison results are inconsistent, it indicates that the prediction failed.At this point, due to incorrect parameters, such as an incorrect register grouping multiple, subsequent instruction processing based on the incorrect number of physical registers allocated is invalid. Therefore, a flushing operation must be performed on the vector processor pipeline to clear all subsequent instructions that have entered the pipeline on the speculative path and release the incorrectly allocated resources, so as to roll back the processor state to the correct node. To avoid repeating the same error in the future, the vector prediction configuration table can be updated using the newly calculated actual vector configuration parameters to correct historical records, thereby achieving adaptive learning and calibration of the prediction mechanism. This application provides a vector processor instruction speculative execution method that breaks the strong serial dependency between vector configuration instructions and subsequent vector arithmetic instructions in the RISC-V architecture by introducing a prediction mechanism based on historical information at the pipeline front end. Before the configuration instruction completes its actual operation, the speculative parameters drive subsequent instructions to complete register renaming and issuance in advance, thereby reducing the execution latency of vector configuration instructions and eliminating pipeline bubbles caused by waiting for configuration results. Especially in dense vector loop computation scenarios, this can improve the instruction throughput and overall computational efficiency of the vector processor.

[0032] In some embodiments of this application, querying the vector prediction configuration table based on the instruction information of the vector configuration instruction includes: using the program counter of the vector configuration instruction or the hash value of the program counter as an index to query the vector prediction configuration table.

[0033] Instructions in a vector processor's instruction stream have unique memory addresses, i.e., program counter values. Due to the locality of reference characteristic exhibited by computer programs during execution, specific vector configuration instructions reside at fixed addresses in memory. Furthermore, configuration instructions at the same address tend to set the same vector length and register grouping multiples during multiple iterations of program execution. Therefore, this application can choose to use the program counter of the vector configuration instruction as a key identifier for associating historical records. At the hardware operation level, the lookup process can be configured in two modes. The first mode uses the complete program counter value or its lower-order bits of the vector configuration instruction directly as the index address to access the vector prediction configuration table. This direct mapping method is logically simple and fast, accurately locating the historical record of a specific instruction. The second mode, to optimize on-chip storage resources and reduce hardware overhead, uses the hash value of the program counter as an index. A specific hash function maps a longer program counter value address width to a shorter index value, and the hash result is used to look up the vector prediction configuration table. This method can significantly reduce the storage capacity required for the vector prediction configuration table while maintaining a high prediction hit rate.

[0034] In some embodiments of this application, the vector prediction configuration table includes multiple configuration items, including one or more of the following: historical vector configuration parameters, valid bits for indicating whether an entry is valid, confidence counter, and program counter identifier.

[0035] To ensure the accuracy of the prediction mechanism, the vector prediction configuration table can contain multiple independent configuration items. Each configuration item, as a basic unit, contains comprehensive information for maintaining the prediction state, such as one or more of the following: historical vector configuration parameters, a valid bit, a confidence counter, and a program counter identifier. Historical vector configuration parameters store the vector length and register block multiple that were actually effective during the most recent or subsequent executions of the vector configuration instruction. When the system query hits this configuration item, these two parameters are read and sent directly as the prediction value to the pipeline controller to guide subsequent resource allocation. The valid bit is a flag indicating the current status of the configuration item. Initially, after the vector processor powers on, resets, or performs a specific flush operation, the initial data in memory is often undefined random values. By introducing the valid bit, it's possible to distinguish whether the currently read data is valid historical data that has been initialized or invalid data that has not yet been written. Only when the valid bit is set is the parameter in the configuration item eligible for adoption, thus preventing the vector processor from being misled by invalid data. The program counter identifier is used to resolve index collisions, especially in architectures using hash indexes. Since hash functions may map instructions from different addresses to the same entry location, the index alone cannot determine whether the current entry truly belongs to the currently executing instruction. Therefore, the configuration item can store a portion of the high-order bits or all bits of the instruction's program counter as a tag. During a query, the hardware not only locates the entry but also compares the current instruction's program counter with the program counter tag in the configuration item. Only when they match is the prediction considered a successful query. Furthermore, a confidence counter can be used to introduce a hysteresis mechanism to enhance prediction stability. It can be a multi-bit saturation counter used to record the historical accuracy of the configuration parameter. When the prediction is verified as correct, the counter value increases, indicating that the prediction has become more reliable; when the prediction fails, the counter value decreases. Therefore, the counter value can be used to determine whether to use the prediction value or whether to overwrite the old record with a new parameter. This mechanism can effectively filter out occasional fluctuations during program execution, preventing a single accidental parameter change from immediately overturning long-term stable prediction parameters, thus ensuring the overall performance stability.

[0036] In some embodiments of this application, determining the predicted vector configuration parameters includes: querying a vector prediction configuration table based on the program counter of the vector configuration instruction; obtaining a first historical configuration parameter corresponding to a cyclic computation scenario; or, obtaining a second historical configuration parameter corresponding to a non-cyclic computation scenario; wherein the first historical configuration parameter is used to characterize the vector configuration parameter of the vector configuration instruction in the cyclic computation scenario, and the second historical configuration parameter is used to characterize the vector configuration parameter corresponding to at least one vector configuration instruction recently executed by the vector processor; and determining the predicted vector configuration parameters based on the first historical configuration parameter or the second historical configuration parameter.

[0037] When the program counter queries the vector prediction configuration table based on vector configuration instructions, two types of historical information can be obtained. First, the first historical configuration parameter corresponding to loop computation scenarios is obtained. Loop computation scenarios involve program code repeatedly jumping within a specific address range, such as in a loop body of matrix operations or image processing. Vector configuration instructions at the same program counter address tend to maintain unchanged parameters across multiple iterations. Therefore, the first historical configuration parameter is essentially the configuration value recorded during the last or most recent execution of that specific program counter address. If the query hits with high confidence, it indicates that the current instruction is highly likely in a stable loop structure, and the first historical configuration parameter can provide high-accuracy prediction. Second, the second historical configuration parameter corresponding to non-loop computation scenarios can be obtained. Non-loop computation scenarios involve sequentially executed code segments or the first entry into a function module. In these scenarios, the program counter address of the current instruction may not yet have a stable historical record in the table, or the program may be in a linear flow with frequent configuration switching. The behavior of the current instruction is often controlled by the global context of program execution, thus exhibiting temporal locality. The second historical configuration parameter is used to characterize the parameter values ​​set by one or more vector configuration instructions most recently executed before the current instruction. For example, if the preceding instructions all set the maximum vector length and specific register multiples for calculation, then even if the current instruction is new, it is highly likely to inherit this configuration pattern. When actually determining the final predicted vector configuration parameters, an arbitration or selection logic can be implemented. For example, the validity and confidence of the first historical configuration parameter can be checked first. If the current instruction is found to be in a high-confidence loop, the first historical configuration parameter is preferred as the prediction result to take advantage of the loop's stability. Conversely, if the query based on the program counter misses or has low confidence, it indicates that the instruction may be in a non-loop or initial execution phase. In this case, a rollback is made and the second historical configuration parameter is adopted, using the most recent vector configuration parameter for prediction.

[0038] In some embodiments of this application, register renaming is configured to determine the number of physical registers required for a vector instruction following a vector configuration instruction based on a predicted register grouping multiple, and to allocate physical registers.

[0039] In some embodiments of this application, when the comparison results are inconsistent, after performing a flushing operation on the vector processor pipeline, the method further includes: controlling the vector processor pipeline to re-fetch instructions starting from the instruction following the vector configuration instruction.

[0040] When the verification logic detects a mismatch between the actually calculated vector configuration parameters and the previously used predicted values, it means that the speculative vector state established based on those predicted values ​​is incorrect, leading to all subsequent vector instructions that depend on that state being in an illegal execution state. To correct this error, the system can perform a flush operation on the vector processor pipeline. This immediately terminates and clears all speculative instructions following the vector configuration instruction and their intermediate data, ensuring that calculation results based on erroneous parameters are not written back to the register file or memory. After the pipeline flush, a re-fetch procedure is triggered. Since the vector configuration instruction that caused the prediction failure has already performed the correct calculation in the execution unit and obtained the correct configuration parameters, this instruction itself does not need to be executed again. The vector processor can calculate the address of the next instruction immediately following the vector configuration instruction based on its address and load that address into the program counter. Subsequently, the instruction fetch unit restarts fetching the instruction stream from this new address. At this point, since the correct actual vector configuration parameters have been updated in the processor's non-speculated architectural state, subsequent vector instructions re-entering the pipeline will reference these correct parameters during the register renaming and issue phases, thus ensuring the accurate execution of subsequent computational tasks. This strategy of only rolling back subsequent instructions can correct errors while preserving as much of the valid work already completed as possible.

[0041] In some embodiments of this application, updating the confidence information in the vector prediction configuration table includes: increasing the value of the confidence counter; updating the vector prediction configuration table using actual vector configuration parameters, including: overwriting the original prediction vector configuration parameters in the vector prediction configuration table with actual vector configuration parameters; and / or, decreasing the value of the confidence counter.

[0042] When the predicted vector configuration parameters match the actual execution results, it indicates that the historical parameters recorded in the current configuration item are stable and reliable in the current program stage. Therefore, the corresponding confidence counter value in the configuration item can be incremented by one until it reaches the maximum value allowed by the counter. For example, for a 2-bit counter, the state may transition from weak confidence (01) to strong confidence (10). When updating the vector prediction configuration table using the actual vector configuration parameters, the actual vector configuration parameters can be used to overwrite the original predicted vector configuration parameters. When the confidence is low, if the prediction fails, it means that the behavior mode of the program has fundamentally changed. At this time, the actual vector configuration parameters that have just been calculated can be directly written into the corresponding table entry to overwrite the old, incorrect prediction values. At the same time, the confidence of the newly written table entry is usually reset to an initial value (e.g., weak confidence) so that a new round of learning can begin. Alternatively, the value of the confidence counter can be reduced. When the prediction fails, the parameters in the table are not immediately replaced. Instead, the value of the confidence counter is decremented by one. By only reducing the confidence without immediately overwriting the parameters, the old prediction values ​​can be given "another chance". If the next execution fails again, the confidence level continues to decrease until it falls below a certain threshold (e.g., to zero), at which point the system will perform the above-mentioned overwrite operation.

[0043] Figure 2 This diagram illustrates a structural block diagram of an instruction speculative execution apparatus for a vector processor according to some embodiments of this application. The instruction speculative execution apparatus 200 includes: a storage unit 230 for storing a vector prediction configuration table, which records historical configuration information; and a speculative control logic unit 220 connected to the storage unit 230, configured to, in response to a vector configuration instruction identified at the front end of the vector processor pipeline, query the vector prediction configuration table in the storage unit 230 based on the instruction information of the vector configuration instruction to determine predicted vector configuration parameters; and further configured to update the speculative vector state at the back end of the vector processor pipeline based on the predicted vector configuration parameters, so as to maintain the speculative vector state before obtaining the actual execution result of the vector configuration instruction. The state performs speculative processing on vector instructions following the vector configuration instruction. The speculative processing includes register renaming and issuance. Verification and recovery logic unit 240, connected to storage unit 230 and vector processor pipeline, is used to determine the actual vector configuration parameters when the actual execution result of the vector configuration instruction is obtained, and compare the actual vector configuration parameters with the predicted vector configuration parameters. When the comparison results are consistent, the speculative processing is confirmed to be effective, and the confidence information in the vector prediction configuration table is updated. When the comparison results are inconsistent, a flushing operation is performed on the vector processor pipeline, and the vector prediction configuration table is updated using the actual vector configuration parameters.

[0044] The instruction speculative execution unit 200 is mainly integrated into the pipeline architecture of the vector processor, including: a speculative control logic unit 220, a memory unit 230, and a verification and recovery logic unit 240. For ease of understanding, the figure also shows the conventional components of the processor pipeline that interact with the instruction speculative execution unit 200, including a program counter 211, an instruction fetch unit 212, a decode unit 213, a register renaming and instruction issue unit 214, a computation execution unit 215, and an instruction completion and commit unit 216.

[0045] Storage unit 230 stores the vector prediction configuration table, recording historical configuration information, including parameters such as historical vector length and register grouping multiples. In hardware implementation, storage unit 230 can be implemented using a cache or a dedicated register file to support fast read and write access. Speculative control logic unit 220 is deployed at the front end of the pipeline, connected to instruction fetch unit 212, decode unit 213, and storage unit 230. Its primary function is as a prediction initiator. When instruction fetch unit 212 or decode unit 213 identifies a vector configuration instruction in the current instruction stream at the pipeline front end, speculative control logic unit 220 immediately responds, extracting the instruction information of the vector configuration instruction, such as the instruction's program counter (PC) value or its hash mapping value, and using this as an index to query storage unit 230. Through the query operation, speculative control logic unit 220 determines the predicted vector configuration parameters for the current instruction. Speculative control logic unit 220 is also responsible for applying the acquired predicted vector configuration parameters to the pipeline, updating the speculative vector state at the back end of the vector processor pipeline. The predicted vector configuration parameters are directly passed to the register renaming and instruction issuing unit 214. Thus, even if the computation execution unit 215 has not yet calculated the exact configuration result, the register renaming and instruction issuing unit 214 can use this speculative vector state to preemptively perform speculative processing on subsequent vector instructions following the vector configuration instruction before obtaining the actual execution result of the vector configuration instruction. The verification and recovery logic unit 240 is deployed at the back end of the pipeline, connected to the computation execution unit 215, the instruction completion submission unit 216, the storage unit 230, and the pipeline control path. Its main function is result adjudication and state correction. After the vector configuration instruction is calculated in the computation execution unit 215, the verification and recovery logic unit 240 obtains the actual execution result of the instruction, thereby determining the actual vector configuration parameters. Subsequently, the verification and recovery logic unit 240 executes comparison logic, comparing the just-calculated actual vector configuration parameters with the previously used predicted vector configuration parameters. When the comparison results are consistent, it indicates that the previous prediction was correct. The verification and recovery logic unit 240 confirms that the prediction processing is valid, allows the instruction completion submission unit 216 to submit the results of subsequent instructions, and sends a signal to the storage unit 230 to update the confidence information in the vector prediction configuration table, such as increasing the value of the saturation counter, thereby strengthening the credibility of the record. When the comparison results are inconsistent, it indicates that the prediction has failed. The verification and recovery logic unit 240 will immediately trigger the recovery mechanism. On the one hand, it sends flushing signals to each stage of the pipeline to perform a flushing operation on the vector processor pipeline to completely remove the renaming and calculation results based on the erroneous prediction.On the other hand, by using the actual vector configuration parameters to update the vector prediction configuration table in memory unit 230, historical records are corrected to avoid repeating the same mistakes. Simultaneously, the pipeline can be controlled to restart instruction fetching from the instruction following the vector configuration instruction, ensuring the correctness of program execution. Through the collaborative work of the aforementioned speculative control logic unit 220, memory unit, and verification and recovery logic unit 240, configuration instructions and arithmetic instructions can be decoupled at the hardware level, significantly improving the execution efficiency of the vector processor.

[0046] Figure 3 The diagram illustrates a schematic of the structure of an instruction speculative execution apparatus for a vector processor, provided in some embodiments of this application. The instruction speculative execution apparatus 300 includes: a query unit 310, configured to query a vector prediction configuration table based on instruction information of a vector configuration instruction identified at the front end of the vector processor pipeline, in response to such a vector configuration instruction, and determine predicted vector configuration parameters; an update unit 320, configured to update the speculative vector state at the back end of the vector processor pipeline based on the predicted vector configuration parameters; a speculation unit 330, configured to perform speculative processing on vector instructions following the vector configuration instruction based on the speculative vector state before obtaining the actual execution result of the vector configuration instruction, the speculative processing including register renaming and issuing; an acquisition unit 340, configured to determine the actual vector configuration parameters when the actual execution result of the vector configuration instruction is obtained; and a comparison unit 350, configured to compare the actual vector configuration parameters with the predicted vector configuration parameters, confirming the validity of the speculative processing and updating the confidence information in the vector prediction configuration table when the comparison results are consistent; and performing a flushing operation on the vector processor pipeline and updating the vector prediction configuration table using the actual vector configuration parameters when the comparison results are inconsistent.

[0047] Based on the same technical concept, this application provides a computer-readable storage medium including instructions, which, when executed by a processor, implement the instruction speculative execution method of the vector processor as provided in the above embodiments.

[0048] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions in other embodiments. Furthermore, the above embodiments can be freely combined as needed.

Claims

1. A method for instruction speculative execution in a vector processor, characterized in that, include: In response to a vector configuration instruction identified at the front end of the vector processor pipeline, the vector prediction configuration table is queried based on the instruction information of the vector configuration instruction to determine the predicted vector configuration parameters. The predicted vector configuration parameters include: vector length and register grouping multiple. The vector prediction configuration table includes multiple configuration items, including: historical vector configuration parameters, valid bits for indicating whether the table entry is valid, confidence counter and program counter identifier. The step of determining the prediction vector configuration parameters includes: querying the vector prediction configuration table based on the program counter of the vector configuration instruction; obtaining a first historical configuration parameter corresponding to a cyclic computing scenario; or obtaining a second historical configuration parameter corresponding to a non-cyclic computing scenario; wherein, the first historical configuration parameter is used to characterize the vector configuration parameter of the vector configuration instruction in the cyclic computing scenario, and the second historical configuration parameter is used to characterize the vector configuration parameter corresponding to at least one vector configuration instruction recently executed by the vector processor; Determining the prediction vector configuration parameter based on the first historical configuration parameter or the second historical configuration parameter includes: determining the prediction vector configuration parameter based on the first historical configuration parameter when the first historical configuration parameter is valid and the confidence level of the first historical configuration parameter meets a preset condition; and determining the prediction vector configuration parameter based on the second historical configuration parameter when the query based on the program counter fails or the confidence level of the first historical configuration parameter does not meet the preset condition. The speculative vector state of the back end of the vector processor pipeline is updated based on the predicted vector configuration parameters. Before obtaining the actual execution result of the vector configuration instruction, speculative processing is performed on the vector instructions following the vector configuration instruction based on the speculative vector state. The speculative processing includes register renaming and issuing. When the actual execution result of the vector configuration instruction is obtained, the actual vector configuration parameters are determined; The actual vector configuration parameters are compared with the predicted vector configuration parameters. When the comparison results are consistent, the speculation process is confirmed to be effective, and the confidence information in the vector prediction configuration table is updated. When the comparison results are inconsistent, a flushing operation is performed on the vector processor pipeline, and the vector prediction configuration table is updated using the actual vector configuration parameters.

2. The instruction speculation execution method for a vector processor according to claim 1, characterized in that, The register renaming is configured to determine the number of physical registers required for vector instructions following the vector configuration instruction based on the predicted register grouping multiple, and to allocate physical registers.

3. The instruction speculation execution method for a vector processor according to claim 2, characterized in that, When the comparison results are inconsistent, after performing a flushing operation on the vector processor pipeline, the method further includes controlling the vector processor pipeline to start fetching instructions again from the next instruction after the vector configuration instruction.

4. The instruction speculation execution method for a vector processor according to claim 3, characterized in that, Updating the confidence information in the vector prediction configuration table includes: Increase the value of the confidence counter; The step of updating the vector prediction configuration table using the actual vector configuration parameters includes: The actual vector configuration parameters are used to override the original prediction vector configuration parameters in the vector prediction configuration table; and / or, Decrease the value of the confidence counter.

5. An instruction speculation execution apparatus for a vector processor, characterized in that, include: A storage unit is used to store a vector prediction configuration table, which records historical configuration information. The speculative control logic unit, connected to the storage unit, is used to respond to a vector configuration instruction identified at the front end of the vector processor pipeline, query the vector prediction configuration table in the storage unit based on the instruction information of the vector configuration instruction, and determine the predicted vector configuration parameters. The vector prediction configuration table includes multiple configuration items, including: historical vector configuration parameters, a valid bit for indicating whether the table entry is valid, a confidence counter, and a program counter identifier. The speculative control logic unit is further configured to query the vector prediction configuration table based on the program counter of the vector configuration instruction; obtain a first historical configuration parameter corresponding to the cyclic computing scenario; or obtain a second historical configuration parameter corresponding to the non-cyclic computing scenario; wherein the first historical configuration parameter is used to characterize the vector configuration parameter of the vector configuration instruction in the cyclic computing scenario, and the second historical configuration parameter is used to characterize the vector configuration parameter corresponding to at least one vector configuration instruction recently executed by the vector processor; The speculative control logic unit is further configured to determine the prediction vector configuration parameter based on the first historical configuration parameter or the second historical configuration parameter, including: when the first historical configuration parameter is valid and the confidence level of the first historical configuration parameter meets a preset condition, determining the prediction vector configuration parameter based on the first historical configuration parameter; when the query based on the program counter fails or the confidence level of the first historical configuration parameter does not meet the preset condition, determining the prediction vector configuration parameter based on the second historical configuration parameter. It is also used to update the speculative vector state of the back end of the vector processor pipeline based on the predicted vector configuration parameters, so as to perform speculative processing on the vector instructions after the vector configuration instructions based on the speculative vector state before obtaining the actual execution result of the vector configuration instructions. The speculative processing includes: register renaming and issuing. The verification and recovery logic unit, connected to the storage unit and the vector processor pipeline, is used to determine the actual vector configuration parameters when the actual execution result of the vector configuration instruction is obtained, and compare the actual vector configuration parameters with the predicted vector configuration parameters; when the comparison result is consistent, the speculation processing is confirmed to be effective, and the confidence information in the vector prediction configuration table is updated; when the comparison result is inconsistent, a flushing operation is performed on the vector processor pipeline, and the vector prediction configuration table is updated using the actual vector configuration parameters.

6. An instruction speculation execution apparatus for a vector processor, characterized in that, include: A query unit is configured to respond to a vector configuration instruction identified at the front end of the vector processor pipeline, query a vector prediction configuration table based on the instruction information of the vector configuration instruction, and determine the predicted vector configuration parameters. The predicted vector configuration parameters include: vector length and register grouping multiple. The vector prediction configuration table includes multiple configuration items, including: historical vector configuration parameters, a valid bit indicating whether an entry is valid, a confidence counter, and a program counter identifier. Determining the predicted vector configuration parameters includes: querying the vector prediction configuration table based on the program counter of the vector configuration instruction; obtaining a first historical configuration parameter corresponding to a loop computation scenario; or, obtaining a second historical configuration parameter corresponding to a non-loop computation scenario; wherein... The first historical configuration parameter is used to characterize the vector configuration parameters of the vector configuration instruction in the loop calculation scenario, and the second historical configuration parameter is used to characterize the vector configuration parameters corresponding to at least one vector configuration instruction recently executed by the vector processor; determining the predicted vector configuration parameters based on the first historical configuration parameter or the second historical configuration parameter includes: determining the predicted vector configuration parameters based on the first historical configuration parameter when the first historical configuration parameter is valid and the confidence level of the first historical configuration parameter meets a preset condition; and determining the predicted vector configuration parameters based on the second historical configuration parameter when the query based on the program counter is not hit or the confidence level of the first historical configuration parameter does not meet the preset condition. An update unit is used to update the speculative vector state of the back end of the vector processor pipeline based on the predicted vector configuration parameters. The speculation unit is used to perform speculation processing on vector instructions following the vector configuration instruction based on the speculative vector state before obtaining the actual execution result of the vector configuration instruction. The speculation processing includes: register renaming and issuance. The acquisition unit is used to determine the actual vector configuration parameters when the actual execution result of the vector configuration instruction is obtained; The comparison unit is used to compare the actual vector configuration parameters with the predicted vector configuration parameters. When the comparison results are consistent, the inference processing is confirmed to be effective, and the confidence information in the vector prediction configuration table is updated. When the comparison results are inconsistent, a flushing operation is performed on the vector processor pipeline, and the vector prediction configuration table is updated using the actual vector configuration parameters.

7. A computer-readable storage medium, characterized in that, The instruction includes instructions that, when executed by a processor, implement the instruction speculative execution method of a vector processor as described in any one of claims 1 to 4.

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